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1/*
2 * SiRFSoC Real Time Clock interface for Linux
3 *
4 * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/err.h>
11#include <linux/rtc.h>
12#include <linux/platform_device.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/regmap.h>
17#include <linux/rtc/sirfsoc_rtciobrg.h>
18
19
20#define RTC_CN 0x00
21#define RTC_ALARM0 0x04
22#define RTC_ALARM1 0x18
23#define RTC_STATUS 0x08
24#define RTC_SW_VALUE 0x40
25#define SIRFSOC_RTC_AL1E (1<<6)
26#define SIRFSOC_RTC_AL1 (1<<4)
27#define SIRFSOC_RTC_HZE (1<<3)
28#define SIRFSOC_RTC_AL0E (1<<2)
29#define SIRFSOC_RTC_HZ (1<<1)
30#define SIRFSOC_RTC_AL0 (1<<0)
31#define RTC_DIV 0x0c
32#define RTC_DEEP_CTRL 0x14
33#define RTC_CLOCK_SWITCH 0x1c
34#define SIRFSOC_RTC_CLK 0x03 /* others are reserved */
35
36/* Refer to RTC DIV switch */
37#define RTC_HZ 16
38
39/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
40#define RTC_SHIFT 4
41
42#define INTR_SYSRTC_CN 0x48
43
44struct sirfsoc_rtc_drv {
45 struct rtc_device *rtc;
46 u32 rtc_base;
47 u32 irq;
48 unsigned irq_wake;
49 /* Overflow for every 8 years extra time */
50 u32 overflow_rtc;
51 spinlock_t lock;
52 struct regmap *regmap;
53#ifdef CONFIG_PM
54 u32 saved_counter;
55 u32 saved_overflow_rtc;
56#endif
57};
58
59static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset)
60{
61 u32 val;
62
63 regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val);
64 return val;
65}
66
67static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv,
68 u32 offset, u32 val)
69{
70 regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val);
71}
72
73static int sirfsoc_rtc_read_alarm(struct device *dev,
74 struct rtc_wkalrm *alrm)
75{
76 unsigned long rtc_alarm, rtc_count;
77 struct sirfsoc_rtc_drv *rtcdrv;
78
79 rtcdrv = dev_get_drvdata(dev);
80
81 spin_lock_irq(&rtcdrv->lock);
82
83 rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
84
85 rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0);
86 memset(alrm, 0, sizeof(struct rtc_wkalrm));
87
88 /*
89 * assume alarm interval not beyond one round counter overflow_rtc:
90 * 0->0xffffffff
91 */
92 /* if alarm is in next overflow cycle */
93 if (rtc_count > rtc_alarm)
94 rtc_time_to_tm((rtcdrv->overflow_rtc + 1)
95 << (BITS_PER_LONG - RTC_SHIFT)
96 | rtc_alarm >> RTC_SHIFT, &(alrm->time));
97 else
98 rtc_time_to_tm(rtcdrv->overflow_rtc
99 << (BITS_PER_LONG - RTC_SHIFT)
100 | rtc_alarm >> RTC_SHIFT, &(alrm->time));
101 if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E)
102 alrm->enabled = 1;
103
104 spin_unlock_irq(&rtcdrv->lock);
105
106 return 0;
107}
108
109static int sirfsoc_rtc_set_alarm(struct device *dev,
110 struct rtc_wkalrm *alrm)
111{
112 unsigned long rtc_status_reg, rtc_alarm;
113 struct sirfsoc_rtc_drv *rtcdrv;
114 rtcdrv = dev_get_drvdata(dev);
115
116 if (alrm->enabled) {
117 rtc_tm_to_time(&(alrm->time), &rtc_alarm);
118
119 spin_lock_irq(&rtcdrv->lock);
120
121 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
122 if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
123 /*
124 * An ongoing alarm in progress - ingore it and not
125 * to return EBUSY
126 */
127 dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
128 }
129
130 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT);
131 rtc_status_reg &= ~0x07; /* mask out the lower status bits */
132 /*
133 * This bit RTC_AL sets it as a wake-up source for Sleep Mode
134 * Writing 1 into this bit will clear it
135 */
136 rtc_status_reg |= SIRFSOC_RTC_AL0;
137 /* enable the RTC alarm interrupt */
138 rtc_status_reg |= SIRFSOC_RTC_AL0E;
139 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
140
141 spin_unlock_irq(&rtcdrv->lock);
142 } else {
143 /*
144 * if this function was called with enabled=0
145 * then it could mean that the application is
146 * trying to cancel an ongoing alarm
147 */
148 spin_lock_irq(&rtcdrv->lock);
149
150 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
151 if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
152 /* clear the RTC status register's alarm bit */
153 rtc_status_reg &= ~0x07;
154 /* write 1 into SIRFSOC_RTC_AL0 to force a clear */
155 rtc_status_reg |= (SIRFSOC_RTC_AL0);
156 /* Clear the Alarm enable bit */
157 rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
158
159 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS,
160 rtc_status_reg);
161 }
162
163 spin_unlock_irq(&rtcdrv->lock);
164 }
165
166 return 0;
167}
168
169static int sirfsoc_rtc_read_time(struct device *dev,
170 struct rtc_time *tm)
171{
172 unsigned long tmp_rtc = 0;
173 struct sirfsoc_rtc_drv *rtcdrv;
174 rtcdrv = dev_get_drvdata(dev);
175 /*
176 * This patch is taken from WinCE - Need to validate this for
177 * correctness. To work around sirfsoc RTC counter double sync logic
178 * fail, read several times to make sure get stable value.
179 */
180 do {
181 tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
182 cpu_relax();
183 } while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN));
184
185 rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) |
186 tmp_rtc >> RTC_SHIFT, tm);
187 return 0;
188}
189
190static int sirfsoc_rtc_set_time(struct device *dev,
191 struct rtc_time *tm)
192{
193 unsigned long rtc_time;
194 struct sirfsoc_rtc_drv *rtcdrv;
195 rtcdrv = dev_get_drvdata(dev);
196
197 rtc_tm_to_time(tm, &rtc_time);
198
199 rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
200
201 sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
202 sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT);
203
204 return 0;
205}
206
207static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
208 unsigned int enabled)
209{
210 unsigned long rtc_status_reg = 0x0;
211 struct sirfsoc_rtc_drv *rtcdrv;
212
213 rtcdrv = dev_get_drvdata(dev);
214
215 spin_lock_irq(&rtcdrv->lock);
216
217 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
218 if (enabled)
219 rtc_status_reg |= SIRFSOC_RTC_AL0E;
220 else
221 rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
222
223 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
224
225 spin_unlock_irq(&rtcdrv->lock);
226
227 return 0;
228
229}
230
231static const struct rtc_class_ops sirfsoc_rtc_ops = {
232 .read_time = sirfsoc_rtc_read_time,
233 .set_time = sirfsoc_rtc_set_time,
234 .read_alarm = sirfsoc_rtc_read_alarm,
235 .set_alarm = sirfsoc_rtc_set_alarm,
236 .alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
237};
238
239static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
240{
241 struct sirfsoc_rtc_drv *rtcdrv = pdata;
242 unsigned long rtc_status_reg = 0x0;
243 unsigned long events = 0x0;
244
245 spin_lock(&rtcdrv->lock);
246
247 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
248 /* this bit will be set ONLY if an alarm was active
249 * and it expired NOW
250 * So this is being used as an ASSERT
251 */
252 if (rtc_status_reg & SIRFSOC_RTC_AL0) {
253 /*
254 * clear the RTC status register's alarm bit
255 * mask out the lower status bits
256 */
257 rtc_status_reg &= ~0x07;
258 /* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
259 rtc_status_reg |= (SIRFSOC_RTC_AL0);
260 /* Clear the Alarm enable bit */
261 rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
262 }
263
264 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
265
266 spin_unlock(&rtcdrv->lock);
267
268 /* this should wake up any apps polling/waiting on the read
269 * after setting the alarm
270 */
271 events |= RTC_IRQF | RTC_AF;
272 rtc_update_irq(rtcdrv->rtc, 1, events);
273
274 return IRQ_HANDLED;
275}
276
277static const struct of_device_id sirfsoc_rtc_of_match[] = {
278 { .compatible = "sirf,prima2-sysrtc"},
279 {},
280};
281
282const struct regmap_config sysrtc_regmap_config = {
283 .reg_bits = 32,
284 .val_bits = 32,
285 .fast_io = true,
286};
287
288MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
289
290static int sirfsoc_rtc_probe(struct platform_device *pdev)
291{
292 int err;
293 unsigned long rtc_div;
294 struct sirfsoc_rtc_drv *rtcdrv;
295 struct device_node *np = pdev->dev.of_node;
296
297 rtcdrv = devm_kzalloc(&pdev->dev,
298 sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
299 if (rtcdrv == NULL)
300 return -ENOMEM;
301
302 spin_lock_init(&rtcdrv->lock);
303
304 err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
305 if (err) {
306 dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
307 return err;
308 }
309
310 platform_set_drvdata(pdev, rtcdrv);
311
312 /* Register rtc alarm as a wakeup source */
313 device_init_wakeup(&pdev->dev, 1);
314
315 rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev,
316 &sysrtc_regmap_config);
317 if (IS_ERR(rtcdrv->regmap)) {
318 err = PTR_ERR(rtcdrv->regmap);
319 dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
320 err);
321 return err;
322 }
323
324 /*
325 * Set SYS_RTC counter in RTC_HZ HZ Units
326 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
327 * If 16HZ, therefore RTC_DIV = 1023;
328 */
329 rtc_div = ((32768 / RTC_HZ) / 2) - 1;
330 sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
331
332 /* 0x3 -> RTC_CLK */
333 sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
334
335 /* reset SYS RTC ALARM0 */
336 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
337
338 /* reset SYS RTC ALARM1 */
339 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
340
341 /* Restore RTC Overflow From Register After Command Reboot */
342 rtcdrv->overflow_rtc =
343 sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
344
345 rtcdrv->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
346 &sirfsoc_rtc_ops, THIS_MODULE);
347 if (IS_ERR(rtcdrv->rtc)) {
348 err = PTR_ERR(rtcdrv->rtc);
349 dev_err(&pdev->dev, "can't register RTC device\n");
350 return err;
351 }
352
353 rtcdrv->irq = platform_get_irq(pdev, 0);
354 err = devm_request_irq(
355 &pdev->dev,
356 rtcdrv->irq,
357 sirfsoc_rtc_irq_handler,
358 IRQF_SHARED,
359 pdev->name,
360 rtcdrv);
361 if (err) {
362 dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
363 return err;
364 }
365
366 return 0;
367}
368
369static int sirfsoc_rtc_remove(struct platform_device *pdev)
370{
371 device_init_wakeup(&pdev->dev, 0);
372
373 return 0;
374}
375
376#ifdef CONFIG_PM_SLEEP
377static int sirfsoc_rtc_suspend(struct device *dev)
378{
379 struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
380 rtcdrv->overflow_rtc =
381 sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
382
383 rtcdrv->saved_counter =
384 sirfsoc_rtc_readl(rtcdrv, RTC_CN);
385 rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
386 if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
387 rtcdrv->irq_wake = 1;
388
389 return 0;
390}
391
392static int sirfsoc_rtc_resume(struct device *dev)
393{
394 u32 tmp;
395 struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
396
397 /*
398 * if resume from snapshot and the rtc power is lost,
399 * restroe the rtc settings
400 */
401 if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) {
402 u32 rtc_div;
403 /* 0x3 -> RTC_CLK */
404 sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
405 /*
406 * Set SYS_RTC counter in RTC_HZ HZ Units
407 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
408 * If 16HZ, therefore RTC_DIV = 1023;
409 */
410 rtc_div = ((32768 / RTC_HZ) / 2) - 1;
411
412 sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
413
414 /* reset SYS RTC ALARM0 */
415 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
416
417 /* reset SYS RTC ALARM1 */
418 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
419 }
420 rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
421
422 /*
423 * if current counter is small than previous,
424 * it means overflow in sleep
425 */
426 tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
427 if (tmp <= rtcdrv->saved_counter)
428 rtcdrv->overflow_rtc++;
429 /*
430 *PWRC Value Be Changed When Suspend, Restore Overflow
431 * In Memory To Register
432 */
433 sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
434
435 if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
436 disable_irq_wake(rtcdrv->irq);
437 rtcdrv->irq_wake = 0;
438 }
439
440 return 0;
441}
442#endif
443
444static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
445 sirfsoc_rtc_suspend, sirfsoc_rtc_resume);
446
447static struct platform_driver sirfsoc_rtc_driver = {
448 .driver = {
449 .name = "sirfsoc-rtc",
450 .pm = &sirfsoc_rtc_pm_ops,
451 .of_match_table = sirfsoc_rtc_of_match,
452 },
453 .probe = sirfsoc_rtc_probe,
454 .remove = sirfsoc_rtc_remove,
455};
456module_platform_driver(sirfsoc_rtc_driver);
457
458MODULE_DESCRIPTION("SiRF SoC rtc driver");
459MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
460MODULE_LICENSE("GPL v2");
461MODULE_ALIAS("platform:sirfsoc-rtc");