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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Broadcom BCM7038 PWM driver
4 * Author: Florian Fainelli
5 *
6 * Copyright (C) 2015 Broadcom Corporation
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/clk.h>
12#include <linux/export.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/spinlock.h>
21
22#define PWM_CTRL 0x00
23#define CTRL_START BIT(0)
24#define CTRL_OEB BIT(1)
25#define CTRL_FORCE_HIGH BIT(2)
26#define CTRL_OPENDRAIN BIT(3)
27#define CTRL_CHAN_OFFS 4
28
29#define PWM_CTRL2 0x04
30#define CTRL2_OUT_SELECT BIT(0)
31
32#define PWM_CH_SIZE 0x8
33
34#define PWM_CWORD_MSB(ch) (0x08 + ((ch) * PWM_CH_SIZE))
35#define PWM_CWORD_LSB(ch) (0x0c + ((ch) * PWM_CH_SIZE))
36
37/* Number of bits for the CWORD value */
38#define CWORD_BIT_SIZE 16
39
40/*
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
43 */
44#define CONST_VAR_F_MAX 32768
45#define CONST_VAR_F_MIN 1
46
47#define PWM_ON(ch) (0x18 + ((ch) * PWM_CH_SIZE))
48#define PWM_ON_MIN 1
49#define PWM_PERIOD(ch) (0x1c + ((ch) * PWM_CH_SIZE))
50#define PWM_PERIOD_MIN 0
51
52#define PWM_ON_PERIOD_MAX 0xff
53
54struct brcmstb_pwm {
55 void __iomem *base;
56 struct clk *clk;
57 struct pwm_chip chip;
58};
59
60static inline u32 brcmstb_pwm_readl(struct brcmstb_pwm *p,
61 unsigned int offset)
62{
63 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
64 return __raw_readl(p->base + offset);
65 else
66 return readl_relaxed(p->base + offset);
67}
68
69static inline void brcmstb_pwm_writel(struct brcmstb_pwm *p, u32 value,
70 unsigned int offset)
71{
72 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
73 __raw_writel(value, p->base + offset);
74 else
75 writel_relaxed(value, p->base + offset);
76}
77
78static inline struct brcmstb_pwm *to_brcmstb_pwm(struct pwm_chip *chip)
79{
80 return container_of(chip, struct brcmstb_pwm, chip);
81}
82
83/*
84 * Fv is derived from the variable frequency output. The variable frequency
85 * output is configured using this formula:
86 *
87 * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
88 *
89 * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
90 *
91 * The period is: (period + 1) / Fv and "on" time is on / (period + 1)
92 *
93 * The PWM core framework specifies that the "duty_ns" parameter is in fact the
94 * "on" time, so this translates directly into our HW programming here.
95 */
96static int brcmstb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
97 u64 duty_ns, u64 period_ns)
98{
99 struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
100 unsigned long pc, dc, cword = CONST_VAR_F_MAX;
101 unsigned int channel = pwm->hwpwm;
102 u32 value;
103
104 /*
105 * If asking for a duty_ns equal to period_ns, we need to substract
106 * the period value by 1 to make it shorter than the "on" time and
107 * produce a flat 100% duty cycle signal, and max out the "on" time
108 */
109 if (duty_ns == period_ns) {
110 dc = PWM_ON_PERIOD_MAX;
111 pc = PWM_ON_PERIOD_MAX - 1;
112 goto done;
113 }
114
115 while (1) {
116 u64 rate;
117
118 /*
119 * Calculate the base rate from base frequency and current
120 * cword
121 */
122 rate = (u64)clk_get_rate(p->clk) * (u64)cword;
123 rate >>= CWORD_BIT_SIZE;
124
125 pc = mul_u64_u64_div_u64(period_ns, rate, NSEC_PER_SEC);
126 dc = mul_u64_u64_div_u64(duty_ns + 1, rate, NSEC_PER_SEC);
127
128 /*
129 * We can be called with separate duty and period updates,
130 * so do not reject dc == 0 right away
131 */
132 if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))
133 return -EINVAL;
134
135 /* We converged on a calculation */
136 if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)
137 break;
138
139 /*
140 * The cword needs to be a power of 2 for the variable
141 * frequency generator to output a 50% duty cycle variable
142 * frequency which is used as input clock to the fixed
143 * frequency generator.
144 */
145 cword >>= 1;
146
147 /*
148 * Desired periods are too large, we do not have a divider
149 * for them
150 */
151 if (cword < CONST_VAR_F_MIN)
152 return -EINVAL;
153 }
154
155done:
156 /*
157 * Configure the defined "cword" value to have the variable frequency
158 * generator output a base frequency for the constant frequency
159 * generator to derive from.
160 */
161 brcmstb_pwm_writel(p, cword >> 8, PWM_CWORD_MSB(channel));
162 brcmstb_pwm_writel(p, cword & 0xff, PWM_CWORD_LSB(channel));
163
164 /* Select constant frequency signal output */
165 value = brcmstb_pwm_readl(p, PWM_CTRL2);
166 value |= CTRL2_OUT_SELECT << (channel * CTRL_CHAN_OFFS);
167 brcmstb_pwm_writel(p, value, PWM_CTRL2);
168
169 /* Configure on and period value */
170 brcmstb_pwm_writel(p, pc, PWM_PERIOD(channel));
171 brcmstb_pwm_writel(p, dc, PWM_ON(channel));
172
173 return 0;
174}
175
176static inline void brcmstb_pwm_enable_set(struct brcmstb_pwm *p,
177 unsigned int channel, bool enable)
178{
179 unsigned int shift = channel * CTRL_CHAN_OFFS;
180 u32 value;
181
182 value = brcmstb_pwm_readl(p, PWM_CTRL);
183
184 if (enable) {
185 value &= ~(CTRL_OEB << shift);
186 value |= (CTRL_START | CTRL_OPENDRAIN) << shift;
187 } else {
188 value &= ~((CTRL_START | CTRL_OPENDRAIN) << shift);
189 value |= CTRL_OEB << shift;
190 }
191
192 brcmstb_pwm_writel(p, value, PWM_CTRL);
193}
194
195static int brcmstb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
196 const struct pwm_state *state)
197{
198 struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
199 int err;
200
201 if (state->polarity != PWM_POLARITY_NORMAL)
202 return -EINVAL;
203
204 if (!state->enabled) {
205 if (pwm->state.enabled)
206 brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
207
208 return 0;
209 }
210
211 err = brcmstb_pwm_config(chip, pwm, state->duty_cycle, state->period);
212 if (err)
213 return err;
214
215 if (!pwm->state.enabled)
216 brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
217
218 return 0;
219}
220
221static const struct pwm_ops brcmstb_pwm_ops = {
222 .apply = brcmstb_pwm_apply,
223};
224
225static const struct of_device_id brcmstb_pwm_of_match[] = {
226 { .compatible = "brcm,bcm7038-pwm", },
227 { /* sentinel */ }
228};
229MODULE_DEVICE_TABLE(of, brcmstb_pwm_of_match);
230
231static int brcmstb_pwm_probe(struct platform_device *pdev)
232{
233 struct brcmstb_pwm *p;
234 int ret;
235
236 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
237 if (!p)
238 return -ENOMEM;
239
240 p->clk = devm_clk_get_enabled(&pdev->dev, NULL);
241 if (IS_ERR(p->clk))
242 return dev_err_probe(&pdev->dev, PTR_ERR(p->clk),
243 "failed to obtain clock\n");
244
245 platform_set_drvdata(pdev, p);
246
247 p->chip.dev = &pdev->dev;
248 p->chip.ops = &brcmstb_pwm_ops;
249 p->chip.npwm = 2;
250
251 p->base = devm_platform_ioremap_resource(pdev, 0);
252 if (IS_ERR(p->base))
253 return PTR_ERR(p->base);
254
255 ret = devm_pwmchip_add(&pdev->dev, &p->chip);
256 if (ret)
257 return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
258
259 return 0;
260}
261
262static int brcmstb_pwm_suspend(struct device *dev)
263{
264 struct brcmstb_pwm *p = dev_get_drvdata(dev);
265
266 clk_disable_unprepare(p->clk);
267
268 return 0;
269}
270
271static int brcmstb_pwm_resume(struct device *dev)
272{
273 struct brcmstb_pwm *p = dev_get_drvdata(dev);
274
275 return clk_prepare_enable(p->clk);
276}
277
278static DEFINE_SIMPLE_DEV_PM_OPS(brcmstb_pwm_pm_ops, brcmstb_pwm_suspend,
279 brcmstb_pwm_resume);
280
281static struct platform_driver brcmstb_pwm_driver = {
282 .probe = brcmstb_pwm_probe,
283 .driver = {
284 .name = "pwm-brcmstb",
285 .of_match_table = brcmstb_pwm_of_match,
286 .pm = pm_ptr(&brcmstb_pwm_pm_ops),
287 },
288};
289module_platform_driver(brcmstb_pwm_driver);
290
291MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
292MODULE_DESCRIPTION("Broadcom STB PWM driver");
293MODULE_ALIAS("platform:pwm-brcmstb");
294MODULE_LICENSE("GPL");
1/*
2 * Broadcom BCM7038 PWM driver
3 * Author: Florian Fainelli
4 *
5 * Copyright (C) 2015 Broadcom Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/clk.h>
21#include <linux/export.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/platform_device.h>
28#include <linux/pwm.h>
29#include <linux/spinlock.h>
30
31#define PWM_CTRL 0x00
32#define CTRL_START BIT(0)
33#define CTRL_OEB BIT(1)
34#define CTRL_FORCE_HIGH BIT(2)
35#define CTRL_OPENDRAIN BIT(3)
36#define CTRL_CHAN_OFFS 4
37
38#define PWM_CTRL2 0x04
39#define CTRL2_OUT_SELECT BIT(0)
40
41#define PWM_CH_SIZE 0x8
42
43#define PWM_CWORD_MSB(ch) (0x08 + ((ch) * PWM_CH_SIZE))
44#define PWM_CWORD_LSB(ch) (0x0c + ((ch) * PWM_CH_SIZE))
45
46/* Number of bits for the CWORD value */
47#define CWORD_BIT_SIZE 16
48
49/*
50 * Maximum control word value allowed when variable-frequency PWM is used as a
51 * clock for the constant-frequency PMW.
52 */
53#define CONST_VAR_F_MAX 32768
54#define CONST_VAR_F_MIN 1
55
56#define PWM_ON(ch) (0x18 + ((ch) * PWM_CH_SIZE))
57#define PWM_ON_MIN 1
58#define PWM_PERIOD(ch) (0x1c + ((ch) * PWM_CH_SIZE))
59#define PWM_PERIOD_MIN 0
60
61#define PWM_ON_PERIOD_MAX 0xff
62
63struct brcmstb_pwm {
64 void __iomem *base;
65 spinlock_t lock;
66 struct clk *clk;
67 struct pwm_chip chip;
68};
69
70static inline u32 brcmstb_pwm_readl(struct brcmstb_pwm *p,
71 unsigned int offset)
72{
73 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
74 return __raw_readl(p->base + offset);
75 else
76 return readl_relaxed(p->base + offset);
77}
78
79static inline void brcmstb_pwm_writel(struct brcmstb_pwm *p, u32 value,
80 unsigned int offset)
81{
82 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
83 __raw_writel(value, p->base + offset);
84 else
85 writel_relaxed(value, p->base + offset);
86}
87
88static inline struct brcmstb_pwm *to_brcmstb_pwm(struct pwm_chip *chip)
89{
90 return container_of(chip, struct brcmstb_pwm, chip);
91}
92
93/*
94 * Fv is derived from the variable frequency output. The variable frequency
95 * output is configured using this formula:
96 *
97 * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
98 *
99 * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
100 *
101 * The period is: (period + 1) / Fv and "on" time is on / (period + 1)
102 *
103 * The PWM core framework specifies that the "duty_ns" parameter is in fact the
104 * "on" time, so this translates directly into our HW programming here.
105 */
106static int brcmstb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
107 int duty_ns, int period_ns)
108{
109 struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
110 unsigned long pc, dc, cword = CONST_VAR_F_MAX;
111 unsigned int channel = pwm->hwpwm;
112 u32 value;
113
114 /*
115 * If asking for a duty_ns equal to period_ns, we need to substract
116 * the period value by 1 to make it shorter than the "on" time and
117 * produce a flat 100% duty cycle signal, and max out the "on" time
118 */
119 if (duty_ns == period_ns) {
120 dc = PWM_ON_PERIOD_MAX;
121 pc = PWM_ON_PERIOD_MAX - 1;
122 goto done;
123 }
124
125 while (1) {
126 u64 rate, tmp;
127
128 /*
129 * Calculate the base rate from base frequency and current
130 * cword
131 */
132 rate = (u64)clk_get_rate(p->clk) * (u64)cword;
133 do_div(rate, 1 << CWORD_BIT_SIZE);
134
135 tmp = period_ns * rate;
136 do_div(tmp, NSEC_PER_SEC);
137 pc = tmp;
138
139 tmp = (duty_ns + 1) * rate;
140 do_div(tmp, NSEC_PER_SEC);
141 dc = tmp;
142
143 /*
144 * We can be called with separate duty and period updates,
145 * so do not reject dc == 0 right away
146 */
147 if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))
148 return -EINVAL;
149
150 /* We converged on a calculation */
151 if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)
152 break;
153
154 /*
155 * The cword needs to be a power of 2 for the variable
156 * frequency generator to output a 50% duty cycle variable
157 * frequency which is used as input clock to the fixed
158 * frequency generator.
159 */
160 cword >>= 1;
161
162 /*
163 * Desired periods are too large, we do not have a divider
164 * for them
165 */
166 if (cword < CONST_VAR_F_MIN)
167 return -EINVAL;
168 }
169
170done:
171 /*
172 * Configure the defined "cword" value to have the variable frequency
173 * generator output a base frequency for the constant frequency
174 * generator to derive from.
175 */
176 spin_lock(&p->lock);
177 brcmstb_pwm_writel(p, cword >> 8, PWM_CWORD_MSB(channel));
178 brcmstb_pwm_writel(p, cword & 0xff, PWM_CWORD_LSB(channel));
179
180 /* Select constant frequency signal output */
181 value = brcmstb_pwm_readl(p, PWM_CTRL2);
182 value |= CTRL2_OUT_SELECT << (channel * CTRL_CHAN_OFFS);
183 brcmstb_pwm_writel(p, value, PWM_CTRL2);
184
185 /* Configure on and period value */
186 brcmstb_pwm_writel(p, pc, PWM_PERIOD(channel));
187 brcmstb_pwm_writel(p, dc, PWM_ON(channel));
188 spin_unlock(&p->lock);
189
190 return 0;
191}
192
193static inline void brcmstb_pwm_enable_set(struct brcmstb_pwm *p,
194 unsigned int channel, bool enable)
195{
196 unsigned int shift = channel * CTRL_CHAN_OFFS;
197 u32 value;
198
199 spin_lock(&p->lock);
200 value = brcmstb_pwm_readl(p, PWM_CTRL);
201
202 if (enable) {
203 value &= ~(CTRL_OEB << shift);
204 value |= (CTRL_START | CTRL_OPENDRAIN) << shift;
205 } else {
206 value &= ~((CTRL_START | CTRL_OPENDRAIN) << shift);
207 value |= CTRL_OEB << shift;
208 }
209
210 brcmstb_pwm_writel(p, value, PWM_CTRL);
211 spin_unlock(&p->lock);
212}
213
214static int brcmstb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
215{
216 struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
217
218 brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
219
220 return 0;
221}
222
223static void brcmstb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
224{
225 struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
226
227 brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
228}
229
230static const struct pwm_ops brcmstb_pwm_ops = {
231 .config = brcmstb_pwm_config,
232 .enable = brcmstb_pwm_enable,
233 .disable = brcmstb_pwm_disable,
234 .owner = THIS_MODULE,
235};
236
237static const struct of_device_id brcmstb_pwm_of_match[] = {
238 { .compatible = "brcm,bcm7038-pwm", },
239 { /* sentinel */ }
240};
241MODULE_DEVICE_TABLE(of, brcmstb_pwm_of_match);
242
243static int brcmstb_pwm_probe(struct platform_device *pdev)
244{
245 struct brcmstb_pwm *p;
246 struct resource *res;
247 int ret;
248
249 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
250 if (!p)
251 return -ENOMEM;
252
253 spin_lock_init(&p->lock);
254
255 p->clk = devm_clk_get(&pdev->dev, NULL);
256 if (IS_ERR(p->clk)) {
257 dev_err(&pdev->dev, "failed to obtain clock\n");
258 return PTR_ERR(p->clk);
259 }
260
261 ret = clk_prepare_enable(p->clk);
262 if (ret < 0) {
263 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
264 return ret;
265 }
266
267 platform_set_drvdata(pdev, p);
268
269 p->chip.dev = &pdev->dev;
270 p->chip.ops = &brcmstb_pwm_ops;
271 p->chip.base = -1;
272 p->chip.npwm = 2;
273
274 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
275 p->base = devm_ioremap_resource(&pdev->dev, res);
276 if (IS_ERR(p->base)) {
277 ret = PTR_ERR(p->base);
278 goto out_clk;
279 }
280
281 ret = pwmchip_add(&p->chip);
282 if (ret) {
283 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
284 goto out_clk;
285 }
286
287 return 0;
288
289out_clk:
290 clk_disable_unprepare(p->clk);
291 return ret;
292}
293
294static int brcmstb_pwm_remove(struct platform_device *pdev)
295{
296 struct brcmstb_pwm *p = platform_get_drvdata(pdev);
297 int ret;
298
299 ret = pwmchip_remove(&p->chip);
300 clk_disable_unprepare(p->clk);
301
302 return ret;
303}
304
305#ifdef CONFIG_PM_SLEEP
306static int brcmstb_pwm_suspend(struct device *dev)
307{
308 struct brcmstb_pwm *p = dev_get_drvdata(dev);
309
310 clk_disable(p->clk);
311
312 return 0;
313}
314
315static int brcmstb_pwm_resume(struct device *dev)
316{
317 struct brcmstb_pwm *p = dev_get_drvdata(dev);
318
319 clk_enable(p->clk);
320
321 return 0;
322}
323#endif
324
325static SIMPLE_DEV_PM_OPS(brcmstb_pwm_pm_ops, brcmstb_pwm_suspend,
326 brcmstb_pwm_resume);
327
328static struct platform_driver brcmstb_pwm_driver = {
329 .probe = brcmstb_pwm_probe,
330 .remove = brcmstb_pwm_remove,
331 .driver = {
332 .name = "pwm-brcmstb",
333 .of_match_table = brcmstb_pwm_of_match,
334 .pm = &brcmstb_pwm_pm_ops,
335 },
336};
337module_platform_driver(brcmstb_pwm_driver);
338
339MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
340MODULE_DESCRIPTION("Broadcom STB PWM driver");
341MODULE_ALIAS("platform:pwm-brcmstb");
342MODULE_LICENSE("GPL");