1/*
  2 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 and
  6 * only version 2 as published by the Free Software Foundation.
  7 *
  8 * This program is distributed in the hope that it will be useful,
  9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11 * GNU General Public License for more details.
 12 *
 13 */
 14
 15#ifndef UFS_QCOM_PHY_I_H_
 16#define UFS_QCOM_PHY_I_H_
 17
 18#include <linux/module.h>
 19#include <linux/clk.h>
 20#include <linux/regulator/consumer.h>
 21#include <linux/slab.h>
 22#include <linux/phy/phy-qcom-ufs.h>
 23#include <linux/platform_device.h>
 24#include <linux/io.h>
 25#include <linux/delay.h>
 26
 27#define readl_poll_timeout(addr, val, cond, sleep_us, timeout_us) \
 28({ \
 29	ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); \
 30	might_sleep_if(timeout_us); \
 31	for (;;) { \
 32		(val) = readl(addr); \
 33		if (cond) \
 34			break; \
 35		if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { \
 36			(val) = readl(addr); \
 37			break; \
 38		} \
 39		if (sleep_us) \
 40			usleep_range(DIV_ROUND_UP(sleep_us, 4), sleep_us); \
 41	} \
 42	(cond) ? 0 : -ETIMEDOUT; \
 43})
 44
 45#define UFS_QCOM_PHY_CAL_ENTRY(reg, val)	\
 46	{				\
 47		.reg_offset = reg,	\
 48		.cfg_value = val,	\
 49	}
 50
 51#define UFS_QCOM_PHY_NAME_LEN	30
 52
 53enum {
 54	MASK_SERDES_START       = 0x1,
 55	MASK_PCS_READY          = 0x1,
 56};
 57
 58enum {
 59	OFFSET_SERDES_START     = 0x0,
 60};
 61
 62struct ufs_qcom_phy_stored_attributes {
 63	u32 att;
 64	u32 value;
 65};
 66
 67
 68struct ufs_qcom_phy_calibration {
 69	u32 reg_offset;
 70	u32 cfg_value;
 71};
 72
 73struct ufs_qcom_phy_vreg {
 74	const char *name;
 75	struct regulator *reg;
 76	int max_uA;
 77	int min_uV;
 78	int max_uV;
 79	bool enabled;
 80};
 81
 82struct ufs_qcom_phy {
 83	struct list_head list;
 84	struct device *dev;
 85	void __iomem *mmio;
 86	void __iomem *dev_ref_clk_ctrl_mmio;
 87	struct clk *tx_iface_clk;
 88	struct clk *rx_iface_clk;
 89	bool is_iface_clk_enabled;
 90	struct clk *ref_clk_src;
 91	struct clk *ref_clk_parent;
 92	struct clk *ref_clk;
 93	bool is_ref_clk_enabled;
 94	bool is_dev_ref_clk_enabled;
 95	struct ufs_qcom_phy_vreg vdda_pll;
 96	struct ufs_qcom_phy_vreg vdda_phy;
 97	struct ufs_qcom_phy_vreg vddp_ref_clk;
 98	unsigned int quirks;
 99
100	/*
101	* If UFS link is put into Hibern8 and if UFS PHY analog hardware is
102	* power collapsed (by clearing UFS_PHY_POWER_DOWN_CONTROL), Hibern8
103	* exit might fail even after powering on UFS PHY analog hardware.
104	* Enabling this quirk will help to solve above issue by doing
105	* custom PHY settings just before PHY analog power collapse.
106	*/
107	#define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE	BIT(0)
108
109	u8 host_ctrl_rev_major;
110	u16 host_ctrl_rev_minor;
111	u16 host_ctrl_rev_step;
112
113	char name[UFS_QCOM_PHY_NAME_LEN];
114	struct ufs_qcom_phy_calibration *cached_regs;
115	int cached_regs_table_size;
116	bool is_powered_on;
117	bool is_started;
118	struct ufs_qcom_phy_specific_ops *phy_spec_ops;
119
120	enum phy_mode mode;
121};
122
123/**
124 * struct ufs_qcom_phy_specific_ops - set of pointers to functions which have a
125 * specific implementation per phy. Each UFS phy, should implement
126 * those functions according to its spec and requirements
127 * @start_serdes: pointer to a function that starts the serdes
128 * @is_physical_coding_sublayer_ready: pointer to a function that
129 * checks pcs readiness. returns 0 for success and non-zero for error.
130 * @set_tx_lane_enable: pointer to a function that enable tx lanes
131 * @power_control: pointer to a function that controls analog rail of phy
132 * and writes to QSERDES_RX_SIGDET_CNTRL attribute
133 */
134struct ufs_qcom_phy_specific_ops {
135	void (*start_serdes)(struct ufs_qcom_phy *phy);
136	int (*is_physical_coding_sublayer_ready)(struct ufs_qcom_phy *phy);
137	void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val);
138	void (*power_control)(struct ufs_qcom_phy *phy, bool val);
139};
140
141struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy);
142int ufs_qcom_phy_power_on(struct phy *generic_phy);
143int ufs_qcom_phy_power_off(struct phy *generic_phy);
144int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common);
145int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common);
146int ufs_qcom_phy_remove(struct phy *generic_phy,
147		       struct ufs_qcom_phy *ufs_qcom_phy);
148struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
149			struct ufs_qcom_phy *common_cfg,
150			const struct phy_ops *ufs_qcom_phy_gen_ops,
151			struct ufs_qcom_phy_specific_ops *phy_spec_ops);
152int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
153			struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A,
154			struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B,
155			bool is_rate_B);
156#endif