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1// SPDX-License-Identifier: ISC
2/*
3 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
4 * Copyright (c) 2015 The Linux Foundation. All rights reserved.
5 */
6#include <linux/module.h>
7#include <linux/of.h>
8#include <linux/platform_device.h>
9#include <linux/clk.h>
10#include <linux/reset.h>
11#include "core.h"
12#include "debug.h"
13#include "pci.h"
14#include "ahb.h"
15
16static const struct of_device_id ath10k_ahb_of_match[] = {
17 { .compatible = "qcom,ipq4019-wifi",
18 .data = (void *)ATH10K_HW_QCA4019
19 },
20 { }
21};
22
23MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match);
24
25#define QCA4019_SRAM_ADDR 0x000C0000
26#define QCA4019_SRAM_LEN 0x00040000 /* 256 kb */
27
28static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar)
29{
30 return &ath10k_pci_priv(ar)->ahb[0];
31}
32
33static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value)
34{
35 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
36
37 iowrite32(value, ar_ahb->mem + offset);
38}
39
40static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset)
41{
42 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
43
44 return ioread32(ar_ahb->mem + offset);
45}
46
47static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset)
48{
49 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
50
51 return ioread32(ar_ahb->gcc_mem + offset);
52}
53
54static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value)
55{
56 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
57
58 iowrite32(value, ar_ahb->tcsr_mem + offset);
59}
60
61static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset)
62{
63 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
64
65 return ioread32(ar_ahb->tcsr_mem + offset);
66}
67
68static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr)
69{
70 return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
71}
72
73static int ath10k_ahb_get_num_banks(struct ath10k *ar)
74{
75 if (ar->hw_rev == ATH10K_HW_QCA4019)
76 return 1;
77
78 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
79 return 1;
80}
81
82static int ath10k_ahb_clock_init(struct ath10k *ar)
83{
84 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
85 struct device *dev;
86
87 dev = &ar_ahb->pdev->dev;
88
89 ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd");
90 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) {
91 ath10k_err(ar, "failed to get cmd clk: %ld\n",
92 PTR_ERR(ar_ahb->cmd_clk));
93 return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV;
94 }
95
96 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref");
97 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) {
98 ath10k_err(ar, "failed to get ref clk: %ld\n",
99 PTR_ERR(ar_ahb->ref_clk));
100 return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV;
101 }
102
103 ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc");
104 if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) {
105 ath10k_err(ar, "failed to get rtc clk: %ld\n",
106 PTR_ERR(ar_ahb->rtc_clk));
107 return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV;
108 }
109
110 return 0;
111}
112
113static void ath10k_ahb_clock_deinit(struct ath10k *ar)
114{
115 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
116
117 ar_ahb->cmd_clk = NULL;
118 ar_ahb->ref_clk = NULL;
119 ar_ahb->rtc_clk = NULL;
120}
121
122static int ath10k_ahb_clock_enable(struct ath10k *ar)
123{
124 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
125 int ret;
126
127 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) ||
128 IS_ERR_OR_NULL(ar_ahb->ref_clk) ||
129 IS_ERR_OR_NULL(ar_ahb->rtc_clk)) {
130 ath10k_err(ar, "clock(s) is/are not initialized\n");
131 ret = -EIO;
132 goto out;
133 }
134
135 ret = clk_prepare_enable(ar_ahb->cmd_clk);
136 if (ret) {
137 ath10k_err(ar, "failed to enable cmd clk: %d\n", ret);
138 goto out;
139 }
140
141 ret = clk_prepare_enable(ar_ahb->ref_clk);
142 if (ret) {
143 ath10k_err(ar, "failed to enable ref clk: %d\n", ret);
144 goto err_cmd_clk_disable;
145 }
146
147 ret = clk_prepare_enable(ar_ahb->rtc_clk);
148 if (ret) {
149 ath10k_err(ar, "failed to enable rtc clk: %d\n", ret);
150 goto err_ref_clk_disable;
151 }
152
153 return 0;
154
155err_ref_clk_disable:
156 clk_disable_unprepare(ar_ahb->ref_clk);
157
158err_cmd_clk_disable:
159 clk_disable_unprepare(ar_ahb->cmd_clk);
160
161out:
162 return ret;
163}
164
165static void ath10k_ahb_clock_disable(struct ath10k *ar)
166{
167 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
168
169 clk_disable_unprepare(ar_ahb->cmd_clk);
170
171 clk_disable_unprepare(ar_ahb->ref_clk);
172
173 clk_disable_unprepare(ar_ahb->rtc_clk);
174}
175
176static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar)
177{
178 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
179 struct device *dev;
180
181 dev = &ar_ahb->pdev->dev;
182
183 ar_ahb->core_cold_rst = devm_reset_control_get_exclusive(dev,
184 "wifi_core_cold");
185 if (IS_ERR(ar_ahb->core_cold_rst)) {
186 ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n",
187 PTR_ERR(ar_ahb->core_cold_rst));
188 return PTR_ERR(ar_ahb->core_cold_rst);
189 }
190
191 ar_ahb->radio_cold_rst = devm_reset_control_get_exclusive(dev,
192 "wifi_radio_cold");
193 if (IS_ERR(ar_ahb->radio_cold_rst)) {
194 ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n",
195 PTR_ERR(ar_ahb->radio_cold_rst));
196 return PTR_ERR(ar_ahb->radio_cold_rst);
197 }
198
199 ar_ahb->radio_warm_rst = devm_reset_control_get_exclusive(dev,
200 "wifi_radio_warm");
201 if (IS_ERR(ar_ahb->radio_warm_rst)) {
202 ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n",
203 PTR_ERR(ar_ahb->radio_warm_rst));
204 return PTR_ERR(ar_ahb->radio_warm_rst);
205 }
206
207 ar_ahb->radio_srif_rst = devm_reset_control_get_exclusive(dev,
208 "wifi_radio_srif");
209 if (IS_ERR(ar_ahb->radio_srif_rst)) {
210 ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n",
211 PTR_ERR(ar_ahb->radio_srif_rst));
212 return PTR_ERR(ar_ahb->radio_srif_rst);
213 }
214
215 ar_ahb->cpu_init_rst = devm_reset_control_get_exclusive(dev,
216 "wifi_cpu_init");
217 if (IS_ERR(ar_ahb->cpu_init_rst)) {
218 ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n",
219 PTR_ERR(ar_ahb->cpu_init_rst));
220 return PTR_ERR(ar_ahb->cpu_init_rst);
221 }
222
223 return 0;
224}
225
226static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar)
227{
228 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
229
230 ar_ahb->core_cold_rst = NULL;
231 ar_ahb->radio_cold_rst = NULL;
232 ar_ahb->radio_warm_rst = NULL;
233 ar_ahb->radio_srif_rst = NULL;
234 ar_ahb->cpu_init_rst = NULL;
235}
236
237static int ath10k_ahb_release_reset(struct ath10k *ar)
238{
239 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
240 int ret;
241
242 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) ||
243 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) ||
244 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) ||
245 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
246 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
247 return -EINVAL;
248 }
249
250 ret = reset_control_deassert(ar_ahb->radio_cold_rst);
251 if (ret) {
252 ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret);
253 return ret;
254 }
255
256 ret = reset_control_deassert(ar_ahb->radio_warm_rst);
257 if (ret) {
258 ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret);
259 return ret;
260 }
261
262 ret = reset_control_deassert(ar_ahb->radio_srif_rst);
263 if (ret) {
264 ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret);
265 return ret;
266 }
267
268 ret = reset_control_deassert(ar_ahb->cpu_init_rst);
269 if (ret) {
270 ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret);
271 return ret;
272 }
273
274 return 0;
275}
276
277static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg,
278 u32 haltack_reg)
279{
280 unsigned long timeout;
281 u32 val;
282
283 /* Issue halt axi bus request */
284 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
285 val |= AHB_AXI_BUS_HALT_REQ;
286 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
287
288 /* Wait for axi bus halted ack */
289 timeout = jiffies + msecs_to_jiffies(ATH10K_AHB_AXI_BUS_HALT_TIMEOUT);
290 do {
291 val = ath10k_ahb_tcsr_read32(ar, haltack_reg);
292 if (val & AHB_AXI_BUS_HALT_ACK)
293 break;
294
295 mdelay(1);
296 } while (time_before(jiffies, timeout));
297
298 if (!(val & AHB_AXI_BUS_HALT_ACK)) {
299 ath10k_err(ar, "failed to halt axi bus: %d\n", val);
300 return;
301 }
302
303 ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n");
304}
305
306static void ath10k_ahb_halt_chip(struct ath10k *ar)
307{
308 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
309 u32 core_id, glb_cfg_reg, haltreq_reg, haltack_reg;
310 u32 val;
311 int ret;
312
313 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) ||
314 IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) ||
315 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) ||
316 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) ||
317 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
318 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
319 return;
320 }
321
322 core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG);
323
324 switch (core_id) {
325 case 0:
326 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI0_GLB_CFG;
327 haltreq_reg = ATH10K_AHB_TCSR_WCSS0_HALTREQ;
328 haltack_reg = ATH10K_AHB_TCSR_WCSS0_HALTACK;
329 break;
330 case 1:
331 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI1_GLB_CFG;
332 haltreq_reg = ATH10K_AHB_TCSR_WCSS1_HALTREQ;
333 haltack_reg = ATH10K_AHB_TCSR_WCSS1_HALTACK;
334 break;
335 default:
336 ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n",
337 core_id);
338 return;
339 }
340
341 ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg);
342
343 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
344 val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK;
345 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
346
347 ret = reset_control_assert(ar_ahb->core_cold_rst);
348 if (ret)
349 ath10k_err(ar, "failed to assert core cold rst: %d\n", ret);
350 msleep(1);
351
352 ret = reset_control_assert(ar_ahb->radio_cold_rst);
353 if (ret)
354 ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret);
355 msleep(1);
356
357 ret = reset_control_assert(ar_ahb->radio_warm_rst);
358 if (ret)
359 ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret);
360 msleep(1);
361
362 ret = reset_control_assert(ar_ahb->radio_srif_rst);
363 if (ret)
364 ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret);
365 msleep(1);
366
367 ret = reset_control_assert(ar_ahb->cpu_init_rst);
368 if (ret)
369 ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret);
370 msleep(10);
371
372 /* Clear halt req and core clock disable req before
373 * deasserting wifi core reset.
374 */
375 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
376 val &= ~AHB_AXI_BUS_HALT_REQ;
377 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
378
379 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
380 val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK;
381 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
382
383 ret = reset_control_deassert(ar_ahb->core_cold_rst);
384 if (ret)
385 ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret);
386
387 ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id);
388}
389
390static irqreturn_t ath10k_ahb_interrupt_handler(int irq, void *arg)
391{
392 struct ath10k *ar = arg;
393
394 if (!ath10k_pci_irq_pending(ar))
395 return IRQ_NONE;
396
397 ath10k_pci_disable_and_clear_legacy_irq(ar);
398 ath10k_pci_irq_msi_fw_mask(ar);
399 napi_schedule(&ar->napi);
400
401 return IRQ_HANDLED;
402}
403
404static int ath10k_ahb_request_irq_legacy(struct ath10k *ar)
405{
406 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
407 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
408 int ret;
409
410 ret = request_irq(ar_ahb->irq,
411 ath10k_ahb_interrupt_handler,
412 IRQF_SHARED, "ath10k_ahb", ar);
413 if (ret) {
414 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
415 ar_ahb->irq, ret);
416 return ret;
417 }
418 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
419
420 return 0;
421}
422
423static void ath10k_ahb_release_irq_legacy(struct ath10k *ar)
424{
425 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
426
427 free_irq(ar_ahb->irq, ar);
428}
429
430static void ath10k_ahb_irq_disable(struct ath10k *ar)
431{
432 ath10k_ce_disable_interrupts(ar);
433 ath10k_pci_disable_and_clear_legacy_irq(ar);
434}
435
436static int ath10k_ahb_resource_init(struct ath10k *ar)
437{
438 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
439 struct platform_device *pdev;
440 struct resource *res;
441 int ret;
442
443 pdev = ar_ahb->pdev;
444
445 ar_ahb->mem = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
446 if (IS_ERR(ar_ahb->mem)) {
447 ath10k_err(ar, "mem ioremap error\n");
448 ret = PTR_ERR(ar_ahb->mem);
449 goto out;
450 }
451
452 ar_ahb->mem_len = resource_size(res);
453
454 ar_ahb->gcc_mem = ioremap(ATH10K_GCC_REG_BASE,
455 ATH10K_GCC_REG_SIZE);
456 if (!ar_ahb->gcc_mem) {
457 ath10k_err(ar, "gcc mem ioremap error\n");
458 ret = -ENOMEM;
459 goto err_mem_unmap;
460 }
461
462 ar_ahb->tcsr_mem = ioremap(ATH10K_TCSR_REG_BASE,
463 ATH10K_TCSR_REG_SIZE);
464 if (!ar_ahb->tcsr_mem) {
465 ath10k_err(ar, "tcsr mem ioremap error\n");
466 ret = -ENOMEM;
467 goto err_gcc_mem_unmap;
468 }
469
470 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
471 if (ret) {
472 ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret);
473 goto err_tcsr_mem_unmap;
474 }
475
476 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
477 if (ret) {
478 ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n",
479 ret);
480 goto err_tcsr_mem_unmap;
481 }
482
483 ret = ath10k_ahb_clock_init(ar);
484 if (ret)
485 goto err_tcsr_mem_unmap;
486
487 ret = ath10k_ahb_rst_ctrl_init(ar);
488 if (ret)
489 goto err_clock_deinit;
490
491 ar_ahb->irq = platform_get_irq_byname(pdev, "legacy");
492 if (ar_ahb->irq < 0) {
493 ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq);
494 ret = ar_ahb->irq;
495 goto err_clock_deinit;
496 }
497
498 ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq);
499
500 ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n",
501 ar_ahb->mem, ar_ahb->mem_len,
502 ar_ahb->gcc_mem, ar_ahb->tcsr_mem);
503 return 0;
504
505err_clock_deinit:
506 ath10k_ahb_clock_deinit(ar);
507
508err_tcsr_mem_unmap:
509 iounmap(ar_ahb->tcsr_mem);
510
511err_gcc_mem_unmap:
512 ar_ahb->tcsr_mem = NULL;
513 iounmap(ar_ahb->gcc_mem);
514
515err_mem_unmap:
516 ar_ahb->gcc_mem = NULL;
517 devm_iounmap(&pdev->dev, ar_ahb->mem);
518
519out:
520 ar_ahb->mem = NULL;
521 return ret;
522}
523
524static void ath10k_ahb_resource_deinit(struct ath10k *ar)
525{
526 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
527 struct device *dev;
528
529 dev = &ar_ahb->pdev->dev;
530
531 if (ar_ahb->mem)
532 devm_iounmap(dev, ar_ahb->mem);
533
534 if (ar_ahb->gcc_mem)
535 iounmap(ar_ahb->gcc_mem);
536
537 if (ar_ahb->tcsr_mem)
538 iounmap(ar_ahb->tcsr_mem);
539
540 ar_ahb->mem = NULL;
541 ar_ahb->gcc_mem = NULL;
542 ar_ahb->tcsr_mem = NULL;
543
544 ath10k_ahb_clock_deinit(ar);
545 ath10k_ahb_rst_ctrl_deinit(ar);
546}
547
548static int ath10k_ahb_prepare_device(struct ath10k *ar)
549{
550 u32 val;
551 int ret;
552
553 ret = ath10k_ahb_clock_enable(ar);
554 if (ret) {
555 ath10k_err(ar, "failed to enable clocks\n");
556 return ret;
557 }
558
559 /* Clock for the target is supplied from outside of target (ie,
560 * external clock module controlled by the host). Target needs
561 * to know what frequency target cpu is configured which is needed
562 * for target internal use. Read target cpu frequency info from
563 * gcc register and write into target's scratch register where
564 * target expects this information.
565 */
566 val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV);
567 ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val);
568
569 ret = ath10k_ahb_release_reset(ar);
570 if (ret)
571 goto err_clk_disable;
572
573 ath10k_ahb_irq_disable(ar);
574
575 ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY);
576
577 ret = ath10k_pci_wait_for_target_init(ar);
578 if (ret)
579 goto err_halt_chip;
580
581 return 0;
582
583err_halt_chip:
584 ath10k_ahb_halt_chip(ar);
585
586err_clk_disable:
587 ath10k_ahb_clock_disable(ar);
588
589 return ret;
590}
591
592static int ath10k_ahb_chip_reset(struct ath10k *ar)
593{
594 int ret;
595
596 ath10k_ahb_halt_chip(ar);
597 ath10k_ahb_clock_disable(ar);
598
599 ret = ath10k_ahb_prepare_device(ar);
600 if (ret)
601 return ret;
602
603 return 0;
604}
605
606static int ath10k_ahb_wake_target_cpu(struct ath10k *ar)
607{
608 u32 addr, val;
609
610 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
611 val = ath10k_ahb_read32(ar, addr);
612 val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK;
613 ath10k_ahb_write32(ar, addr, val);
614
615 return 0;
616}
617
618static int ath10k_ahb_hif_start(struct ath10k *ar)
619{
620 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n");
621
622 ath10k_core_napi_enable(ar);
623 ath10k_ce_enable_interrupts(ar);
624 ath10k_pci_enable_legacy_irq(ar);
625
626 ath10k_pci_rx_post(ar);
627
628 return 0;
629}
630
631static void ath10k_ahb_hif_stop(struct ath10k *ar)
632{
633 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
634
635 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n");
636
637 ath10k_ahb_irq_disable(ar);
638 synchronize_irq(ar_ahb->irq);
639
640 ath10k_core_napi_sync_disable(ar);
641
642 ath10k_pci_flush(ar);
643}
644
645static int ath10k_ahb_hif_power_up(struct ath10k *ar,
646 enum ath10k_firmware_mode fw_mode)
647{
648 int ret;
649
650 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n");
651
652 ret = ath10k_ahb_chip_reset(ar);
653 if (ret) {
654 ath10k_err(ar, "failed to reset chip: %d\n", ret);
655 goto out;
656 }
657
658 ret = ath10k_pci_init_pipes(ar);
659 if (ret) {
660 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
661 goto out;
662 }
663
664 ret = ath10k_pci_init_config(ar);
665 if (ret) {
666 ath10k_err(ar, "failed to setup init config: %d\n", ret);
667 goto err_ce_deinit;
668 }
669
670 ret = ath10k_ahb_wake_target_cpu(ar);
671 if (ret) {
672 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
673 goto err_ce_deinit;
674 }
675
676 return 0;
677
678err_ce_deinit:
679 ath10k_pci_ce_deinit(ar);
680out:
681 return ret;
682}
683
684static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
685{
686 u32 val = 0, region = addr & 0xfffff;
687
688 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
689
690 if (region >= QCA4019_SRAM_ADDR && region <=
691 (QCA4019_SRAM_ADDR + QCA4019_SRAM_LEN)) {
692 /* SRAM contents for QCA4019 can be directly accessed and
693 * no conversions are required
694 */
695 val |= region;
696 } else {
697 val |= 0x100000 | region;
698 }
699
700 return val;
701}
702
703static const struct ath10k_hif_ops ath10k_ahb_hif_ops = {
704 .tx_sg = ath10k_pci_hif_tx_sg,
705 .diag_read = ath10k_pci_hif_diag_read,
706 .diag_write = ath10k_pci_diag_write_mem,
707 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
708 .start = ath10k_ahb_hif_start,
709 .stop = ath10k_ahb_hif_stop,
710 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
711 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
712 .send_complete_check = ath10k_pci_hif_send_complete_check,
713 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
714 .power_up = ath10k_ahb_hif_power_up,
715 .power_down = ath10k_pci_hif_power_down,
716 .read32 = ath10k_ahb_read32,
717 .write32 = ath10k_ahb_write32,
718};
719
720static const struct ath10k_bus_ops ath10k_ahb_bus_ops = {
721 .read32 = ath10k_ahb_read32,
722 .write32 = ath10k_ahb_write32,
723 .get_num_banks = ath10k_ahb_get_num_banks,
724};
725
726static int ath10k_ahb_probe(struct platform_device *pdev)
727{
728 struct ath10k *ar;
729 struct ath10k_ahb *ar_ahb;
730 struct ath10k_pci *ar_pci;
731 enum ath10k_hw_rev hw_rev;
732 size_t size;
733 int ret;
734 struct ath10k_bus_params bus_params = {};
735
736 hw_rev = (uintptr_t)of_device_get_match_data(&pdev->dev);
737 if (!hw_rev) {
738 dev_err(&pdev->dev, "OF data missing\n");
739 return -EINVAL;
740 }
741
742 size = sizeof(*ar_pci) + sizeof(*ar_ahb);
743 ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB,
744 hw_rev, &ath10k_ahb_hif_ops);
745 if (!ar) {
746 dev_err(&pdev->dev, "failed to allocate core\n");
747 return -ENOMEM;
748 }
749
750 ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n");
751
752 ar_pci = ath10k_pci_priv(ar);
753 ar_ahb = ath10k_ahb_priv(ar);
754
755 ar_ahb->pdev = pdev;
756 platform_set_drvdata(pdev, ar);
757
758 ret = ath10k_ahb_resource_init(ar);
759 if (ret)
760 goto err_core_destroy;
761
762 ar->dev_id = 0;
763 ar_pci->mem = ar_ahb->mem;
764 ar_pci->mem_len = ar_ahb->mem_len;
765 ar_pci->ar = ar;
766 ar_pci->ce.bus_ops = &ath10k_ahb_bus_ops;
767 ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr;
768 ar->ce_priv = &ar_pci->ce;
769
770 ret = ath10k_pci_setup_resource(ar);
771 if (ret) {
772 ath10k_err(ar, "failed to setup resource: %d\n", ret);
773 goto err_resource_deinit;
774 }
775
776 ath10k_pci_init_napi(ar);
777
778 ret = ath10k_ahb_request_irq_legacy(ar);
779 if (ret)
780 goto err_free_pipes;
781
782 ret = ath10k_ahb_prepare_device(ar);
783 if (ret)
784 goto err_free_irq;
785
786 ath10k_pci_ce_deinit(ar);
787
788 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
789 bus_params.chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
790 if (bus_params.chip_id == 0xffffffff) {
791 ath10k_err(ar, "failed to get chip id\n");
792 ret = -ENODEV;
793 goto err_halt_device;
794 }
795
796 ret = ath10k_core_register(ar, &bus_params);
797 if (ret) {
798 ath10k_err(ar, "failed to register driver core: %d\n", ret);
799 goto err_halt_device;
800 }
801
802 return 0;
803
804err_halt_device:
805 ath10k_ahb_halt_chip(ar);
806 ath10k_ahb_clock_disable(ar);
807
808err_free_irq:
809 ath10k_ahb_release_irq_legacy(ar);
810
811err_free_pipes:
812 ath10k_pci_release_resource(ar);
813
814err_resource_deinit:
815 ath10k_ahb_resource_deinit(ar);
816
817err_core_destroy:
818 ath10k_core_destroy(ar);
819
820 return ret;
821}
822
823static void ath10k_ahb_remove(struct platform_device *pdev)
824{
825 struct ath10k *ar = platform_get_drvdata(pdev);
826
827 ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n");
828
829 ath10k_core_unregister(ar);
830 ath10k_ahb_irq_disable(ar);
831 ath10k_ahb_release_irq_legacy(ar);
832 ath10k_pci_release_resource(ar);
833 ath10k_ahb_halt_chip(ar);
834 ath10k_ahb_clock_disable(ar);
835 ath10k_ahb_resource_deinit(ar);
836 ath10k_core_destroy(ar);
837}
838
839static struct platform_driver ath10k_ahb_driver = {
840 .driver = {
841 .name = "ath10k_ahb",
842 .of_match_table = ath10k_ahb_of_match,
843 },
844 .probe = ath10k_ahb_probe,
845 .remove_new = ath10k_ahb_remove,
846};
847
848int ath10k_ahb_init(void)
849{
850 int ret;
851
852 ret = platform_driver_register(&ath10k_ahb_driver);
853 if (ret)
854 printk(KERN_ERR "failed to register ath10k ahb driver: %d\n",
855 ret);
856 return ret;
857}
858
859void ath10k_ahb_exit(void)
860{
861 platform_driver_unregister(&ath10k_ahb_driver);
862}
1/*
2 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
3 * Copyright (c) 2015 The Linux Foundation. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/clk.h>
21#include <linux/reset.h>
22#include "core.h"
23#include "debug.h"
24#include "pci.h"
25#include "ahb.h"
26
27static const struct of_device_id ath10k_ahb_of_match[] = {
28 { .compatible = "qcom,ipq4019-wifi",
29 .data = (void *)ATH10K_HW_QCA4019
30 },
31 { }
32};
33
34MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match);
35
36#define QCA4019_SRAM_ADDR 0x000C0000
37#define QCA4019_SRAM_LEN 0x00040000 /* 256 kb */
38
39static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar)
40{
41 return &((struct ath10k_pci *)ar->drv_priv)->ahb[0];
42}
43
44static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value)
45{
46 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
47
48 iowrite32(value, ar_ahb->mem + offset);
49}
50
51static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset)
52{
53 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
54
55 return ioread32(ar_ahb->mem + offset);
56}
57
58static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset)
59{
60 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
61
62 return ioread32(ar_ahb->gcc_mem + offset);
63}
64
65static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value)
66{
67 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
68
69 iowrite32(value, ar_ahb->tcsr_mem + offset);
70}
71
72static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset)
73{
74 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
75
76 return ioread32(ar_ahb->tcsr_mem + offset);
77}
78
79static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr)
80{
81 return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
82}
83
84static int ath10k_ahb_get_num_banks(struct ath10k *ar)
85{
86 if (ar->hw_rev == ATH10K_HW_QCA4019)
87 return 1;
88
89 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
90 return 1;
91}
92
93static int ath10k_ahb_clock_init(struct ath10k *ar)
94{
95 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
96 struct device *dev;
97
98 dev = &ar_ahb->pdev->dev;
99
100 ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd");
101 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) {
102 ath10k_err(ar, "failed to get cmd clk: %ld\n",
103 PTR_ERR(ar_ahb->cmd_clk));
104 return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV;
105 }
106
107 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref");
108 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) {
109 ath10k_err(ar, "failed to get ref clk: %ld\n",
110 PTR_ERR(ar_ahb->ref_clk));
111 return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV;
112 }
113
114 ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc");
115 if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) {
116 ath10k_err(ar, "failed to get rtc clk: %ld\n",
117 PTR_ERR(ar_ahb->rtc_clk));
118 return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV;
119 }
120
121 return 0;
122}
123
124static void ath10k_ahb_clock_deinit(struct ath10k *ar)
125{
126 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
127
128 ar_ahb->cmd_clk = NULL;
129 ar_ahb->ref_clk = NULL;
130 ar_ahb->rtc_clk = NULL;
131}
132
133static int ath10k_ahb_clock_enable(struct ath10k *ar)
134{
135 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
136 struct device *dev;
137 int ret;
138
139 dev = &ar_ahb->pdev->dev;
140
141 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) ||
142 IS_ERR_OR_NULL(ar_ahb->ref_clk) ||
143 IS_ERR_OR_NULL(ar_ahb->rtc_clk)) {
144 ath10k_err(ar, "clock(s) is/are not initialized\n");
145 ret = -EIO;
146 goto out;
147 }
148
149 ret = clk_prepare_enable(ar_ahb->cmd_clk);
150 if (ret) {
151 ath10k_err(ar, "failed to enable cmd clk: %d\n", ret);
152 goto out;
153 }
154
155 ret = clk_prepare_enable(ar_ahb->ref_clk);
156 if (ret) {
157 ath10k_err(ar, "failed to enable ref clk: %d\n", ret);
158 goto err_cmd_clk_disable;
159 }
160
161 ret = clk_prepare_enable(ar_ahb->rtc_clk);
162 if (ret) {
163 ath10k_err(ar, "failed to enable rtc clk: %d\n", ret);
164 goto err_ref_clk_disable;
165 }
166
167 return 0;
168
169err_ref_clk_disable:
170 clk_disable_unprepare(ar_ahb->ref_clk);
171
172err_cmd_clk_disable:
173 clk_disable_unprepare(ar_ahb->cmd_clk);
174
175out:
176 return ret;
177}
178
179static void ath10k_ahb_clock_disable(struct ath10k *ar)
180{
181 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
182
183 if (!IS_ERR_OR_NULL(ar_ahb->cmd_clk))
184 clk_disable_unprepare(ar_ahb->cmd_clk);
185
186 if (!IS_ERR_OR_NULL(ar_ahb->ref_clk))
187 clk_disable_unprepare(ar_ahb->ref_clk);
188
189 if (!IS_ERR_OR_NULL(ar_ahb->rtc_clk))
190 clk_disable_unprepare(ar_ahb->rtc_clk);
191}
192
193static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar)
194{
195 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
196 struct device *dev;
197
198 dev = &ar_ahb->pdev->dev;
199
200 ar_ahb->core_cold_rst = devm_reset_control_get_exclusive(dev,
201 "wifi_core_cold");
202 if (IS_ERR(ar_ahb->core_cold_rst)) {
203 ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n",
204 PTR_ERR(ar_ahb->core_cold_rst));
205 return PTR_ERR(ar_ahb->core_cold_rst);
206 }
207
208 ar_ahb->radio_cold_rst = devm_reset_control_get_exclusive(dev,
209 "wifi_radio_cold");
210 if (IS_ERR(ar_ahb->radio_cold_rst)) {
211 ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n",
212 PTR_ERR(ar_ahb->radio_cold_rst));
213 return PTR_ERR(ar_ahb->radio_cold_rst);
214 }
215
216 ar_ahb->radio_warm_rst = devm_reset_control_get_exclusive(dev,
217 "wifi_radio_warm");
218 if (IS_ERR(ar_ahb->radio_warm_rst)) {
219 ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n",
220 PTR_ERR(ar_ahb->radio_warm_rst));
221 return PTR_ERR(ar_ahb->radio_warm_rst);
222 }
223
224 ar_ahb->radio_srif_rst = devm_reset_control_get_exclusive(dev,
225 "wifi_radio_srif");
226 if (IS_ERR(ar_ahb->radio_srif_rst)) {
227 ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n",
228 PTR_ERR(ar_ahb->radio_srif_rst));
229 return PTR_ERR(ar_ahb->radio_srif_rst);
230 }
231
232 ar_ahb->cpu_init_rst = devm_reset_control_get_exclusive(dev,
233 "wifi_cpu_init");
234 if (IS_ERR(ar_ahb->cpu_init_rst)) {
235 ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n",
236 PTR_ERR(ar_ahb->cpu_init_rst));
237 return PTR_ERR(ar_ahb->cpu_init_rst);
238 }
239
240 return 0;
241}
242
243static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar)
244{
245 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
246
247 ar_ahb->core_cold_rst = NULL;
248 ar_ahb->radio_cold_rst = NULL;
249 ar_ahb->radio_warm_rst = NULL;
250 ar_ahb->radio_srif_rst = NULL;
251 ar_ahb->cpu_init_rst = NULL;
252}
253
254static int ath10k_ahb_release_reset(struct ath10k *ar)
255{
256 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
257 int ret;
258
259 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) ||
260 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) ||
261 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) ||
262 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
263 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
264 return -EINVAL;
265 }
266
267 ret = reset_control_deassert(ar_ahb->radio_cold_rst);
268 if (ret) {
269 ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret);
270 return ret;
271 }
272
273 ret = reset_control_deassert(ar_ahb->radio_warm_rst);
274 if (ret) {
275 ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret);
276 return ret;
277 }
278
279 ret = reset_control_deassert(ar_ahb->radio_srif_rst);
280 if (ret) {
281 ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret);
282 return ret;
283 }
284
285 ret = reset_control_deassert(ar_ahb->cpu_init_rst);
286 if (ret) {
287 ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret);
288 return ret;
289 }
290
291 return 0;
292}
293
294static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg,
295 u32 haltack_reg)
296{
297 unsigned long timeout;
298 u32 val;
299
300 /* Issue halt axi bus request */
301 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
302 val |= AHB_AXI_BUS_HALT_REQ;
303 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
304
305 /* Wait for axi bus halted ack */
306 timeout = jiffies + msecs_to_jiffies(ATH10K_AHB_AXI_BUS_HALT_TIMEOUT);
307 do {
308 val = ath10k_ahb_tcsr_read32(ar, haltack_reg);
309 if (val & AHB_AXI_BUS_HALT_ACK)
310 break;
311
312 mdelay(1);
313 } while (time_before(jiffies, timeout));
314
315 if (!(val & AHB_AXI_BUS_HALT_ACK)) {
316 ath10k_err(ar, "failed to halt axi bus: %d\n", val);
317 return;
318 }
319
320 ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n");
321}
322
323static void ath10k_ahb_halt_chip(struct ath10k *ar)
324{
325 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
326 u32 core_id, glb_cfg_reg, haltreq_reg, haltack_reg;
327 u32 val;
328 int ret;
329
330 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) ||
331 IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) ||
332 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) ||
333 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) ||
334 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
335 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
336 return;
337 }
338
339 core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG);
340
341 switch (core_id) {
342 case 0:
343 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI0_GLB_CFG;
344 haltreq_reg = ATH10K_AHB_TCSR_WCSS0_HALTREQ;
345 haltack_reg = ATH10K_AHB_TCSR_WCSS0_HALTACK;
346 break;
347 case 1:
348 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI1_GLB_CFG;
349 haltreq_reg = ATH10K_AHB_TCSR_WCSS1_HALTREQ;
350 haltack_reg = ATH10K_AHB_TCSR_WCSS1_HALTACK;
351 break;
352 default:
353 ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n",
354 core_id);
355 return;
356 }
357
358 ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg);
359
360 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
361 val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK;
362 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
363
364 ret = reset_control_assert(ar_ahb->core_cold_rst);
365 if (ret)
366 ath10k_err(ar, "failed to assert core cold rst: %d\n", ret);
367 msleep(1);
368
369 ret = reset_control_assert(ar_ahb->radio_cold_rst);
370 if (ret)
371 ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret);
372 msleep(1);
373
374 ret = reset_control_assert(ar_ahb->radio_warm_rst);
375 if (ret)
376 ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret);
377 msleep(1);
378
379 ret = reset_control_assert(ar_ahb->radio_srif_rst);
380 if (ret)
381 ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret);
382 msleep(1);
383
384 ret = reset_control_assert(ar_ahb->cpu_init_rst);
385 if (ret)
386 ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret);
387 msleep(10);
388
389 /* Clear halt req and core clock disable req before
390 * deasserting wifi core reset.
391 */
392 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
393 val &= ~AHB_AXI_BUS_HALT_REQ;
394 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
395
396 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
397 val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK;
398 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
399
400 ret = reset_control_deassert(ar_ahb->core_cold_rst);
401 if (ret)
402 ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret);
403
404 ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id);
405}
406
407static irqreturn_t ath10k_ahb_interrupt_handler(int irq, void *arg)
408{
409 struct ath10k *ar = arg;
410
411 if (!ath10k_pci_irq_pending(ar))
412 return IRQ_NONE;
413
414 ath10k_pci_disable_and_clear_legacy_irq(ar);
415 ath10k_pci_irq_msi_fw_mask(ar);
416 napi_schedule(&ar->napi);
417
418 return IRQ_HANDLED;
419}
420
421static int ath10k_ahb_request_irq_legacy(struct ath10k *ar)
422{
423 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
424 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
425 int ret;
426
427 ret = request_irq(ar_ahb->irq,
428 ath10k_ahb_interrupt_handler,
429 IRQF_SHARED, "ath10k_ahb", ar);
430 if (ret) {
431 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
432 ar_ahb->irq, ret);
433 return ret;
434 }
435 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
436
437 return 0;
438}
439
440static void ath10k_ahb_release_irq_legacy(struct ath10k *ar)
441{
442 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
443
444 free_irq(ar_ahb->irq, ar);
445}
446
447static void ath10k_ahb_irq_disable(struct ath10k *ar)
448{
449 ath10k_ce_disable_interrupts(ar);
450 ath10k_pci_disable_and_clear_legacy_irq(ar);
451}
452
453static int ath10k_ahb_resource_init(struct ath10k *ar)
454{
455 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
456 struct platform_device *pdev;
457 struct device *dev;
458 struct resource *res;
459 int ret;
460
461 pdev = ar_ahb->pdev;
462 dev = &pdev->dev;
463
464 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
465 if (!res) {
466 ath10k_err(ar, "failed to get memory resource\n");
467 ret = -ENXIO;
468 goto out;
469 }
470
471 ar_ahb->mem = devm_ioremap_resource(&pdev->dev, res);
472 if (IS_ERR(ar_ahb->mem)) {
473 ath10k_err(ar, "mem ioremap error\n");
474 ret = PTR_ERR(ar_ahb->mem);
475 goto out;
476 }
477
478 ar_ahb->mem_len = resource_size(res);
479
480 ar_ahb->gcc_mem = ioremap_nocache(ATH10K_GCC_REG_BASE,
481 ATH10K_GCC_REG_SIZE);
482 if (!ar_ahb->gcc_mem) {
483 ath10k_err(ar, "gcc mem ioremap error\n");
484 ret = -ENOMEM;
485 goto err_mem_unmap;
486 }
487
488 ar_ahb->tcsr_mem = ioremap_nocache(ATH10K_TCSR_REG_BASE,
489 ATH10K_TCSR_REG_SIZE);
490 if (!ar_ahb->tcsr_mem) {
491 ath10k_err(ar, "tcsr mem ioremap error\n");
492 ret = -ENOMEM;
493 goto err_gcc_mem_unmap;
494 }
495
496 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
497 if (ret) {
498 ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret);
499 goto err_tcsr_mem_unmap;
500 }
501
502 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
503 if (ret) {
504 ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n",
505 ret);
506 goto err_tcsr_mem_unmap;
507 }
508
509 ret = ath10k_ahb_clock_init(ar);
510 if (ret)
511 goto err_tcsr_mem_unmap;
512
513 ret = ath10k_ahb_rst_ctrl_init(ar);
514 if (ret)
515 goto err_clock_deinit;
516
517 ar_ahb->irq = platform_get_irq_byname(pdev, "legacy");
518 if (ar_ahb->irq < 0) {
519 ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq);
520 ret = ar_ahb->irq;
521 goto err_clock_deinit;
522 }
523
524 ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq);
525
526 ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n",
527 ar_ahb->mem, ar_ahb->mem_len,
528 ar_ahb->gcc_mem, ar_ahb->tcsr_mem);
529 return 0;
530
531err_clock_deinit:
532 ath10k_ahb_clock_deinit(ar);
533
534err_tcsr_mem_unmap:
535 iounmap(ar_ahb->tcsr_mem);
536
537err_gcc_mem_unmap:
538 ar_ahb->tcsr_mem = NULL;
539 iounmap(ar_ahb->gcc_mem);
540
541err_mem_unmap:
542 ar_ahb->gcc_mem = NULL;
543 devm_iounmap(&pdev->dev, ar_ahb->mem);
544
545out:
546 ar_ahb->mem = NULL;
547 return ret;
548}
549
550static void ath10k_ahb_resource_deinit(struct ath10k *ar)
551{
552 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
553 struct device *dev;
554
555 dev = &ar_ahb->pdev->dev;
556
557 if (ar_ahb->mem)
558 devm_iounmap(dev, ar_ahb->mem);
559
560 if (ar_ahb->gcc_mem)
561 iounmap(ar_ahb->gcc_mem);
562
563 if (ar_ahb->tcsr_mem)
564 iounmap(ar_ahb->tcsr_mem);
565
566 ar_ahb->mem = NULL;
567 ar_ahb->gcc_mem = NULL;
568 ar_ahb->tcsr_mem = NULL;
569
570 ath10k_ahb_clock_deinit(ar);
571 ath10k_ahb_rst_ctrl_deinit(ar);
572}
573
574static int ath10k_ahb_prepare_device(struct ath10k *ar)
575{
576 u32 val;
577 int ret;
578
579 ret = ath10k_ahb_clock_enable(ar);
580 if (ret) {
581 ath10k_err(ar, "failed to enable clocks\n");
582 return ret;
583 }
584
585 /* Clock for the target is supplied from outside of target (ie,
586 * external clock module controlled by the host). Target needs
587 * to know what frequency target cpu is configured which is needed
588 * for target internal use. Read target cpu frequency info from
589 * gcc register and write into target's scratch register where
590 * target expects this information.
591 */
592 val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV);
593 ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val);
594
595 ret = ath10k_ahb_release_reset(ar);
596 if (ret)
597 goto err_clk_disable;
598
599 ath10k_ahb_irq_disable(ar);
600
601 ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY);
602
603 ret = ath10k_pci_wait_for_target_init(ar);
604 if (ret)
605 goto err_halt_chip;
606
607 return 0;
608
609err_halt_chip:
610 ath10k_ahb_halt_chip(ar);
611
612err_clk_disable:
613 ath10k_ahb_clock_disable(ar);
614
615 return ret;
616}
617
618static int ath10k_ahb_chip_reset(struct ath10k *ar)
619{
620 int ret;
621
622 ath10k_ahb_halt_chip(ar);
623 ath10k_ahb_clock_disable(ar);
624
625 ret = ath10k_ahb_prepare_device(ar);
626 if (ret)
627 return ret;
628
629 return 0;
630}
631
632static int ath10k_ahb_wake_target_cpu(struct ath10k *ar)
633{
634 u32 addr, val;
635
636 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
637 val = ath10k_ahb_read32(ar, addr);
638 val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK;
639 ath10k_ahb_write32(ar, addr, val);
640
641 return 0;
642}
643
644static int ath10k_ahb_hif_start(struct ath10k *ar)
645{
646 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n");
647
648 napi_enable(&ar->napi);
649 ath10k_ce_enable_interrupts(ar);
650 ath10k_pci_enable_legacy_irq(ar);
651
652 ath10k_pci_rx_post(ar);
653
654 return 0;
655}
656
657static void ath10k_ahb_hif_stop(struct ath10k *ar)
658{
659 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
660
661 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n");
662
663 ath10k_ahb_irq_disable(ar);
664 synchronize_irq(ar_ahb->irq);
665
666 ath10k_pci_flush(ar);
667
668 napi_synchronize(&ar->napi);
669 napi_disable(&ar->napi);
670}
671
672static int ath10k_ahb_hif_power_up(struct ath10k *ar)
673{
674 int ret;
675
676 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n");
677
678 ret = ath10k_ahb_chip_reset(ar);
679 if (ret) {
680 ath10k_err(ar, "failed to reset chip: %d\n", ret);
681 goto out;
682 }
683
684 ret = ath10k_pci_init_pipes(ar);
685 if (ret) {
686 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
687 goto out;
688 }
689
690 ret = ath10k_pci_init_config(ar);
691 if (ret) {
692 ath10k_err(ar, "failed to setup init config: %d\n", ret);
693 goto err_ce_deinit;
694 }
695
696 ret = ath10k_ahb_wake_target_cpu(ar);
697 if (ret) {
698 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
699 goto err_ce_deinit;
700 }
701
702 return 0;
703
704err_ce_deinit:
705 ath10k_pci_ce_deinit(ar);
706out:
707 return ret;
708}
709
710static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
711{
712 u32 val = 0, region = addr & 0xfffff;
713
714 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
715
716 if (region >= QCA4019_SRAM_ADDR && region <=
717 (QCA4019_SRAM_ADDR + QCA4019_SRAM_LEN)) {
718 /* SRAM contents for QCA4019 can be directly accessed and
719 * no conversions are required
720 */
721 val |= region;
722 } else {
723 val |= 0x100000 | region;
724 }
725
726 return val;
727}
728
729static const struct ath10k_hif_ops ath10k_ahb_hif_ops = {
730 .tx_sg = ath10k_pci_hif_tx_sg,
731 .diag_read = ath10k_pci_hif_diag_read,
732 .diag_write = ath10k_pci_diag_write_mem,
733 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
734 .start = ath10k_ahb_hif_start,
735 .stop = ath10k_ahb_hif_stop,
736 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
737 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
738 .send_complete_check = ath10k_pci_hif_send_complete_check,
739 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
740 .power_up = ath10k_ahb_hif_power_up,
741 .power_down = ath10k_pci_hif_power_down,
742 .read32 = ath10k_ahb_read32,
743 .write32 = ath10k_ahb_write32,
744};
745
746static const struct ath10k_bus_ops ath10k_ahb_bus_ops = {
747 .read32 = ath10k_ahb_read32,
748 .write32 = ath10k_ahb_write32,
749 .get_num_banks = ath10k_ahb_get_num_banks,
750};
751
752static int ath10k_ahb_probe(struct platform_device *pdev)
753{
754 struct ath10k *ar;
755 struct ath10k_ahb *ar_ahb;
756 struct ath10k_pci *ar_pci;
757 const struct of_device_id *of_id;
758 enum ath10k_hw_rev hw_rev;
759 size_t size;
760 int ret;
761 u32 chip_id;
762
763 of_id = of_match_device(ath10k_ahb_of_match, &pdev->dev);
764 if (!of_id) {
765 dev_err(&pdev->dev, "failed to find matching device tree id\n");
766 return -EINVAL;
767 }
768
769 hw_rev = (enum ath10k_hw_rev)of_id->data;
770
771 size = sizeof(*ar_pci) + sizeof(*ar_ahb);
772 ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB,
773 hw_rev, &ath10k_ahb_hif_ops);
774 if (!ar) {
775 dev_err(&pdev->dev, "failed to allocate core\n");
776 return -ENOMEM;
777 }
778
779 ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n");
780
781 ar_pci = ath10k_pci_priv(ar);
782 ar_ahb = ath10k_ahb_priv(ar);
783
784 ar_ahb->pdev = pdev;
785 platform_set_drvdata(pdev, ar);
786
787 ret = ath10k_ahb_resource_init(ar);
788 if (ret)
789 goto err_core_destroy;
790
791 ar->dev_id = 0;
792 ar_pci->mem = ar_ahb->mem;
793 ar_pci->mem_len = ar_ahb->mem_len;
794 ar_pci->ar = ar;
795 ar_pci->ce.bus_ops = &ath10k_ahb_bus_ops;
796 ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr;
797 ar->ce_priv = &ar_pci->ce;
798
799 ret = ath10k_pci_setup_resource(ar);
800 if (ret) {
801 ath10k_err(ar, "failed to setup resource: %d\n", ret);
802 goto err_resource_deinit;
803 }
804
805 ath10k_pci_init_napi(ar);
806
807 ret = ath10k_ahb_request_irq_legacy(ar);
808 if (ret)
809 goto err_free_pipes;
810
811 ret = ath10k_ahb_prepare_device(ar);
812 if (ret)
813 goto err_free_irq;
814
815 ath10k_pci_ce_deinit(ar);
816
817 chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
818 if (chip_id == 0xffffffff) {
819 ath10k_err(ar, "failed to get chip id\n");
820 ret = -ENODEV;
821 goto err_halt_device;
822 }
823
824 ret = ath10k_core_register(ar, chip_id);
825 if (ret) {
826 ath10k_err(ar, "failed to register driver core: %d\n", ret);
827 goto err_halt_device;
828 }
829
830 return 0;
831
832err_halt_device:
833 ath10k_ahb_halt_chip(ar);
834 ath10k_ahb_clock_disable(ar);
835
836err_free_irq:
837 ath10k_ahb_release_irq_legacy(ar);
838
839err_free_pipes:
840 ath10k_pci_free_pipes(ar);
841
842err_resource_deinit:
843 ath10k_ahb_resource_deinit(ar);
844
845err_core_destroy:
846 ath10k_core_destroy(ar);
847 platform_set_drvdata(pdev, NULL);
848
849 return ret;
850}
851
852static int ath10k_ahb_remove(struct platform_device *pdev)
853{
854 struct ath10k *ar = platform_get_drvdata(pdev);
855 struct ath10k_ahb *ar_ahb;
856
857 if (!ar)
858 return -EINVAL;
859
860 ar_ahb = ath10k_ahb_priv(ar);
861
862 if (!ar_ahb)
863 return -EINVAL;
864
865 ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n");
866
867 ath10k_core_unregister(ar);
868 ath10k_ahb_irq_disable(ar);
869 ath10k_ahb_release_irq_legacy(ar);
870 ath10k_pci_release_resource(ar);
871 ath10k_ahb_halt_chip(ar);
872 ath10k_ahb_clock_disable(ar);
873 ath10k_ahb_resource_deinit(ar);
874 ath10k_core_destroy(ar);
875
876 platform_set_drvdata(pdev, NULL);
877
878 return 0;
879}
880
881static struct platform_driver ath10k_ahb_driver = {
882 .driver = {
883 .name = "ath10k_ahb",
884 .of_match_table = ath10k_ahb_of_match,
885 },
886 .probe = ath10k_ahb_probe,
887 .remove = ath10k_ahb_remove,
888};
889
890int ath10k_ahb_init(void)
891{
892 int ret;
893
894 ret = platform_driver_register(&ath10k_ahb_driver);
895 if (ret)
896 printk(KERN_ERR "failed to register ath10k ahb driver: %d\n",
897 ret);
898 return ret;
899}
900
901void ath10k_ahb_exit(void)
902{
903 platform_driver_unregister(&ath10k_ahb_driver);
904}