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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * drivers/net/ethernet/ibm/emac/mal.c
4 *
5 * Memory Access Layer (MAL) support
6 *
7 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
8 * <benh@kernel.crashing.org>
9 *
10 * Based on the arch/ppc version of the driver:
11 *
12 * Copyright (c) 2004, 2005 Zultys Technologies.
13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14 *
15 * Based on original work by
16 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
17 * David Gibson <hermes@gibson.dropbear.id.au>,
18 *
19 * Armin Kuster <akuster@mvista.com>
20 * Copyright 2002 MontaVista Softare Inc.
21 */
22
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/of.h>
26#include <linux/of_irq.h>
27#include <linux/platform_device.h>
28
29#include "core.h"
30#include <asm/dcr-regs.h>
31
32static int mal_count;
33
34int mal_register_commac(struct mal_instance *mal, struct mal_commac *commac)
35{
36 unsigned long flags;
37
38 spin_lock_irqsave(&mal->lock, flags);
39
40 MAL_DBG(mal, "reg(%08x, %08x)" NL,
41 commac->tx_chan_mask, commac->rx_chan_mask);
42
43 /* Don't let multiple commacs claim the same channel(s) */
44 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
45 (mal->rx_chan_mask & commac->rx_chan_mask)) {
46 spin_unlock_irqrestore(&mal->lock, flags);
47 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
48 mal->index);
49 return -EBUSY;
50 }
51
52 if (list_empty(&mal->list))
53 napi_enable(&mal->napi);
54 mal->tx_chan_mask |= commac->tx_chan_mask;
55 mal->rx_chan_mask |= commac->rx_chan_mask;
56 list_add(&commac->list, &mal->list);
57
58 spin_unlock_irqrestore(&mal->lock, flags);
59
60 return 0;
61}
62
63void mal_unregister_commac(struct mal_instance *mal,
64 struct mal_commac *commac)
65{
66 unsigned long flags;
67
68 spin_lock_irqsave(&mal->lock, flags);
69
70 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
71 commac->tx_chan_mask, commac->rx_chan_mask);
72
73 mal->tx_chan_mask &= ~commac->tx_chan_mask;
74 mal->rx_chan_mask &= ~commac->rx_chan_mask;
75 list_del_init(&commac->list);
76 if (list_empty(&mal->list))
77 napi_disable(&mal->napi);
78
79 spin_unlock_irqrestore(&mal->lock, flags);
80}
81
82int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
83{
84 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
85 size > MAL_MAX_RX_SIZE);
86
87 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
88
89 if (size & 0xf) {
90 printk(KERN_WARNING
91 "mal%d: incorrect RX size %lu for the channel %d\n",
92 mal->index, size, channel);
93 return -EINVAL;
94 }
95
96 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
97 return 0;
98}
99
100int mal_tx_bd_offset(struct mal_instance *mal, int channel)
101{
102 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
103
104 return channel * NUM_TX_BUFF;
105}
106
107int mal_rx_bd_offset(struct mal_instance *mal, int channel)
108{
109 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
110 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
111}
112
113void mal_enable_tx_channel(struct mal_instance *mal, int channel)
114{
115 unsigned long flags;
116
117 spin_lock_irqsave(&mal->lock, flags);
118
119 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
120
121 set_mal_dcrn(mal, MAL_TXCASR,
122 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
123
124 spin_unlock_irqrestore(&mal->lock, flags);
125}
126
127void mal_disable_tx_channel(struct mal_instance *mal, int channel)
128{
129 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
130
131 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
132}
133
134void mal_enable_rx_channel(struct mal_instance *mal, int channel)
135{
136 unsigned long flags;
137
138 /*
139 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
140 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value
141 * for the bitmask
142 */
143 if (!(channel % 8))
144 channel >>= 3;
145
146 spin_lock_irqsave(&mal->lock, flags);
147
148 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
149
150 set_mal_dcrn(mal, MAL_RXCASR,
151 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
152
153 spin_unlock_irqrestore(&mal->lock, flags);
154}
155
156void mal_disable_rx_channel(struct mal_instance *mal, int channel)
157{
158 /*
159 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
160 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value
161 * for the bitmask
162 */
163 if (!(channel % 8))
164 channel >>= 3;
165
166 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
167
168 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
169}
170
171void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
172{
173 unsigned long flags;
174
175 spin_lock_irqsave(&mal->lock, flags);
176
177 MAL_DBG(mal, "poll_add(%p)" NL, commac);
178
179 /* starts disabled */
180 set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
181
182 list_add_tail(&commac->poll_list, &mal->poll_list);
183
184 spin_unlock_irqrestore(&mal->lock, flags);
185}
186
187void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
188{
189 unsigned long flags;
190
191 spin_lock_irqsave(&mal->lock, flags);
192
193 MAL_DBG(mal, "poll_del(%p)" NL, commac);
194
195 list_del(&commac->poll_list);
196
197 spin_unlock_irqrestore(&mal->lock, flags);
198}
199
200/* synchronized by mal_poll() */
201static inline void mal_enable_eob_irq(struct mal_instance *mal)
202{
203 MAL_DBG2(mal, "enable_irq" NL);
204
205 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
206 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
207}
208
209/* synchronized by NAPI state */
210static inline void mal_disable_eob_irq(struct mal_instance *mal)
211{
212 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
213 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
214
215 MAL_DBG2(mal, "disable_irq" NL);
216}
217
218static irqreturn_t mal_serr(int irq, void *dev_instance)
219{
220 struct mal_instance *mal = dev_instance;
221
222 u32 esr = get_mal_dcrn(mal, MAL_ESR);
223
224 /* Clear the error status register */
225 set_mal_dcrn(mal, MAL_ESR, esr);
226
227 MAL_DBG(mal, "SERR %08x" NL, esr);
228
229 if (esr & MAL_ESR_EVB) {
230 if (esr & MAL_ESR_DE) {
231 /* We ignore Descriptor error,
232 * TXDE or RXDE interrupt will be generated anyway.
233 */
234 return IRQ_HANDLED;
235 }
236
237 if (esr & MAL_ESR_PEIN) {
238 /* PLB error, it's probably buggy hardware or
239 * incorrect physical address in BD (i.e. bug)
240 */
241 if (net_ratelimit())
242 printk(KERN_ERR
243 "mal%d: system error, "
244 "PLB (ESR = 0x%08x)\n",
245 mal->index, esr);
246 return IRQ_HANDLED;
247 }
248
249 /* OPB error, it's probably buggy hardware or incorrect
250 * EBC setup
251 */
252 if (net_ratelimit())
253 printk(KERN_ERR
254 "mal%d: system error, OPB (ESR = 0x%08x)\n",
255 mal->index, esr);
256 }
257 return IRQ_HANDLED;
258}
259
260static inline void mal_schedule_poll(struct mal_instance *mal)
261{
262 if (likely(napi_schedule_prep(&mal->napi))) {
263 MAL_DBG2(mal, "schedule_poll" NL);
264 spin_lock(&mal->lock);
265 mal_disable_eob_irq(mal);
266 spin_unlock(&mal->lock);
267 __napi_schedule(&mal->napi);
268 } else
269 MAL_DBG2(mal, "already in poll" NL);
270}
271
272static irqreturn_t mal_txeob(int irq, void *dev_instance)
273{
274 struct mal_instance *mal = dev_instance;
275
276 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
277
278 MAL_DBG2(mal, "txeob %08x" NL, r);
279
280 mal_schedule_poll(mal);
281 set_mal_dcrn(mal, MAL_TXEOBISR, r);
282
283#ifdef CONFIG_PPC_DCR_NATIVE
284 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
285 mtdcri(SDR0, DCRN_SDR_ICINTSTAT,
286 (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICTX));
287#endif
288
289 return IRQ_HANDLED;
290}
291
292static irqreturn_t mal_rxeob(int irq, void *dev_instance)
293{
294 struct mal_instance *mal = dev_instance;
295
296 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
297
298 MAL_DBG2(mal, "rxeob %08x" NL, r);
299
300 mal_schedule_poll(mal);
301 set_mal_dcrn(mal, MAL_RXEOBISR, r);
302
303#ifdef CONFIG_PPC_DCR_NATIVE
304 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
305 mtdcri(SDR0, DCRN_SDR_ICINTSTAT,
306 (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICRX));
307#endif
308
309 return IRQ_HANDLED;
310}
311
312static irqreturn_t mal_txde(int irq, void *dev_instance)
313{
314 struct mal_instance *mal = dev_instance;
315
316 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
317 set_mal_dcrn(mal, MAL_TXDEIR, deir);
318
319 MAL_DBG(mal, "txde %08x" NL, deir);
320
321 if (net_ratelimit())
322 printk(KERN_ERR
323 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
324 mal->index, deir);
325
326 return IRQ_HANDLED;
327}
328
329static irqreturn_t mal_rxde(int irq, void *dev_instance)
330{
331 struct mal_instance *mal = dev_instance;
332 struct list_head *l;
333
334 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
335
336 MAL_DBG(mal, "rxde %08x" NL, deir);
337
338 list_for_each(l, &mal->list) {
339 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
340 if (deir & mc->rx_chan_mask) {
341 set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags);
342 mc->ops->rxde(mc->dev);
343 }
344 }
345
346 mal_schedule_poll(mal);
347 set_mal_dcrn(mal, MAL_RXDEIR, deir);
348
349 return IRQ_HANDLED;
350}
351
352static irqreturn_t mal_int(int irq, void *dev_instance)
353{
354 struct mal_instance *mal = dev_instance;
355 u32 esr = get_mal_dcrn(mal, MAL_ESR);
356
357 if (esr & MAL_ESR_EVB) {
358 /* descriptor error */
359 if (esr & MAL_ESR_DE) {
360 if (esr & MAL_ESR_CIDT)
361 return mal_rxde(irq, dev_instance);
362 else
363 return mal_txde(irq, dev_instance);
364 } else { /* SERR */
365 return mal_serr(irq, dev_instance);
366 }
367 }
368 return IRQ_HANDLED;
369}
370
371void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
372{
373 /* Spinlock-type semantics: only one caller disable poll at a time */
374 while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags))
375 msleep(1);
376
377 /* Synchronize with the MAL NAPI poller */
378 napi_synchronize(&mal->napi);
379}
380
381void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
382{
383 smp_wmb();
384 clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
385
386 /* Feels better to trigger a poll here to catch up with events that
387 * may have happened on this channel while disabled. It will most
388 * probably be delayed until the next interrupt but that's mostly a
389 * non-issue in the context where this is called.
390 */
391 napi_schedule(&mal->napi);
392}
393
394static int mal_poll(struct napi_struct *napi, int budget)
395{
396 struct mal_instance *mal = container_of(napi, struct mal_instance, napi);
397 struct list_head *l;
398 int received = 0;
399 unsigned long flags;
400
401 MAL_DBG2(mal, "poll(%d)" NL, budget);
402
403 /* Process TX skbs */
404 list_for_each(l, &mal->poll_list) {
405 struct mal_commac *mc =
406 list_entry(l, struct mal_commac, poll_list);
407 mc->ops->poll_tx(mc->dev);
408 }
409
410 /* Process RX skbs.
411 *
412 * We _might_ need something more smart here to enforce polling
413 * fairness.
414 */
415 list_for_each(l, &mal->poll_list) {
416 struct mal_commac *mc =
417 list_entry(l, struct mal_commac, poll_list);
418 int n;
419 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
420 continue;
421 n = mc->ops->poll_rx(mc->dev, budget - received);
422 if (n) {
423 received += n;
424 if (received >= budget)
425 return budget;
426 }
427 }
428
429 if (napi_complete_done(napi, received)) {
430 /* We need to disable IRQs to protect from RXDE IRQ here */
431 spin_lock_irqsave(&mal->lock, flags);
432 mal_enable_eob_irq(mal);
433 spin_unlock_irqrestore(&mal->lock, flags);
434 }
435
436 /* Check for "rotting" packet(s) */
437 list_for_each(l, &mal->poll_list) {
438 struct mal_commac *mc =
439 list_entry(l, struct mal_commac, poll_list);
440 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
441 continue;
442 if (unlikely(mc->ops->peek_rx(mc->dev) ||
443 test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) {
444 MAL_DBG2(mal, "rotting packet" NL);
445 if (!napi_schedule(napi))
446 goto more_work;
447
448 spin_lock_irqsave(&mal->lock, flags);
449 mal_disable_eob_irq(mal);
450 spin_unlock_irqrestore(&mal->lock, flags);
451 }
452 mc->ops->poll_tx(mc->dev);
453 }
454
455 more_work:
456 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received);
457 return received;
458}
459
460static void mal_reset(struct mal_instance *mal)
461{
462 int n = 10;
463
464 MAL_DBG(mal, "reset" NL);
465
466 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
467
468 /* Wait for reset to complete (1 system clock) */
469 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
470 --n;
471
472 if (unlikely(!n))
473 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
474}
475
476int mal_get_regs_len(struct mal_instance *mal)
477{
478 return sizeof(struct emac_ethtool_regs_subhdr) +
479 sizeof(struct mal_regs);
480}
481
482void *mal_dump_regs(struct mal_instance *mal, void *buf)
483{
484 struct emac_ethtool_regs_subhdr *hdr = buf;
485 struct mal_regs *regs = (struct mal_regs *)(hdr + 1);
486 int i;
487
488 hdr->version = mal->version;
489 hdr->index = mal->index;
490
491 regs->tx_count = mal->num_tx_chans;
492 regs->rx_count = mal->num_rx_chans;
493
494 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
495 regs->esr = get_mal_dcrn(mal, MAL_ESR);
496 regs->ier = get_mal_dcrn(mal, MAL_IER);
497 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
498 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
499 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
500 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
501 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
502 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
503 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
504 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
505
506 for (i = 0; i < regs->tx_count; ++i)
507 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
508
509 for (i = 0; i < regs->rx_count; ++i) {
510 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
511 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
512 }
513 return regs + 1;
514}
515
516static int mal_probe(struct platform_device *ofdev)
517{
518 struct mal_instance *mal;
519 int err = 0, i, bd_size;
520 int index = mal_count++;
521 unsigned int dcr_base;
522 const u32 *prop;
523 u32 cfg;
524 unsigned long irqflags;
525 irq_handler_t hdlr_serr, hdlr_txde, hdlr_rxde;
526
527 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
528 if (!mal)
529 return -ENOMEM;
530
531 mal->index = index;
532 mal->ofdev = ofdev;
533 mal->version = of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal2") ? 2 : 1;
534
535 MAL_DBG(mal, "probe" NL);
536
537 prop = of_get_property(ofdev->dev.of_node, "num-tx-chans", NULL);
538 if (prop == NULL) {
539 printk(KERN_ERR
540 "mal%d: can't find MAL num-tx-chans property!\n",
541 index);
542 err = -ENODEV;
543 goto fail;
544 }
545 mal->num_tx_chans = prop[0];
546
547 prop = of_get_property(ofdev->dev.of_node, "num-rx-chans", NULL);
548 if (prop == NULL) {
549 printk(KERN_ERR
550 "mal%d: can't find MAL num-rx-chans property!\n",
551 index);
552 err = -ENODEV;
553 goto fail;
554 }
555 mal->num_rx_chans = prop[0];
556
557 dcr_base = dcr_resource_start(ofdev->dev.of_node, 0);
558 if (dcr_base == 0) {
559 printk(KERN_ERR
560 "mal%d: can't find DCR resource!\n", index);
561 err = -ENODEV;
562 goto fail;
563 }
564 mal->dcr_host = dcr_map(ofdev->dev.of_node, dcr_base, 0x100);
565 if (!DCR_MAP_OK(mal->dcr_host)) {
566 printk(KERN_ERR
567 "mal%d: failed to map DCRs !\n", index);
568 err = -ENODEV;
569 goto fail;
570 }
571
572 if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-405ez")) {
573#if defined(CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT) && \
574 defined(CONFIG_IBM_EMAC_MAL_COMMON_ERR)
575 mal->features |= (MAL_FTR_CLEAR_ICINTSTAT |
576 MAL_FTR_COMMON_ERR_INT);
577#else
578 printk(KERN_ERR "%pOF: Support for 405EZ not enabled!\n",
579 ofdev->dev.of_node);
580 err = -ENODEV;
581 goto fail;
582#endif
583 }
584
585 mal->txeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
586 mal->rxeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
587 mal->serr_irq = irq_of_parse_and_map(ofdev->dev.of_node, 2);
588
589 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
590 mal->txde_irq = mal->rxde_irq = mal->serr_irq;
591 } else {
592 mal->txde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 3);
593 mal->rxde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 4);
594 }
595
596 if (!mal->txeob_irq || !mal->rxeob_irq || !mal->serr_irq ||
597 !mal->txde_irq || !mal->rxde_irq) {
598 printk(KERN_ERR
599 "mal%d: failed to map interrupts !\n", index);
600 err = -ENODEV;
601 goto fail_unmap;
602 }
603
604 INIT_LIST_HEAD(&mal->poll_list);
605 INIT_LIST_HEAD(&mal->list);
606 spin_lock_init(&mal->lock);
607
608 init_dummy_netdev(&mal->dummy_dev);
609
610 netif_napi_add_weight(&mal->dummy_dev, &mal->napi, mal_poll,
611 CONFIG_IBM_EMAC_POLL_WEIGHT);
612
613 /* Load power-on reset defaults */
614 mal_reset(mal);
615
616 /* Set the MAL configuration register */
617 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
618 cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA;
619
620 /* Current Axon is not happy with priority being non-0, it can
621 * deadlock, fix it up here
622 */
623 if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-axon"))
624 cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10);
625
626 /* Apply configuration */
627 set_mal_dcrn(mal, MAL_CFG, cfg);
628
629 /* Allocate space for BD rings */
630 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
631 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
632
633 bd_size = sizeof(struct mal_descriptor) *
634 (NUM_TX_BUFF * mal->num_tx_chans +
635 NUM_RX_BUFF * mal->num_rx_chans);
636 mal->bd_virt = dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
637 GFP_KERNEL);
638 if (mal->bd_virt == NULL) {
639 err = -ENOMEM;
640 goto fail_unmap;
641 }
642
643 for (i = 0; i < mal->num_tx_chans; ++i)
644 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
645 sizeof(struct mal_descriptor) *
646 mal_tx_bd_offset(mal, i));
647
648 for (i = 0; i < mal->num_rx_chans; ++i)
649 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
650 sizeof(struct mal_descriptor) *
651 mal_rx_bd_offset(mal, i));
652
653 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
654 irqflags = IRQF_SHARED;
655 hdlr_serr = hdlr_txde = hdlr_rxde = mal_int;
656 } else {
657 irqflags = 0;
658 hdlr_serr = mal_serr;
659 hdlr_txde = mal_txde;
660 hdlr_rxde = mal_rxde;
661 }
662
663 err = request_irq(mal->serr_irq, hdlr_serr, irqflags, "MAL SERR", mal);
664 if (err)
665 goto fail2;
666 err = request_irq(mal->txde_irq, hdlr_txde, irqflags, "MAL TX DE", mal);
667 if (err)
668 goto fail3;
669 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
670 if (err)
671 goto fail4;
672 err = request_irq(mal->rxde_irq, hdlr_rxde, irqflags, "MAL RX DE", mal);
673 if (err)
674 goto fail5;
675 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
676 if (err)
677 goto fail6;
678
679 /* Enable all MAL SERR interrupt sources */
680 set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS);
681
682 /* Enable EOB interrupt */
683 mal_enable_eob_irq(mal);
684
685 printk(KERN_INFO
686 "MAL v%d %pOF, %d TX channels, %d RX channels\n",
687 mal->version, ofdev->dev.of_node,
688 mal->num_tx_chans, mal->num_rx_chans);
689
690 /* Advertise this instance to the rest of the world */
691 wmb();
692 platform_set_drvdata(ofdev, mal);
693
694 return 0;
695
696 fail6:
697 free_irq(mal->rxde_irq, mal);
698 fail5:
699 free_irq(mal->txeob_irq, mal);
700 fail4:
701 free_irq(mal->txde_irq, mal);
702 fail3:
703 free_irq(mal->serr_irq, mal);
704 fail2:
705 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
706 fail_unmap:
707 dcr_unmap(mal->dcr_host, 0x100);
708 fail:
709 kfree(mal);
710
711 return err;
712}
713
714static void mal_remove(struct platform_device *ofdev)
715{
716 struct mal_instance *mal = platform_get_drvdata(ofdev);
717
718 MAL_DBG(mal, "remove" NL);
719
720 /* Synchronize with scheduled polling */
721 napi_disable(&mal->napi);
722
723 if (!list_empty(&mal->list))
724 /* This is *very* bad */
725 WARN(1, KERN_EMERG
726 "mal%d: commac list is not empty on remove!\n",
727 mal->index);
728
729 free_irq(mal->serr_irq, mal);
730 free_irq(mal->txde_irq, mal);
731 free_irq(mal->txeob_irq, mal);
732 free_irq(mal->rxde_irq, mal);
733 free_irq(mal->rxeob_irq, mal);
734
735 mal_reset(mal);
736
737 dma_free_coherent(&ofdev->dev,
738 sizeof(struct mal_descriptor) *
739 (NUM_TX_BUFF * mal->num_tx_chans +
740 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
741 mal->bd_dma);
742 kfree(mal);
743}
744
745static const struct of_device_id mal_platform_match[] =
746{
747 {
748 .compatible = "ibm,mcmal",
749 },
750 {
751 .compatible = "ibm,mcmal2",
752 },
753 /* Backward compat */
754 {
755 .type = "mcmal-dma",
756 .compatible = "ibm,mcmal",
757 },
758 {
759 .type = "mcmal-dma",
760 .compatible = "ibm,mcmal2",
761 },
762 {},
763};
764
765static struct platform_driver mal_of_driver = {
766 .driver = {
767 .name = "mcmal",
768 .of_match_table = mal_platform_match,
769 },
770 .probe = mal_probe,
771 .remove_new = mal_remove,
772};
773
774int __init mal_init(void)
775{
776 return platform_driver_register(&mal_of_driver);
777}
778
779void mal_exit(void)
780{
781 platform_driver_unregister(&mal_of_driver);
782}
1/*
2 * drivers/net/ethernet/ibm/emac/mal.c
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7 * <benh@kernel.crashing.org>
8 *
9 * Based on the arch/ppc version of the driver:
10 *
11 * Copyright (c) 2004, 2005 Zultys Technologies.
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 *
14 * Based on original work by
15 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
16 * David Gibson <hermes@gibson.dropbear.id.au>,
17 *
18 * Armin Kuster <akuster@mvista.com>
19 * Copyright 2002 MontaVista Softare Inc.
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
25 *
26 */
27
28#include <linux/delay.h>
29#include <linux/slab.h>
30#include <linux/of_irq.h>
31
32#include "core.h"
33#include <asm/dcr-regs.h>
34
35static int mal_count;
36
37int mal_register_commac(struct mal_instance *mal, struct mal_commac *commac)
38{
39 unsigned long flags;
40
41 spin_lock_irqsave(&mal->lock, flags);
42
43 MAL_DBG(mal, "reg(%08x, %08x)" NL,
44 commac->tx_chan_mask, commac->rx_chan_mask);
45
46 /* Don't let multiple commacs claim the same channel(s) */
47 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
48 (mal->rx_chan_mask & commac->rx_chan_mask)) {
49 spin_unlock_irqrestore(&mal->lock, flags);
50 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
51 mal->index);
52 return -EBUSY;
53 }
54
55 if (list_empty(&mal->list))
56 napi_enable(&mal->napi);
57 mal->tx_chan_mask |= commac->tx_chan_mask;
58 mal->rx_chan_mask |= commac->rx_chan_mask;
59 list_add(&commac->list, &mal->list);
60
61 spin_unlock_irqrestore(&mal->lock, flags);
62
63 return 0;
64}
65
66void mal_unregister_commac(struct mal_instance *mal,
67 struct mal_commac *commac)
68{
69 unsigned long flags;
70
71 spin_lock_irqsave(&mal->lock, flags);
72
73 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
74 commac->tx_chan_mask, commac->rx_chan_mask);
75
76 mal->tx_chan_mask &= ~commac->tx_chan_mask;
77 mal->rx_chan_mask &= ~commac->rx_chan_mask;
78 list_del_init(&commac->list);
79 if (list_empty(&mal->list))
80 napi_disable(&mal->napi);
81
82 spin_unlock_irqrestore(&mal->lock, flags);
83}
84
85int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
86{
87 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
88 size > MAL_MAX_RX_SIZE);
89
90 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
91
92 if (size & 0xf) {
93 printk(KERN_WARNING
94 "mal%d: incorrect RX size %lu for the channel %d\n",
95 mal->index, size, channel);
96 return -EINVAL;
97 }
98
99 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
100 return 0;
101}
102
103int mal_tx_bd_offset(struct mal_instance *mal, int channel)
104{
105 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
106
107 return channel * NUM_TX_BUFF;
108}
109
110int mal_rx_bd_offset(struct mal_instance *mal, int channel)
111{
112 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
113 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
114}
115
116void mal_enable_tx_channel(struct mal_instance *mal, int channel)
117{
118 unsigned long flags;
119
120 spin_lock_irqsave(&mal->lock, flags);
121
122 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
123
124 set_mal_dcrn(mal, MAL_TXCASR,
125 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
126
127 spin_unlock_irqrestore(&mal->lock, flags);
128}
129
130void mal_disable_tx_channel(struct mal_instance *mal, int channel)
131{
132 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
133
134 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
135}
136
137void mal_enable_rx_channel(struct mal_instance *mal, int channel)
138{
139 unsigned long flags;
140
141 /*
142 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
143 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value
144 * for the bitmask
145 */
146 if (!(channel % 8))
147 channel >>= 3;
148
149 spin_lock_irqsave(&mal->lock, flags);
150
151 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
152
153 set_mal_dcrn(mal, MAL_RXCASR,
154 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
155
156 spin_unlock_irqrestore(&mal->lock, flags);
157}
158
159void mal_disable_rx_channel(struct mal_instance *mal, int channel)
160{
161 /*
162 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
163 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value
164 * for the bitmask
165 */
166 if (!(channel % 8))
167 channel >>= 3;
168
169 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
170
171 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
172}
173
174void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
175{
176 unsigned long flags;
177
178 spin_lock_irqsave(&mal->lock, flags);
179
180 MAL_DBG(mal, "poll_add(%p)" NL, commac);
181
182 /* starts disabled */
183 set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
184
185 list_add_tail(&commac->poll_list, &mal->poll_list);
186
187 spin_unlock_irqrestore(&mal->lock, flags);
188}
189
190void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
191{
192 unsigned long flags;
193
194 spin_lock_irqsave(&mal->lock, flags);
195
196 MAL_DBG(mal, "poll_del(%p)" NL, commac);
197
198 list_del(&commac->poll_list);
199
200 spin_unlock_irqrestore(&mal->lock, flags);
201}
202
203/* synchronized by mal_poll() */
204static inline void mal_enable_eob_irq(struct mal_instance *mal)
205{
206 MAL_DBG2(mal, "enable_irq" NL);
207
208 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
209 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
210}
211
212/* synchronized by NAPI state */
213static inline void mal_disable_eob_irq(struct mal_instance *mal)
214{
215 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
216 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
217
218 MAL_DBG2(mal, "disable_irq" NL);
219}
220
221static irqreturn_t mal_serr(int irq, void *dev_instance)
222{
223 struct mal_instance *mal = dev_instance;
224
225 u32 esr = get_mal_dcrn(mal, MAL_ESR);
226
227 /* Clear the error status register */
228 set_mal_dcrn(mal, MAL_ESR, esr);
229
230 MAL_DBG(mal, "SERR %08x" NL, esr);
231
232 if (esr & MAL_ESR_EVB) {
233 if (esr & MAL_ESR_DE) {
234 /* We ignore Descriptor error,
235 * TXDE or RXDE interrupt will be generated anyway.
236 */
237 return IRQ_HANDLED;
238 }
239
240 if (esr & MAL_ESR_PEIN) {
241 /* PLB error, it's probably buggy hardware or
242 * incorrect physical address in BD (i.e. bug)
243 */
244 if (net_ratelimit())
245 printk(KERN_ERR
246 "mal%d: system error, "
247 "PLB (ESR = 0x%08x)\n",
248 mal->index, esr);
249 return IRQ_HANDLED;
250 }
251
252 /* OPB error, it's probably buggy hardware or incorrect
253 * EBC setup
254 */
255 if (net_ratelimit())
256 printk(KERN_ERR
257 "mal%d: system error, OPB (ESR = 0x%08x)\n",
258 mal->index, esr);
259 }
260 return IRQ_HANDLED;
261}
262
263static inline void mal_schedule_poll(struct mal_instance *mal)
264{
265 if (likely(napi_schedule_prep(&mal->napi))) {
266 MAL_DBG2(mal, "schedule_poll" NL);
267 spin_lock(&mal->lock);
268 mal_disable_eob_irq(mal);
269 spin_unlock(&mal->lock);
270 __napi_schedule(&mal->napi);
271 } else
272 MAL_DBG2(mal, "already in poll" NL);
273}
274
275static irqreturn_t mal_txeob(int irq, void *dev_instance)
276{
277 struct mal_instance *mal = dev_instance;
278
279 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
280
281 MAL_DBG2(mal, "txeob %08x" NL, r);
282
283 mal_schedule_poll(mal);
284 set_mal_dcrn(mal, MAL_TXEOBISR, r);
285
286#ifdef CONFIG_PPC_DCR_NATIVE
287 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
288 mtdcri(SDR0, DCRN_SDR_ICINTSTAT,
289 (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICTX));
290#endif
291
292 return IRQ_HANDLED;
293}
294
295static irqreturn_t mal_rxeob(int irq, void *dev_instance)
296{
297 struct mal_instance *mal = dev_instance;
298
299 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
300
301 MAL_DBG2(mal, "rxeob %08x" NL, r);
302
303 mal_schedule_poll(mal);
304 set_mal_dcrn(mal, MAL_RXEOBISR, r);
305
306#ifdef CONFIG_PPC_DCR_NATIVE
307 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
308 mtdcri(SDR0, DCRN_SDR_ICINTSTAT,
309 (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICRX));
310#endif
311
312 return IRQ_HANDLED;
313}
314
315static irqreturn_t mal_txde(int irq, void *dev_instance)
316{
317 struct mal_instance *mal = dev_instance;
318
319 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
320 set_mal_dcrn(mal, MAL_TXDEIR, deir);
321
322 MAL_DBG(mal, "txde %08x" NL, deir);
323
324 if (net_ratelimit())
325 printk(KERN_ERR
326 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
327 mal->index, deir);
328
329 return IRQ_HANDLED;
330}
331
332static irqreturn_t mal_rxde(int irq, void *dev_instance)
333{
334 struct mal_instance *mal = dev_instance;
335 struct list_head *l;
336
337 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
338
339 MAL_DBG(mal, "rxde %08x" NL, deir);
340
341 list_for_each(l, &mal->list) {
342 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
343 if (deir & mc->rx_chan_mask) {
344 set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags);
345 mc->ops->rxde(mc->dev);
346 }
347 }
348
349 mal_schedule_poll(mal);
350 set_mal_dcrn(mal, MAL_RXDEIR, deir);
351
352 return IRQ_HANDLED;
353}
354
355static irqreturn_t mal_int(int irq, void *dev_instance)
356{
357 struct mal_instance *mal = dev_instance;
358 u32 esr = get_mal_dcrn(mal, MAL_ESR);
359
360 if (esr & MAL_ESR_EVB) {
361 /* descriptor error */
362 if (esr & MAL_ESR_DE) {
363 if (esr & MAL_ESR_CIDT)
364 return mal_rxde(irq, dev_instance);
365 else
366 return mal_txde(irq, dev_instance);
367 } else { /* SERR */
368 return mal_serr(irq, dev_instance);
369 }
370 }
371 return IRQ_HANDLED;
372}
373
374void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
375{
376 /* Spinlock-type semantics: only one caller disable poll at a time */
377 while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags))
378 msleep(1);
379
380 /* Synchronize with the MAL NAPI poller */
381 napi_synchronize(&mal->napi);
382}
383
384void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
385{
386 smp_wmb();
387 clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
388
389 /* Feels better to trigger a poll here to catch up with events that
390 * may have happened on this channel while disabled. It will most
391 * probably be delayed until the next interrupt but that's mostly a
392 * non-issue in the context where this is called.
393 */
394 napi_schedule(&mal->napi);
395}
396
397static int mal_poll(struct napi_struct *napi, int budget)
398{
399 struct mal_instance *mal = container_of(napi, struct mal_instance, napi);
400 struct list_head *l;
401 int received = 0;
402 unsigned long flags;
403
404 MAL_DBG2(mal, "poll(%d)" NL, budget);
405
406 /* Process TX skbs */
407 list_for_each(l, &mal->poll_list) {
408 struct mal_commac *mc =
409 list_entry(l, struct mal_commac, poll_list);
410 mc->ops->poll_tx(mc->dev);
411 }
412
413 /* Process RX skbs.
414 *
415 * We _might_ need something more smart here to enforce polling
416 * fairness.
417 */
418 list_for_each(l, &mal->poll_list) {
419 struct mal_commac *mc =
420 list_entry(l, struct mal_commac, poll_list);
421 int n;
422 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
423 continue;
424 n = mc->ops->poll_rx(mc->dev, budget - received);
425 if (n) {
426 received += n;
427 if (received >= budget)
428 return budget;
429 }
430 }
431
432 if (napi_complete_done(napi, received)) {
433 /* We need to disable IRQs to protect from RXDE IRQ here */
434 spin_lock_irqsave(&mal->lock, flags);
435 mal_enable_eob_irq(mal);
436 spin_unlock_irqrestore(&mal->lock, flags);
437 }
438
439 /* Check for "rotting" packet(s) */
440 list_for_each(l, &mal->poll_list) {
441 struct mal_commac *mc =
442 list_entry(l, struct mal_commac, poll_list);
443 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
444 continue;
445 if (unlikely(mc->ops->peek_rx(mc->dev) ||
446 test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) {
447 MAL_DBG2(mal, "rotting packet" NL);
448 if (!napi_reschedule(napi))
449 goto more_work;
450
451 spin_lock_irqsave(&mal->lock, flags);
452 mal_disable_eob_irq(mal);
453 spin_unlock_irqrestore(&mal->lock, flags);
454 }
455 mc->ops->poll_tx(mc->dev);
456 }
457
458 more_work:
459 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received);
460 return received;
461}
462
463static void mal_reset(struct mal_instance *mal)
464{
465 int n = 10;
466
467 MAL_DBG(mal, "reset" NL);
468
469 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
470
471 /* Wait for reset to complete (1 system clock) */
472 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
473 --n;
474
475 if (unlikely(!n))
476 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
477}
478
479int mal_get_regs_len(struct mal_instance *mal)
480{
481 return sizeof(struct emac_ethtool_regs_subhdr) +
482 sizeof(struct mal_regs);
483}
484
485void *mal_dump_regs(struct mal_instance *mal, void *buf)
486{
487 struct emac_ethtool_regs_subhdr *hdr = buf;
488 struct mal_regs *regs = (struct mal_regs *)(hdr + 1);
489 int i;
490
491 hdr->version = mal->version;
492 hdr->index = mal->index;
493
494 regs->tx_count = mal->num_tx_chans;
495 regs->rx_count = mal->num_rx_chans;
496
497 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
498 regs->esr = get_mal_dcrn(mal, MAL_ESR);
499 regs->ier = get_mal_dcrn(mal, MAL_IER);
500 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
501 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
502 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
503 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
504 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
505 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
506 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
507 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
508
509 for (i = 0; i < regs->tx_count; ++i)
510 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
511
512 for (i = 0; i < regs->rx_count; ++i) {
513 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
514 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
515 }
516 return regs + 1;
517}
518
519static int mal_probe(struct platform_device *ofdev)
520{
521 struct mal_instance *mal;
522 int err = 0, i, bd_size;
523 int index = mal_count++;
524 unsigned int dcr_base;
525 const u32 *prop;
526 u32 cfg;
527 unsigned long irqflags;
528 irq_handler_t hdlr_serr, hdlr_txde, hdlr_rxde;
529
530 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
531 if (!mal)
532 return -ENOMEM;
533
534 mal->index = index;
535 mal->ofdev = ofdev;
536 mal->version = of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal2") ? 2 : 1;
537
538 MAL_DBG(mal, "probe" NL);
539
540 prop = of_get_property(ofdev->dev.of_node, "num-tx-chans", NULL);
541 if (prop == NULL) {
542 printk(KERN_ERR
543 "mal%d: can't find MAL num-tx-chans property!\n",
544 index);
545 err = -ENODEV;
546 goto fail;
547 }
548 mal->num_tx_chans = prop[0];
549
550 prop = of_get_property(ofdev->dev.of_node, "num-rx-chans", NULL);
551 if (prop == NULL) {
552 printk(KERN_ERR
553 "mal%d: can't find MAL num-rx-chans property!\n",
554 index);
555 err = -ENODEV;
556 goto fail;
557 }
558 mal->num_rx_chans = prop[0];
559
560 dcr_base = dcr_resource_start(ofdev->dev.of_node, 0);
561 if (dcr_base == 0) {
562 printk(KERN_ERR
563 "mal%d: can't find DCR resource!\n", index);
564 err = -ENODEV;
565 goto fail;
566 }
567 mal->dcr_host = dcr_map(ofdev->dev.of_node, dcr_base, 0x100);
568 if (!DCR_MAP_OK(mal->dcr_host)) {
569 printk(KERN_ERR
570 "mal%d: failed to map DCRs !\n", index);
571 err = -ENODEV;
572 goto fail;
573 }
574
575 if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-405ez")) {
576#if defined(CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT) && \
577 defined(CONFIG_IBM_EMAC_MAL_COMMON_ERR)
578 mal->features |= (MAL_FTR_CLEAR_ICINTSTAT |
579 MAL_FTR_COMMON_ERR_INT);
580#else
581 printk(KERN_ERR "%pOF: Support for 405EZ not enabled!\n",
582 ofdev->dev.of_node);
583 err = -ENODEV;
584 goto fail;
585#endif
586 }
587
588 mal->txeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
589 mal->rxeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
590 mal->serr_irq = irq_of_parse_and_map(ofdev->dev.of_node, 2);
591
592 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
593 mal->txde_irq = mal->rxde_irq = mal->serr_irq;
594 } else {
595 mal->txde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 3);
596 mal->rxde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 4);
597 }
598
599 if (!mal->txeob_irq || !mal->rxeob_irq || !mal->serr_irq ||
600 !mal->txde_irq || !mal->rxde_irq) {
601 printk(KERN_ERR
602 "mal%d: failed to map interrupts !\n", index);
603 err = -ENODEV;
604 goto fail_unmap;
605 }
606
607 INIT_LIST_HEAD(&mal->poll_list);
608 INIT_LIST_HEAD(&mal->list);
609 spin_lock_init(&mal->lock);
610
611 init_dummy_netdev(&mal->dummy_dev);
612
613 netif_napi_add(&mal->dummy_dev, &mal->napi, mal_poll,
614 CONFIG_IBM_EMAC_POLL_WEIGHT);
615
616 /* Load power-on reset defaults */
617 mal_reset(mal);
618
619 /* Set the MAL configuration register */
620 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
621 cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA;
622
623 /* Current Axon is not happy with priority being non-0, it can
624 * deadlock, fix it up here
625 */
626 if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-axon"))
627 cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10);
628
629 /* Apply configuration */
630 set_mal_dcrn(mal, MAL_CFG, cfg);
631
632 /* Allocate space for BD rings */
633 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
634 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
635
636 bd_size = sizeof(struct mal_descriptor) *
637 (NUM_TX_BUFF * mal->num_tx_chans +
638 NUM_RX_BUFF * mal->num_rx_chans);
639 mal->bd_virt = dma_zalloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
640 GFP_KERNEL);
641 if (mal->bd_virt == NULL) {
642 err = -ENOMEM;
643 goto fail_unmap;
644 }
645
646 for (i = 0; i < mal->num_tx_chans; ++i)
647 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
648 sizeof(struct mal_descriptor) *
649 mal_tx_bd_offset(mal, i));
650
651 for (i = 0; i < mal->num_rx_chans; ++i)
652 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
653 sizeof(struct mal_descriptor) *
654 mal_rx_bd_offset(mal, i));
655
656 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
657 irqflags = IRQF_SHARED;
658 hdlr_serr = hdlr_txde = hdlr_rxde = mal_int;
659 } else {
660 irqflags = 0;
661 hdlr_serr = mal_serr;
662 hdlr_txde = mal_txde;
663 hdlr_rxde = mal_rxde;
664 }
665
666 err = request_irq(mal->serr_irq, hdlr_serr, irqflags, "MAL SERR", mal);
667 if (err)
668 goto fail2;
669 err = request_irq(mal->txde_irq, hdlr_txde, irqflags, "MAL TX DE", mal);
670 if (err)
671 goto fail3;
672 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
673 if (err)
674 goto fail4;
675 err = request_irq(mal->rxde_irq, hdlr_rxde, irqflags, "MAL RX DE", mal);
676 if (err)
677 goto fail5;
678 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
679 if (err)
680 goto fail6;
681
682 /* Enable all MAL SERR interrupt sources */
683 set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS);
684
685 /* Enable EOB interrupt */
686 mal_enable_eob_irq(mal);
687
688 printk(KERN_INFO
689 "MAL v%d %pOF, %d TX channels, %d RX channels\n",
690 mal->version, ofdev->dev.of_node,
691 mal->num_tx_chans, mal->num_rx_chans);
692
693 /* Advertise this instance to the rest of the world */
694 wmb();
695 platform_set_drvdata(ofdev, mal);
696
697 return 0;
698
699 fail6:
700 free_irq(mal->rxde_irq, mal);
701 fail5:
702 free_irq(mal->txeob_irq, mal);
703 fail4:
704 free_irq(mal->txde_irq, mal);
705 fail3:
706 free_irq(mal->serr_irq, mal);
707 fail2:
708 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
709 fail_unmap:
710 dcr_unmap(mal->dcr_host, 0x100);
711 fail:
712 kfree(mal);
713
714 return err;
715}
716
717static int mal_remove(struct platform_device *ofdev)
718{
719 struct mal_instance *mal = platform_get_drvdata(ofdev);
720
721 MAL_DBG(mal, "remove" NL);
722
723 /* Synchronize with scheduled polling */
724 napi_disable(&mal->napi);
725
726 if (!list_empty(&mal->list))
727 /* This is *very* bad */
728 WARN(1, KERN_EMERG
729 "mal%d: commac list is not empty on remove!\n",
730 mal->index);
731
732 free_irq(mal->serr_irq, mal);
733 free_irq(mal->txde_irq, mal);
734 free_irq(mal->txeob_irq, mal);
735 free_irq(mal->rxde_irq, mal);
736 free_irq(mal->rxeob_irq, mal);
737
738 mal_reset(mal);
739
740 dma_free_coherent(&ofdev->dev,
741 sizeof(struct mal_descriptor) *
742 (NUM_TX_BUFF * mal->num_tx_chans +
743 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
744 mal->bd_dma);
745 kfree(mal);
746
747 return 0;
748}
749
750static const struct of_device_id mal_platform_match[] =
751{
752 {
753 .compatible = "ibm,mcmal",
754 },
755 {
756 .compatible = "ibm,mcmal2",
757 },
758 /* Backward compat */
759 {
760 .type = "mcmal-dma",
761 .compatible = "ibm,mcmal",
762 },
763 {
764 .type = "mcmal-dma",
765 .compatible = "ibm,mcmal2",
766 },
767 {},
768};
769
770static struct platform_driver mal_of_driver = {
771 .driver = {
772 .name = "mcmal",
773 .of_match_table = mal_platform_match,
774 },
775 .probe = mal_probe,
776 .remove = mal_remove,
777};
778
779int __init mal_init(void)
780{
781 return platform_driver_register(&mal_of_driver);
782}
783
784void mal_exit(void)
785{
786 platform_driver_unregister(&mal_of_driver);
787}