1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef FS_ENET_FEC_H
 3#define FS_ENET_FEC_H
 4
 
 
 
 5#define FEC_MAX_MULTICAST_ADDRS	64
 6
 7/* Interrupt events/masks.
 8*/
 9#define FEC_ENET_HBERR	0x80000000U	/* Heartbeat error          */
10#define FEC_ENET_BABR	0x40000000U	/* Babbling receiver        */
11#define FEC_ENET_BABT	0x20000000U	/* Babbling transmitter     */
12#define FEC_ENET_GRA	0x10000000U	/* Graceful stop complete   */
13#define FEC_ENET_TXF	0x08000000U	/* Full frame transmitted   */
14#define FEC_ENET_TXB	0x04000000U	/* A buffer was transmitted */
15#define FEC_ENET_RXF	0x02000000U	/* Full frame received      */
16#define FEC_ENET_RXB	0x01000000U	/* A buffer was received    */
17#define FEC_ENET_MII	0x00800000U	/* MII interrupt            */
18#define FEC_ENET_EBERR	0x00400000U	/* SDMA bus error           */
19
20#define FEC_ECNTRL_PINMUX	0x00000004
21#define FEC_ECNTRL_ETHER_EN	0x00000002
22#define FEC_ECNTRL_RESET	0x00000001
23
24/* RMII mode enabled only when MII_MODE bit is set too. */
25#define FEC_RCNTRL_RMII_MODE	(0x00000100 | \
26				 FEC_RCNTRL_MII_MODE | FEC_RCNTRL_FCE)
27#define FEC_RCNTRL_FCE		0x00000020
28#define FEC_RCNTRL_BC_REJ	0x00000010
29#define FEC_RCNTRL_PROM		0x00000008
30#define FEC_RCNTRL_MII_MODE	0x00000004
31#define FEC_RCNTRL_DRT		0x00000002
32#define FEC_RCNTRL_LOOP		0x00000001
33
34#define FEC_TCNTRL_FDEN		0x00000004
35#define FEC_TCNTRL_HBC		0x00000002
36#define FEC_TCNTRL_GTS		0x00000001
37
38/*
39 * Delay to wait for FEC reset command to complete (in us)
40 */
41#define FEC_RESET_DELAY		50
42#endif

 1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef FS_ENET_FEC_H
 3#define FS_ENET_FEC_H
 4
 5/* CRC polynomium used by the FEC for the multicast group filtering */
 6#define FEC_CRC_POLY   0x04C11DB7
 7
 8#define FEC_MAX_MULTICAST_ADDRS	64
 9
10/* Interrupt events/masks.
11*/
12#define FEC_ENET_HBERR	0x80000000U	/* Heartbeat error          */
13#define FEC_ENET_BABR	0x40000000U	/* Babbling receiver        */
14#define FEC_ENET_BABT	0x20000000U	/* Babbling transmitter     */
15#define FEC_ENET_GRA	0x10000000U	/* Graceful stop complete   */
16#define FEC_ENET_TXF	0x08000000U	/* Full frame transmitted   */
17#define FEC_ENET_TXB	0x04000000U	/* A buffer was transmitted */
18#define FEC_ENET_RXF	0x02000000U	/* Full frame received      */
19#define FEC_ENET_RXB	0x01000000U	/* A buffer was received    */
20#define FEC_ENET_MII	0x00800000U	/* MII interrupt            */
21#define FEC_ENET_EBERR	0x00400000U	/* SDMA bus error           */
22
23#define FEC_ECNTRL_PINMUX	0x00000004
24#define FEC_ECNTRL_ETHER_EN	0x00000002
25#define FEC_ECNTRL_RESET	0x00000001
26
27/* RMII mode enabled only when MII_MODE bit is set too. */
28#define FEC_RCNTRL_RMII_MODE	(0x00000100 | \
29				 FEC_RCNTRL_MII_MODE | FEC_RCNTRL_FCE)
30#define FEC_RCNTRL_FCE		0x00000020
31#define FEC_RCNTRL_BC_REJ	0x00000010
32#define FEC_RCNTRL_PROM		0x00000008
33#define FEC_RCNTRL_MII_MODE	0x00000004
34#define FEC_RCNTRL_DRT		0x00000002
35#define FEC_RCNTRL_LOOP		0x00000001
36
37#define FEC_TCNTRL_FDEN		0x00000004
38#define FEC_TCNTRL_HBC		0x00000002
39#define FEC_TCNTRL_GTS		0x00000001
40
41/*
42 * Delay to wait for FEC reset command to complete (in us)
43 */
44#define FEC_RESET_DELAY		50
45#endif