1// SPDX-License-Identifier: GPL-2.0+
   2/* Renesas R-Car CAN FD device driver
   3 *
   4 * Copyright (C) 2015 Renesas Electronics Corp.
 
 
 
 
 
   5 */
   6
   7/* The R-Car CAN FD controller can operate in either one of the below two modes
   8 *  - CAN FD only mode
   9 *  - Classical CAN (CAN 2.0) only mode
  10 *
  11 * This driver puts the controller in CAN FD only mode by default. In this
  12 * mode, the controller acts as a CAN FD node that can also interoperate with
  13 * CAN 2.0 nodes.
  14 *
  15 * To switch the controller to Classical CAN (CAN 2.0) only mode, add
  16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
  17 * also required to switch modes.
  18 *
  19 * Note: The h/w manual register naming convention is clumsy and not acceptable
  20 * to use as it is in the driver. However, those names are added as comments
  21 * wherever it is modified to a readable name.
  22 */
  23
  24#include <linux/bitmap.h>
  25#include <linux/bitops.h>
  26#include <linux/can/dev.h>
  27#include <linux/clk.h>
  28#include <linux/errno.h>
  29#include <linux/ethtool.h>
  30#include <linux/interrupt.h>
  31#include <linux/iopoll.h>
  32#include <linux/kernel.h>
  33#include <linux/module.h>
  34#include <linux/moduleparam.h>
 
 
 
 
  35#include <linux/netdevice.h>
  36#include <linux/of.h>
  37#include <linux/phy/phy.h>
  38#include <linux/platform_device.h>
  39#include <linux/reset.h>
  40#include <linux/types.h>
 
 
 
 
 
 
  41
  42#define RCANFD_DRV_NAME			"rcar_canfd"
  43
  44/* Global register bits */
  45
  46/* RSCFDnCFDGRMCFG */
  47#define RCANFD_GRMCFG_RCMC		BIT(0)
  48
  49/* RSCFDnCFDGCFG / RSCFDnGCFG */
  50#define RCANFD_GCFG_EEFE		BIT(6)
  51#define RCANFD_GCFG_CMPOC		BIT(5)	/* CAN FD only */
  52#define RCANFD_GCFG_DCS			BIT(4)
  53#define RCANFD_GCFG_DCE			BIT(1)
  54#define RCANFD_GCFG_TPRI		BIT(0)
  55
  56/* RSCFDnCFDGCTR / RSCFDnGCTR */
  57#define RCANFD_GCTR_TSRST		BIT(16)
  58#define RCANFD_GCTR_CFMPOFIE		BIT(11)	/* CAN FD only */
  59#define RCANFD_GCTR_THLEIE		BIT(10)
  60#define RCANFD_GCTR_MEIE		BIT(9)
  61#define RCANFD_GCTR_DEIE		BIT(8)
  62#define RCANFD_GCTR_GSLPR		BIT(2)
  63#define RCANFD_GCTR_GMDC_MASK		(0x3)
  64#define RCANFD_GCTR_GMDC_GOPM		(0x0)
  65#define RCANFD_GCTR_GMDC_GRESET		(0x1)
  66#define RCANFD_GCTR_GMDC_GTEST		(0x2)
  67
  68/* RSCFDnCFDGSTS / RSCFDnGSTS */
  69#define RCANFD_GSTS_GRAMINIT		BIT(3)
  70#define RCANFD_GSTS_GSLPSTS		BIT(2)
  71#define RCANFD_GSTS_GHLTSTS		BIT(1)
  72#define RCANFD_GSTS_GRSTSTS		BIT(0)
  73/* Non-operational status */
  74#define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
  75
  76/* RSCFDnCFDGERFL / RSCFDnGERFL */
  77#define RCANFD_GERFL_EEF0_7		GENMASK(23, 16)
  78#define RCANFD_GERFL_EEF(ch)		BIT(16 + (ch))
  79#define RCANFD_GERFL_CMPOF		BIT(3)	/* CAN FD only */
  80#define RCANFD_GERFL_THLES		BIT(2)
  81#define RCANFD_GERFL_MES		BIT(1)
  82#define RCANFD_GERFL_DEF		BIT(0)
  83
  84#define RCANFD_GERFL_ERR(gpriv, x) \
  85	((x) & (reg_gen4(gpriv, RCANFD_GERFL_EEF0_7, \
  86			 RCANFD_GERFL_EEF(0) | RCANFD_GERFL_EEF(1)) | \
  87		RCANFD_GERFL_MES | \
  88		((gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0)))
  89
  90/* AFL Rx rules registers */
  91
  92/* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
  93#define RCANFD_GAFLCFG_SETRNC(gpriv, n, x) \
  94	(((x) & reg_gen4(gpriv, 0x1ff, 0xff)) << \
  95	 (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8)))
  96
  97#define RCANFD_GAFLCFG_GETRNC(gpriv, n, x) \
  98	(((x) >> (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8))) & \
  99	 reg_gen4(gpriv, 0x1ff, 0xff))
 100
 101/* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 102#define RCANFD_GAFLECTR_AFLDAE		BIT(8)
 103#define RCANFD_GAFLECTR_AFLPN(gpriv, x)	((x) & reg_gen4(gpriv, 0x7f, 0x1f))
 104
 105/* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 106#define RCANFD_GAFLID_GAFLLB		BIT(29)
 107
 108/* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
 109#define RCANFD_GAFLP1_GAFLFDP(x)	(1 << (x))
 110
 111/* Channel register bits */
 112
 113/* RSCFDnCmCFG - Classical CAN only */
 114#define RCANFD_CFG_SJW(x)		(((x) & 0x3) << 24)
 115#define RCANFD_CFG_TSEG2(x)		(((x) & 0x7) << 20)
 116#define RCANFD_CFG_TSEG1(x)		(((x) & 0xf) << 16)
 117#define RCANFD_CFG_BRP(x)		(((x) & 0x3ff) << 0)
 118
 119/* RSCFDnCFDCmNCFG - CAN FD only */
 120#define RCANFD_NCFG_NTSEG2(gpriv, x) \
 121	(((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 25, 24))
 122
 123#define RCANFD_NCFG_NTSEG1(gpriv, x) \
 124	(((x) & reg_gen4(gpriv, 0xff, 0x7f)) << reg_gen4(gpriv, 17, 16))
 125
 126#define RCANFD_NCFG_NSJW(gpriv, x) \
 127	(((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 10, 11))
 128
 129#define RCANFD_NCFG_NBRP(x)		(((x) & 0x3ff) << 0)
 130
 131/* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 132#define RCANFD_CCTR_CTME		BIT(24)
 133#define RCANFD_CCTR_ERRD		BIT(23)
 134#define RCANFD_CCTR_BOM_MASK		(0x3 << 21)
 135#define RCANFD_CCTR_BOM_ISO		(0x0 << 21)
 136#define RCANFD_CCTR_BOM_BENTRY		(0x1 << 21)
 137#define RCANFD_CCTR_BOM_BEND		(0x2 << 21)
 138#define RCANFD_CCTR_TDCVFIE		BIT(19)
 139#define RCANFD_CCTR_SOCOIE		BIT(18)
 140#define RCANFD_CCTR_EOCOIE		BIT(17)
 141#define RCANFD_CCTR_TAIE		BIT(16)
 142#define RCANFD_CCTR_ALIE		BIT(15)
 143#define RCANFD_CCTR_BLIE		BIT(14)
 144#define RCANFD_CCTR_OLIE		BIT(13)
 145#define RCANFD_CCTR_BORIE		BIT(12)
 146#define RCANFD_CCTR_BOEIE		BIT(11)
 147#define RCANFD_CCTR_EPIE		BIT(10)
 148#define RCANFD_CCTR_EWIE		BIT(9)
 149#define RCANFD_CCTR_BEIE		BIT(8)
 150#define RCANFD_CCTR_CSLPR		BIT(2)
 151#define RCANFD_CCTR_CHMDC_MASK		(0x3)
 152#define RCANFD_CCTR_CHDMC_COPM		(0x0)
 153#define RCANFD_CCTR_CHDMC_CRESET	(0x1)
 154#define RCANFD_CCTR_CHDMC_CHLT		(0x2)
 155
 156/* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 157#define RCANFD_CSTS_COMSTS		BIT(7)
 158#define RCANFD_CSTS_RECSTS		BIT(6)
 159#define RCANFD_CSTS_TRMSTS		BIT(5)
 160#define RCANFD_CSTS_BOSTS		BIT(4)
 161#define RCANFD_CSTS_EPSTS		BIT(3)
 162#define RCANFD_CSTS_SLPSTS		BIT(2)
 163#define RCANFD_CSTS_HLTSTS		BIT(1)
 164#define RCANFD_CSTS_CRSTSTS		BIT(0)
 165
 166#define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
 167#define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
 168
 169/* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 170#define RCANFD_CERFL_ADERR		BIT(14)
 171#define RCANFD_CERFL_B0ERR		BIT(13)
 172#define RCANFD_CERFL_B1ERR		BIT(12)
 173#define RCANFD_CERFL_CERR		BIT(11)
 174#define RCANFD_CERFL_AERR		BIT(10)
 175#define RCANFD_CERFL_FERR		BIT(9)
 176#define RCANFD_CERFL_SERR		BIT(8)
 177#define RCANFD_CERFL_ALF		BIT(7)
 178#define RCANFD_CERFL_BLF		BIT(6)
 179#define RCANFD_CERFL_OVLF		BIT(5)
 180#define RCANFD_CERFL_BORF		BIT(4)
 181#define RCANFD_CERFL_BOEF		BIT(3)
 182#define RCANFD_CERFL_EPF		BIT(2)
 183#define RCANFD_CERFL_EWF		BIT(1)
 184#define RCANFD_CERFL_BEF		BIT(0)
 185
 186#define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
 187
 188/* RSCFDnCFDCmDCFG */
 189#define RCANFD_DCFG_DSJW(gpriv, x)	(((x) & reg_gen4(gpriv, 0xf, 0x7)) << 24)
 190
 191#define RCANFD_DCFG_DTSEG2(gpriv, x) \
 192	(((x) & reg_gen4(gpriv, 0x0f, 0x7)) << reg_gen4(gpriv, 16, 20))
 193
 194#define RCANFD_DCFG_DTSEG1(gpriv, x) \
 195	(((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 8, 16))
 196
 197#define RCANFD_DCFG_DBRP(x)		(((x) & 0xff) << 0)
 198
 199/* RSCFDnCFDCmFDCFG */
 200#define RCANFD_GEN4_FDCFG_CLOE		BIT(30)
 201#define RCANFD_GEN4_FDCFG_FDOE		BIT(28)
 202#define RCANFD_FDCFG_TDCE		BIT(9)
 203#define RCANFD_FDCFG_TDCOC		BIT(8)
 204#define RCANFD_FDCFG_TDCO(x)		(((x) & 0x7f) >> 16)
 205
 206/* RSCFDnCFDRFCCx */
 207#define RCANFD_RFCC_RFIM		BIT(12)
 208#define RCANFD_RFCC_RFDC(x)		(((x) & 0x7) << 8)
 209#define RCANFD_RFCC_RFPLS(x)		(((x) & 0x7) << 4)
 210#define RCANFD_RFCC_RFIE		BIT(1)
 211#define RCANFD_RFCC_RFE			BIT(0)
 212
 213/* RSCFDnCFDRFSTSx */
 214#define RCANFD_RFSTS_RFIF		BIT(3)
 215#define RCANFD_RFSTS_RFMLT		BIT(2)
 216#define RCANFD_RFSTS_RFFLL		BIT(1)
 217#define RCANFD_RFSTS_RFEMP		BIT(0)
 218
 219/* RSCFDnCFDRFIDx */
 220#define RCANFD_RFID_RFIDE		BIT(31)
 221#define RCANFD_RFID_RFRTR		BIT(30)
 222
 223/* RSCFDnCFDRFPTRx */
 224#define RCANFD_RFPTR_RFDLC(x)		(((x) >> 28) & 0xf)
 225#define RCANFD_RFPTR_RFPTR(x)		(((x) >> 16) & 0xfff)
 226#define RCANFD_RFPTR_RFTS(x)		(((x) >> 0) & 0xffff)
 227
 228/* RSCFDnCFDRFFDSTSx */
 229#define RCANFD_RFFDSTS_RFFDF		BIT(2)
 230#define RCANFD_RFFDSTS_RFBRS		BIT(1)
 231#define RCANFD_RFFDSTS_RFESI		BIT(0)
 232
 233/* Common FIFO bits */
 234
 235/* RSCFDnCFDCFCCk */
 236#define RCANFD_CFCC_CFTML(gpriv, x)	\
 237	(((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 16, 20))
 238#define RCANFD_CFCC_CFM(gpriv, x)	(((x) & 0x3) << reg_gen4(gpriv,  8, 16))
 239#define RCANFD_CFCC_CFIM		BIT(12)
 240#define RCANFD_CFCC_CFDC(gpriv, x)	(((x) & 0x7) << reg_gen4(gpriv, 21,  8))
 241#define RCANFD_CFCC_CFPLS(x)		(((x) & 0x7) << 4)
 242#define RCANFD_CFCC_CFTXIE		BIT(2)
 243#define RCANFD_CFCC_CFE			BIT(0)
 244
 245/* RSCFDnCFDCFSTSk */
 246#define RCANFD_CFSTS_CFMC(x)		(((x) >> 8) & 0xff)
 247#define RCANFD_CFSTS_CFTXIF		BIT(4)
 248#define RCANFD_CFSTS_CFMLT		BIT(2)
 249#define RCANFD_CFSTS_CFFLL		BIT(1)
 250#define RCANFD_CFSTS_CFEMP		BIT(0)
 251
 252/* RSCFDnCFDCFIDk */
 253#define RCANFD_CFID_CFIDE		BIT(31)
 254#define RCANFD_CFID_CFRTR		BIT(30)
 255#define RCANFD_CFID_CFID_MASK(x)	((x) & 0x1fffffff)
 256
 257/* RSCFDnCFDCFPTRk */
 258#define RCANFD_CFPTR_CFDLC(x)		(((x) & 0xf) << 28)
 259#define RCANFD_CFPTR_CFPTR(x)		(((x) & 0xfff) << 16)
 260#define RCANFD_CFPTR_CFTS(x)		(((x) & 0xff) << 0)
 261
 262/* RSCFDnCFDCFFDCSTSk */
 263#define RCANFD_CFFDCSTS_CFFDF		BIT(2)
 264#define RCANFD_CFFDCSTS_CFBRS		BIT(1)
 265#define RCANFD_CFFDCSTS_CFESI		BIT(0)
 266
 267/* This controller supports either Classical CAN only mode or CAN FD only mode.
 268 * These modes are supported in two separate set of register maps & names.
 269 * However, some of the register offsets are common for both modes. Those
 270 * offsets are listed below as Common registers.
 271 *
 272 * The CAN FD only mode specific registers & Classical CAN only mode specific
 273 * registers are listed separately. Their register names starts with
 274 * RCANFD_F_xxx & RCANFD_C_xxx respectively.
 275 */
 276
 277/* Common registers */
 278
 279/* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
 280#define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
 281/* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 282#define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
 283/* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 284#define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
 285/* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 286#define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
 287
 288/* RSCFDnCFDGCFG / RSCFDnGCFG */
 289#define RCANFD_GCFG			(0x0084)
 290/* RSCFDnCFDGCTR / RSCFDnGCTR */
 291#define RCANFD_GCTR			(0x0088)
 292/* RSCFDnCFDGCTS / RSCFDnGCTS */
 293#define RCANFD_GSTS			(0x008c)
 294/* RSCFDnCFDGERFL / RSCFDnGERFL */
 295#define RCANFD_GERFL			(0x0090)
 296/* RSCFDnCFDGTSC / RSCFDnGTSC */
 297#define RCANFD_GTSC			(0x0094)
 298/* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 299#define RCANFD_GAFLECTR			(0x0098)
 300/* RSCFDnCFDGAFLCFG / RSCFDnGAFLCFG */
 301#define RCANFD_GAFLCFG(ch)		(0x009c + (0x04 * ((ch) / 2)))
 
 
 302/* RSCFDnCFDRMNB / RSCFDnRMNB */
 303#define RCANFD_RMNB			(0x00a4)
 304/* RSCFDnCFDRMND / RSCFDnRMND */
 305#define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
 306
 307/* RSCFDnCFDRFCCx / RSCFDnRFCCx */
 308#define RCANFD_RFCC(gpriv, x)		(reg_gen4(gpriv, 0x00c0, 0x00b8) + (0x04 * (x)))
 309/* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
 310#define RCANFD_RFSTS(gpriv, x)		(RCANFD_RFCC(gpriv, x) + 0x20)
 311/* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
 312#define RCANFD_RFPCTR(gpriv, x)		(RCANFD_RFCC(gpriv, x) + 0x40)
 313
 314/* Common FIFO Control registers */
 315
 316/* RSCFDnCFDCFCCx / RSCFDnCFCCx */
 317#define RCANFD_CFCC(gpriv, ch, idx) \
 318	(reg_gen4(gpriv, 0x0120, 0x0118) + (0x0c * (ch)) + (0x04 * (idx)))
 319/* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
 320#define RCANFD_CFSTS(gpriv, ch, idx) \
 321	(reg_gen4(gpriv, 0x01e0, 0x0178) + (0x0c * (ch)) + (0x04 * (idx)))
 322/* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
 323#define RCANFD_CFPCTR(gpriv, ch, idx) \
 324	(reg_gen4(gpriv, 0x0240, 0x01d8) + (0x0c * (ch)) + (0x04 * (idx)))
 325
 326/* RSCFDnCFDFESTS / RSCFDnFESTS */
 327#define RCANFD_FESTS			(0x0238)
 328/* RSCFDnCFDFFSTS / RSCFDnFFSTS */
 329#define RCANFD_FFSTS			(0x023c)
 330/* RSCFDnCFDFMSTS / RSCFDnFMSTS */
 331#define RCANFD_FMSTS			(0x0240)
 332/* RSCFDnCFDRFISTS / RSCFDnRFISTS */
 333#define RCANFD_RFISTS			(0x0244)
 334/* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
 335#define RCANFD_CFRISTS			(0x0248)
 336/* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
 337#define RCANFD_CFTISTS			(0x024c)
 338
 339/* RSCFDnCFDTMCp / RSCFDnTMCp */
 340#define RCANFD_TMC(p)			(0x0250 + (0x01 * (p)))
 341/* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
 342#define RCANFD_TMSTS(p)			(0x02d0 + (0x01 * (p)))
 343
 344/* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
 345#define RCANFD_TMTRSTS(y)		(0x0350 + (0x04 * (y)))
 346/* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
 347#define RCANFD_TMTARSTS(y)		(0x0360 + (0x04 * (y)))
 348/* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
 349#define RCANFD_TMTCSTS(y)		(0x0370 + (0x04 * (y)))
 350/* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
 351#define RCANFD_TMTASTS(y)		(0x0380 + (0x04 * (y)))
 352/* RSCFDnCFDTMIECy / RSCFDnTMIECy */
 353#define RCANFD_TMIEC(y)			(0x0390 + (0x04 * (y)))
 354
 355/* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
 356#define RCANFD_TXQCC(m)			(0x03a0 + (0x04 * (m)))
 357/* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
 358#define RCANFD_TXQSTS(m)		(0x03c0 + (0x04 * (m)))
 359/* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
 360#define RCANFD_TXQPCTR(m)		(0x03e0 + (0x04 * (m)))
 361
 362/* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
 363#define RCANFD_THLCC(m)			(0x0400 + (0x04 * (m)))
 364/* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
 365#define RCANFD_THLSTS(m)		(0x0420 + (0x04 * (m)))
 366/* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
 367#define RCANFD_THLPCTR(m)		(0x0440 + (0x04 * (m)))
 368
 369/* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
 370#define RCANFD_GTINTSTS0		(0x0460)
 371/* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
 372#define RCANFD_GTINTSTS1		(0x0464)
 373/* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
 374#define RCANFD_GTSTCFG			(0x0468)
 375/* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
 376#define RCANFD_GTSTCTR			(0x046c)
 377/* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
 378#define RCANFD_GLOCKK			(0x047c)
 379/* RSCFDnCFDGRMCFG */
 380#define RCANFD_GRMCFG			(0x04fc)
 381
 382/* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 383#define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
 384/* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
 385#define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
 386/* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
 387#define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
 388/* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
 389#define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
 390
 391/* Classical CAN only mode register map */
 392
 393/* RSCFDnGAFLXXXj offset */
 394#define RCANFD_C_GAFL_OFFSET		(0x0500)
 395
 396/* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
 397#define RCANFD_C_RMID(q)		(0x0600 + (0x10 * (q)))
 398#define RCANFD_C_RMPTR(q)		(0x0604 + (0x10 * (q)))
 399#define RCANFD_C_RMDF0(q)		(0x0608 + (0x10 * (q)))
 400#define RCANFD_C_RMDF1(q)		(0x060c + (0x10 * (q)))
 401
 402/* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
 403#define RCANFD_C_RFOFFSET	(0x0e00)
 404#define RCANFD_C_RFID(x)	(RCANFD_C_RFOFFSET + (0x10 * (x)))
 405#define RCANFD_C_RFPTR(x)	(RCANFD_C_RFOFFSET + 0x04 + (0x10 * (x)))
 406#define RCANFD_C_RFDF(x, df) \
 407		(RCANFD_C_RFOFFSET + 0x08 + (0x10 * (x)) + (0x04 * (df)))
 
 408
 409/* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
 410#define RCANFD_C_CFOFFSET		(0x0e80)
 411
 412#define RCANFD_C_CFID(ch, idx) \
 413	(RCANFD_C_CFOFFSET + (0x30 * (ch)) + (0x10 * (idx)))
 414
 415#define RCANFD_C_CFPTR(ch, idx)	\
 416	(RCANFD_C_CFOFFSET + 0x04 + (0x30 * (ch)) + (0x10 * (idx)))
 417
 418#define RCANFD_C_CFDF(ch, idx, df) \
 419	(RCANFD_C_CFOFFSET + 0x08 + (0x30 * (ch)) + (0x10 * (idx)) + (0x04 * (df)))
 420
 421/* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
 422#define RCANFD_C_TMID(p)		(0x1000 + (0x10 * (p)))
 423#define RCANFD_C_TMPTR(p)		(0x1004 + (0x10 * (p)))
 424#define RCANFD_C_TMDF0(p)		(0x1008 + (0x10 * (p)))
 425#define RCANFD_C_TMDF1(p)		(0x100c + (0x10 * (p)))
 426
 427/* RSCFDnTHLACCm */
 428#define RCANFD_C_THLACC(m)		(0x1800 + (0x04 * (m)))
 429/* RSCFDnRPGACCr */
 430#define RCANFD_C_RPGACC(r)		(0x1900 + (0x04 * (r)))
 431
 432/* R-Car Gen4 Classical and CAN FD mode specific register map */
 433#define RCANFD_GEN4_FDCFG(m)		(0x1404 + (0x20 * (m)))
 434
 435#define RCANFD_GEN4_GAFL_OFFSET		(0x1800)
 436
 437/* CAN FD mode specific register map */
 438
 439/* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
 440#define RCANFD_F_DCFG(gpriv, m)		(reg_gen4(gpriv, 0x1400, 0x0500) + (0x20 * (m)))
 441#define RCANFD_F_CFDCFG(m)		(0x0504 + (0x20 * (m)))
 442#define RCANFD_F_CFDCTR(m)		(0x0508 + (0x20 * (m)))
 443#define RCANFD_F_CFDSTS(m)		(0x050c + (0x20 * (m)))
 444#define RCANFD_F_CFDCRC(m)		(0x0510 + (0x20 * (m)))
 445
 446/* RSCFDnCFDGAFLXXXj offset */
 447#define RCANFD_F_GAFL_OFFSET		(0x1000)
 448
 449/* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
 450#define RCANFD_F_RMID(q)		(0x2000 + (0x20 * (q)))
 451#define RCANFD_F_RMPTR(q)		(0x2004 + (0x20 * (q)))
 452#define RCANFD_F_RMFDSTS(q)		(0x2008 + (0x20 * (q)))
 453#define RCANFD_F_RMDF(q, b)		(0x200c + (0x04 * (b)) + (0x20 * (q)))
 454
 455/* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
 456#define RCANFD_F_RFOFFSET(gpriv)	reg_gen4(gpriv, 0x6000, 0x3000)
 457#define RCANFD_F_RFID(gpriv, x)		(RCANFD_F_RFOFFSET(gpriv) + (0x80 * (x)))
 458#define RCANFD_F_RFPTR(gpriv, x)	(RCANFD_F_RFOFFSET(gpriv) + 0x04 + (0x80 * (x)))
 459#define RCANFD_F_RFFDSTS(gpriv, x)	(RCANFD_F_RFOFFSET(gpriv) + 0x08 + (0x80 * (x)))
 460#define RCANFD_F_RFDF(gpriv, x, df) \
 461	(RCANFD_F_RFOFFSET(gpriv) + 0x0c + (0x80 * (x)) + (0x04 * (df)))
 
 
 462
 463/* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
 464#define RCANFD_F_CFOFFSET(gpriv)	reg_gen4(gpriv, 0x6400, 0x3400)
 465
 466#define RCANFD_F_CFID(gpriv, ch, idx) \
 467	(RCANFD_F_CFOFFSET(gpriv) + (0x180 * (ch)) + (0x80 * (idx)))
 468
 469#define RCANFD_F_CFPTR(gpriv, ch, idx) \
 470	(RCANFD_F_CFOFFSET(gpriv) + 0x04 + (0x180 * (ch)) + (0x80 * (idx)))
 471
 472#define RCANFD_F_CFFDCSTS(gpriv, ch, idx) \
 473	(RCANFD_F_CFOFFSET(gpriv) + 0x08 + (0x180 * (ch)) + (0x80 * (idx)))
 474
 475#define RCANFD_F_CFDF(gpriv, ch, idx, df) \
 476	(RCANFD_F_CFOFFSET(gpriv) + 0x0c + (0x180 * (ch)) + (0x80 * (idx)) + \
 477	 (0x04 * (df)))
 478
 479/* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
 480#define RCANFD_F_TMID(p)		(0x4000 + (0x20 * (p)))
 481#define RCANFD_F_TMPTR(p)		(0x4004 + (0x20 * (p)))
 482#define RCANFD_F_TMFDCTR(p)		(0x4008 + (0x20 * (p)))
 483#define RCANFD_F_TMDF(p, b)		(0x400c + (0x20 * (p)) + (0x04 * (b)))
 484
 485/* RSCFDnCFDTHLACCm */
 486#define RCANFD_F_THLACC(m)		(0x6000 + (0x04 * (m)))
 487/* RSCFDnCFDRPGACCr */
 488#define RCANFD_F_RPGACC(r)		(0x6400 + (0x04 * (r)))
 489
 490/* Constants */
 491#define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
 492#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
 493
 494#define RCANFD_NUM_CHANNELS		8	/* Eight channels max */
 495#define RCANFD_CHANNELS_MASK		BIT((RCANFD_NUM_CHANNELS) - 1)
 496
 497#define RCANFD_GAFL_PAGENUM(entry)	((entry) / 16)
 498#define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
 499
 500/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
 501 * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
 502 * number is added to RFFIFO index.
 503 */
 504#define RCANFD_RFFIFO_IDX		0
 505
 506/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
 507 * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
 508 */
 509#define RCANFD_CFFIFO_IDX		0
 510
 511/* fCAN clock select register settings */
 512enum rcar_canfd_fcanclk {
 513	RCANFD_CANFDCLK = 0,		/* CANFD clock */
 514	RCANFD_EXTCLK,			/* Externally input clock */
 515};
 516
 517struct rcar_canfd_global;
 518
 519struct rcar_canfd_hw_info {
 520	u8 max_channels;
 521	u8 postdiv;
 522	/* hardware features */
 523	unsigned shared_global_irqs:1;	/* Has shared global irqs */
 524	unsigned multi_channel_irqs:1;	/* Has multiple channel irqs */
 525};
 526
 527/* Channel priv data */
 528struct rcar_canfd_channel {
 529	struct can_priv can;			/* Must be the first member */
 530	struct net_device *ndev;
 531	struct rcar_canfd_global *gpriv;	/* Controller reference */
 532	void __iomem *base;			/* Register base address */
 533	struct phy *transceiver;		/* Optional transceiver */
 534	struct napi_struct napi;
 
 535	u32 tx_head;				/* Incremented on xmit */
 536	u32 tx_tail;				/* Incremented on xmit done */
 537	u32 channel;				/* Channel number */
 538	spinlock_t tx_lock;			/* To protect tx path */
 539};
 540
 541/* Global priv data */
 542struct rcar_canfd_global {
 543	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
 544	void __iomem *base;		/* Register base address */
 545	struct platform_device *pdev;	/* Respective platform device */
 546	struct clk *clkp;		/* Peripheral clock */
 547	struct clk *can_clk;		/* fCAN clock */
 548	enum rcar_canfd_fcanclk fcan;	/* CANFD or Ext clock */
 549	unsigned long channels_mask;	/* Enabled channels mask */
 550	bool fdmode;			/* CAN FD or Classical CAN only mode */
 551	struct reset_control *rstc1;
 552	struct reset_control *rstc2;
 553	const struct rcar_canfd_hw_info *info;
 554};
 555
 556/* CAN FD mode nominal rate constants */
 557static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
 558	.name = RCANFD_DRV_NAME,
 559	.tseg1_min = 2,
 560	.tseg1_max = 128,
 561	.tseg2_min = 2,
 562	.tseg2_max = 32,
 563	.sjw_max = 32,
 564	.brp_min = 1,
 565	.brp_max = 1024,
 566	.brp_inc = 1,
 567};
 568
 569/* CAN FD mode data rate constants */
 570static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
 571	.name = RCANFD_DRV_NAME,
 572	.tseg1_min = 2,
 573	.tseg1_max = 16,
 574	.tseg2_min = 2,
 575	.tseg2_max = 8,
 576	.sjw_max = 8,
 577	.brp_min = 1,
 578	.brp_max = 256,
 579	.brp_inc = 1,
 580};
 581
 582/* Classical CAN mode bitrate constants */
 583static const struct can_bittiming_const rcar_canfd_bittiming_const = {
 584	.name = RCANFD_DRV_NAME,
 585	.tseg1_min = 4,
 586	.tseg1_max = 16,
 587	.tseg2_min = 2,
 588	.tseg2_max = 8,
 589	.sjw_max = 4,
 590	.brp_min = 1,
 591	.brp_max = 1024,
 592	.brp_inc = 1,
 593};
 594
 595static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
 596	.max_channels = 2,
 597	.postdiv = 2,
 598	.shared_global_irqs = 1,
 599};
 600
 601static const struct rcar_canfd_hw_info rcar_gen4_hw_info = {
 602	.max_channels = 8,
 603	.postdiv = 2,
 604	.shared_global_irqs = 1,
 605};
 606
 607static const struct rcar_canfd_hw_info rzg2l_hw_info = {
 608	.max_channels = 2,
 609	.postdiv = 1,
 610	.multi_channel_irqs = 1,
 611};
 612
 613/* Helper functions */
 614static inline bool is_gen4(struct rcar_canfd_global *gpriv)
 615{
 616	return gpriv->info == &rcar_gen4_hw_info;
 617}
 618
 619static inline u32 reg_gen4(struct rcar_canfd_global *gpriv,
 620			   u32 gen4, u32 not_gen4)
 621{
 622	return is_gen4(gpriv) ? gen4 : not_gen4;
 623}
 624
 625static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
 626{
 627	u32 data = readl(reg);
 628
 629	data &= ~mask;
 630	data |= (val & mask);
 631	writel(data, reg);
 632}
 633
 634static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
 635{
 636	return readl(base + (offset));
 637}
 638
 639static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
 640{
 641	writel(val, base + (offset));
 642}
 643
 644static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
 645{
 646	rcar_canfd_update(val, val, base + (reg));
 647}
 648
 649static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
 650{
 651	rcar_canfd_update(val, 0, base + (reg));
 652}
 653
 654static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
 655				  u32 mask, u32 val)
 656{
 657	rcar_canfd_update(mask, val, base + (reg));
 658}
 659
 660static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
 661				struct canfd_frame *cf, u32 off)
 662{
 663	u32 i, lwords;
 664
 665	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 666	for (i = 0; i < lwords; i++)
 667		*((u32 *)cf->data + i) =
 668			rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
 669}
 670
 671static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
 672				struct canfd_frame *cf, u32 off)
 673{
 674	u32 i, lwords;
 675
 676	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 677	for (i = 0; i < lwords; i++)
 678		rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
 679				 *((u32 *)cf->data + i));
 680}
 681
 682static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
 683{
 684	u32 i;
 685
 686	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
 687		can_free_echo_skb(ndev, i, NULL);
 688}
 689
 690static void rcar_canfd_set_mode(struct rcar_canfd_global *gpriv)
 691{
 692	if (is_gen4(gpriv)) {
 693		u32 ch, val = gpriv->fdmode ? RCANFD_GEN4_FDCFG_FDOE
 694					    : RCANFD_GEN4_FDCFG_CLOE;
 695
 696		for_each_set_bit(ch, &gpriv->channels_mask,
 697				 gpriv->info->max_channels)
 698			rcar_canfd_set_bit(gpriv->base, RCANFD_GEN4_FDCFG(ch),
 699					   val);
 700	} else {
 701		if (gpriv->fdmode)
 702			rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
 703					   RCANFD_GRMCFG_RCMC);
 704		else
 705			rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
 706					     RCANFD_GRMCFG_RCMC);
 707	}
 708}
 709
 710static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
 711{
 712	u32 sts, ch;
 713	int err;
 714
 715	/* Check RAMINIT flag as CAN RAM initialization takes place
 716	 * after the MCU reset
 717	 */
 718	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 719				 !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
 720	if (err) {
 721		dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
 722		return err;
 723	}
 724
 725	/* Transition to Global Reset mode */
 726	rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
 727	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
 728			      RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
 729
 730	/* Ensure Global reset mode */
 731	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 732				 (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
 733	if (err) {
 734		dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
 735		return err;
 736	}
 737
 738	/* Reset Global error flags */
 739	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
 740
 741	/* Set the controller into appropriate mode */
 742	rcar_canfd_set_mode(gpriv);
 
 
 
 
 
 743
 744	/* Transition all Channels to reset mode */
 745	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
 746		rcar_canfd_clear_bit(gpriv->base,
 747				     RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
 748
 749		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 750				      RCANFD_CCTR_CHMDC_MASK,
 751				      RCANFD_CCTR_CHDMC_CRESET);
 752
 753		/* Ensure Channel reset mode */
 754		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
 755					 (sts & RCANFD_CSTS_CRSTSTS),
 756					 2, 500000);
 757		if (err) {
 758			dev_dbg(&gpriv->pdev->dev,
 759				"channel %u reset failed\n", ch);
 760			return err;
 761		}
 762	}
 763	return 0;
 764}
 765
 766static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
 767{
 768	u32 cfg, ch;
 769
 770	/* Global configuration settings */
 771
 772	/* ECC Error flag Enable */
 773	cfg = RCANFD_GCFG_EEFE;
 774
 775	if (gpriv->fdmode)
 776		/* Truncate payload to configured message size RFPLS */
 777		cfg |= RCANFD_GCFG_CMPOC;
 778
 779	/* Set External Clock if selected */
 780	if (gpriv->fcan != RCANFD_CANFDCLK)
 781		cfg |= RCANFD_GCFG_DCS;
 782
 783	rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
 784
 785	/* Channel configuration settings */
 786	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
 787		rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
 788				   RCANFD_CCTR_ERRD);
 789		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 790				      RCANFD_CCTR_BOM_MASK,
 791				      RCANFD_CCTR_BOM_BENTRY);
 792	}
 793}
 794
 795static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 796					   u32 ch)
 797{
 798	u32 cfg;
 799	int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
 800	u32 ridx = ch + RCANFD_RFFIFO_IDX;
 801
 802	if (ch == 0) {
 803		start = 0; /* Channel 0 always starts from 0th rule */
 804	} else {
 805		/* Get number of Channel 0 rules and adjust */
 806		cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG(ch));
 807		start = RCANFD_GAFLCFG_GETRNC(gpriv, 0, cfg);
 808	}
 809
 810	/* Enable write access to entry */
 811	page = RCANFD_GAFL_PAGENUM(start);
 812	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
 813			   (RCANFD_GAFLECTR_AFLPN(gpriv, page) |
 814			    RCANFD_GAFLECTR_AFLDAE));
 815
 816	/* Write number of rules for channel */
 817	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG(ch),
 818			   RCANFD_GAFLCFG_SETRNC(gpriv, ch, num_rules));
 819	if (is_gen4(gpriv))
 820		offset = RCANFD_GEN4_GAFL_OFFSET;
 821	else if (gpriv->fdmode)
 822		offset = RCANFD_F_GAFL_OFFSET;
 823	else
 824		offset = RCANFD_C_GAFL_OFFSET;
 825
 826	/* Accept all IDs */
 827	rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
 828	/* IDE or RTR is not considered for matching */
 829	rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
 830	/* Any data length accepted */
 831	rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
 832	/* Place the msg in corresponding Rx FIFO entry */
 833	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, start),
 834			   RCANFD_GAFLP1_GAFLFDP(ridx));
 835
 836	/* Disable write access to page */
 837	rcar_canfd_clear_bit(gpriv->base,
 838			     RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
 839}
 840
 841static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
 842{
 843	/* Rx FIFO is used for reception */
 844	u32 cfg;
 845	u16 rfdc, rfpls;
 846
 847	/* Select Rx FIFO based on channel */
 848	u32 ridx = ch + RCANFD_RFFIFO_IDX;
 849
 850	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
 851	if (gpriv->fdmode)
 852		rfpls = 7;	/* b111 - Max 64 bytes payload */
 853	else
 854		rfpls = 0;	/* b000 - Max 8 bytes payload */
 855
 856	cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
 857		RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
 858	rcar_canfd_write(gpriv->base, RCANFD_RFCC(gpriv, ridx), cfg);
 859}
 860
 861static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
 862{
 863	/* Tx/Rx(Common) FIFO configured in Tx mode is
 864	 * used for transmission
 865	 *
 866	 * Each channel has 3 Common FIFO dedicated to them.
 867	 * Use the 1st (index 0) out of 3
 868	 */
 869	u32 cfg;
 870	u16 cftml, cfm, cfdc, cfpls;
 871
 872	cftml = 0;		/* 0th buffer */
 873	cfm = 1;		/* b01 - Transmit mode */
 874	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
 875	if (gpriv->fdmode)
 876		cfpls = 7;	/* b111 - Max 64 bytes payload */
 877	else
 878		cfpls = 0;	/* b000 - Max 8 bytes payload */
 879
 880	cfg = (RCANFD_CFCC_CFTML(gpriv, cftml) | RCANFD_CFCC_CFM(gpriv, cfm) |
 881		RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(gpriv, cfdc) |
 882		RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
 883	rcar_canfd_write(gpriv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), cfg);
 884
 885	if (gpriv->fdmode)
 886		/* Clear FD mode specific control/status register */
 887		rcar_canfd_write(gpriv->base,
 888				 RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), 0);
 889}
 890
 891static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
 892{
 893	u32 ctr;
 894
 895	/* Clear any stray error interrupt flags */
 896	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 897
 898	/* Global interrupts setup */
 899	ctr = RCANFD_GCTR_MEIE;
 900	if (gpriv->fdmode)
 901		ctr |= RCANFD_GCTR_CFMPOFIE;
 902
 903	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
 904}
 905
 906static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
 907						 *gpriv)
 908{
 909	/* Disable all interrupts */
 910	rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
 911
 912	/* Clear any stray error interrupt flags */
 913	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 914}
 915
 916static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
 917						 *priv)
 918{
 919	u32 ctr, ch = priv->channel;
 920
 921	/* Clear any stray error flags */
 922	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 923
 924	/* Channel interrupts setup */
 925	ctr = (RCANFD_CCTR_TAIE |
 926	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 927	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 928	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 929	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 930	rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
 931}
 932
 933static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
 934						  *priv)
 935{
 936	u32 ctr, ch = priv->channel;
 937
 938	ctr = (RCANFD_CCTR_TAIE |
 939	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 940	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 941	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 942	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 943	rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
 944
 945	/* Clear any stray error flags */
 946	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 947}
 948
 949static void rcar_canfd_global_error(struct net_device *ndev)
 950{
 951	struct rcar_canfd_channel *priv = netdev_priv(ndev);
 952	struct rcar_canfd_global *gpriv = priv->gpriv;
 953	struct net_device_stats *stats = &ndev->stats;
 954	u32 ch = priv->channel;
 955	u32 gerfl, sts;
 956	u32 ridx = ch + RCANFD_RFFIFO_IDX;
 957
 958	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
 959	if (gerfl & RCANFD_GERFL_EEF(ch)) {
 960		netdev_dbg(ndev, "Ch%u: ECC Error flag\n", ch);
 
 
 
 
 961		stats->tx_dropped++;
 962	}
 963	if (gerfl & RCANFD_GERFL_MES) {
 964		sts = rcar_canfd_read(priv->base,
 965				      RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
 966		if (sts & RCANFD_CFSTS_CFMLT) {
 967			netdev_dbg(ndev, "Tx Message Lost flag\n");
 968			stats->tx_dropped++;
 969			rcar_canfd_write(priv->base,
 970					 RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
 971					 sts & ~RCANFD_CFSTS_CFMLT);
 972		}
 973
 974		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
 975		if (sts & RCANFD_RFSTS_RFMLT) {
 976			netdev_dbg(ndev, "Rx Message Lost flag\n");
 977			stats->rx_dropped++;
 978			rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
 979					 sts & ~RCANFD_RFSTS_RFMLT);
 980		}
 981	}
 982	if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
 983		/* Message Lost flag will be set for respective channel
 984		 * when this condition happens with counters and flags
 985		 * already updated.
 986		 */
 987		netdev_dbg(ndev, "global payload overflow interrupt\n");
 988	}
 989
 990	/* Clear all global error interrupts. Only affected channels bits
 991	 * get cleared
 992	 */
 993	rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
 994}
 995
 996static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
 997			     u16 txerr, u16 rxerr)
 998{
 999	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1000	struct net_device_stats *stats = &ndev->stats;
1001	struct can_frame *cf;
1002	struct sk_buff *skb;
1003	u32 ch = priv->channel;
1004
1005	netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
1006
1007	/* Propagate the error condition to the CAN stack */
1008	skb = alloc_can_err_skb(ndev, &cf);
1009	if (!skb) {
1010		stats->rx_dropped++;
1011		return;
1012	}
1013
1014	/* Channel error interrupts */
1015	if (cerfl & RCANFD_CERFL_BEF) {
1016		netdev_dbg(ndev, "Bus error\n");
1017		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
1018		cf->data[2] = CAN_ERR_PROT_UNSPEC;
1019		priv->can.can_stats.bus_error++;
1020	}
1021	if (cerfl & RCANFD_CERFL_ADERR) {
1022		netdev_dbg(ndev, "ACK Delimiter Error\n");
1023		stats->tx_errors++;
1024		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
1025	}
1026	if (cerfl & RCANFD_CERFL_B0ERR) {
1027		netdev_dbg(ndev, "Bit Error (dominant)\n");
1028		stats->tx_errors++;
1029		cf->data[2] |= CAN_ERR_PROT_BIT0;
1030	}
1031	if (cerfl & RCANFD_CERFL_B1ERR) {
1032		netdev_dbg(ndev, "Bit Error (recessive)\n");
1033		stats->tx_errors++;
1034		cf->data[2] |= CAN_ERR_PROT_BIT1;
1035	}
1036	if (cerfl & RCANFD_CERFL_CERR) {
1037		netdev_dbg(ndev, "CRC Error\n");
1038		stats->rx_errors++;
1039		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1040	}
1041	if (cerfl & RCANFD_CERFL_AERR) {
1042		netdev_dbg(ndev, "ACK Error\n");
1043		stats->tx_errors++;
1044		cf->can_id |= CAN_ERR_ACK;
1045		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
1046	}
1047	if (cerfl & RCANFD_CERFL_FERR) {
1048		netdev_dbg(ndev, "Form Error\n");
1049		stats->rx_errors++;
1050		cf->data[2] |= CAN_ERR_PROT_FORM;
1051	}
1052	if (cerfl & RCANFD_CERFL_SERR) {
1053		netdev_dbg(ndev, "Stuff Error\n");
1054		stats->rx_errors++;
1055		cf->data[2] |= CAN_ERR_PROT_STUFF;
1056	}
1057	if (cerfl & RCANFD_CERFL_ALF) {
1058		netdev_dbg(ndev, "Arbitration lost Error\n");
1059		priv->can.can_stats.arbitration_lost++;
1060		cf->can_id |= CAN_ERR_LOSTARB;
1061		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
1062	}
1063	if (cerfl & RCANFD_CERFL_BLF) {
1064		netdev_dbg(ndev, "Bus Lock Error\n");
1065		stats->rx_errors++;
1066		cf->can_id |= CAN_ERR_BUSERROR;
1067	}
1068	if (cerfl & RCANFD_CERFL_EWF) {
1069		netdev_dbg(ndev, "Error warning interrupt\n");
1070		priv->can.state = CAN_STATE_ERROR_WARNING;
1071		priv->can.can_stats.error_warning++;
1072		cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1073		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
1074			CAN_ERR_CRTL_RX_WARNING;
1075		cf->data[6] = txerr;
1076		cf->data[7] = rxerr;
1077	}
1078	if (cerfl & RCANFD_CERFL_EPF) {
1079		netdev_dbg(ndev, "Error passive interrupt\n");
1080		priv->can.state = CAN_STATE_ERROR_PASSIVE;
1081		priv->can.can_stats.error_passive++;
1082		cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1083		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1084			CAN_ERR_CRTL_RX_PASSIVE;
1085		cf->data[6] = txerr;
1086		cf->data[7] = rxerr;
1087	}
1088	if (cerfl & RCANFD_CERFL_BOEF) {
1089		netdev_dbg(ndev, "Bus-off entry interrupt\n");
1090		rcar_canfd_tx_failure_cleanup(ndev);
1091		priv->can.state = CAN_STATE_BUS_OFF;
1092		priv->can.can_stats.bus_off++;
1093		can_bus_off(ndev);
1094		cf->can_id |= CAN_ERR_BUSOFF;
1095	}
1096	if (cerfl & RCANFD_CERFL_OVLF) {
1097		netdev_dbg(ndev,
1098			   "Overload Frame Transmission error interrupt\n");
1099		stats->tx_errors++;
1100		cf->can_id |= CAN_ERR_PROT;
1101		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1102	}
1103
1104	/* Clear channel error interrupts that are handled */
1105	rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1106			 RCANFD_CERFL_ERR(~cerfl));
 
 
1107	netif_rx(skb);
1108}
1109
1110static void rcar_canfd_tx_done(struct net_device *ndev)
1111{
1112	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1113	struct rcar_canfd_global *gpriv = priv->gpriv;
1114	struct net_device_stats *stats = &ndev->stats;
1115	u32 sts;
1116	unsigned long flags;
1117	u32 ch = priv->channel;
1118
1119	do {
1120		u8 unsent, sent;
1121
1122		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1123		stats->tx_packets++;
1124		stats->tx_bytes += can_get_echo_skb(ndev, sent, NULL);
 
 
1125
1126		spin_lock_irqsave(&priv->tx_lock, flags);
1127		priv->tx_tail++;
1128		sts = rcar_canfd_read(priv->base,
1129				      RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1130		unsent = RCANFD_CFSTS_CFMC(sts);
1131
1132		/* Wake producer only when there is room */
1133		if (unsent != RCANFD_FIFO_DEPTH)
1134			netif_wake_queue(ndev);
1135
1136		if (priv->tx_head - priv->tx_tail <= unsent) {
1137			spin_unlock_irqrestore(&priv->tx_lock, flags);
1138			break;
1139		}
1140		spin_unlock_irqrestore(&priv->tx_lock, flags);
1141
1142	} while (1);
1143
1144	/* Clear interrupt */
1145	rcar_canfd_write(priv->base, RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
1146			 sts & ~RCANFD_CFSTS_CFTXIF);
1147}
1148
1149static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch)
1150{
1151	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1152	struct net_device *ndev = priv->ndev;
1153	u32 gerfl;
1154
1155	/* Handle global error interrupts */
1156	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1157	if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1158		rcar_canfd_global_error(ndev);
1159}
1160
1161static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
1162{
1163	struct rcar_canfd_global *gpriv = dev_id;
1164	u32 ch;
1165
1166	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1167		rcar_canfd_handle_global_err(gpriv, ch);
1168
1169	return IRQ_HANDLED;
1170}
1171
1172static void rcar_canfd_handle_global_receive(struct rcar_canfd_global *gpriv, u32 ch)
1173{
1174	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1175	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1176	u32 sts, cc;
1177
1178	/* Handle Rx interrupts */
1179	sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1180	cc = rcar_canfd_read(priv->base, RCANFD_RFCC(gpriv, ridx));
1181	if (likely(sts & RCANFD_RFSTS_RFIF &&
1182		   cc & RCANFD_RFCC_RFIE)) {
1183		if (napi_schedule_prep(&priv->napi)) {
1184			/* Disable Rx FIFO interrupts */
1185			rcar_canfd_clear_bit(priv->base,
1186					     RCANFD_RFCC(gpriv, ridx),
1187					     RCANFD_RFCC_RFIE);
1188			__napi_schedule(&priv->napi);
1189		}
1190	}
1191}
1192
1193static irqreturn_t rcar_canfd_global_receive_fifo_interrupt(int irq, void *dev_id)
1194{
1195	struct rcar_canfd_global *gpriv = dev_id;
1196	u32 ch;
1197
1198	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1199		rcar_canfd_handle_global_receive(gpriv, ch);
1200
1201	return IRQ_HANDLED;
1202}
1203
1204static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1205{
1206	struct rcar_canfd_global *gpriv = dev_id;
1207	u32 ch;
 
 
 
1208
1209	/* Global error interrupts still indicate a condition specific
1210	 * to a channel. RxFIFO interrupt is a global interrupt.
1211	 */
1212	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1213		rcar_canfd_handle_global_err(gpriv, ch);
1214		rcar_canfd_handle_global_receive(gpriv, ch);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1215	}
1216	return IRQ_HANDLED;
1217}
1218
1219static void rcar_canfd_state_change(struct net_device *ndev,
1220				    u16 txerr, u16 rxerr)
1221{
1222	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1223	struct net_device_stats *stats = &ndev->stats;
1224	enum can_state rx_state, tx_state, state = priv->can.state;
1225	struct can_frame *cf;
1226	struct sk_buff *skb;
1227
1228	/* Handle transition from error to normal states */
1229	if (txerr < 96 && rxerr < 96)
1230		state = CAN_STATE_ERROR_ACTIVE;
1231	else if (txerr < 128 && rxerr < 128)
1232		state = CAN_STATE_ERROR_WARNING;
1233
1234	if (state != priv->can.state) {
1235		netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1236			   state, priv->can.state, txerr, rxerr);
1237		skb = alloc_can_err_skb(ndev, &cf);
1238		if (!skb) {
1239			stats->rx_dropped++;
1240			return;
1241		}
1242		tx_state = txerr >= rxerr ? state : 0;
1243		rx_state = txerr <= rxerr ? state : 0;
1244
1245		can_change_state(ndev, cf, tx_state, rx_state);
 
 
1246		netif_rx(skb);
1247	}
1248}
1249
1250static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
1251{
1252	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1253	struct net_device *ndev = priv->ndev;
1254	u32 sts;
1255
1256	/* Handle Tx interrupts */
1257	sts = rcar_canfd_read(priv->base,
1258			      RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1259	if (likely(sts & RCANFD_CFSTS_CFTXIF))
1260		rcar_canfd_tx_done(ndev);
1261}
1262
1263static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id)
1264{
1265	struct rcar_canfd_channel *priv = dev_id;
1266
1267	rcar_canfd_handle_channel_tx(priv->gpriv, priv->channel);
1268
1269	return IRQ_HANDLED;
1270}
1271
1272static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch)
1273{
1274	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1275	struct net_device *ndev = priv->ndev;
1276	u16 txerr, rxerr;
1277	u32 sts, cerfl;
1278
1279	/* Handle channel error interrupts */
1280	cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1281	sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1282	txerr = RCANFD_CSTS_TECCNT(sts);
1283	rxerr = RCANFD_CSTS_RECCNT(sts);
1284	if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1285		rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1286
1287	/* Handle state change to lower states */
1288	if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
1289		     priv->can.state != CAN_STATE_BUS_OFF))
1290		rcar_canfd_state_change(ndev, txerr, rxerr);
1291}
1292
1293static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id)
1294{
1295	struct rcar_canfd_channel *priv = dev_id;
1296
1297	rcar_canfd_handle_channel_err(priv->gpriv, priv->channel);
1298
1299	return IRQ_HANDLED;
1300}
1301
1302static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1303{
1304	struct rcar_canfd_global *gpriv = dev_id;
1305	u32 ch;
 
 
 
1306
1307	/* Common FIFO is a per channel resource */
1308	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1309		rcar_canfd_handle_channel_err(gpriv, ch);
1310		rcar_canfd_handle_channel_tx(gpriv, ch);
1311	}
 
 
 
 
 
 
 
 
 
 
 
 
1312
 
 
 
 
 
 
1313	return IRQ_HANDLED;
1314}
1315
1316static void rcar_canfd_set_bittiming(struct net_device *dev)
1317{
1318	struct rcar_canfd_channel *priv = netdev_priv(dev);
1319	struct rcar_canfd_global *gpriv = priv->gpriv;
1320	const struct can_bittiming *bt = &priv->can.bittiming;
1321	const struct can_bittiming *dbt = &priv->can.data_bittiming;
1322	u16 brp, sjw, tseg1, tseg2;
1323	u32 cfg;
1324	u32 ch = priv->channel;
1325
1326	/* Nominal bit timing settings */
1327	brp = bt->brp - 1;
1328	sjw = bt->sjw - 1;
1329	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1330	tseg2 = bt->phase_seg2 - 1;
1331
1332	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1333		/* CAN FD only mode */
1334		cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) | RCANFD_NCFG_NBRP(brp) |
1335		       RCANFD_NCFG_NSJW(gpriv, sjw) | RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1336
1337		rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1338		netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1339			   brp, sjw, tseg1, tseg2);
1340
1341		/* Data bit timing settings */
1342		brp = dbt->brp - 1;
1343		sjw = dbt->sjw - 1;
1344		tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1345		tseg2 = dbt->phase_seg2 - 1;
1346
1347		cfg = (RCANFD_DCFG_DTSEG1(gpriv, tseg1) | RCANFD_DCFG_DBRP(brp) |
1348		       RCANFD_DCFG_DSJW(gpriv, sjw) | RCANFD_DCFG_DTSEG2(gpriv, tseg2));
1349
1350		rcar_canfd_write(priv->base, RCANFD_F_DCFG(gpriv, ch), cfg);
1351		netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1352			   brp, sjw, tseg1, tseg2);
1353	} else {
1354		/* Classical CAN only mode */
1355		if (is_gen4(gpriv)) {
1356			cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) |
1357			       RCANFD_NCFG_NBRP(brp) |
1358			       RCANFD_NCFG_NSJW(gpriv, sjw) |
1359			       RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1360		} else {
1361			cfg = (RCANFD_CFG_TSEG1(tseg1) |
1362			       RCANFD_CFG_BRP(brp) |
1363			       RCANFD_CFG_SJW(sjw) |
1364			       RCANFD_CFG_TSEG2(tseg2));
1365		}
1366
1367		rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1368		netdev_dbg(priv->ndev,
1369			   "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1370			   brp, sjw, tseg1, tseg2);
1371	}
1372}
1373
1374static int rcar_canfd_start(struct net_device *ndev)
1375{
1376	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1377	struct rcar_canfd_global *gpriv = priv->gpriv;
1378	int err = -EOPNOTSUPP;
1379	u32 sts, ch = priv->channel;
1380	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1381
1382	rcar_canfd_set_bittiming(ndev);
1383
1384	rcar_canfd_enable_channel_interrupts(priv);
1385
1386	/* Set channel to Operational mode */
1387	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1388			      RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1389
1390	/* Verify channel mode change */
1391	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1392				 (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1393	if (err) {
1394		netdev_err(ndev, "channel %u communication state failed\n", ch);
1395		goto fail_mode_change;
1396	}
1397
1398	/* Enable Common & Rx FIFO */
1399	rcar_canfd_set_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1400			   RCANFD_CFCC_CFE);
1401	rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1402
1403	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1404	return 0;
1405
1406fail_mode_change:
1407	rcar_canfd_disable_channel_interrupts(priv);
1408	return err;
1409}
1410
1411static int rcar_canfd_open(struct net_device *ndev)
1412{
1413	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1414	struct rcar_canfd_global *gpriv = priv->gpriv;
1415	int err;
1416
1417	err = phy_power_on(priv->transceiver);
1418	if (err) {
1419		netdev_err(ndev, "failed to power on PHY: %pe\n", ERR_PTR(err));
1420		return err;
1421	}
1422
1423	/* Peripheral clock is already enabled in probe */
1424	err = clk_prepare_enable(gpriv->can_clk);
1425	if (err) {
1426		netdev_err(ndev, "failed to enable CAN clock: %pe\n", ERR_PTR(err));
1427		goto out_phy;
1428	}
1429
1430	err = open_candev(ndev);
1431	if (err) {
1432		netdev_err(ndev, "open_candev() failed: %pe\n", ERR_PTR(err));
1433		goto out_can_clock;
1434	}
1435
1436	napi_enable(&priv->napi);
1437	err = rcar_canfd_start(ndev);
1438	if (err)
1439		goto out_close;
1440	netif_start_queue(ndev);
 
1441	return 0;
1442out_close:
1443	napi_disable(&priv->napi);
1444	close_candev(ndev);
1445out_can_clock:
1446	clk_disable_unprepare(gpriv->can_clk);
1447out_phy:
1448	phy_power_off(priv->transceiver);
1449	return err;
1450}
1451
1452static void rcar_canfd_stop(struct net_device *ndev)
1453{
1454	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1455	struct rcar_canfd_global *gpriv = priv->gpriv;
1456	int err;
1457	u32 sts, ch = priv->channel;
1458	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1459
1460	/* Transition to channel reset mode  */
1461	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1462			      RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1463
1464	/* Check Channel reset mode */
1465	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1466				 (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1467	if (err)
1468		netdev_err(ndev, "channel %u reset failed\n", ch);
1469
1470	rcar_canfd_disable_channel_interrupts(priv);
1471
1472	/* Disable Common & Rx FIFO */
1473	rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1474			     RCANFD_CFCC_CFE);
1475	rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1476
1477	/* Set the state as STOPPED */
1478	priv->can.state = CAN_STATE_STOPPED;
1479}
1480
1481static int rcar_canfd_close(struct net_device *ndev)
1482{
1483	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1484	struct rcar_canfd_global *gpriv = priv->gpriv;
1485
1486	netif_stop_queue(ndev);
1487	rcar_canfd_stop(ndev);
1488	napi_disable(&priv->napi);
1489	clk_disable_unprepare(gpriv->can_clk);
1490	close_candev(ndev);
1491	phy_power_off(priv->transceiver);
1492	return 0;
1493}
1494
1495static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1496					 struct net_device *ndev)
1497{
1498	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1499	struct rcar_canfd_global *gpriv = priv->gpriv;
1500	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1501	u32 sts = 0, id, dlc;
1502	unsigned long flags;
1503	u32 ch = priv->channel;
1504
1505	if (can_dev_dropped_skb(ndev, skb))
1506		return NETDEV_TX_OK;
1507
1508	if (cf->can_id & CAN_EFF_FLAG) {
1509		id = cf->can_id & CAN_EFF_MASK;
1510		id |= RCANFD_CFID_CFIDE;
1511	} else {
1512		id = cf->can_id & CAN_SFF_MASK;
1513	}
1514
1515	if (cf->can_id & CAN_RTR_FLAG)
1516		id |= RCANFD_CFID_CFRTR;
1517
1518	dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len));
1519
1520	if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1521		rcar_canfd_write(priv->base,
1522				 RCANFD_F_CFID(gpriv, ch, RCANFD_CFFIFO_IDX), id);
1523		rcar_canfd_write(priv->base,
1524				 RCANFD_F_CFPTR(gpriv, ch, RCANFD_CFFIFO_IDX), dlc);
1525
1526		if (can_is_canfd_skb(skb)) {
1527			/* CAN FD frame format */
1528			sts |= RCANFD_CFFDCSTS_CFFDF;
1529			if (cf->flags & CANFD_BRS)
1530				sts |= RCANFD_CFFDCSTS_CFBRS;
1531
1532			if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1533				sts |= RCANFD_CFFDCSTS_CFESI;
1534		}
1535
1536		rcar_canfd_write(priv->base,
1537				 RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), sts);
1538
1539		rcar_canfd_put_data(priv, cf,
1540				    RCANFD_F_CFDF(gpriv, ch, RCANFD_CFFIFO_IDX, 0));
1541	} else {
1542		rcar_canfd_write(priv->base,
1543				 RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1544		rcar_canfd_write(priv->base,
1545				 RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1546		rcar_canfd_put_data(priv, cf,
1547				    RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1548	}
1549
1550	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0);
 
1551
1552	spin_lock_irqsave(&priv->tx_lock, flags);
1553	priv->tx_head++;
1554
1555	/* Stop the queue if we've filled all FIFO entries */
1556	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1557		netif_stop_queue(ndev);
1558
1559	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
1560	 * pointer for the Common FIFO
1561	 */
1562	rcar_canfd_write(priv->base,
1563			 RCANFD_CFPCTR(gpriv, ch, RCANFD_CFFIFO_IDX), 0xff);
1564
1565	spin_unlock_irqrestore(&priv->tx_lock, flags);
1566	return NETDEV_TX_OK;
1567}
1568
1569static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1570{
1571	struct net_device_stats *stats = &priv->ndev->stats;
1572	struct rcar_canfd_global *gpriv = priv->gpriv;
1573	struct canfd_frame *cf;
1574	struct sk_buff *skb;
1575	u32 sts = 0, id, dlc;
1576	u32 ch = priv->channel;
1577	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1578
1579	if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1580		id = rcar_canfd_read(priv->base, RCANFD_F_RFID(gpriv, ridx));
1581		dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(gpriv, ridx));
1582
1583		sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(gpriv, ridx));
1584
1585		if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) &&
1586		    sts & RCANFD_RFFDSTS_RFFDF)
1587			skb = alloc_canfd_skb(priv->ndev, &cf);
1588		else
1589			skb = alloc_can_skb(priv->ndev,
1590					    (struct can_frame **)&cf);
1591	} else {
1592		id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1593		dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1594		skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1595	}
1596
1597	if (!skb) {
1598		stats->rx_dropped++;
1599		return;
1600	}
1601
1602	if (id & RCANFD_RFID_RFIDE)
1603		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1604	else
1605		cf->can_id = id & CAN_SFF_MASK;
1606
1607	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1608		if (sts & RCANFD_RFFDSTS_RFFDF)
1609			cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1610		else
1611			cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1612
1613		if (sts & RCANFD_RFFDSTS_RFESI) {
1614			cf->flags |= CANFD_ESI;
1615			netdev_dbg(priv->ndev, "ESI Error\n");
1616		}
1617
1618		if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1619			cf->can_id |= CAN_RTR_FLAG;
1620		} else {
1621			if (sts & RCANFD_RFFDSTS_RFBRS)
1622				cf->flags |= CANFD_BRS;
1623
1624			rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1625		}
1626	} else {
1627		cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1628		if (id & RCANFD_RFID_RFRTR)
1629			cf->can_id |= CAN_RTR_FLAG;
1630		else if (is_gen4(gpriv))
1631			rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1632		else
1633			rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1634	}
1635
1636	/* Write 0xff to RFPC to increment the CPU-side
1637	 * pointer of the Rx FIFO
1638	 */
1639	rcar_canfd_write(priv->base, RCANFD_RFPCTR(gpriv, ridx), 0xff);
 
 
1640
1641	if (!(cf->can_id & CAN_RTR_FLAG))
1642		stats->rx_bytes += cf->len;
1643	stats->rx_packets++;
1644	netif_receive_skb(skb);
1645}
1646
1647static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1648{
1649	struct rcar_canfd_channel *priv =
1650		container_of(napi, struct rcar_canfd_channel, napi);
1651	struct rcar_canfd_global *gpriv = priv->gpriv;
1652	int num_pkts;
1653	u32 sts;
1654	u32 ch = priv->channel;
1655	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1656
1657	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1658		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1659		/* Check FIFO empty condition */
1660		if (sts & RCANFD_RFSTS_RFEMP)
1661			break;
1662
1663		rcar_canfd_rx_pkt(priv);
1664
1665		/* Clear interrupt bit */
1666		if (sts & RCANFD_RFSTS_RFIF)
1667			rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
1668					 sts & ~RCANFD_RFSTS_RFIF);
1669	}
1670
1671	/* All packets processed */
1672	if (num_pkts < quota) {
1673		if (napi_complete_done(napi, num_pkts)) {
1674			/* Enable Rx FIFO interrupts */
1675			rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx),
1676					   RCANFD_RFCC_RFIE);
1677		}
1678	}
1679	return num_pkts;
1680}
1681
1682static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1683{
1684	int err;
1685
1686	switch (mode) {
1687	case CAN_MODE_START:
1688		err = rcar_canfd_start(ndev);
1689		if (err)
1690			return err;
1691		netif_wake_queue(ndev);
1692		return 0;
1693	default:
1694		return -EOPNOTSUPP;
1695	}
1696}
1697
1698static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1699				       struct can_berr_counter *bec)
1700{
1701	struct rcar_canfd_channel *priv = netdev_priv(dev);
1702	u32 val, ch = priv->channel;
1703
1704	/* Peripheral clock is already enabled in probe */
1705	val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1706	bec->txerr = RCANFD_CSTS_TECCNT(val);
1707	bec->rxerr = RCANFD_CSTS_RECCNT(val);
1708	return 0;
1709}
1710
1711static const struct net_device_ops rcar_canfd_netdev_ops = {
1712	.ndo_open = rcar_canfd_open,
1713	.ndo_stop = rcar_canfd_close,
1714	.ndo_start_xmit = rcar_canfd_start_xmit,
1715	.ndo_change_mtu = can_change_mtu,
1716};
1717
1718static const struct ethtool_ops rcar_canfd_ethtool_ops = {
1719	.get_ts_info = ethtool_op_get_ts_info,
1720};
1721
1722static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1723				    u32 fcan_freq, struct phy *transceiver)
1724{
1725	const struct rcar_canfd_hw_info *info = gpriv->info;
1726	struct platform_device *pdev = gpriv->pdev;
1727	struct device *dev = &pdev->dev;
1728	struct rcar_canfd_channel *priv;
1729	struct net_device *ndev;
1730	int err = -ENODEV;
1731
1732	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1733	if (!ndev)
1734		return -ENOMEM;
1735
 
 
1736	priv = netdev_priv(ndev);
1737
1738	ndev->netdev_ops = &rcar_canfd_netdev_ops;
1739	ndev->ethtool_ops = &rcar_canfd_ethtool_ops;
1740	ndev->flags |= IFF_ECHO;
1741	priv->ndev = ndev;
1742	priv->base = gpriv->base;
1743	priv->transceiver = transceiver;
1744	priv->channel = ch;
1745	priv->gpriv = gpriv;
1746	if (transceiver)
1747		priv->can.bitrate_max = transceiver->attrs.max_link_rate;
1748	priv->can.clock.freq = fcan_freq;
1749	dev_info(dev, "can_clk rate is %u\n", priv->can.clock.freq);
1750
1751	if (info->multi_channel_irqs) {
1752		char *irq_name;
1753		int err_irq;
1754		int tx_irq;
1755
1756		err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
1757		if (err_irq < 0) {
1758			err = err_irq;
1759			goto fail;
1760		}
1761
1762		tx_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_trx" : "ch1_trx");
1763		if (tx_irq < 0) {
1764			err = tx_irq;
1765			goto fail;
1766		}
1767
1768		irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_err",
1769					  ch);
1770		if (!irq_name) {
1771			err = -ENOMEM;
1772			goto fail;
1773		}
1774		err = devm_request_irq(dev, err_irq,
1775				       rcar_canfd_channel_err_interrupt, 0,
1776				       irq_name, priv);
1777		if (err) {
1778			dev_err(dev, "devm_request_irq CH Err %d failed: %pe\n",
1779				err_irq, ERR_PTR(err));
1780			goto fail;
1781		}
1782		irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_trx",
1783					  ch);
1784		if (!irq_name) {
1785			err = -ENOMEM;
1786			goto fail;
1787		}
1788		err = devm_request_irq(dev, tx_irq,
1789				       rcar_canfd_channel_tx_interrupt, 0,
1790				       irq_name, priv);
1791		if (err) {
1792			dev_err(dev, "devm_request_irq Tx %d failed: %pe\n",
1793				tx_irq, ERR_PTR(err));
1794			goto fail;
1795		}
1796	}
1797
1798	if (gpriv->fdmode) {
1799		priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1800		priv->can.data_bittiming_const =
1801			&rcar_canfd_data_bittiming_const;
1802
1803		/* Controller starts in CAN FD only mode */
1804		err = can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1805		if (err)
1806			goto fail;
1807		priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1808	} else {
1809		/* Controller starts in Classical CAN only mode */
1810		priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1811		priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1812	}
1813
1814	priv->can.do_set_mode = rcar_canfd_do_set_mode;
1815	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1816	SET_NETDEV_DEV(ndev, dev);
 
1817
1818	netif_napi_add_weight(ndev, &priv->napi, rcar_canfd_rx_poll,
1819			      RCANFD_NAPI_WEIGHT);
1820	spin_lock_init(&priv->tx_lock);
1821	gpriv->ch[priv->channel] = priv;
1822	err = register_candev(ndev);
1823	if (err) {
1824		dev_err(dev, "register_candev() failed: %pe\n", ERR_PTR(err));
 
1825		goto fail_candev;
1826	}
1827	dev_info(dev, "device registered (channel %u)\n", priv->channel);
 
 
 
1828	return 0;
1829
1830fail_candev:
1831	netif_napi_del(&priv->napi);
1832fail:
1833	free_candev(ndev);
 
1834	return err;
1835}
1836
1837static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1838{
1839	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1840
1841	if (priv) {
1842		unregister_candev(priv->ndev);
1843		netif_napi_del(&priv->napi);
1844		free_candev(priv->ndev);
1845	}
1846}
1847
1848static int rcar_canfd_probe(struct platform_device *pdev)
1849{
1850	struct phy *transceivers[RCANFD_NUM_CHANNELS] = { NULL, };
1851	const struct rcar_canfd_hw_info *info;
1852	struct device *dev = &pdev->dev;
1853	void __iomem *addr;
1854	u32 sts, ch, fcan_freq;
1855	struct rcar_canfd_global *gpriv;
1856	struct device_node *of_child;
1857	unsigned long channels_mask = 0;
1858	int err, ch_irq, g_irq;
1859	int g_err_irq, g_recc_irq;
1860	bool fdmode = true;			/* CAN FD only mode - default */
1861	char name[9] = "channelX";
1862	int i;
1863
1864	info = of_device_get_match_data(dev);
1865
1866	if (of_property_read_bool(dev->of_node, "renesas,no-can-fd"))
1867		fdmode = false;			/* Classical CAN only mode */
1868
1869	for (i = 0; i < info->max_channels; ++i) {
1870		name[7] = '0' + i;
1871		of_child = of_get_child_by_name(dev->of_node, name);
1872		if (of_child && of_device_is_available(of_child)) {
1873			channels_mask |= BIT(i);
1874			transceivers[i] = devm_of_phy_optional_get(dev,
1875							of_child, NULL);
1876		}
1877		of_node_put(of_child);
1878		if (IS_ERR(transceivers[i]))
1879			return PTR_ERR(transceivers[i]);
 
 
1880	}
1881
1882	if (info->shared_global_irqs) {
1883		ch_irq = platform_get_irq_byname_optional(pdev, "ch_int");
1884		if (ch_irq < 0) {
1885			/* For backward compatibility get irq by index */
1886			ch_irq = platform_get_irq(pdev, 0);
1887			if (ch_irq < 0)
1888				return ch_irq;
1889		}
1890
1891		g_irq = platform_get_irq_byname_optional(pdev, "g_int");
1892		if (g_irq < 0) {
1893			/* For backward compatibility get irq by index */
1894			g_irq = platform_get_irq(pdev, 1);
1895			if (g_irq < 0)
1896				return g_irq;
1897		}
1898	} else {
1899		g_err_irq = platform_get_irq_byname(pdev, "g_err");
1900		if (g_err_irq < 0)
1901			return g_err_irq;
1902
1903		g_recc_irq = platform_get_irq_byname(pdev, "g_recc");
1904		if (g_recc_irq < 0)
1905			return g_recc_irq;
1906	}
1907
1908	/* Global controller context */
1909	gpriv = devm_kzalloc(dev, sizeof(*gpriv), GFP_KERNEL);
1910	if (!gpriv)
1911		return -ENOMEM;
1912
 
1913	gpriv->pdev = pdev;
1914	gpriv->channels_mask = channels_mask;
1915	gpriv->fdmode = fdmode;
1916	gpriv->info = info;
1917
1918	gpriv->rstc1 = devm_reset_control_get_optional_exclusive(dev, "rstp_n");
1919	if (IS_ERR(gpriv->rstc1))
1920		return dev_err_probe(dev, PTR_ERR(gpriv->rstc1),
1921				     "failed to get rstp_n\n");
1922
1923	gpriv->rstc2 = devm_reset_control_get_optional_exclusive(dev, "rstc_n");
1924	if (IS_ERR(gpriv->rstc2))
1925		return dev_err_probe(dev, PTR_ERR(gpriv->rstc2),
1926				     "failed to get rstc_n\n");
1927
1928	/* Peripheral clock */
1929	gpriv->clkp = devm_clk_get(dev, "fck");
1930	if (IS_ERR(gpriv->clkp))
1931		return dev_err_probe(dev, PTR_ERR(gpriv->clkp),
1932				     "cannot get peripheral clock\n");
 
 
 
1933
1934	/* fCAN clock: Pick External clock. If not available fallback to
1935	 * CANFD clock
1936	 */
1937	gpriv->can_clk = devm_clk_get(dev, "can_clk");
1938	if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1939		gpriv->can_clk = devm_clk_get(dev, "canfd");
1940		if (IS_ERR(gpriv->can_clk))
1941			return dev_err_probe(dev, PTR_ERR(gpriv->can_clk),
1942					     "cannot get canfd clock\n");
1943
 
 
1944		gpriv->fcan = RCANFD_CANFDCLK;
1945
1946	} else {
1947		gpriv->fcan = RCANFD_EXTCLK;
1948	}
1949	fcan_freq = clk_get_rate(gpriv->can_clk);
1950
1951	if (gpriv->fcan == RCANFD_CANFDCLK)
1952		/* CANFD clock is further divided by (1/2) within the IP */
1953		fcan_freq /= info->postdiv;
1954
1955	addr = devm_platform_ioremap_resource(pdev, 0);
 
1956	if (IS_ERR(addr)) {
1957		err = PTR_ERR(addr);
1958		goto fail_dev;
1959	}
1960	gpriv->base = addr;
1961
1962	/* Request IRQ that's common for both channels */
1963	if (info->shared_global_irqs) {
1964		err = devm_request_irq(dev, ch_irq,
1965				       rcar_canfd_channel_interrupt, 0,
1966				       "canfd.ch_int", gpriv);
1967		if (err) {
1968			dev_err(dev, "devm_request_irq %d failed: %pe\n",
1969				ch_irq, ERR_PTR(err));
1970			goto fail_dev;
1971		}
1972
1973		err = devm_request_irq(dev, g_irq, rcar_canfd_global_interrupt,
1974				       0, "canfd.g_int", gpriv);
1975		if (err) {
1976			dev_err(dev, "devm_request_irq %d failed: %pe\n",
1977				g_irq, ERR_PTR(err));
1978			goto fail_dev;
1979		}
1980	} else {
1981		err = devm_request_irq(dev, g_recc_irq,
1982				       rcar_canfd_global_receive_fifo_interrupt, 0,
1983				       "canfd.g_recc", gpriv);
1984
1985		if (err) {
1986			dev_err(dev, "devm_request_irq %d failed: %pe\n",
1987				g_recc_irq, ERR_PTR(err));
1988			goto fail_dev;
1989		}
1990
1991		err = devm_request_irq(dev, g_err_irq,
1992				       rcar_canfd_global_err_interrupt, 0,
1993				       "canfd.g_err", gpriv);
1994		if (err) {
1995			dev_err(dev, "devm_request_irq %d failed: %pe\n",
1996				g_err_irq, ERR_PTR(err));
1997			goto fail_dev;
1998		}
1999	}
2000
2001	err = reset_control_reset(gpriv->rstc1);
2002	if (err)
2003		goto fail_dev;
2004	err = reset_control_reset(gpriv->rstc2);
 
 
 
2005	if (err) {
2006		reset_control_assert(gpriv->rstc1);
 
2007		goto fail_dev;
2008	}
2009
2010	/* Enable peripheral clock for register access */
2011	err = clk_prepare_enable(gpriv->clkp);
2012	if (err) {
2013		dev_err(dev, "failed to enable peripheral clock: %pe\n",
2014			ERR_PTR(err));
2015		goto fail_reset;
2016	}
2017
2018	err = rcar_canfd_reset_controller(gpriv);
2019	if (err) {
2020		dev_err(dev, "reset controller failed: %pe\n", ERR_PTR(err));
2021		goto fail_clk;
2022	}
2023
2024	/* Controller in Global reset & Channel reset mode */
2025	rcar_canfd_configure_controller(gpriv);
2026
2027	/* Configure per channel attributes */
2028	for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2029		/* Configure Channel's Rx fifo */
2030		rcar_canfd_configure_rx(gpriv, ch);
2031
2032		/* Configure Channel's Tx (Common) fifo */
2033		rcar_canfd_configure_tx(gpriv, ch);
2034
2035		/* Configure receive rules */
2036		rcar_canfd_configure_afl_rules(gpriv, ch);
2037	}
2038
2039	/* Configure common interrupts */
2040	rcar_canfd_enable_global_interrupts(gpriv);
2041
2042	/* Start Global operation mode */
2043	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
2044			      RCANFD_GCTR_GMDC_GOPM);
2045
2046	/* Verify mode change */
2047	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
2048				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
2049	if (err) {
2050		dev_err(dev, "global operational mode failed\n");
2051		goto fail_mode;
2052	}
2053
2054	for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2055		err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq,
2056					       transceivers[ch]);
2057		if (err)
2058			goto fail_channel;
2059	}
2060
2061	platform_set_drvdata(pdev, gpriv);
2062	dev_info(dev, "global operational state (clk %d, fdmode %d)\n",
2063		 gpriv->fcan, gpriv->fdmode);
2064	return 0;
2065
2066fail_channel:
2067	for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels)
2068		rcar_canfd_channel_remove(gpriv, ch);
2069fail_mode:
2070	rcar_canfd_disable_global_interrupts(gpriv);
2071fail_clk:
2072	clk_disable_unprepare(gpriv->clkp);
2073fail_reset:
2074	reset_control_assert(gpriv->rstc1);
2075	reset_control_assert(gpriv->rstc2);
2076fail_dev:
2077	return err;
2078}
2079
2080static void rcar_canfd_remove(struct platform_device *pdev)
2081{
2082	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
2083	u32 ch;
2084
2085	rcar_canfd_reset_controller(gpriv);
2086	rcar_canfd_disable_global_interrupts(gpriv);
2087
2088	for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2089		rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
2090		rcar_canfd_channel_remove(gpriv, ch);
2091	}
2092
2093	/* Enter global sleep mode */
2094	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
2095	clk_disable_unprepare(gpriv->clkp);
2096	reset_control_assert(gpriv->rstc1);
2097	reset_control_assert(gpriv->rstc2);
2098}
2099
2100static int __maybe_unused rcar_canfd_suspend(struct device *dev)
2101{
2102	return 0;
2103}
2104
2105static int __maybe_unused rcar_canfd_resume(struct device *dev)
2106{
2107	return 0;
2108}
2109
2110static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
2111			 rcar_canfd_resume);
2112
2113static const __maybe_unused struct of_device_id rcar_canfd_of_table[] = {
2114	{ .compatible = "renesas,r8a779a0-canfd", .data = &rcar_gen4_hw_info },
2115	{ .compatible = "renesas,rcar-gen3-canfd", .data = &rcar_gen3_hw_info },
2116	{ .compatible = "renesas,rcar-gen4-canfd", .data = &rcar_gen4_hw_info },
2117	{ .compatible = "renesas,rzg2l-canfd", .data = &rzg2l_hw_info },
2118	{ }
2119};
2120
2121MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
2122
2123static struct platform_driver rcar_canfd_driver = {
2124	.driver = {
2125		.name = RCANFD_DRV_NAME,
2126		.of_match_table = of_match_ptr(rcar_canfd_of_table),
2127		.pm = &rcar_canfd_pm_ops,
2128	},
2129	.probe = rcar_canfd_probe,
2130	.remove_new = rcar_canfd_remove,
2131};
2132
2133module_platform_driver(rcar_canfd_driver);
2134
2135MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
2136MODULE_LICENSE("GPL");
2137MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
2138MODULE_ALIAS("platform:" RCANFD_DRV_NAME);