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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * LPDDR2-NVM MTD driver. This module provides read, write, erase, lock/unlock
4 * support for LPDDR2-NVM PCM memories
5 *
6 * Copyright © 2012 Micron Technology, Inc.
7 *
8 * Vincenzo Aliberti <vincenzo.aliberti@gmail.com>
9 * Domenico Manna <domenico.manna@gmail.com>
10 * Many thanks to Andrea Vigilante for initial enabling
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
14
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/mtd/map.h>
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/partitions.h>
22#include <linux/slab.h>
23#include <linux/platform_device.h>
24#include <linux/ioport.h>
25#include <linux/err.h>
26
27/* Parameters */
28#define ERASE_BLOCKSIZE (0x00020000/2) /* in Word */
29#define WRITE_BUFFSIZE (0x00000400/2) /* in Word */
30#define OW_BASE_ADDRESS 0x00000000 /* OW offset */
31#define BUS_WIDTH 0x00000020 /* x32 devices */
32
33/* PFOW symbols address offset */
34#define PFOW_QUERY_STRING_P (0x0000/2) /* in Word */
35#define PFOW_QUERY_STRING_F (0x0002/2) /* in Word */
36#define PFOW_QUERY_STRING_O (0x0004/2) /* in Word */
37#define PFOW_QUERY_STRING_W (0x0006/2) /* in Word */
38
39/* OW registers address */
40#define CMD_CODE_OFS (0x0080/2) /* in Word */
41#define CMD_DATA_OFS (0x0084/2) /* in Word */
42#define CMD_ADD_L_OFS (0x0088/2) /* in Word */
43#define CMD_ADD_H_OFS (0x008A/2) /* in Word */
44#define MPR_L_OFS (0x0090/2) /* in Word */
45#define MPR_H_OFS (0x0092/2) /* in Word */
46#define CMD_EXEC_OFS (0x00C0/2) /* in Word */
47#define STATUS_REG_OFS (0x00CC/2) /* in Word */
48#define PRG_BUFFER_OFS (0x0010/2) /* in Word */
49
50/* Datamask */
51#define MR_CFGMASK 0x8000
52#define SR_OK_DATAMASK 0x0080
53
54/* LPDDR2-NVM Commands */
55#define LPDDR2_NVM_LOCK 0x0061
56#define LPDDR2_NVM_UNLOCK 0x0062
57#define LPDDR2_NVM_SW_PROGRAM 0x0041
58#define LPDDR2_NVM_SW_OVERWRITE 0x0042
59#define LPDDR2_NVM_BUF_PROGRAM 0x00E9
60#define LPDDR2_NVM_BUF_OVERWRITE 0x00EA
61#define LPDDR2_NVM_ERASE 0x0020
62
63/* LPDDR2-NVM Registers offset */
64#define LPDDR2_MODE_REG_DATA 0x0040
65#define LPDDR2_MODE_REG_CFG 0x0050
66
67/*
68 * Internal Type Definitions
69 * pcm_int_data contains memory controller details:
70 * @reg_data : LPDDR2_MODE_REG_DATA register address after remapping
71 * @reg_cfg : LPDDR2_MODE_REG_CFG register address after remapping
72 * &bus_width: memory bus-width (eg: x16 2 Bytes, x32 4 Bytes)
73 */
74struct pcm_int_data {
75 void __iomem *ctl_regs;
76 int bus_width;
77};
78
79static DEFINE_MUTEX(lpdd2_nvm_mutex);
80
81/*
82 * Build a map_word starting from an u_long
83 */
84static inline map_word build_map_word(u_long myword)
85{
86 map_word val = { {0} };
87 val.x[0] = myword;
88 return val;
89}
90
91/*
92 * Build Mode Register Configuration DataMask based on device bus-width
93 */
94static inline u_int build_mr_cfgmask(u_int bus_width)
95{
96 u_int val = MR_CFGMASK;
97
98 if (bus_width == 0x0004) /* x32 device */
99 val = val << 16;
100
101 return val;
102}
103
104/*
105 * Build Status Register OK DataMask based on device bus-width
106 */
107static inline u_int build_sr_ok_datamask(u_int bus_width)
108{
109 u_int val = SR_OK_DATAMASK;
110
111 if (bus_width == 0x0004) /* x32 device */
112 val = (val << 16)+val;
113
114 return val;
115}
116
117/*
118 * Evaluates Overlay Window Control Registers address
119 */
120static inline u_long ow_reg_add(struct map_info *map, u_long offset)
121{
122 u_long val = 0;
123 struct pcm_int_data *pcm_data = map->fldrv_priv;
124
125 val = map->pfow_base + offset*pcm_data->bus_width;
126
127 return val;
128}
129
130/*
131 * Enable lpddr2-nvm Overlay Window
132 * Overlay Window is a memory mapped area containing all LPDDR2-NVM registers
133 * used by device commands as well as uservisible resources like Device Status
134 * Register, Device ID, etc
135 */
136static inline void ow_enable(struct map_info *map)
137{
138 struct pcm_int_data *pcm_data = map->fldrv_priv;
139
140 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
141 pcm_data->ctl_regs + LPDDR2_MODE_REG_CFG);
142 writel_relaxed(0x01, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA);
143}
144
145/*
146 * Disable lpddr2-nvm Overlay Window
147 * Overlay Window is a memory mapped area containing all LPDDR2-NVM registers
148 * used by device commands as well as uservisible resources like Device Status
149 * Register, Device ID, etc
150 */
151static inline void ow_disable(struct map_info *map)
152{
153 struct pcm_int_data *pcm_data = map->fldrv_priv;
154
155 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
156 pcm_data->ctl_regs + LPDDR2_MODE_REG_CFG);
157 writel_relaxed(0x02, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA);
158}
159
160/*
161 * Execute lpddr2-nvm operations
162 */
163static int lpddr2_nvm_do_op(struct map_info *map, u_long cmd_code,
164 u_long cmd_data, u_long cmd_add, u_long cmd_mpr, u_char *buf)
165{
166 map_word add_l = { {0} }, add_h = { {0} }, mpr_l = { {0} },
167 mpr_h = { {0} }, data_l = { {0} }, cmd = { {0} },
168 exec_cmd = { {0} }, sr;
169 map_word data_h = { {0} }; /* only for 2x x16 devices stacked */
170 u_long i, status_reg, prg_buff_ofs;
171 struct pcm_int_data *pcm_data = map->fldrv_priv;
172 u_int sr_ok_datamask = build_sr_ok_datamask(pcm_data->bus_width);
173
174 /* Builds low and high words for OW Control Registers */
175 add_l.x[0] = cmd_add & 0x0000FFFF;
176 add_h.x[0] = (cmd_add >> 16) & 0x0000FFFF;
177 mpr_l.x[0] = cmd_mpr & 0x0000FFFF;
178 mpr_h.x[0] = (cmd_mpr >> 16) & 0x0000FFFF;
179 cmd.x[0] = cmd_code & 0x0000FFFF;
180 exec_cmd.x[0] = 0x0001;
181 data_l.x[0] = cmd_data & 0x0000FFFF;
182 data_h.x[0] = (cmd_data >> 16) & 0x0000FFFF; /* only for 2x x16 */
183
184 /* Set Overlay Window Control Registers */
185 map_write(map, cmd, ow_reg_add(map, CMD_CODE_OFS));
186 map_write(map, data_l, ow_reg_add(map, CMD_DATA_OFS));
187 map_write(map, add_l, ow_reg_add(map, CMD_ADD_L_OFS));
188 map_write(map, add_h, ow_reg_add(map, CMD_ADD_H_OFS));
189 map_write(map, mpr_l, ow_reg_add(map, MPR_L_OFS));
190 map_write(map, mpr_h, ow_reg_add(map, MPR_H_OFS));
191 if (pcm_data->bus_width == 0x0004) { /* 2x16 devices stacked */
192 map_write(map, cmd, ow_reg_add(map, CMD_CODE_OFS) + 2);
193 map_write(map, data_h, ow_reg_add(map, CMD_DATA_OFS) + 2);
194 map_write(map, add_l, ow_reg_add(map, CMD_ADD_L_OFS) + 2);
195 map_write(map, add_h, ow_reg_add(map, CMD_ADD_H_OFS) + 2);
196 map_write(map, mpr_l, ow_reg_add(map, MPR_L_OFS) + 2);
197 map_write(map, mpr_h, ow_reg_add(map, MPR_H_OFS) + 2);
198 }
199
200 /* Fill Program Buffer */
201 if ((cmd_code == LPDDR2_NVM_BUF_PROGRAM) ||
202 (cmd_code == LPDDR2_NVM_BUF_OVERWRITE)) {
203 prg_buff_ofs = (map_read(map,
204 ow_reg_add(map, PRG_BUFFER_OFS))).x[0];
205 for (i = 0; i < cmd_mpr; i++) {
206 map_write(map, build_map_word(buf[i]), map->pfow_base +
207 prg_buff_ofs + i);
208 }
209 }
210
211 /* Command Execute */
212 map_write(map, exec_cmd, ow_reg_add(map, CMD_EXEC_OFS));
213 if (pcm_data->bus_width == 0x0004) /* 2x16 devices stacked */
214 map_write(map, exec_cmd, ow_reg_add(map, CMD_EXEC_OFS) + 2);
215
216 /* Status Register Check */
217 do {
218 sr = map_read(map, ow_reg_add(map, STATUS_REG_OFS));
219 status_reg = sr.x[0];
220 if (pcm_data->bus_width == 0x0004) {/* 2x16 devices stacked */
221 sr = map_read(map, ow_reg_add(map,
222 STATUS_REG_OFS) + 2);
223 status_reg += sr.x[0] << 16;
224 }
225 } while ((status_reg & sr_ok_datamask) != sr_ok_datamask);
226
227 return (((status_reg & sr_ok_datamask) == sr_ok_datamask) ? 0 : -EIO);
228}
229
230/*
231 * Execute lpddr2-nvm operations @ block level
232 */
233static int lpddr2_nvm_do_block_op(struct mtd_info *mtd, loff_t start_add,
234 uint64_t len, u_char block_op)
235{
236 struct map_info *map = mtd->priv;
237 u_long add, end_add;
238 int ret = 0;
239
240 mutex_lock(&lpdd2_nvm_mutex);
241
242 ow_enable(map);
243
244 add = start_add;
245 end_add = add + len;
246
247 do {
248 ret = lpddr2_nvm_do_op(map, block_op, 0x00, add, add, NULL);
249 if (ret)
250 goto out;
251 add += mtd->erasesize;
252 } while (add < end_add);
253
254out:
255 ow_disable(map);
256 mutex_unlock(&lpdd2_nvm_mutex);
257 return ret;
258}
259
260/*
261 * verify presence of PFOW string
262 */
263static int lpddr2_nvm_pfow_present(struct map_info *map)
264{
265 map_word pfow_val[4];
266 unsigned int found = 1;
267
268 mutex_lock(&lpdd2_nvm_mutex);
269
270 ow_enable(map);
271
272 /* Load string from array */
273 pfow_val[0] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_P));
274 pfow_val[1] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_F));
275 pfow_val[2] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_O));
276 pfow_val[3] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_W));
277
278 /* Verify the string loaded vs expected */
279 if (!map_word_equal(map, build_map_word('P'), pfow_val[0]))
280 found = 0;
281 if (!map_word_equal(map, build_map_word('F'), pfow_val[1]))
282 found = 0;
283 if (!map_word_equal(map, build_map_word('O'), pfow_val[2]))
284 found = 0;
285 if (!map_word_equal(map, build_map_word('W'), pfow_val[3]))
286 found = 0;
287
288 ow_disable(map);
289
290 mutex_unlock(&lpdd2_nvm_mutex);
291
292 return found;
293}
294
295/*
296 * lpddr2_nvm driver read method
297 */
298static int lpddr2_nvm_read(struct mtd_info *mtd, loff_t start_add,
299 size_t len, size_t *retlen, u_char *buf)
300{
301 struct map_info *map = mtd->priv;
302
303 mutex_lock(&lpdd2_nvm_mutex);
304
305 *retlen = len;
306
307 map_copy_from(map, buf, start_add, *retlen);
308
309 mutex_unlock(&lpdd2_nvm_mutex);
310 return 0;
311}
312
313/*
314 * lpddr2_nvm driver write method
315 */
316static int lpddr2_nvm_write(struct mtd_info *mtd, loff_t start_add,
317 size_t len, size_t *retlen, const u_char *buf)
318{
319 struct map_info *map = mtd->priv;
320 struct pcm_int_data *pcm_data = map->fldrv_priv;
321 u_long add, current_len, tot_len, target_len, my_data;
322 u_char *write_buf = (u_char *)buf;
323 int ret = 0;
324
325 mutex_lock(&lpdd2_nvm_mutex);
326
327 ow_enable(map);
328
329 /* Set start value for the variables */
330 add = start_add;
331 target_len = len;
332 tot_len = 0;
333
334 while (tot_len < target_len) {
335 if (!(IS_ALIGNED(add, mtd->writesize))) { /* do sw program */
336 my_data = write_buf[tot_len];
337 my_data += (write_buf[tot_len+1]) << 8;
338 if (pcm_data->bus_width == 0x0004) {/* 2x16 devices */
339 my_data += (write_buf[tot_len+2]) << 16;
340 my_data += (write_buf[tot_len+3]) << 24;
341 }
342 ret = lpddr2_nvm_do_op(map, LPDDR2_NVM_SW_OVERWRITE,
343 my_data, add, 0x00, NULL);
344 if (ret)
345 goto out;
346
347 add += pcm_data->bus_width;
348 tot_len += pcm_data->bus_width;
349 } else { /* do buffer program */
350 current_len = min(target_len - tot_len,
351 (u_long) mtd->writesize);
352 ret = lpddr2_nvm_do_op(map, LPDDR2_NVM_BUF_OVERWRITE,
353 0x00, add, current_len, write_buf + tot_len);
354 if (ret)
355 goto out;
356
357 add += current_len;
358 tot_len += current_len;
359 }
360 }
361
362out:
363 *retlen = tot_len;
364 ow_disable(map);
365 mutex_unlock(&lpdd2_nvm_mutex);
366 return ret;
367}
368
369/*
370 * lpddr2_nvm driver erase method
371 */
372static int lpddr2_nvm_erase(struct mtd_info *mtd, struct erase_info *instr)
373{
374 return lpddr2_nvm_do_block_op(mtd, instr->addr, instr->len,
375 LPDDR2_NVM_ERASE);
376}
377
378/*
379 * lpddr2_nvm driver unlock method
380 */
381static int lpddr2_nvm_unlock(struct mtd_info *mtd, loff_t start_add,
382 uint64_t len)
383{
384 return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_UNLOCK);
385}
386
387/*
388 * lpddr2_nvm driver lock method
389 */
390static int lpddr2_nvm_lock(struct mtd_info *mtd, loff_t start_add,
391 uint64_t len)
392{
393 return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_LOCK);
394}
395
396static const struct mtd_info lpddr2_nvm_mtd_info = {
397 .type = MTD_RAM,
398 .writesize = 1,
399 .flags = (MTD_CAP_NVRAM | MTD_POWERUP_LOCK),
400 ._read = lpddr2_nvm_read,
401 ._write = lpddr2_nvm_write,
402 ._erase = lpddr2_nvm_erase,
403 ._unlock = lpddr2_nvm_unlock,
404 ._lock = lpddr2_nvm_lock,
405};
406
407/*
408 * lpddr2_nvm driver probe method
409 */
410static int lpddr2_nvm_probe(struct platform_device *pdev)
411{
412 struct map_info *map;
413 struct mtd_info *mtd;
414 struct resource *add_range;
415 struct pcm_int_data *pcm_data;
416
417 /* Allocate memory control_regs data structures */
418 pcm_data = devm_kzalloc(&pdev->dev, sizeof(*pcm_data), GFP_KERNEL);
419 if (!pcm_data)
420 return -ENOMEM;
421
422 pcm_data->bus_width = BUS_WIDTH;
423
424 /* Allocate memory for map_info & mtd_info data structures */
425 map = devm_kzalloc(&pdev->dev, sizeof(*map), GFP_KERNEL);
426 if (!map)
427 return -ENOMEM;
428
429 mtd = devm_kzalloc(&pdev->dev, sizeof(*mtd), GFP_KERNEL);
430 if (!mtd)
431 return -ENOMEM;
432
433 /* lpddr2_nvm address range */
434 add_range = platform_get_resource(pdev, IORESOURCE_MEM, 0);
435 if (!add_range)
436 return -ENODEV;
437
438 /* Populate map_info data structure */
439 *map = (struct map_info) {
440 .virt = devm_ioremap_resource(&pdev->dev, add_range),
441 .name = pdev->dev.init_name,
442 .phys = add_range->start,
443 .size = resource_size(add_range),
444 .bankwidth = pcm_data->bus_width / 2,
445 .pfow_base = OW_BASE_ADDRESS,
446 .fldrv_priv = pcm_data,
447 };
448
449 if (IS_ERR(map->virt))
450 return PTR_ERR(map->virt);
451
452 simple_map_init(map); /* fill with default methods */
453
454 pcm_data->ctl_regs = devm_platform_ioremap_resource(pdev, 1);
455 if (IS_ERR(pcm_data->ctl_regs))
456 return PTR_ERR(pcm_data->ctl_regs);
457
458 /* Populate mtd_info data structure */
459 *mtd = lpddr2_nvm_mtd_info;
460 mtd->dev.parent = &pdev->dev;
461 mtd->name = pdev->dev.init_name;
462 mtd->priv = map;
463 mtd->size = resource_size(add_range);
464 mtd->erasesize = ERASE_BLOCKSIZE * pcm_data->bus_width;
465 mtd->writebufsize = WRITE_BUFFSIZE * pcm_data->bus_width;
466
467 /* Verify the presence of the device looking for PFOW string */
468 if (!lpddr2_nvm_pfow_present(map)) {
469 pr_err("device not recognized\n");
470 return -EINVAL;
471 }
472 /* Parse partitions and register the MTD device */
473 return mtd_device_register(mtd, NULL, 0);
474}
475
476/*
477 * lpddr2_nvm driver remove method
478 */
479static void lpddr2_nvm_remove(struct platform_device *pdev)
480{
481 WARN_ON(mtd_device_unregister(dev_get_drvdata(&pdev->dev)));
482}
483
484/* Initialize platform_driver data structure for lpddr2_nvm */
485static struct platform_driver lpddr2_nvm_drv = {
486 .driver = {
487 .name = "lpddr2_nvm",
488 },
489 .probe = lpddr2_nvm_probe,
490 .remove_new = lpddr2_nvm_remove,
491};
492
493module_platform_driver(lpddr2_nvm_drv);
494MODULE_LICENSE("GPL");
495MODULE_AUTHOR("Vincenzo Aliberti <vincenzo.aliberti@gmail.com>");
496MODULE_DESCRIPTION("MTD driver for LPDDR2-NVM PCM memories");
1/*
2 * LPDDR2-NVM MTD driver. This module provides read, write, erase, lock/unlock
3 * support for LPDDR2-NVM PCM memories
4 *
5 * Copyright © 2012 Micron Technology, Inc.
6 *
7 * Vincenzo Aliberti <vincenzo.aliberti@gmail.com>
8 * Domenico Manna <domenico.manna@gmail.com>
9 * Many thanks to Andrea Vigilante for initial enabling
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
23
24#include <linux/init.h>
25#include <linux/io.h>
26#include <linux/module.h>
27#include <linux/kernel.h>
28#include <linux/mtd/map.h>
29#include <linux/mtd/mtd.h>
30#include <linux/mtd/partitions.h>
31#include <linux/slab.h>
32#include <linux/platform_device.h>
33#include <linux/ioport.h>
34#include <linux/err.h>
35
36/* Parameters */
37#define ERASE_BLOCKSIZE (0x00020000/2) /* in Word */
38#define WRITE_BUFFSIZE (0x00000400/2) /* in Word */
39#define OW_BASE_ADDRESS 0x00000000 /* OW offset */
40#define BUS_WIDTH 0x00000020 /* x32 devices */
41
42/* PFOW symbols address offset */
43#define PFOW_QUERY_STRING_P (0x0000/2) /* in Word */
44#define PFOW_QUERY_STRING_F (0x0002/2) /* in Word */
45#define PFOW_QUERY_STRING_O (0x0004/2) /* in Word */
46#define PFOW_QUERY_STRING_W (0x0006/2) /* in Word */
47
48/* OW registers address */
49#define CMD_CODE_OFS (0x0080/2) /* in Word */
50#define CMD_DATA_OFS (0x0084/2) /* in Word */
51#define CMD_ADD_L_OFS (0x0088/2) /* in Word */
52#define CMD_ADD_H_OFS (0x008A/2) /* in Word */
53#define MPR_L_OFS (0x0090/2) /* in Word */
54#define MPR_H_OFS (0x0092/2) /* in Word */
55#define CMD_EXEC_OFS (0x00C0/2) /* in Word */
56#define STATUS_REG_OFS (0x00CC/2) /* in Word */
57#define PRG_BUFFER_OFS (0x0010/2) /* in Word */
58
59/* Datamask */
60#define MR_CFGMASK 0x8000
61#define SR_OK_DATAMASK 0x0080
62
63/* LPDDR2-NVM Commands */
64#define LPDDR2_NVM_LOCK 0x0061
65#define LPDDR2_NVM_UNLOCK 0x0062
66#define LPDDR2_NVM_SW_PROGRAM 0x0041
67#define LPDDR2_NVM_SW_OVERWRITE 0x0042
68#define LPDDR2_NVM_BUF_PROGRAM 0x00E9
69#define LPDDR2_NVM_BUF_OVERWRITE 0x00EA
70#define LPDDR2_NVM_ERASE 0x0020
71
72/* LPDDR2-NVM Registers offset */
73#define LPDDR2_MODE_REG_DATA 0x0040
74#define LPDDR2_MODE_REG_CFG 0x0050
75
76/*
77 * Internal Type Definitions
78 * pcm_int_data contains memory controller details:
79 * @reg_data : LPDDR2_MODE_REG_DATA register address after remapping
80 * @reg_cfg : LPDDR2_MODE_REG_CFG register address after remapping
81 * &bus_width: memory bus-width (eg: x16 2 Bytes, x32 4 Bytes)
82 */
83struct pcm_int_data {
84 void __iomem *ctl_regs;
85 int bus_width;
86};
87
88static DEFINE_MUTEX(lpdd2_nvm_mutex);
89
90/*
91 * Build a map_word starting from an u_long
92 */
93static inline map_word build_map_word(u_long myword)
94{
95 map_word val = { {0} };
96 val.x[0] = myword;
97 return val;
98}
99
100/*
101 * Build Mode Register Configuration DataMask based on device bus-width
102 */
103static inline u_int build_mr_cfgmask(u_int bus_width)
104{
105 u_int val = MR_CFGMASK;
106
107 if (bus_width == 0x0004) /* x32 device */
108 val = val << 16;
109
110 return val;
111}
112
113/*
114 * Build Status Register OK DataMask based on device bus-width
115 */
116static inline u_int build_sr_ok_datamask(u_int bus_width)
117{
118 u_int val = SR_OK_DATAMASK;
119
120 if (bus_width == 0x0004) /* x32 device */
121 val = (val << 16)+val;
122
123 return val;
124}
125
126/*
127 * Evaluates Overlay Window Control Registers address
128 */
129static inline u_long ow_reg_add(struct map_info *map, u_long offset)
130{
131 u_long val = 0;
132 struct pcm_int_data *pcm_data = map->fldrv_priv;
133
134 val = map->pfow_base + offset*pcm_data->bus_width;
135
136 return val;
137}
138
139/*
140 * Enable lpddr2-nvm Overlay Window
141 * Overlay Window is a memory mapped area containing all LPDDR2-NVM registers
142 * used by device commands as well as uservisible resources like Device Status
143 * Register, Device ID, etc
144 */
145static inline void ow_enable(struct map_info *map)
146{
147 struct pcm_int_data *pcm_data = map->fldrv_priv;
148
149 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
150 pcm_data->ctl_regs + LPDDR2_MODE_REG_CFG);
151 writel_relaxed(0x01, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA);
152}
153
154/*
155 * Disable lpddr2-nvm Overlay Window
156 * Overlay Window is a memory mapped area containing all LPDDR2-NVM registers
157 * used by device commands as well as uservisible resources like Device Status
158 * Register, Device ID, etc
159 */
160static inline void ow_disable(struct map_info *map)
161{
162 struct pcm_int_data *pcm_data = map->fldrv_priv;
163
164 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
165 pcm_data->ctl_regs + LPDDR2_MODE_REG_CFG);
166 writel_relaxed(0x02, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA);
167}
168
169/*
170 * Execute lpddr2-nvm operations
171 */
172static int lpddr2_nvm_do_op(struct map_info *map, u_long cmd_code,
173 u_long cmd_data, u_long cmd_add, u_long cmd_mpr, u_char *buf)
174{
175 map_word add_l = { {0} }, add_h = { {0} }, mpr_l = { {0} },
176 mpr_h = { {0} }, data_l = { {0} }, cmd = { {0} },
177 exec_cmd = { {0} }, sr;
178 map_word data_h = { {0} }; /* only for 2x x16 devices stacked */
179 u_long i, status_reg, prg_buff_ofs;
180 struct pcm_int_data *pcm_data = map->fldrv_priv;
181 u_int sr_ok_datamask = build_sr_ok_datamask(pcm_data->bus_width);
182
183 /* Builds low and high words for OW Control Registers */
184 add_l.x[0] = cmd_add & 0x0000FFFF;
185 add_h.x[0] = (cmd_add >> 16) & 0x0000FFFF;
186 mpr_l.x[0] = cmd_mpr & 0x0000FFFF;
187 mpr_h.x[0] = (cmd_mpr >> 16) & 0x0000FFFF;
188 cmd.x[0] = cmd_code & 0x0000FFFF;
189 exec_cmd.x[0] = 0x0001;
190 data_l.x[0] = cmd_data & 0x0000FFFF;
191 data_h.x[0] = (cmd_data >> 16) & 0x0000FFFF; /* only for 2x x16 */
192
193 /* Set Overlay Window Control Registers */
194 map_write(map, cmd, ow_reg_add(map, CMD_CODE_OFS));
195 map_write(map, data_l, ow_reg_add(map, CMD_DATA_OFS));
196 map_write(map, add_l, ow_reg_add(map, CMD_ADD_L_OFS));
197 map_write(map, add_h, ow_reg_add(map, CMD_ADD_H_OFS));
198 map_write(map, mpr_l, ow_reg_add(map, MPR_L_OFS));
199 map_write(map, mpr_h, ow_reg_add(map, MPR_H_OFS));
200 if (pcm_data->bus_width == 0x0004) { /* 2x16 devices stacked */
201 map_write(map, cmd, ow_reg_add(map, CMD_CODE_OFS) + 2);
202 map_write(map, data_h, ow_reg_add(map, CMD_DATA_OFS) + 2);
203 map_write(map, add_l, ow_reg_add(map, CMD_ADD_L_OFS) + 2);
204 map_write(map, add_h, ow_reg_add(map, CMD_ADD_H_OFS) + 2);
205 map_write(map, mpr_l, ow_reg_add(map, MPR_L_OFS) + 2);
206 map_write(map, mpr_h, ow_reg_add(map, MPR_H_OFS) + 2);
207 }
208
209 /* Fill Program Buffer */
210 if ((cmd_code == LPDDR2_NVM_BUF_PROGRAM) ||
211 (cmd_code == LPDDR2_NVM_BUF_OVERWRITE)) {
212 prg_buff_ofs = (map_read(map,
213 ow_reg_add(map, PRG_BUFFER_OFS))).x[0];
214 for (i = 0; i < cmd_mpr; i++) {
215 map_write(map, build_map_word(buf[i]), map->pfow_base +
216 prg_buff_ofs + i);
217 }
218 }
219
220 /* Command Execute */
221 map_write(map, exec_cmd, ow_reg_add(map, CMD_EXEC_OFS));
222 if (pcm_data->bus_width == 0x0004) /* 2x16 devices stacked */
223 map_write(map, exec_cmd, ow_reg_add(map, CMD_EXEC_OFS) + 2);
224
225 /* Status Register Check */
226 do {
227 sr = map_read(map, ow_reg_add(map, STATUS_REG_OFS));
228 status_reg = sr.x[0];
229 if (pcm_data->bus_width == 0x0004) {/* 2x16 devices stacked */
230 sr = map_read(map, ow_reg_add(map,
231 STATUS_REG_OFS) + 2);
232 status_reg += sr.x[0] << 16;
233 }
234 } while ((status_reg & sr_ok_datamask) != sr_ok_datamask);
235
236 return (((status_reg & sr_ok_datamask) == sr_ok_datamask) ? 0 : -EIO);
237}
238
239/*
240 * Execute lpddr2-nvm operations @ block level
241 */
242static int lpddr2_nvm_do_block_op(struct mtd_info *mtd, loff_t start_add,
243 uint64_t len, u_char block_op)
244{
245 struct map_info *map = mtd->priv;
246 u_long add, end_add;
247 int ret = 0;
248
249 mutex_lock(&lpdd2_nvm_mutex);
250
251 ow_enable(map);
252
253 add = start_add;
254 end_add = add + len;
255
256 do {
257 ret = lpddr2_nvm_do_op(map, block_op, 0x00, add, add, NULL);
258 if (ret)
259 goto out;
260 add += mtd->erasesize;
261 } while (add < end_add);
262
263out:
264 ow_disable(map);
265 mutex_unlock(&lpdd2_nvm_mutex);
266 return ret;
267}
268
269/*
270 * verify presence of PFOW string
271 */
272static int lpddr2_nvm_pfow_present(struct map_info *map)
273{
274 map_word pfow_val[4];
275 unsigned int found = 1;
276
277 mutex_lock(&lpdd2_nvm_mutex);
278
279 ow_enable(map);
280
281 /* Load string from array */
282 pfow_val[0] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_P));
283 pfow_val[1] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_F));
284 pfow_val[2] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_O));
285 pfow_val[3] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_W));
286
287 /* Verify the string loaded vs expected */
288 if (!map_word_equal(map, build_map_word('P'), pfow_val[0]))
289 found = 0;
290 if (!map_word_equal(map, build_map_word('F'), pfow_val[1]))
291 found = 0;
292 if (!map_word_equal(map, build_map_word('O'), pfow_val[2]))
293 found = 0;
294 if (!map_word_equal(map, build_map_word('W'), pfow_val[3]))
295 found = 0;
296
297 ow_disable(map);
298
299 mutex_unlock(&lpdd2_nvm_mutex);
300
301 return found;
302}
303
304/*
305 * lpddr2_nvm driver read method
306 */
307static int lpddr2_nvm_read(struct mtd_info *mtd, loff_t start_add,
308 size_t len, size_t *retlen, u_char *buf)
309{
310 struct map_info *map = mtd->priv;
311
312 mutex_lock(&lpdd2_nvm_mutex);
313
314 *retlen = len;
315
316 map_copy_from(map, buf, start_add, *retlen);
317
318 mutex_unlock(&lpdd2_nvm_mutex);
319 return 0;
320}
321
322/*
323 * lpddr2_nvm driver write method
324 */
325static int lpddr2_nvm_write(struct mtd_info *mtd, loff_t start_add,
326 size_t len, size_t *retlen, const u_char *buf)
327{
328 struct map_info *map = mtd->priv;
329 struct pcm_int_data *pcm_data = map->fldrv_priv;
330 u_long add, current_len, tot_len, target_len, my_data;
331 u_char *write_buf = (u_char *)buf;
332 int ret = 0;
333
334 mutex_lock(&lpdd2_nvm_mutex);
335
336 ow_enable(map);
337
338 /* Set start value for the variables */
339 add = start_add;
340 target_len = len;
341 tot_len = 0;
342
343 while (tot_len < target_len) {
344 if (!(IS_ALIGNED(add, mtd->writesize))) { /* do sw program */
345 my_data = write_buf[tot_len];
346 my_data += (write_buf[tot_len+1]) << 8;
347 if (pcm_data->bus_width == 0x0004) {/* 2x16 devices */
348 my_data += (write_buf[tot_len+2]) << 16;
349 my_data += (write_buf[tot_len+3]) << 24;
350 }
351 ret = lpddr2_nvm_do_op(map, LPDDR2_NVM_SW_OVERWRITE,
352 my_data, add, 0x00, NULL);
353 if (ret)
354 goto out;
355
356 add += pcm_data->bus_width;
357 tot_len += pcm_data->bus_width;
358 } else { /* do buffer program */
359 current_len = min(target_len - tot_len,
360 (u_long) mtd->writesize);
361 ret = lpddr2_nvm_do_op(map, LPDDR2_NVM_BUF_OVERWRITE,
362 0x00, add, current_len, write_buf + tot_len);
363 if (ret)
364 goto out;
365
366 add += current_len;
367 tot_len += current_len;
368 }
369 }
370
371out:
372 *retlen = tot_len;
373 ow_disable(map);
374 mutex_unlock(&lpdd2_nvm_mutex);
375 return ret;
376}
377
378/*
379 * lpddr2_nvm driver erase method
380 */
381static int lpddr2_nvm_erase(struct mtd_info *mtd, struct erase_info *instr)
382{
383 return lpddr2_nvm_do_block_op(mtd, instr->addr, instr->len,
384 LPDDR2_NVM_ERASE);
385}
386
387/*
388 * lpddr2_nvm driver unlock method
389 */
390static int lpddr2_nvm_unlock(struct mtd_info *mtd, loff_t start_add,
391 uint64_t len)
392{
393 return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_UNLOCK);
394}
395
396/*
397 * lpddr2_nvm driver lock method
398 */
399static int lpddr2_nvm_lock(struct mtd_info *mtd, loff_t start_add,
400 uint64_t len)
401{
402 return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_LOCK);
403}
404
405/*
406 * lpddr2_nvm driver probe method
407 */
408static int lpddr2_nvm_probe(struct platform_device *pdev)
409{
410 struct map_info *map;
411 struct mtd_info *mtd;
412 struct resource *add_range;
413 struct resource *control_regs;
414 struct pcm_int_data *pcm_data;
415
416 /* Allocate memory control_regs data structures */
417 pcm_data = devm_kzalloc(&pdev->dev, sizeof(*pcm_data), GFP_KERNEL);
418 if (!pcm_data)
419 return -ENOMEM;
420
421 pcm_data->bus_width = BUS_WIDTH;
422
423 /* Allocate memory for map_info & mtd_info data structures */
424 map = devm_kzalloc(&pdev->dev, sizeof(*map), GFP_KERNEL);
425 if (!map)
426 return -ENOMEM;
427
428 mtd = devm_kzalloc(&pdev->dev, sizeof(*mtd), GFP_KERNEL);
429 if (!mtd)
430 return -ENOMEM;
431
432 /* lpddr2_nvm address range */
433 add_range = platform_get_resource(pdev, IORESOURCE_MEM, 0);
434
435 /* Populate map_info data structure */
436 *map = (struct map_info) {
437 .virt = devm_ioremap_resource(&pdev->dev, add_range),
438 .name = pdev->dev.init_name,
439 .phys = add_range->start,
440 .size = resource_size(add_range),
441 .bankwidth = pcm_data->bus_width / 2,
442 .pfow_base = OW_BASE_ADDRESS,
443 .fldrv_priv = pcm_data,
444 };
445 if (IS_ERR(map->virt))
446 return PTR_ERR(map->virt);
447
448 simple_map_init(map); /* fill with default methods */
449
450 control_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
451 pcm_data->ctl_regs = devm_ioremap_resource(&pdev->dev, control_regs);
452 if (IS_ERR(pcm_data->ctl_regs))
453 return PTR_ERR(pcm_data->ctl_regs);
454
455 /* Populate mtd_info data structure */
456 *mtd = (struct mtd_info) {
457 .dev = { .parent = &pdev->dev },
458 .name = pdev->dev.init_name,
459 .type = MTD_RAM,
460 .priv = map,
461 .size = resource_size(add_range),
462 .erasesize = ERASE_BLOCKSIZE * pcm_data->bus_width,
463 .writesize = 1,
464 .writebufsize = WRITE_BUFFSIZE * pcm_data->bus_width,
465 .flags = (MTD_CAP_NVRAM | MTD_POWERUP_LOCK),
466 ._read = lpddr2_nvm_read,
467 ._write = lpddr2_nvm_write,
468 ._erase = lpddr2_nvm_erase,
469 ._unlock = lpddr2_nvm_unlock,
470 ._lock = lpddr2_nvm_lock,
471 };
472
473 /* Verify the presence of the device looking for PFOW string */
474 if (!lpddr2_nvm_pfow_present(map)) {
475 pr_err("device not recognized\n");
476 return -EINVAL;
477 }
478 /* Parse partitions and register the MTD device */
479 return mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
480}
481
482/*
483 * lpddr2_nvm driver remove method
484 */
485static int lpddr2_nvm_remove(struct platform_device *pdev)
486{
487 return mtd_device_unregister(dev_get_drvdata(&pdev->dev));
488}
489
490/* Initialize platform_driver data structure for lpddr2_nvm */
491static struct platform_driver lpddr2_nvm_drv = {
492 .driver = {
493 .name = "lpddr2_nvm",
494 },
495 .probe = lpddr2_nvm_probe,
496 .remove = lpddr2_nvm_remove,
497};
498
499module_platform_driver(lpddr2_nvm_drv);
500MODULE_LICENSE("GPL");
501MODULE_AUTHOR("Vincenzo Aliberti <vincenzo.aliberti@gmail.com>");
502MODULE_DESCRIPTION("MTD driver for LPDDR2-NVM PCM memories");