Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Atmel SMC (Static Memory Controller) helper functions.
4 *
5 * Copyright (C) 2017 Atmel
6 * Copyright (C) 2017 Free Electrons
7 *
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
9 */
10
11#include <linux/mfd/syscon/atmel-smc.h>
12#include <linux/string.h>
13
14/**
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
17 *
18 * Set all fields to 0 so that one can start defining a new config.
19 */
20void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf)
21{
22 memset(conf, 0, sizeof(*conf));
23}
24EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_init);
25
26/**
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
28 * format expected by the SMC engine
29 * @ncycles: number of MCK clk cycles
30 * @msbpos: position of the MSB part of the timing field
31 * @msbwidth: width of the MSB part of the timing field
32 * @msbfactor: factor applied to the MSB
33 * @encodedval: param used to store the encoding result
34 *
35 * This function encodes the @ncycles value as described in the datasheet
36 * (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic
37 * helper which called with different parameter depending on the encoding
38 * scheme.
39 *
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
41 * the encodedval is contains the maximum val. Otherwise, 0 is returned.
42 */
43static int atmel_smc_cs_encode_ncycles(unsigned int ncycles,
44 unsigned int msbpos,
45 unsigned int msbwidth,
46 unsigned int msbfactor,
47 unsigned int *encodedval)
48{
49 unsigned int lsbmask = GENMASK(msbpos - 1, 0);
50 unsigned int msbmask = GENMASK(msbwidth - 1, 0);
51 unsigned int msb, lsb;
52 int ret = 0;
53
54 msb = ncycles / msbfactor;
55 lsb = ncycles % msbfactor;
56
57 if (lsb > lsbmask) {
58 lsb = 0;
59 msb++;
60 }
61
62 /*
63 * Let's just put the maximum we can if the requested setting does
64 * not fit in the register field.
65 * We still return -ERANGE in case the caller cares.
66 */
67 if (msb > msbmask) {
68 msb = msbmask;
69 lsb = lsbmask;
70 ret = -ERANGE;
71 }
72
73 *encodedval = (msb << msbpos) | lsb;
74
75 return ret;
76}
77
78/**
79 * atmel_smc_cs_conf_set_timing - set the SMC CS conf Txx parameter to a
80 * specific value
81 * @conf: SMC CS conf descriptor
82 * @shift: the position of the Txx field in the TIMINGS register
83 * @ncycles: value (expressed in MCK clk cycles) to assign to this Txx
84 * parameter
85 *
86 * This function encodes the @ncycles value as described in the datasheet
87 * (section "SMC Timings Register"), and then stores the result in the
88 * @conf->timings field at @shift position.
89 *
90 * Returns -EINVAL if shift is invalid, -ERANGE if ncycles does not fit in
91 * the field, and 0 otherwise.
92 */
93int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
94 unsigned int shift, unsigned int ncycles)
95{
96 unsigned int val;
97 int ret;
98
99 if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT &&
100 shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT &&
101 shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT &&
102 shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT &&
103 shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT)
104 return -EINVAL;
105
106 /*
107 * The formula described in atmel datasheets (section "HSMC Timings
108 * Register"):
109 *
110 * ncycles = (Txx[3] * 64) + Txx[2:0]
111 */
112 ret = atmel_smc_cs_encode_ncycles(ncycles, 3, 1, 64, &val);
113 conf->timings &= ~GENMASK(shift + 3, shift);
114 conf->timings |= val << shift;
115
116 return ret;
117}
118EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_timing);
119
120/**
121 * atmel_smc_cs_conf_set_setup - set the SMC CS conf xx_SETUP parameter to a
122 * specific value
123 * @conf: SMC CS conf descriptor
124 * @shift: the position of the xx_SETUP field in the SETUP register
125 * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_SETUP
126 * parameter
127 *
128 * This function encodes the @ncycles value as described in the datasheet
129 * (section "SMC Setup Register"), and then stores the result in the
130 * @conf->setup field at @shift position.
131 *
132 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
133 * the field, and 0 otherwise.
134 */
135int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
136 unsigned int shift, unsigned int ncycles)
137{
138 unsigned int val;
139 int ret;
140
141 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
142 shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
143 return -EINVAL;
144
145 /*
146 * The formula described in atmel datasheets (section "SMC Setup
147 * Register"):
148 *
149 * ncycles = (128 * xx_SETUP[5]) + xx_SETUP[4:0]
150 */
151 ret = atmel_smc_cs_encode_ncycles(ncycles, 5, 1, 128, &val);
152 conf->setup &= ~GENMASK(shift + 7, shift);
153 conf->setup |= val << shift;
154
155 return ret;
156}
157EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_setup);
158
159/**
160 * atmel_smc_cs_conf_set_pulse - set the SMC CS conf xx_PULSE parameter to a
161 * specific value
162 * @conf: SMC CS conf descriptor
163 * @shift: the position of the xx_PULSE field in the PULSE register
164 * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_PULSE
165 * parameter
166 *
167 * This function encodes the @ncycles value as described in the datasheet
168 * (section "SMC Pulse Register"), and then stores the result in the
169 * @conf->setup field at @shift position.
170 *
171 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
172 * the field, and 0 otherwise.
173 */
174int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
175 unsigned int shift, unsigned int ncycles)
176{
177 unsigned int val;
178 int ret;
179
180 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
181 shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
182 return -EINVAL;
183
184 /*
185 * The formula described in atmel datasheets (section "SMC Pulse
186 * Register"):
187 *
188 * ncycles = (256 * xx_PULSE[6]) + xx_PULSE[5:0]
189 */
190 ret = atmel_smc_cs_encode_ncycles(ncycles, 6, 1, 256, &val);
191 conf->pulse &= ~GENMASK(shift + 7, shift);
192 conf->pulse |= val << shift;
193
194 return ret;
195}
196EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_pulse);
197
198/**
199 * atmel_smc_cs_conf_set_cycle - set the SMC CS conf xx_CYCLE parameter to a
200 * specific value
201 * @conf: SMC CS conf descriptor
202 * @shift: the position of the xx_CYCLE field in the CYCLE register
203 * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_CYCLE
204 * parameter
205 *
206 * This function encodes the @ncycles value as described in the datasheet
207 * (section "SMC Cycle Register"), and then stores the result in the
208 * @conf->setup field at @shift position.
209 *
210 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
211 * the field, and 0 otherwise.
212 */
213int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
214 unsigned int shift, unsigned int ncycles)
215{
216 unsigned int val;
217 int ret;
218
219 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT)
220 return -EINVAL;
221
222 /*
223 * The formula described in atmel datasheets (section "SMC Cycle
224 * Register"):
225 *
226 * ncycles = (xx_CYCLE[8:7] * 256) + xx_CYCLE[6:0]
227 */
228 ret = atmel_smc_cs_encode_ncycles(ncycles, 7, 2, 256, &val);
229 conf->cycle &= ~GENMASK(shift + 15, shift);
230 conf->cycle |= val << shift;
231
232 return ret;
233}
234EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_cycle);
235
236/**
237 * atmel_smc_cs_conf_apply - apply an SMC CS conf
238 * @regmap: the SMC regmap
239 * @cs: the CS id
240 * @conf: the SMC CS conf to apply
241 *
242 * Applies an SMC CS configuration.
243 * Only valid on at91sam9 SoCs.
244 */
245void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
246 const struct atmel_smc_cs_conf *conf)
247{
248 regmap_write(regmap, ATMEL_SMC_SETUP(cs), conf->setup);
249 regmap_write(regmap, ATMEL_SMC_PULSE(cs), conf->pulse);
250 regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle);
251 regmap_write(regmap, ATMEL_SMC_MODE(cs), conf->mode);
252}
253EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_apply);
254
255/**
256 * atmel_hsmc_cs_conf_apply - apply an SMC CS conf
257 * @regmap: the HSMC regmap
258 * @cs: the CS id
259 * @layout: the layout of registers
260 * @conf: the SMC CS conf to apply
261 *
262 * Applies an SMC CS configuration.
263 * Only valid on post-sama5 SoCs.
264 */
265void atmel_hsmc_cs_conf_apply(struct regmap *regmap,
266 const struct atmel_hsmc_reg_layout *layout,
267 int cs, const struct atmel_smc_cs_conf *conf)
268{
269 regmap_write(regmap, ATMEL_HSMC_SETUP(layout, cs), conf->setup);
270 regmap_write(regmap, ATMEL_HSMC_PULSE(layout, cs), conf->pulse);
271 regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle);
272 regmap_write(regmap, ATMEL_HSMC_TIMINGS(layout, cs), conf->timings);
273 regmap_write(regmap, ATMEL_HSMC_MODE(layout, cs), conf->mode);
274}
275EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_apply);
276
277/**
278 * atmel_smc_cs_conf_get - retrieve the current SMC CS conf
279 * @regmap: the SMC regmap
280 * @cs: the CS id
281 * @conf: the SMC CS conf object to store the current conf
282 *
283 * Retrieve the SMC CS configuration.
284 * Only valid on at91sam9 SoCs.
285 */
286void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
287 struct atmel_smc_cs_conf *conf)
288{
289 regmap_read(regmap, ATMEL_SMC_SETUP(cs), &conf->setup);
290 regmap_read(regmap, ATMEL_SMC_PULSE(cs), &conf->pulse);
291 regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle);
292 regmap_read(regmap, ATMEL_SMC_MODE(cs), &conf->mode);
293}
294EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_get);
295
296/**
297 * atmel_hsmc_cs_conf_get - retrieve the current SMC CS conf
298 * @regmap: the HSMC regmap
299 * @cs: the CS id
300 * @layout: the layout of registers
301 * @conf: the SMC CS conf object to store the current conf
302 *
303 * Retrieve the SMC CS configuration.
304 * Only valid on post-sama5 SoCs.
305 */
306void atmel_hsmc_cs_conf_get(struct regmap *regmap,
307 const struct atmel_hsmc_reg_layout *layout,
308 int cs, struct atmel_smc_cs_conf *conf)
309{
310 regmap_read(regmap, ATMEL_HSMC_SETUP(layout, cs), &conf->setup);
311 regmap_read(regmap, ATMEL_HSMC_PULSE(layout, cs), &conf->pulse);
312 regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle);
313 regmap_read(regmap, ATMEL_HSMC_TIMINGS(layout, cs), &conf->timings);
314 regmap_read(regmap, ATMEL_HSMC_MODE(layout, cs), &conf->mode);
315}
316EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_get);
317
318static const struct atmel_hsmc_reg_layout sama5d3_reg_layout = {
319 .timing_regs_offset = 0x600,
320};
321
322static const struct atmel_hsmc_reg_layout sama5d2_reg_layout = {
323 .timing_regs_offset = 0x700,
324};
325
326static const struct of_device_id atmel_smc_ids[] __maybe_unused = {
327 { .compatible = "atmel,at91sam9260-smc", .data = NULL },
328 { .compatible = "atmel,sama5d3-smc", .data = &sama5d3_reg_layout },
329 { .compatible = "atmel,sama5d2-smc", .data = &sama5d2_reg_layout },
330 { /* sentinel */ },
331};
332
333/**
334 * atmel_hsmc_get_reg_layout - retrieve the layout of HSMC registers
335 * @np: the HSMC regmap
336 *
337 * Retrieve the layout of HSMC registers.
338 *
339 * Returns NULL in case of SMC, a struct atmel_hsmc_reg_layout pointer
340 * in HSMC case, otherwise ERR_PTR(-EINVAL).
341 */
342const struct atmel_hsmc_reg_layout *
343atmel_hsmc_get_reg_layout(struct device_node *np)
344{
345 const struct of_device_id *match;
346
347 match = of_match_node(atmel_smc_ids, np);
348
349 return match ? match->data : ERR_PTR(-EINVAL);
350}
351EXPORT_SYMBOL_GPL(atmel_hsmc_get_reg_layout);
1/*
2 * Atmel SMC (Static Memory Controller) helper functions.
3 *
4 * Copyright (C) 2017 Atmel
5 * Copyright (C) 2017 Free Electrons
6 *
7 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/mfd/syscon/atmel-smc.h>
15
16/**
17 * atmel_smc_cs_conf_init - initialize a SMC CS conf
18 * @conf: the SMC CS conf to initialize
19 *
20 * Set all fields to 0 so that one can start defining a new config.
21 */
22void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf)
23{
24 memset(conf, 0, sizeof(*conf));
25}
26EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_init);
27
28/**
29 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
30 * format expected by the SMC engine
31 * @ncycles: number of MCK clk cycles
32 * @msbpos: position of the MSB part of the timing field
33 * @msbwidth: width of the MSB part of the timing field
34 * @msbfactor: factor applied to the MSB
35 * @encodedval: param used to store the encoding result
36 *
37 * This function encodes the @ncycles value as described in the datasheet
38 * (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic
39 * helper which called with different parameter depending on the encoding
40 * scheme.
41 *
42 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
43 * the encodedval is contains the maximum val. Otherwise, 0 is returned.
44 */
45static int atmel_smc_cs_encode_ncycles(unsigned int ncycles,
46 unsigned int msbpos,
47 unsigned int msbwidth,
48 unsigned int msbfactor,
49 unsigned int *encodedval)
50{
51 unsigned int lsbmask = GENMASK(msbpos - 1, 0);
52 unsigned int msbmask = GENMASK(msbwidth - 1, 0);
53 unsigned int msb, lsb;
54 int ret = 0;
55
56 msb = ncycles / msbfactor;
57 lsb = ncycles % msbfactor;
58
59 if (lsb > lsbmask) {
60 lsb = 0;
61 msb++;
62 }
63
64 /*
65 * Let's just put the maximum we can if the requested setting does
66 * not fit in the register field.
67 * We still return -ERANGE in case the caller cares.
68 */
69 if (msb > msbmask) {
70 msb = msbmask;
71 lsb = lsbmask;
72 ret = -ERANGE;
73 }
74
75 *encodedval = (msb << msbpos) | lsb;
76
77 return ret;
78}
79
80/**
81 * atmel_smc_cs_conf_set_timing - set the SMC CS conf Txx parameter to a
82 * specific value
83 * @conf: SMC CS conf descriptor
84 * @shift: the position of the Txx field in the TIMINGS register
85 * @ncycles: value (expressed in MCK clk cycles) to assign to this Txx
86 * parameter
87 *
88 * This function encodes the @ncycles value as described in the datasheet
89 * (section "SMC Timings Register"), and then stores the result in the
90 * @conf->timings field at @shift position.
91 *
92 * Returns -EINVAL if shift is invalid, -ERANGE if ncycles does not fit in
93 * the field, and 0 otherwise.
94 */
95int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
96 unsigned int shift, unsigned int ncycles)
97{
98 unsigned int val;
99 int ret;
100
101 if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT &&
102 shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT &&
103 shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT &&
104 shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT &&
105 shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT)
106 return -EINVAL;
107
108 /*
109 * The formula described in atmel datasheets (section "HSMC Timings
110 * Register"):
111 *
112 * ncycles = (Txx[3] * 64) + Txx[2:0]
113 */
114 ret = atmel_smc_cs_encode_ncycles(ncycles, 3, 1, 64, &val);
115 conf->timings &= ~GENMASK(shift + 3, shift);
116 conf->timings |= val << shift;
117
118 return ret;
119}
120EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_timing);
121
122/**
123 * atmel_smc_cs_conf_set_setup - set the SMC CS conf xx_SETUP parameter to a
124 * specific value
125 * @conf: SMC CS conf descriptor
126 * @shift: the position of the xx_SETUP field in the SETUP register
127 * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_SETUP
128 * parameter
129 *
130 * This function encodes the @ncycles value as described in the datasheet
131 * (section "SMC Setup Register"), and then stores the result in the
132 * @conf->setup field at @shift position.
133 *
134 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
135 * the field, and 0 otherwise.
136 */
137int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
138 unsigned int shift, unsigned int ncycles)
139{
140 unsigned int val;
141 int ret;
142
143 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
144 shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
145 return -EINVAL;
146
147 /*
148 * The formula described in atmel datasheets (section "SMC Setup
149 * Register"):
150 *
151 * ncycles = (128 * xx_SETUP[5]) + xx_SETUP[4:0]
152 */
153 ret = atmel_smc_cs_encode_ncycles(ncycles, 5, 1, 128, &val);
154 conf->setup &= ~GENMASK(shift + 7, shift);
155 conf->setup |= val << shift;
156
157 return ret;
158}
159EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_setup);
160
161/**
162 * atmel_smc_cs_conf_set_pulse - set the SMC CS conf xx_PULSE parameter to a
163 * specific value
164 * @conf: SMC CS conf descriptor
165 * @shift: the position of the xx_PULSE field in the PULSE register
166 * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_PULSE
167 * parameter
168 *
169 * This function encodes the @ncycles value as described in the datasheet
170 * (section "SMC Pulse Register"), and then stores the result in the
171 * @conf->setup field at @shift position.
172 *
173 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
174 * the field, and 0 otherwise.
175 */
176int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
177 unsigned int shift, unsigned int ncycles)
178{
179 unsigned int val;
180 int ret;
181
182 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
183 shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
184 return -EINVAL;
185
186 /*
187 * The formula described in atmel datasheets (section "SMC Pulse
188 * Register"):
189 *
190 * ncycles = (256 * xx_PULSE[6]) + xx_PULSE[5:0]
191 */
192 ret = atmel_smc_cs_encode_ncycles(ncycles, 6, 1, 256, &val);
193 conf->pulse &= ~GENMASK(shift + 7, shift);
194 conf->pulse |= val << shift;
195
196 return ret;
197}
198EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_pulse);
199
200/**
201 * atmel_smc_cs_conf_set_cycle - set the SMC CS conf xx_CYCLE parameter to a
202 * specific value
203 * @conf: SMC CS conf descriptor
204 * @shift: the position of the xx_CYCLE field in the CYCLE register
205 * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_CYCLE
206 * parameter
207 *
208 * This function encodes the @ncycles value as described in the datasheet
209 * (section "SMC Cycle Register"), and then stores the result in the
210 * @conf->setup field at @shift position.
211 *
212 * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
213 * the field, and 0 otherwise.
214 */
215int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
216 unsigned int shift, unsigned int ncycles)
217{
218 unsigned int val;
219 int ret;
220
221 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT)
222 return -EINVAL;
223
224 /*
225 * The formula described in atmel datasheets (section "SMC Cycle
226 * Register"):
227 *
228 * ncycles = (xx_CYCLE[8:7] * 256) + xx_CYCLE[6:0]
229 */
230 ret = atmel_smc_cs_encode_ncycles(ncycles, 7, 2, 256, &val);
231 conf->cycle &= ~GENMASK(shift + 15, shift);
232 conf->cycle |= val << shift;
233
234 return ret;
235}
236EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_cycle);
237
238/**
239 * atmel_smc_cs_conf_apply - apply an SMC CS conf
240 * @regmap: the SMC regmap
241 * @cs: the CS id
242 * @conf the SMC CS conf to apply
243 *
244 * Applies an SMC CS configuration.
245 * Only valid on at91sam9/avr32 SoCs.
246 */
247void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
248 const struct atmel_smc_cs_conf *conf)
249{
250 regmap_write(regmap, ATMEL_SMC_SETUP(cs), conf->setup);
251 regmap_write(regmap, ATMEL_SMC_PULSE(cs), conf->pulse);
252 regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle);
253 regmap_write(regmap, ATMEL_SMC_MODE(cs), conf->mode);
254}
255EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_apply);
256
257/**
258 * atmel_hsmc_cs_conf_apply - apply an SMC CS conf
259 * @regmap: the HSMC regmap
260 * @cs: the CS id
261 * @layout: the layout of registers
262 * @conf the SMC CS conf to apply
263 *
264 * Applies an SMC CS configuration.
265 * Only valid on post-sama5 SoCs.
266 */
267void atmel_hsmc_cs_conf_apply(struct regmap *regmap,
268 const struct atmel_hsmc_reg_layout *layout,
269 int cs, const struct atmel_smc_cs_conf *conf)
270{
271 regmap_write(regmap, ATMEL_HSMC_SETUP(layout, cs), conf->setup);
272 regmap_write(regmap, ATMEL_HSMC_PULSE(layout, cs), conf->pulse);
273 regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle);
274 regmap_write(regmap, ATMEL_HSMC_TIMINGS(layout, cs), conf->timings);
275 regmap_write(regmap, ATMEL_HSMC_MODE(layout, cs), conf->mode);
276}
277EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_apply);
278
279/**
280 * atmel_smc_cs_conf_get - retrieve the current SMC CS conf
281 * @regmap: the SMC regmap
282 * @cs: the CS id
283 * @conf: the SMC CS conf object to store the current conf
284 *
285 * Retrieve the SMC CS configuration.
286 * Only valid on at91sam9/avr32 SoCs.
287 */
288void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
289 struct atmel_smc_cs_conf *conf)
290{
291 regmap_read(regmap, ATMEL_SMC_SETUP(cs), &conf->setup);
292 regmap_read(regmap, ATMEL_SMC_PULSE(cs), &conf->pulse);
293 regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle);
294 regmap_read(regmap, ATMEL_SMC_MODE(cs), &conf->mode);
295}
296EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_get);
297
298/**
299 * atmel_hsmc_cs_conf_get - retrieve the current SMC CS conf
300 * @regmap: the HSMC regmap
301 * @cs: the CS id
302 * @layout: the layout of registers
303 * @conf: the SMC CS conf object to store the current conf
304 *
305 * Retrieve the SMC CS configuration.
306 * Only valid on post-sama5 SoCs.
307 */
308void atmel_hsmc_cs_conf_get(struct regmap *regmap,
309 const struct atmel_hsmc_reg_layout *layout,
310 int cs, struct atmel_smc_cs_conf *conf)
311{
312 regmap_read(regmap, ATMEL_HSMC_SETUP(layout, cs), &conf->setup);
313 regmap_read(regmap, ATMEL_HSMC_PULSE(layout, cs), &conf->pulse);
314 regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle);
315 regmap_read(regmap, ATMEL_HSMC_TIMINGS(layout, cs), &conf->timings);
316 regmap_read(regmap, ATMEL_HSMC_MODE(layout, cs), &conf->mode);
317}
318EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_get);
319
320static const struct atmel_hsmc_reg_layout sama5d3_reg_layout = {
321 .timing_regs_offset = 0x600,
322};
323
324static const struct atmel_hsmc_reg_layout sama5d2_reg_layout = {
325 .timing_regs_offset = 0x700,
326};
327
328static const struct of_device_id atmel_smc_ids[] = {
329 { .compatible = "atmel,at91sam9260-smc", .data = NULL },
330 { .compatible = "atmel,sama5d3-smc", .data = &sama5d3_reg_layout },
331 { .compatible = "atmel,sama5d2-smc", .data = &sama5d2_reg_layout },
332 { /* sentinel */ },
333};
334
335/**
336 * atmel_hsmc_get_reg_layout - retrieve the layout of HSMC registers
337 * @np: the HSMC regmap
338 *
339 * Retrieve the layout of HSMC registers.
340 *
341 * Returns NULL in case of SMC, a struct atmel_hsmc_reg_layout pointer
342 * in HSMC case, otherwise ERR_PTR(-EINVAL).
343 */
344const struct atmel_hsmc_reg_layout *
345atmel_hsmc_get_reg_layout(struct device_node *np)
346{
347 const struct of_device_id *match;
348
349 match = of_match_node(atmel_smc_ids, np);
350
351 return match ? match->data : ERR_PTR(-EINVAL);
352}
353EXPORT_SYMBOL_GPL(atmel_hsmc_get_reg_layout);