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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for MIPS Goldfish Programmable Interrupt Controller.
4 *
5 * Author: Miodrag Dinic <miodrag.dinic@mips.com>
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/interrupt.h>
11#include <linux/irq.h>
12#include <linux/irqchip.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/irqdomain.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17
18#define GFPIC_NR_IRQS 32
19
20/* 8..39 Cascaded Goldfish PIC interrupts */
21#define GFPIC_IRQ_BASE 8
22
23#define GFPIC_REG_IRQ_PENDING 0x04
24#define GFPIC_REG_IRQ_DISABLE_ALL 0x08
25#define GFPIC_REG_IRQ_DISABLE 0x0c
26#define GFPIC_REG_IRQ_ENABLE 0x10
27
28struct goldfish_pic_data {
29 void __iomem *base;
30 struct irq_domain *irq_domain;
31};
32
33static void goldfish_pic_cascade(struct irq_desc *desc)
34{
35 struct goldfish_pic_data *gfpic = irq_desc_get_handler_data(desc);
36 struct irq_chip *host_chip = irq_desc_get_chip(desc);
37 u32 pending, hwirq;
38
39 chained_irq_enter(host_chip, desc);
40
41 pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING);
42 while (pending) {
43 hwirq = __fls(pending);
44 generic_handle_domain_irq(gfpic->irq_domain, hwirq);
45 pending &= ~(1 << hwirq);
46 }
47
48 chained_irq_exit(host_chip, desc);
49}
50
51static const struct irq_domain_ops goldfish_irq_domain_ops = {
52 .xlate = irq_domain_xlate_onecell,
53};
54
55static int __init goldfish_pic_of_init(struct device_node *of_node,
56 struct device_node *parent)
57{
58 struct goldfish_pic_data *gfpic;
59 struct irq_chip_generic *gc;
60 struct irq_chip_type *ct;
61 unsigned int parent_irq;
62 int ret = 0;
63
64 gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
65 if (!gfpic) {
66 ret = -ENOMEM;
67 goto out_err;
68 }
69
70 parent_irq = irq_of_parse_and_map(of_node, 0);
71 if (!parent_irq) {
72 pr_err("Failed to map parent IRQ!\n");
73 ret = -EINVAL;
74 goto out_free;
75 }
76
77 gfpic->base = of_iomap(of_node, 0);
78 if (!gfpic->base) {
79 pr_err("Failed to map base address!\n");
80 ret = -ENOMEM;
81 goto out_unmap_irq;
82 }
83
84 /* Mask interrupts. */
85 writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
86
87 gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
88 handle_level_irq);
89 if (!gc) {
90 pr_err("Failed to allocate chip structures!\n");
91 ret = -ENOMEM;
92 goto out_iounmap;
93 }
94
95 ct = gc->chip_types;
96 ct->regs.enable = GFPIC_REG_IRQ_ENABLE;
97 ct->regs.disable = GFPIC_REG_IRQ_DISABLE;
98 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
99 ct->chip.irq_mask = irq_gc_mask_disable_reg;
100
101 irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0,
102 IRQ_NOPROBE | IRQ_LEVEL, 0);
103
104 gfpic->irq_domain = irq_domain_add_legacy(of_node, GFPIC_NR_IRQS,
105 GFPIC_IRQ_BASE, 0,
106 &goldfish_irq_domain_ops,
107 NULL);
108 if (!gfpic->irq_domain) {
109 pr_err("Failed to add irqdomain!\n");
110 ret = -ENOMEM;
111 goto out_destroy_generic_chip;
112 }
113
114 irq_set_chained_handler_and_data(parent_irq,
115 goldfish_pic_cascade, gfpic);
116
117 pr_info("Successfully registered.\n");
118 return 0;
119
120out_destroy_generic_chip:
121 irq_destroy_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS),
122 IRQ_NOPROBE | IRQ_LEVEL, 0);
123out_iounmap:
124 iounmap(gfpic->base);
125out_unmap_irq:
126 irq_dispose_mapping(parent_irq);
127out_free:
128 kfree(gfpic);
129out_err:
130 pr_err("Failed to initialize! (errno = %d)\n", ret);
131 return ret;
132}
133
134IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);
1/*
2 * Driver for MIPS Goldfish Programmable Interrupt Controller.
3 *
4 * Author: Miodrag Dinic <miodrag.dinic@mips.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/irqchip.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/irqdomain.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21
22#define GFPIC_NR_IRQS 32
23
24/* 8..39 Cascaded Goldfish PIC interrupts */
25#define GFPIC_IRQ_BASE 8
26
27#define GFPIC_REG_IRQ_PENDING 0x04
28#define GFPIC_REG_IRQ_DISABLE_ALL 0x08
29#define GFPIC_REG_IRQ_DISABLE 0x0c
30#define GFPIC_REG_IRQ_ENABLE 0x10
31
32struct goldfish_pic_data {
33 void __iomem *base;
34 struct irq_domain *irq_domain;
35};
36
37static void goldfish_pic_cascade(struct irq_desc *desc)
38{
39 struct goldfish_pic_data *gfpic = irq_desc_get_handler_data(desc);
40 struct irq_chip *host_chip = irq_desc_get_chip(desc);
41 u32 pending, hwirq, virq;
42
43 chained_irq_enter(host_chip, desc);
44
45 pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING);
46 while (pending) {
47 hwirq = __fls(pending);
48 virq = irq_linear_revmap(gfpic->irq_domain, hwirq);
49 generic_handle_irq(virq);
50 pending &= ~(1 << hwirq);
51 }
52
53 chained_irq_exit(host_chip, desc);
54}
55
56static const struct irq_domain_ops goldfish_irq_domain_ops = {
57 .xlate = irq_domain_xlate_onecell,
58};
59
60static int __init goldfish_pic_of_init(struct device_node *of_node,
61 struct device_node *parent)
62{
63 struct goldfish_pic_data *gfpic;
64 struct irq_chip_generic *gc;
65 struct irq_chip_type *ct;
66 unsigned int parent_irq;
67 int ret = 0;
68
69 gfpic = kzalloc(sizeof(*gfpic), GFP_KERNEL);
70 if (!gfpic) {
71 ret = -ENOMEM;
72 goto out_err;
73 }
74
75 parent_irq = irq_of_parse_and_map(of_node, 0);
76 if (!parent_irq) {
77 pr_err("Failed to map parent IRQ!\n");
78 ret = -EINVAL;
79 goto out_free;
80 }
81
82 gfpic->base = of_iomap(of_node, 0);
83 if (!gfpic->base) {
84 pr_err("Failed to map base address!\n");
85 ret = -ENOMEM;
86 goto out_unmap_irq;
87 }
88
89 /* Mask interrupts. */
90 writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
91
92 gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base,
93 handle_level_irq);
94 if (!gc) {
95 pr_err("Failed to allocate chip structures!\n");
96 ret = -ENOMEM;
97 goto out_iounmap;
98 }
99
100 ct = gc->chip_types;
101 ct->regs.enable = GFPIC_REG_IRQ_ENABLE;
102 ct->regs.disable = GFPIC_REG_IRQ_DISABLE;
103 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
104 ct->chip.irq_mask = irq_gc_mask_disable_reg;
105
106 irq_setup_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS), 0,
107 IRQ_NOPROBE | IRQ_LEVEL, 0);
108
109 gfpic->irq_domain = irq_domain_add_legacy(of_node, GFPIC_NR_IRQS,
110 GFPIC_IRQ_BASE, 0,
111 &goldfish_irq_domain_ops,
112 NULL);
113 if (!gfpic->irq_domain) {
114 pr_err("Failed to add irqdomain!\n");
115 ret = -ENOMEM;
116 goto out_destroy_generic_chip;
117 }
118
119 irq_set_chained_handler_and_data(parent_irq,
120 goldfish_pic_cascade, gfpic);
121
122 pr_info("Successfully registered.\n");
123 return 0;
124
125out_destroy_generic_chip:
126 irq_destroy_generic_chip(gc, IRQ_MSK(GFPIC_NR_IRQS),
127 IRQ_NOPROBE | IRQ_LEVEL, 0);
128out_iounmap:
129 iounmap(gfpic->base);
130out_unmap_irq:
131 irq_dispose_mapping(parent_irq);
132out_free:
133 kfree(gfpic);
134out_err:
135 pr_err("Failed to initialize! (errno = %d)\n", ret);
136 return ret;
137}
138
139IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);