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1/*
2 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
3 *
4 * Copyright (C) 2011 Weinmann Medical GmbH
5 * Author: Nikolaus Voss <n.voss@weinmann.de>
6 *
7 * Evolved from original work by:
8 * Copyright (C) 2004 Rick Bronson
9 * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
10 *
11 * Borrowed heavily from original work by:
12 * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 */
19
20#include <linux/clk.h>
21#include <linux/completion.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/err.h>
25#include <linux/i2c.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/platform_device.h>
32#include <linux/slab.h>
33#include <linux/platform_data/dma-atmel.h>
34#include <linux/pm_runtime.h>
35#include <linux/pinctrl/consumer.h>
36
37#define DEFAULT_TWI_CLK_HZ 100000 /* max 400 Kbits/s */
38#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
39#define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */
40#define AUTOSUSPEND_TIMEOUT 2000
41#define AT91_I2C_MAX_ALT_CMD_DATA_SIZE 256
42
43/* AT91 TWI register definitions */
44#define AT91_TWI_CR 0x0000 /* Control Register */
45#define AT91_TWI_START BIT(0) /* Send a Start Condition */
46#define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */
47#define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */
48#define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
49#define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */
50#define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
51#define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
52#define AT91_TWI_SWRST BIT(7) /* Software Reset */
53#define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */
54#define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
55#define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */
56#define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */
57#define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */
58#define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */
59#define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */
60
61#define AT91_TWI_MMR 0x0004 /* Master Mode Register */
62#define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */
63#define AT91_TWI_MREAD BIT(12) /* Master Read Direction */
64
65#define AT91_TWI_IADR 0x000c /* Internal Address Register */
66
67#define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */
68#define AT91_TWI_CWGR_HOLD_MAX 0x1f
69#define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
70
71#define AT91_TWI_SR 0x0020 /* Status Register */
72#define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */
73#define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */
74#define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */
75#define AT91_TWI_OVRE BIT(6) /* Overrun Error */
76#define AT91_TWI_UNRE BIT(7) /* Underrun Error */
77#define AT91_TWI_NACK BIT(8) /* Not Acknowledged */
78#define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */
79
80#define AT91_TWI_INT_MASK \
81 (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK)
82
83#define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */
84#define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
85#define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */
86#define AT91_TWI_RHR 0x0030 /* Receive Holding Register */
87#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
88
89#define AT91_TWI_ACR 0x0040 /* Alternative Command Register */
90#define AT91_TWI_ACR_DATAL(len) ((len) & 0xff)
91#define AT91_TWI_ACR_DIR BIT(8)
92
93#define AT91_TWI_FMR 0x0050 /* FIFO Mode Register */
94#define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0)
95#define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0)
96#define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4)
97#define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4)
98#define AT91_TWI_ONE_DATA 0x0
99#define AT91_TWI_TWO_DATA 0x1
100#define AT91_TWI_FOUR_DATA 0x2
101
102#define AT91_TWI_FLR 0x0054 /* FIFO Level Register */
103
104#define AT91_TWI_FSR 0x0060 /* FIFO Status Register */
105#define AT91_TWI_FIER 0x0064 /* FIFO Interrupt Enable Register */
106#define AT91_TWI_FIDR 0x0068 /* FIFO Interrupt Disable Register */
107#define AT91_TWI_FIMR 0x006c /* FIFO Interrupt Mask Register */
108
109#define AT91_TWI_VER 0x00fc /* Version Register */
110
111struct at91_twi_pdata {
112 unsigned clk_max_div;
113 unsigned clk_offset;
114 bool has_unre_flag;
115 bool has_alt_cmd;
116 bool has_hold_field;
117 struct at_dma_slave dma_slave;
118};
119
120struct at91_twi_dma {
121 struct dma_chan *chan_rx;
122 struct dma_chan *chan_tx;
123 struct scatterlist sg[2];
124 struct dma_async_tx_descriptor *data_desc;
125 enum dma_data_direction direction;
126 bool buf_mapped;
127 bool xfer_in_progress;
128};
129
130struct at91_twi_dev {
131 struct device *dev;
132 void __iomem *base;
133 struct completion cmd_complete;
134 struct clk *clk;
135 u8 *buf;
136 size_t buf_len;
137 struct i2c_msg *msg;
138 int irq;
139 unsigned imr;
140 unsigned transfer_status;
141 struct i2c_adapter adapter;
142 unsigned twi_cwgr_reg;
143 struct at91_twi_pdata *pdata;
144 bool use_dma;
145 bool use_alt_cmd;
146 bool recv_len_abort;
147 u32 fifo_size;
148 struct at91_twi_dma dma;
149};
150
151static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
152{
153 return readl_relaxed(dev->base + reg);
154}
155
156static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
157{
158 writel_relaxed(val, dev->base + reg);
159}
160
161static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
162{
163 at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_INT_MASK);
164}
165
166static void at91_twi_irq_save(struct at91_twi_dev *dev)
167{
168 dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & AT91_TWI_INT_MASK;
169 at91_disable_twi_interrupts(dev);
170}
171
172static void at91_twi_irq_restore(struct at91_twi_dev *dev)
173{
174 at91_twi_write(dev, AT91_TWI_IER, dev->imr);
175}
176
177static void at91_init_twi_bus(struct at91_twi_dev *dev)
178{
179 at91_disable_twi_interrupts(dev);
180 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
181 /* FIFO should be enabled immediately after the software reset */
182 if (dev->fifo_size)
183 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_FIFOEN);
184 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
185 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
186 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
187}
188
189/*
190 * Calculate symmetric clock as stated in datasheet:
191 * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
192 */
193static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
194{
195 int ckdiv, cdiv, div, hold = 0;
196 struct at91_twi_pdata *pdata = dev->pdata;
197 int offset = pdata->clk_offset;
198 int max_ckdiv = pdata->clk_max_div;
199 u32 twd_hold_time_ns = 0;
200
201 div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
202 2 * twi_clk) - offset);
203 ckdiv = fls(div >> 8);
204 cdiv = div >> ckdiv;
205
206 if (ckdiv > max_ckdiv) {
207 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
208 ckdiv, max_ckdiv);
209 ckdiv = max_ckdiv;
210 cdiv = 255;
211 }
212
213 if (pdata->has_hold_field) {
214 of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
215 &twd_hold_time_ns);
216
217 /*
218 * hold time = HOLD + 3 x T_peripheral_clock
219 * Use clk rate in kHz to prevent overflows when computing
220 * hold.
221 */
222 hold = DIV_ROUND_UP(twd_hold_time_ns
223 * (clk_get_rate(dev->clk) / 1000), 1000000);
224 hold -= 3;
225 if (hold < 0)
226 hold = 0;
227 if (hold > AT91_TWI_CWGR_HOLD_MAX) {
228 dev_warn(dev->dev,
229 "HOLD field set to its maximum value (%d instead of %d)\n",
230 AT91_TWI_CWGR_HOLD_MAX, hold);
231 hold = AT91_TWI_CWGR_HOLD_MAX;
232 }
233 }
234
235 dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
236 | AT91_TWI_CWGR_HOLD(hold);
237
238 dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
239 cdiv, ckdiv, hold, twd_hold_time_ns);
240}
241
242static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
243{
244 struct at91_twi_dma *dma = &dev->dma;
245
246 at91_twi_irq_save(dev);
247
248 if (dma->xfer_in_progress) {
249 if (dma->direction == DMA_FROM_DEVICE)
250 dmaengine_terminate_all(dma->chan_rx);
251 else
252 dmaengine_terminate_all(dma->chan_tx);
253 dma->xfer_in_progress = false;
254 }
255 if (dma->buf_mapped) {
256 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg[0]),
257 dev->buf_len, dma->direction);
258 dma->buf_mapped = false;
259 }
260
261 at91_twi_irq_restore(dev);
262}
263
264static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
265{
266 if (!dev->buf_len)
267 return;
268
269 /* 8bit write works with and without FIFO */
270 writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR);
271
272 /* send stop when last byte has been written */
273 if (--dev->buf_len == 0)
274 if (!dev->use_alt_cmd)
275 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
276
277 dev_dbg(dev->dev, "wrote 0x%x, to go %zu\n", *dev->buf, dev->buf_len);
278
279 ++dev->buf;
280}
281
282static void at91_twi_write_data_dma_callback(void *data)
283{
284 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
285
286 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
287 dev->buf_len, DMA_TO_DEVICE);
288
289 /*
290 * When this callback is called, THR/TX FIFO is likely not to be empty
291 * yet. So we have to wait for TXCOMP or NACK bits to be set into the
292 * Status Register to be sure that the STOP bit has been sent and the
293 * transfer is completed. The NACK interrupt has already been enabled,
294 * we just have to enable TXCOMP one.
295 */
296 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
297 if (!dev->use_alt_cmd)
298 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
299}
300
301static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
302{
303 dma_addr_t dma_addr;
304 struct dma_async_tx_descriptor *txdesc;
305 struct at91_twi_dma *dma = &dev->dma;
306 struct dma_chan *chan_tx = dma->chan_tx;
307 unsigned int sg_len = 1;
308
309 if (!dev->buf_len)
310 return;
311
312 dma->direction = DMA_TO_DEVICE;
313
314 at91_twi_irq_save(dev);
315 dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
316 DMA_TO_DEVICE);
317 if (dma_mapping_error(dev->dev, dma_addr)) {
318 dev_err(dev->dev, "dma map failed\n");
319 return;
320 }
321 dma->buf_mapped = true;
322 at91_twi_irq_restore(dev);
323
324 if (dev->fifo_size) {
325 size_t part1_len, part2_len;
326 struct scatterlist *sg;
327 unsigned fifo_mr;
328
329 sg_len = 0;
330
331 part1_len = dev->buf_len & ~0x3;
332 if (part1_len) {
333 sg = &dma->sg[sg_len++];
334 sg_dma_len(sg) = part1_len;
335 sg_dma_address(sg) = dma_addr;
336 }
337
338 part2_len = dev->buf_len & 0x3;
339 if (part2_len) {
340 sg = &dma->sg[sg_len++];
341 sg_dma_len(sg) = part2_len;
342 sg_dma_address(sg) = dma_addr + part1_len;
343 }
344
345 /*
346 * DMA controller is triggered when at least 4 data can be
347 * written into the TX FIFO
348 */
349 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
350 fifo_mr &= ~AT91_TWI_FMR_TXRDYM_MASK;
351 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_FOUR_DATA);
352 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
353 } else {
354 sg_dma_len(&dma->sg[0]) = dev->buf_len;
355 sg_dma_address(&dma->sg[0]) = dma_addr;
356 }
357
358 txdesc = dmaengine_prep_slave_sg(chan_tx, dma->sg, sg_len,
359 DMA_MEM_TO_DEV,
360 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
361 if (!txdesc) {
362 dev_err(dev->dev, "dma prep slave sg failed\n");
363 goto error;
364 }
365
366 txdesc->callback = at91_twi_write_data_dma_callback;
367 txdesc->callback_param = dev;
368
369 dma->xfer_in_progress = true;
370 dmaengine_submit(txdesc);
371 dma_async_issue_pending(chan_tx);
372
373 return;
374
375error:
376 at91_twi_dma_cleanup(dev);
377}
378
379static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
380{
381 /*
382 * If we are in this case, it means there is garbage data in RHR, so
383 * delete them.
384 */
385 if (!dev->buf_len) {
386 at91_twi_read(dev, AT91_TWI_RHR);
387 return;
388 }
389
390 /* 8bit read works with and without FIFO */
391 *dev->buf = readb_relaxed(dev->base + AT91_TWI_RHR);
392 --dev->buf_len;
393
394 /* return if aborting, we only needed to read RHR to clear RXRDY*/
395 if (dev->recv_len_abort)
396 return;
397
398 /* handle I2C_SMBUS_BLOCK_DATA */
399 if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
400 /* ensure length byte is a valid value */
401 if (*dev->buf <= I2C_SMBUS_BLOCK_MAX && *dev->buf > 0) {
402 dev->msg->flags &= ~I2C_M_RECV_LEN;
403 dev->buf_len += *dev->buf;
404 dev->msg->len = dev->buf_len + 1;
405 dev_dbg(dev->dev, "received block length %zu\n",
406 dev->buf_len);
407 } else {
408 /* abort and send the stop by reading one more byte */
409 dev->recv_len_abort = true;
410 dev->buf_len = 1;
411 }
412 }
413
414 /* send stop if second but last byte has been read */
415 if (!dev->use_alt_cmd && dev->buf_len == 1)
416 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
417
418 dev_dbg(dev->dev, "read 0x%x, to go %zu\n", *dev->buf, dev->buf_len);
419
420 ++dev->buf;
421}
422
423static void at91_twi_read_data_dma_callback(void *data)
424{
425 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
426 unsigned ier = AT91_TWI_TXCOMP;
427
428 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
429 dev->buf_len, DMA_FROM_DEVICE);
430
431 if (!dev->use_alt_cmd) {
432 /* The last two bytes have to be read without using dma */
433 dev->buf += dev->buf_len - 2;
434 dev->buf_len = 2;
435 ier |= AT91_TWI_RXRDY;
436 }
437 at91_twi_write(dev, AT91_TWI_IER, ier);
438}
439
440static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
441{
442 dma_addr_t dma_addr;
443 struct dma_async_tx_descriptor *rxdesc;
444 struct at91_twi_dma *dma = &dev->dma;
445 struct dma_chan *chan_rx = dma->chan_rx;
446 size_t buf_len;
447
448 buf_len = (dev->use_alt_cmd) ? dev->buf_len : dev->buf_len - 2;
449 dma->direction = DMA_FROM_DEVICE;
450
451 /* Keep in mind that we won't use dma to read the last two bytes */
452 at91_twi_irq_save(dev);
453 dma_addr = dma_map_single(dev->dev, dev->buf, buf_len, DMA_FROM_DEVICE);
454 if (dma_mapping_error(dev->dev, dma_addr)) {
455 dev_err(dev->dev, "dma map failed\n");
456 return;
457 }
458 dma->buf_mapped = true;
459 at91_twi_irq_restore(dev);
460
461 if (dev->fifo_size && IS_ALIGNED(buf_len, 4)) {
462 unsigned fifo_mr;
463
464 /*
465 * DMA controller is triggered when at least 4 data can be
466 * read from the RX FIFO
467 */
468 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
469 fifo_mr &= ~AT91_TWI_FMR_RXRDYM_MASK;
470 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_FOUR_DATA);
471 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
472 }
473
474 sg_dma_len(&dma->sg[0]) = buf_len;
475 sg_dma_address(&dma->sg[0]) = dma_addr;
476
477 rxdesc = dmaengine_prep_slave_sg(chan_rx, dma->sg, 1, DMA_DEV_TO_MEM,
478 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
479 if (!rxdesc) {
480 dev_err(dev->dev, "dma prep slave sg failed\n");
481 goto error;
482 }
483
484 rxdesc->callback = at91_twi_read_data_dma_callback;
485 rxdesc->callback_param = dev;
486
487 dma->xfer_in_progress = true;
488 dmaengine_submit(rxdesc);
489 dma_async_issue_pending(dma->chan_rx);
490
491 return;
492
493error:
494 at91_twi_dma_cleanup(dev);
495}
496
497static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
498{
499 struct at91_twi_dev *dev = dev_id;
500 const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
501 const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
502
503 if (!irqstatus)
504 return IRQ_NONE;
505 /*
506 * In reception, the behavior of the twi device (before sama5d2) is
507 * weird. There is some magic about RXRDY flag! When a data has been
508 * almost received, the reception of a new one is anticipated if there
509 * is no stop command to send. That is the reason why ask for sending
510 * the stop command not on the last data but on the second last one.
511 *
512 * Unfortunately, we could still have the RXRDY flag set even if the
513 * transfer is done and we have read the last data. It might happen
514 * when the i2c slave device sends too quickly data after receiving the
515 * ack from the master. The data has been almost received before having
516 * the order to send stop. In this case, sending the stop command could
517 * cause a RXRDY interrupt with a TXCOMP one. It is better to manage
518 * the RXRDY interrupt first in order to not keep garbage data in the
519 * Receive Holding Register for the next transfer.
520 */
521 if (irqstatus & AT91_TWI_RXRDY)
522 at91_twi_read_next_byte(dev);
523
524 /*
525 * When a NACK condition is detected, the I2C controller sets the NACK,
526 * TXCOMP and TXRDY bits all together in the Status Register (SR).
527 *
528 * 1 - Handling NACK errors with CPU write transfer.
529 *
530 * In such case, we should not write the next byte into the Transmit
531 * Holding Register (THR) otherwise the I2C controller would start a new
532 * transfer and the I2C slave is likely to reply by another NACK.
533 *
534 * 2 - Handling NACK errors with DMA write transfer.
535 *
536 * By setting the TXRDY bit in the SR, the I2C controller also triggers
537 * the DMA controller to write the next data into the THR. Then the
538 * result depends on the hardware version of the I2C controller.
539 *
540 * 2a - Without support of the Alternative Command mode.
541 *
542 * This is the worst case: the DMA controller is triggered to write the
543 * next data into the THR, hence starting a new transfer: the I2C slave
544 * is likely to reply by another NACK.
545 * Concurrently, this interrupt handler is likely to be called to manage
546 * the first NACK before the I2C controller detects the second NACK and
547 * sets once again the NACK bit into the SR.
548 * When handling the first NACK, this interrupt handler disables the I2C
549 * controller interruptions, especially the NACK interrupt.
550 * Hence, the NACK bit is pending into the SR. This is why we should
551 * read the SR to clear all pending interrupts at the beginning of
552 * at91_do_twi_transfer() before actually starting a new transfer.
553 *
554 * 2b - With support of the Alternative Command mode.
555 *
556 * When a NACK condition is detected, the I2C controller also locks the
557 * THR (and sets the LOCK bit in the SR): even though the DMA controller
558 * is triggered by the TXRDY bit to write the next data into the THR,
559 * this data actually won't go on the I2C bus hence a second NACK is not
560 * generated.
561 */
562 if (irqstatus & (AT91_TWI_TXCOMP | AT91_TWI_NACK)) {
563 at91_disable_twi_interrupts(dev);
564 complete(&dev->cmd_complete);
565 } else if (irqstatus & AT91_TWI_TXRDY) {
566 at91_twi_write_next_byte(dev);
567 }
568
569 /* catch error flags */
570 dev->transfer_status |= status;
571
572 return IRQ_HANDLED;
573}
574
575static int at91_do_twi_transfer(struct at91_twi_dev *dev)
576{
577 int ret;
578 unsigned long time_left;
579 bool has_unre_flag = dev->pdata->has_unre_flag;
580 bool has_alt_cmd = dev->pdata->has_alt_cmd;
581
582 /*
583 * WARNING: the TXCOMP bit in the Status Register is NOT a clear on
584 * read flag but shows the state of the transmission at the time the
585 * Status Register is read. According to the programmer datasheet,
586 * TXCOMP is set when both holding register and internal shifter are
587 * empty and STOP condition has been sent.
588 * Consequently, we should enable NACK interrupt rather than TXCOMP to
589 * detect transmission failure.
590 * Indeed let's take the case of an i2c write command using DMA.
591 * Whenever the slave doesn't acknowledge a byte, the LOCK, NACK and
592 * TXCOMP bits are set together into the Status Register.
593 * LOCK is a clear on write bit, which is set to prevent the DMA
594 * controller from sending new data on the i2c bus after a NACK
595 * condition has happened. Once locked, this i2c peripheral stops
596 * triggering the DMA controller for new data but it is more than
597 * likely that a new DMA transaction is already in progress, writing
598 * into the Transmit Holding Register. Since the peripheral is locked,
599 * these new data won't be sent to the i2c bus but they will remain
600 * into the Transmit Holding Register, so TXCOMP bit is cleared.
601 * Then when the interrupt handler is called, the Status Register is
602 * read: the TXCOMP bit is clear but NACK bit is still set. The driver
603 * manage the error properly, without waiting for timeout.
604 * This case can be reproduced easyly when writing into an at24 eeprom.
605 *
606 * Besides, the TXCOMP bit is already set before the i2c transaction
607 * has been started. For read transactions, this bit is cleared when
608 * writing the START bit into the Control Register. So the
609 * corresponding interrupt can safely be enabled just after.
610 * However for write transactions managed by the CPU, we first write
611 * into THR, so TXCOMP is cleared. Then we can safely enable TXCOMP
612 * interrupt. If TXCOMP interrupt were enabled before writing into THR,
613 * the interrupt handler would be called immediately and the i2c command
614 * would be reported as completed.
615 * Also when a write transaction is managed by the DMA controller,
616 * enabling the TXCOMP interrupt in this function may lead to a race
617 * condition since we don't know whether the TXCOMP interrupt is enabled
618 * before or after the DMA has started to write into THR. So the TXCOMP
619 * interrupt is enabled later by at91_twi_write_data_dma_callback().
620 * Immediately after in that DMA callback, if the alternative command
621 * mode is not used, we still need to send the STOP condition manually
622 * writing the corresponding bit into the Control Register.
623 */
624
625 dev_dbg(dev->dev, "transfer: %s %zu bytes.\n",
626 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
627
628 reinit_completion(&dev->cmd_complete);
629 dev->transfer_status = 0;
630
631 /* Clear pending interrupts, such as NACK. */
632 at91_twi_read(dev, AT91_TWI_SR);
633
634 if (dev->fifo_size) {
635 unsigned fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
636
637 /* Reset FIFO mode register */
638 fifo_mr &= ~(AT91_TWI_FMR_TXRDYM_MASK |
639 AT91_TWI_FMR_RXRDYM_MASK);
640 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_ONE_DATA);
641 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_ONE_DATA);
642 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
643
644 /* Flush FIFOs */
645 at91_twi_write(dev, AT91_TWI_CR,
646 AT91_TWI_THRCLR | AT91_TWI_RHRCLR);
647 }
648
649 if (!dev->buf_len) {
650 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
651 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
652 } else if (dev->msg->flags & I2C_M_RD) {
653 unsigned start_flags = AT91_TWI_START;
654
655 /* if only one byte is to be read, immediately stop transfer */
656 if (!dev->use_alt_cmd && dev->buf_len <= 1 &&
657 !(dev->msg->flags & I2C_M_RECV_LEN))
658 start_flags |= AT91_TWI_STOP;
659 at91_twi_write(dev, AT91_TWI_CR, start_flags);
660 /*
661 * When using dma without alternative command mode, the last
662 * byte has to be read manually in order to not send the stop
663 * command too late and then to receive extra data.
664 * In practice, there are some issues if you use the dma to
665 * read n-1 bytes because of latency.
666 * Reading n-2 bytes with dma and the two last ones manually
667 * seems to be the best solution.
668 */
669 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
670 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
671 at91_twi_read_data_dma(dev);
672 } else {
673 at91_twi_write(dev, AT91_TWI_IER,
674 AT91_TWI_TXCOMP |
675 AT91_TWI_NACK |
676 AT91_TWI_RXRDY);
677 }
678 } else {
679 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
680 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
681 at91_twi_write_data_dma(dev);
682 } else {
683 at91_twi_write_next_byte(dev);
684 at91_twi_write(dev, AT91_TWI_IER,
685 AT91_TWI_TXCOMP |
686 AT91_TWI_NACK |
687 AT91_TWI_TXRDY);
688 }
689 }
690
691 time_left = wait_for_completion_timeout(&dev->cmd_complete,
692 dev->adapter.timeout);
693 if (time_left == 0) {
694 dev->transfer_status |= at91_twi_read(dev, AT91_TWI_SR);
695 dev_err(dev->dev, "controller timed out\n");
696 at91_init_twi_bus(dev);
697 ret = -ETIMEDOUT;
698 goto error;
699 }
700 if (dev->transfer_status & AT91_TWI_NACK) {
701 dev_dbg(dev->dev, "received nack\n");
702 ret = -EREMOTEIO;
703 goto error;
704 }
705 if (dev->transfer_status & AT91_TWI_OVRE) {
706 dev_err(dev->dev, "overrun while reading\n");
707 ret = -EIO;
708 goto error;
709 }
710 if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
711 dev_err(dev->dev, "underrun while writing\n");
712 ret = -EIO;
713 goto error;
714 }
715 if ((has_alt_cmd || dev->fifo_size) &&
716 (dev->transfer_status & AT91_TWI_LOCK)) {
717 dev_err(dev->dev, "tx locked\n");
718 ret = -EIO;
719 goto error;
720 }
721 if (dev->recv_len_abort) {
722 dev_err(dev->dev, "invalid smbus block length recvd\n");
723 ret = -EPROTO;
724 goto error;
725 }
726
727 dev_dbg(dev->dev, "transfer complete\n");
728
729 return 0;
730
731error:
732 /* first stop DMA transfer if still in progress */
733 at91_twi_dma_cleanup(dev);
734 /* then flush THR/FIFO and unlock TX if locked */
735 if ((has_alt_cmd || dev->fifo_size) &&
736 (dev->transfer_status & AT91_TWI_LOCK)) {
737 dev_dbg(dev->dev, "unlock tx\n");
738 at91_twi_write(dev, AT91_TWI_CR,
739 AT91_TWI_THRCLR | AT91_TWI_LOCKCLR);
740 }
741 return ret;
742}
743
744static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
745{
746 struct at91_twi_dev *dev = i2c_get_adapdata(adap);
747 int ret;
748 unsigned int_addr_flag = 0;
749 struct i2c_msg *m_start = msg;
750 bool is_read;
751
752 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
753
754 ret = pm_runtime_get_sync(dev->dev);
755 if (ret < 0)
756 goto out;
757
758 if (num == 2) {
759 int internal_address = 0;
760 int i;
761
762 /* 1st msg is put into the internal address, start with 2nd */
763 m_start = &msg[1];
764 for (i = 0; i < msg->len; ++i) {
765 const unsigned addr = msg->buf[msg->len - 1 - i];
766
767 internal_address |= addr << (8 * i);
768 int_addr_flag += AT91_TWI_IADRSZ_1;
769 }
770 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
771 }
772
773 dev->use_alt_cmd = false;
774 is_read = (m_start->flags & I2C_M_RD);
775 if (dev->pdata->has_alt_cmd) {
776 if (m_start->len > 0 &&
777 m_start->len < AT91_I2C_MAX_ALT_CMD_DATA_SIZE) {
778 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMEN);
779 at91_twi_write(dev, AT91_TWI_ACR,
780 AT91_TWI_ACR_DATAL(m_start->len) |
781 ((is_read) ? AT91_TWI_ACR_DIR : 0));
782 dev->use_alt_cmd = true;
783 } else {
784 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMDIS);
785 }
786 }
787
788 at91_twi_write(dev, AT91_TWI_MMR,
789 (m_start->addr << 16) |
790 int_addr_flag |
791 ((!dev->use_alt_cmd && is_read) ? AT91_TWI_MREAD : 0));
792
793 dev->buf_len = m_start->len;
794 dev->buf = m_start->buf;
795 dev->msg = m_start;
796 dev->recv_len_abort = false;
797
798 ret = at91_do_twi_transfer(dev);
799
800 ret = (ret < 0) ? ret : num;
801out:
802 pm_runtime_mark_last_busy(dev->dev);
803 pm_runtime_put_autosuspend(dev->dev);
804
805 return ret;
806}
807
808/*
809 * The hardware can handle at most two messages concatenated by a
810 * repeated start via it's internal address feature.
811 */
812static const struct i2c_adapter_quirks at91_twi_quirks = {
813 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR,
814 .max_comb_1st_msg_len = 3,
815};
816
817static u32 at91_twi_func(struct i2c_adapter *adapter)
818{
819 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
820 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
821}
822
823static const struct i2c_algorithm at91_twi_algorithm = {
824 .master_xfer = at91_twi_xfer,
825 .functionality = at91_twi_func,
826};
827
828static struct at91_twi_pdata at91rm9200_config = {
829 .clk_max_div = 5,
830 .clk_offset = 3,
831 .has_unre_flag = true,
832 .has_alt_cmd = false,
833 .has_hold_field = false,
834};
835
836static struct at91_twi_pdata at91sam9261_config = {
837 .clk_max_div = 5,
838 .clk_offset = 4,
839 .has_unre_flag = false,
840 .has_alt_cmd = false,
841 .has_hold_field = false,
842};
843
844static struct at91_twi_pdata at91sam9260_config = {
845 .clk_max_div = 7,
846 .clk_offset = 4,
847 .has_unre_flag = false,
848 .has_alt_cmd = false,
849 .has_hold_field = false,
850};
851
852static struct at91_twi_pdata at91sam9g20_config = {
853 .clk_max_div = 7,
854 .clk_offset = 4,
855 .has_unre_flag = false,
856 .has_alt_cmd = false,
857 .has_hold_field = false,
858};
859
860static struct at91_twi_pdata at91sam9g10_config = {
861 .clk_max_div = 7,
862 .clk_offset = 4,
863 .has_unre_flag = false,
864 .has_alt_cmd = false,
865 .has_hold_field = false,
866};
867
868static const struct platform_device_id at91_twi_devtypes[] = {
869 {
870 .name = "i2c-at91rm9200",
871 .driver_data = (unsigned long) &at91rm9200_config,
872 }, {
873 .name = "i2c-at91sam9261",
874 .driver_data = (unsigned long) &at91sam9261_config,
875 }, {
876 .name = "i2c-at91sam9260",
877 .driver_data = (unsigned long) &at91sam9260_config,
878 }, {
879 .name = "i2c-at91sam9g20",
880 .driver_data = (unsigned long) &at91sam9g20_config,
881 }, {
882 .name = "i2c-at91sam9g10",
883 .driver_data = (unsigned long) &at91sam9g10_config,
884 }, {
885 /* sentinel */
886 }
887};
888
889#if defined(CONFIG_OF)
890static struct at91_twi_pdata at91sam9x5_config = {
891 .clk_max_div = 7,
892 .clk_offset = 4,
893 .has_unre_flag = false,
894 .has_alt_cmd = false,
895 .has_hold_field = false,
896};
897
898static struct at91_twi_pdata sama5d4_config = {
899 .clk_max_div = 7,
900 .clk_offset = 4,
901 .has_unre_flag = false,
902 .has_alt_cmd = false,
903 .has_hold_field = true,
904};
905
906static struct at91_twi_pdata sama5d2_config = {
907 .clk_max_div = 7,
908 .clk_offset = 4,
909 .has_unre_flag = true,
910 .has_alt_cmd = true,
911 .has_hold_field = true,
912};
913
914static const struct of_device_id atmel_twi_dt_ids[] = {
915 {
916 .compatible = "atmel,at91rm9200-i2c",
917 .data = &at91rm9200_config,
918 } , {
919 .compatible = "atmel,at91sam9260-i2c",
920 .data = &at91sam9260_config,
921 } , {
922 .compatible = "atmel,at91sam9261-i2c",
923 .data = &at91sam9261_config,
924 } , {
925 .compatible = "atmel,at91sam9g20-i2c",
926 .data = &at91sam9g20_config,
927 } , {
928 .compatible = "atmel,at91sam9g10-i2c",
929 .data = &at91sam9g10_config,
930 }, {
931 .compatible = "atmel,at91sam9x5-i2c",
932 .data = &at91sam9x5_config,
933 }, {
934 .compatible = "atmel,sama5d4-i2c",
935 .data = &sama5d4_config,
936 }, {
937 .compatible = "atmel,sama5d2-i2c",
938 .data = &sama5d2_config,
939 }, {
940 /* sentinel */
941 }
942};
943MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
944#endif
945
946static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
947{
948 int ret = 0;
949 struct dma_slave_config slave_config;
950 struct at91_twi_dma *dma = &dev->dma;
951 enum dma_slave_buswidth addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
952
953 /*
954 * The actual width of the access will be chosen in
955 * dmaengine_prep_slave_sg():
956 * for each buffer in the scatter-gather list, if its size is aligned
957 * to addr_width then addr_width accesses will be performed to transfer
958 * the buffer. On the other hand, if the buffer size is not aligned to
959 * addr_width then the buffer is transferred using single byte accesses.
960 * Please refer to the Atmel eXtended DMA controller driver.
961 * When FIFOs are used, the TXRDYM threshold can always be set to
962 * trigger the XDMAC when at least 4 data can be written into the TX
963 * FIFO, even if single byte accesses are performed.
964 * However the RXRDYM threshold must be set to fit the access width,
965 * deduced from buffer length, so the XDMAC is triggered properly to
966 * read data from the RX FIFO.
967 */
968 if (dev->fifo_size)
969 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
970
971 memset(&slave_config, 0, sizeof(slave_config));
972 slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
973 slave_config.src_addr_width = addr_width;
974 slave_config.src_maxburst = 1;
975 slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
976 slave_config.dst_addr_width = addr_width;
977 slave_config.dst_maxburst = 1;
978 slave_config.device_fc = false;
979
980 dma->chan_tx = dma_request_slave_channel_reason(dev->dev, "tx");
981 if (IS_ERR(dma->chan_tx)) {
982 ret = PTR_ERR(dma->chan_tx);
983 dma->chan_tx = NULL;
984 goto error;
985 }
986
987 dma->chan_rx = dma_request_slave_channel_reason(dev->dev, "rx");
988 if (IS_ERR(dma->chan_rx)) {
989 ret = PTR_ERR(dma->chan_rx);
990 dma->chan_rx = NULL;
991 goto error;
992 }
993
994 slave_config.direction = DMA_MEM_TO_DEV;
995 if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
996 dev_err(dev->dev, "failed to configure tx channel\n");
997 ret = -EINVAL;
998 goto error;
999 }
1000
1001 slave_config.direction = DMA_DEV_TO_MEM;
1002 if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
1003 dev_err(dev->dev, "failed to configure rx channel\n");
1004 ret = -EINVAL;
1005 goto error;
1006 }
1007
1008 sg_init_table(dma->sg, 2);
1009 dma->buf_mapped = false;
1010 dma->xfer_in_progress = false;
1011 dev->use_dma = true;
1012
1013 dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
1014 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
1015
1016 return ret;
1017
1018error:
1019 if (ret != -EPROBE_DEFER)
1020 dev_info(dev->dev, "can't get DMA channel, continue without DMA support\n");
1021 if (dma->chan_rx)
1022 dma_release_channel(dma->chan_rx);
1023 if (dma->chan_tx)
1024 dma_release_channel(dma->chan_tx);
1025 return ret;
1026}
1027
1028static struct at91_twi_pdata *at91_twi_get_driver_data(
1029 struct platform_device *pdev)
1030{
1031 if (pdev->dev.of_node) {
1032 const struct of_device_id *match;
1033 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
1034 if (!match)
1035 return NULL;
1036 return (struct at91_twi_pdata *)match->data;
1037 }
1038 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
1039}
1040
1041static int at91_twi_probe(struct platform_device *pdev)
1042{
1043 struct at91_twi_dev *dev;
1044 struct resource *mem;
1045 int rc;
1046 u32 phy_addr;
1047 u32 bus_clk_rate;
1048
1049 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1050 if (!dev)
1051 return -ENOMEM;
1052 init_completion(&dev->cmd_complete);
1053 dev->dev = &pdev->dev;
1054
1055 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1056 if (!mem)
1057 return -ENODEV;
1058 phy_addr = mem->start;
1059
1060 dev->pdata = at91_twi_get_driver_data(pdev);
1061 if (!dev->pdata)
1062 return -ENODEV;
1063
1064 dev->base = devm_ioremap_resource(&pdev->dev, mem);
1065 if (IS_ERR(dev->base))
1066 return PTR_ERR(dev->base);
1067
1068 dev->irq = platform_get_irq(pdev, 0);
1069 if (dev->irq < 0)
1070 return dev->irq;
1071
1072 rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
1073 dev_name(dev->dev), dev);
1074 if (rc) {
1075 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
1076 return rc;
1077 }
1078
1079 platform_set_drvdata(pdev, dev);
1080
1081 dev->clk = devm_clk_get(dev->dev, NULL);
1082 if (IS_ERR(dev->clk)) {
1083 dev_err(dev->dev, "no clock defined\n");
1084 return -ENODEV;
1085 }
1086 rc = clk_prepare_enable(dev->clk);
1087 if (rc)
1088 return rc;
1089
1090 if (dev->dev->of_node) {
1091 rc = at91_twi_configure_dma(dev, phy_addr);
1092 if (rc == -EPROBE_DEFER) {
1093 clk_disable_unprepare(dev->clk);
1094 return rc;
1095 }
1096 }
1097
1098 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1099 &dev->fifo_size)) {
1100 dev_info(dev->dev, "Using FIFO (%u data)\n", dev->fifo_size);
1101 }
1102
1103 rc = of_property_read_u32(dev->dev->of_node, "clock-frequency",
1104 &bus_clk_rate);
1105 if (rc)
1106 bus_clk_rate = DEFAULT_TWI_CLK_HZ;
1107
1108 at91_calc_twi_clock(dev, bus_clk_rate);
1109 at91_init_twi_bus(dev);
1110
1111 snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
1112 i2c_set_adapdata(&dev->adapter, dev);
1113 dev->adapter.owner = THIS_MODULE;
1114 dev->adapter.class = I2C_CLASS_DEPRECATED;
1115 dev->adapter.algo = &at91_twi_algorithm;
1116 dev->adapter.quirks = &at91_twi_quirks;
1117 dev->adapter.dev.parent = dev->dev;
1118 dev->adapter.nr = pdev->id;
1119 dev->adapter.timeout = AT91_I2C_TIMEOUT;
1120 dev->adapter.dev.of_node = pdev->dev.of_node;
1121
1122 pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT);
1123 pm_runtime_use_autosuspend(dev->dev);
1124 pm_runtime_set_active(dev->dev);
1125 pm_runtime_enable(dev->dev);
1126
1127 rc = i2c_add_numbered_adapter(&dev->adapter);
1128 if (rc) {
1129 clk_disable_unprepare(dev->clk);
1130
1131 pm_runtime_disable(dev->dev);
1132 pm_runtime_set_suspended(dev->dev);
1133
1134 return rc;
1135 }
1136
1137 dev_info(dev->dev, "AT91 i2c bus driver (hw version: %#x).\n",
1138 at91_twi_read(dev, AT91_TWI_VER));
1139 return 0;
1140}
1141
1142static int at91_twi_remove(struct platform_device *pdev)
1143{
1144 struct at91_twi_dev *dev = platform_get_drvdata(pdev);
1145
1146 i2c_del_adapter(&dev->adapter);
1147 clk_disable_unprepare(dev->clk);
1148
1149 pm_runtime_disable(dev->dev);
1150 pm_runtime_set_suspended(dev->dev);
1151
1152 return 0;
1153}
1154
1155#ifdef CONFIG_PM
1156
1157static int at91_twi_runtime_suspend(struct device *dev)
1158{
1159 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1160
1161 clk_disable_unprepare(twi_dev->clk);
1162
1163 pinctrl_pm_select_sleep_state(dev);
1164
1165 return 0;
1166}
1167
1168static int at91_twi_runtime_resume(struct device *dev)
1169{
1170 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1171
1172 pinctrl_pm_select_default_state(dev);
1173
1174 return clk_prepare_enable(twi_dev->clk);
1175}
1176
1177static int at91_twi_suspend_noirq(struct device *dev)
1178{
1179 if (!pm_runtime_status_suspended(dev))
1180 at91_twi_runtime_suspend(dev);
1181
1182 return 0;
1183}
1184
1185static int at91_twi_resume_noirq(struct device *dev)
1186{
1187 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1188 int ret;
1189
1190 if (!pm_runtime_status_suspended(dev)) {
1191 ret = at91_twi_runtime_resume(dev);
1192 if (ret)
1193 return ret;
1194 }
1195
1196 pm_runtime_mark_last_busy(dev);
1197 pm_request_autosuspend(dev);
1198
1199 at91_init_twi_bus(twi_dev);
1200
1201 return 0;
1202}
1203
1204static const struct dev_pm_ops at91_twi_pm = {
1205 .suspend_noirq = at91_twi_suspend_noirq,
1206 .resume_noirq = at91_twi_resume_noirq,
1207 .runtime_suspend = at91_twi_runtime_suspend,
1208 .runtime_resume = at91_twi_runtime_resume,
1209};
1210
1211#define at91_twi_pm_ops (&at91_twi_pm)
1212#else
1213#define at91_twi_pm_ops NULL
1214#endif
1215
1216static struct platform_driver at91_twi_driver = {
1217 .probe = at91_twi_probe,
1218 .remove = at91_twi_remove,
1219 .id_table = at91_twi_devtypes,
1220 .driver = {
1221 .name = "at91_i2c",
1222 .of_match_table = of_match_ptr(atmel_twi_dt_ids),
1223 .pm = at91_twi_pm_ops,
1224 },
1225};
1226
1227static int __init at91_twi_init(void)
1228{
1229 return platform_driver_register(&at91_twi_driver);
1230}
1231
1232static void __exit at91_twi_exit(void)
1233{
1234 platform_driver_unregister(&at91_twi_driver);
1235}
1236
1237subsys_initcall(at91_twi_init);
1238module_exit(at91_twi_exit);
1239
1240MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
1241MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
1242MODULE_LICENSE("GPL");
1243MODULE_ALIAS("platform:at91_i2c");