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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * GPIO interface for Intel Poulsbo SCH
4 *
5 * Copyright (c) 2010 CompuLab Ltd
6 * Author: Denis Turischev <denis@compulab.co.il>
7 */
8
9#include <linux/acpi.h>
10#include <linux/bitops.h>
11#include <linux/errno.h>
12#include <linux/gpio/driver.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pci_ids.h>
18#include <linux/platform_device.h>
19#include <linux/types.h>
20
21#define GEN 0x00
22#define GIO 0x04
23#define GLV 0x08
24#define GTPE 0x0c
25#define GTNE 0x10
26#define GGPE 0x14
27#define GSMI 0x18
28#define GTS 0x1c
29
30#define CORE_BANK_OFFSET 0x00
31#define RESUME_BANK_OFFSET 0x20
32
33/*
34 * iLB datasheet describes GPE0BLK registers, in particular GPE0E.GPIO bit.
35 * Document Number: 328195-001
36 */
37#define GPE0E_GPIO 14
38
39struct sch_gpio {
40 struct gpio_chip chip;
41 spinlock_t lock;
42 unsigned short iobase;
43 unsigned short resume_base;
44
45 /* GPE handling */
46 u32 gpe;
47 acpi_gpe_handler gpe_handler;
48};
49
50static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio,
51 unsigned int reg)
52{
53 unsigned int base = CORE_BANK_OFFSET;
54
55 if (gpio >= sch->resume_base) {
56 gpio -= sch->resume_base;
57 base = RESUME_BANK_OFFSET;
58 }
59
60 return base + reg + gpio / 8;
61}
62
63static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio)
64{
65 if (gpio >= sch->resume_base)
66 gpio -= sch->resume_base;
67 return gpio % 8;
68}
69
70static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg)
71{
72 unsigned short offset, bit;
73 u8 reg_val;
74
75 offset = sch_gpio_offset(sch, gpio, reg);
76 bit = sch_gpio_bit(sch, gpio);
77
78 reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
79
80 return reg_val;
81}
82
83static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg,
84 int val)
85{
86 unsigned short offset, bit;
87 u8 reg_val;
88
89 offset = sch_gpio_offset(sch, gpio, reg);
90 bit = sch_gpio_bit(sch, gpio);
91
92 reg_val = inb(sch->iobase + offset);
93
94 if (val)
95 outb(reg_val | BIT(bit), sch->iobase + offset);
96 else
97 outb((reg_val & ~BIT(bit)), sch->iobase + offset);
98}
99
100static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned int gpio_num)
101{
102 struct sch_gpio *sch = gpiochip_get_data(gc);
103 unsigned long flags;
104
105 spin_lock_irqsave(&sch->lock, flags);
106 sch_gpio_reg_set(sch, gpio_num, GIO, 1);
107 spin_unlock_irqrestore(&sch->lock, flags);
108 return 0;
109}
110
111static int sch_gpio_get(struct gpio_chip *gc, unsigned int gpio_num)
112{
113 struct sch_gpio *sch = gpiochip_get_data(gc);
114
115 return sch_gpio_reg_get(sch, gpio_num, GLV);
116}
117
118static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)
119{
120 struct sch_gpio *sch = gpiochip_get_data(gc);
121 unsigned long flags;
122
123 spin_lock_irqsave(&sch->lock, flags);
124 sch_gpio_reg_set(sch, gpio_num, GLV, val);
125 spin_unlock_irqrestore(&sch->lock, flags);
126}
127
128static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num,
129 int val)
130{
131 struct sch_gpio *sch = gpiochip_get_data(gc);
132 unsigned long flags;
133
134 spin_lock_irqsave(&sch->lock, flags);
135 sch_gpio_reg_set(sch, gpio_num, GIO, 0);
136 spin_unlock_irqrestore(&sch->lock, flags);
137
138 /*
139 * according to the datasheet, writing to the level register has no
140 * effect when GPIO is programmed as input.
141 * Actually the level register is read-only when configured as input.
142 * Thus presetting the output level before switching to output is _NOT_ possible.
143 * Hence we set the level after configuring the GPIO as output.
144 * But we cannot prevent a short low pulse if direction is set to high
145 * and an external pull-up is connected.
146 */
147 sch_gpio_set(gc, gpio_num, val);
148 return 0;
149}
150
151static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num)
152{
153 struct sch_gpio *sch = gpiochip_get_data(gc);
154
155 if (sch_gpio_reg_get(sch, gpio_num, GIO))
156 return GPIO_LINE_DIRECTION_IN;
157
158 return GPIO_LINE_DIRECTION_OUT;
159}
160
161static const struct gpio_chip sch_gpio_chip = {
162 .label = "sch_gpio",
163 .owner = THIS_MODULE,
164 .direction_input = sch_gpio_direction_in,
165 .get = sch_gpio_get,
166 .direction_output = sch_gpio_direction_out,
167 .set = sch_gpio_set,
168 .get_direction = sch_gpio_get_direction,
169};
170
171static int sch_irq_type(struct irq_data *d, unsigned int type)
172{
173 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
174 struct sch_gpio *sch = gpiochip_get_data(gc);
175 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
176 unsigned long flags;
177 int rising, falling;
178
179 switch (type & IRQ_TYPE_SENSE_MASK) {
180 case IRQ_TYPE_EDGE_RISING:
181 rising = 1;
182 falling = 0;
183 break;
184 case IRQ_TYPE_EDGE_FALLING:
185 rising = 0;
186 falling = 1;
187 break;
188 case IRQ_TYPE_EDGE_BOTH:
189 rising = 1;
190 falling = 1;
191 break;
192 default:
193 return -EINVAL;
194 }
195
196 spin_lock_irqsave(&sch->lock, flags);
197
198 sch_gpio_reg_set(sch, gpio_num, GTPE, rising);
199 sch_gpio_reg_set(sch, gpio_num, GTNE, falling);
200
201 irq_set_handler_locked(d, handle_edge_irq);
202
203 spin_unlock_irqrestore(&sch->lock, flags);
204
205 return 0;
206}
207
208static void sch_irq_ack(struct irq_data *d)
209{
210 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
211 struct sch_gpio *sch = gpiochip_get_data(gc);
212 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
213 unsigned long flags;
214
215 spin_lock_irqsave(&sch->lock, flags);
216 sch_gpio_reg_set(sch, gpio_num, GTS, 1);
217 spin_unlock_irqrestore(&sch->lock, flags);
218}
219
220static void sch_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t gpio_num, int val)
221{
222 struct sch_gpio *sch = gpiochip_get_data(gc);
223 unsigned long flags;
224
225 spin_lock_irqsave(&sch->lock, flags);
226 sch_gpio_reg_set(sch, gpio_num, GGPE, val);
227 spin_unlock_irqrestore(&sch->lock, flags);
228}
229
230static void sch_irq_mask(struct irq_data *d)
231{
232 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
233 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
234
235 sch_irq_mask_unmask(gc, gpio_num, 0);
236 gpiochip_disable_irq(gc, gpio_num);
237}
238
239static void sch_irq_unmask(struct irq_data *d)
240{
241 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
242 irq_hw_number_t gpio_num = irqd_to_hwirq(d);
243
244 gpiochip_enable_irq(gc, gpio_num);
245 sch_irq_mask_unmask(gc, gpio_num, 1);
246}
247
248static const struct irq_chip sch_irqchip = {
249 .name = "sch_gpio",
250 .irq_ack = sch_irq_ack,
251 .irq_mask = sch_irq_mask,
252 .irq_unmask = sch_irq_unmask,
253 .irq_set_type = sch_irq_type,
254 .flags = IRQCHIP_IMMUTABLE,
255 GPIOCHIP_IRQ_RESOURCE_HELPERS,
256};
257
258static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context)
259{
260 struct sch_gpio *sch = context;
261 struct gpio_chip *gc = &sch->chip;
262 unsigned long core_status, resume_status;
263 unsigned long pending;
264 unsigned long flags;
265 int offset;
266 u32 ret;
267
268 spin_lock_irqsave(&sch->lock, flags);
269
270 core_status = inl(sch->iobase + CORE_BANK_OFFSET + GTS);
271 resume_status = inl(sch->iobase + RESUME_BANK_OFFSET + GTS);
272
273 spin_unlock_irqrestore(&sch->lock, flags);
274
275 pending = (resume_status << sch->resume_base) | core_status;
276 for_each_set_bit(offset, &pending, sch->chip.ngpio)
277 generic_handle_domain_irq(gc->irq.domain, offset);
278
279 /* Set returning value depending on whether we handled an interrupt */
280 ret = pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;
281
282 /* Acknowledge GPE to ACPICA */
283 ret |= ACPI_REENABLE_GPE;
284
285 return ret;
286}
287
288static void sch_gpio_remove_gpe_handler(void *data)
289{
290 struct sch_gpio *sch = data;
291
292 acpi_disable_gpe(NULL, sch->gpe);
293 acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
294}
295
296static int sch_gpio_install_gpe_handler(struct sch_gpio *sch)
297{
298 struct device *dev = sch->chip.parent;
299 acpi_status status;
300
301 status = acpi_install_gpe_handler(NULL, sch->gpe, ACPI_GPE_LEVEL_TRIGGERED,
302 sch->gpe_handler, sch);
303 if (ACPI_FAILURE(status)) {
304 dev_err(dev, "Failed to install GPE handler for %u: %s\n",
305 sch->gpe, acpi_format_exception(status));
306 return -ENODEV;
307 }
308
309 status = acpi_enable_gpe(NULL, sch->gpe);
310 if (ACPI_FAILURE(status)) {
311 dev_err(dev, "Failed to enable GPE handler for %u: %s\n",
312 sch->gpe, acpi_format_exception(status));
313 acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
314 return -ENODEV;
315 }
316
317 return devm_add_action_or_reset(dev, sch_gpio_remove_gpe_handler, sch);
318}
319
320static int sch_gpio_probe(struct platform_device *pdev)
321{
322 struct gpio_irq_chip *girq;
323 struct sch_gpio *sch;
324 struct resource *res;
325 int ret;
326
327 sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
328 if (!sch)
329 return -ENOMEM;
330
331 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
332 if (!res)
333 return -EBUSY;
334
335 if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
336 pdev->name))
337 return -EBUSY;
338
339 spin_lock_init(&sch->lock);
340 sch->iobase = res->start;
341 sch->chip = sch_gpio_chip;
342 sch->chip.label = dev_name(&pdev->dev);
343 sch->chip.parent = &pdev->dev;
344
345 switch (pdev->id) {
346 case PCI_DEVICE_ID_INTEL_SCH_LPC:
347 sch->resume_base = 10;
348 sch->chip.ngpio = 14;
349
350 /*
351 * GPIO[6:0] enabled by default
352 * GPIO7 is configured by the CMC as SLPIOVR
353 * Enable GPIO[9:8] core powered gpios explicitly
354 */
355 sch_gpio_reg_set(sch, 8, GEN, 1);
356 sch_gpio_reg_set(sch, 9, GEN, 1);
357 /*
358 * SUS_GPIO[2:0] enabled by default
359 * Enable SUS_GPIO3 resume powered gpio explicitly
360 */
361 sch_gpio_reg_set(sch, 13, GEN, 1);
362 break;
363
364 case PCI_DEVICE_ID_INTEL_ITC_LPC:
365 sch->resume_base = 5;
366 sch->chip.ngpio = 14;
367 break;
368
369 case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
370 sch->resume_base = 21;
371 sch->chip.ngpio = 30;
372 break;
373
374 case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
375 sch->resume_base = 2;
376 sch->chip.ngpio = 8;
377 break;
378
379 default:
380 return -ENODEV;
381 }
382
383 girq = &sch->chip.irq;
384 gpio_irq_chip_set_chip(girq, &sch_irqchip);
385 girq->num_parents = 0;
386 girq->parents = NULL;
387 girq->parent_handler = NULL;
388 girq->default_type = IRQ_TYPE_NONE;
389 girq->handler = handle_bad_irq;
390
391 /* GPE setup is optional */
392 sch->gpe = GPE0E_GPIO;
393 sch->gpe_handler = sch_gpio_gpe_handler;
394
395 ret = sch_gpio_install_gpe_handler(sch);
396 if (ret)
397 dev_warn(&pdev->dev, "Can't setup GPE, no IRQ support\n");
398
399 return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
400}
401
402static struct platform_driver sch_gpio_driver = {
403 .driver = {
404 .name = "sch_gpio",
405 },
406 .probe = sch_gpio_probe,
407};
408
409module_platform_driver(sch_gpio_driver);
410
411MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
412MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
413MODULE_LICENSE("GPL v2");
414MODULE_ALIAS("platform:sch_gpio");
1/*
2 * GPIO interface for Intel Poulsbo SCH
3 *
4 * Copyright (c) 2010 CompuLab Ltd
5 * Author: Denis Turischev <denis@compulab.co.il>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License 2 as published
9 * by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; see the file COPYING. If not, write to
18 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/io.h>
25#include <linux/errno.h>
26#include <linux/acpi.h>
27#include <linux/platform_device.h>
28#include <linux/pci_ids.h>
29
30#include <linux/gpio.h>
31
32#define GEN 0x00
33#define GIO 0x04
34#define GLV 0x08
35
36struct sch_gpio {
37 struct gpio_chip chip;
38 spinlock_t lock;
39 unsigned short iobase;
40 unsigned short core_base;
41 unsigned short resume_base;
42};
43
44static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
45 unsigned reg)
46{
47 unsigned base = 0;
48
49 if (gpio >= sch->resume_base) {
50 gpio -= sch->resume_base;
51 base += 0x20;
52 }
53
54 return base + reg + gpio / 8;
55}
56
57static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
58{
59 if (gpio >= sch->resume_base)
60 gpio -= sch->resume_base;
61 return gpio % 8;
62}
63
64static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned gpio, unsigned reg)
65{
66 unsigned short offset, bit;
67 u8 reg_val;
68
69 offset = sch_gpio_offset(sch, gpio, reg);
70 bit = sch_gpio_bit(sch, gpio);
71
72 reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
73
74 return reg_val;
75}
76
77static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned gpio, unsigned reg,
78 int val)
79{
80 unsigned short offset, bit;
81 u8 reg_val;
82
83 offset = sch_gpio_offset(sch, gpio, reg);
84 bit = sch_gpio_bit(sch, gpio);
85
86 reg_val = inb(sch->iobase + offset);
87
88 if (val)
89 outb(reg_val | BIT(bit), sch->iobase + offset);
90 else
91 outb((reg_val & ~BIT(bit)), sch->iobase + offset);
92}
93
94static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
95{
96 struct sch_gpio *sch = gpiochip_get_data(gc);
97
98 spin_lock(&sch->lock);
99 sch_gpio_reg_set(sch, gpio_num, GIO, 1);
100 spin_unlock(&sch->lock);
101 return 0;
102}
103
104static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
105{
106 struct sch_gpio *sch = gpiochip_get_data(gc);
107 return sch_gpio_reg_get(sch, gpio_num, GLV);
108}
109
110static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
111{
112 struct sch_gpio *sch = gpiochip_get_data(gc);
113
114 spin_lock(&sch->lock);
115 sch_gpio_reg_set(sch, gpio_num, GLV, val);
116 spin_unlock(&sch->lock);
117}
118
119static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
120 int val)
121{
122 struct sch_gpio *sch = gpiochip_get_data(gc);
123
124 spin_lock(&sch->lock);
125 sch_gpio_reg_set(sch, gpio_num, GIO, 0);
126 spin_unlock(&sch->lock);
127
128 /*
129 * according to the datasheet, writing to the level register has no
130 * effect when GPIO is programmed as input.
131 * Actually the the level register is read-only when configured as input.
132 * Thus presetting the output level before switching to output is _NOT_ possible.
133 * Hence we set the level after configuring the GPIO as output.
134 * But we cannot prevent a short low pulse if direction is set to high
135 * and an external pull-up is connected.
136 */
137 sch_gpio_set(gc, gpio_num, val);
138 return 0;
139}
140
141static const struct gpio_chip sch_gpio_chip = {
142 .label = "sch_gpio",
143 .owner = THIS_MODULE,
144 .direction_input = sch_gpio_direction_in,
145 .get = sch_gpio_get,
146 .direction_output = sch_gpio_direction_out,
147 .set = sch_gpio_set,
148};
149
150static int sch_gpio_probe(struct platform_device *pdev)
151{
152 struct sch_gpio *sch;
153 struct resource *res;
154
155 sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
156 if (!sch)
157 return -ENOMEM;
158
159 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
160 if (!res)
161 return -EBUSY;
162
163 if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
164 pdev->name))
165 return -EBUSY;
166
167 spin_lock_init(&sch->lock);
168 sch->iobase = res->start;
169 sch->chip = sch_gpio_chip;
170 sch->chip.label = dev_name(&pdev->dev);
171 sch->chip.parent = &pdev->dev;
172
173 switch (pdev->id) {
174 case PCI_DEVICE_ID_INTEL_SCH_LPC:
175 sch->core_base = 0;
176 sch->resume_base = 10;
177 sch->chip.ngpio = 14;
178
179 /*
180 * GPIO[6:0] enabled by default
181 * GPIO7 is configured by the CMC as SLPIOVR
182 * Enable GPIO[9:8] core powered gpios explicitly
183 */
184 sch_gpio_reg_set(sch, 8, GEN, 1);
185 sch_gpio_reg_set(sch, 9, GEN, 1);
186 /*
187 * SUS_GPIO[2:0] enabled by default
188 * Enable SUS_GPIO3 resume powered gpio explicitly
189 */
190 sch_gpio_reg_set(sch, 13, GEN, 1);
191 break;
192
193 case PCI_DEVICE_ID_INTEL_ITC_LPC:
194 sch->core_base = 0;
195 sch->resume_base = 5;
196 sch->chip.ngpio = 14;
197 break;
198
199 case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
200 sch->core_base = 0;
201 sch->resume_base = 21;
202 sch->chip.ngpio = 30;
203 break;
204
205 case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
206 sch->core_base = 0;
207 sch->resume_base = 2;
208 sch->chip.ngpio = 8;
209 break;
210
211 default:
212 return -ENODEV;
213 }
214
215 platform_set_drvdata(pdev, sch);
216
217 return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
218}
219
220static struct platform_driver sch_gpio_driver = {
221 .driver = {
222 .name = "sch_gpio",
223 },
224 .probe = sch_gpio_probe,
225};
226
227module_platform_driver(sch_gpio_driver);
228
229MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
230MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
231MODULE_LICENSE("GPL");
232MODULE_ALIAS("platform:sch_gpio");