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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2016,2017 IBM Corporation.
4 */
5
6#define pr_fmt(fmt) "xive: " fmt
7
8#include <linux/types.h>
9#include <linux/irq.h>
10#include <linux/smp.h>
11#include <linux/interrupt.h>
12#include <linux/init.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_fdt.h>
16#include <linux/slab.h>
17#include <linux/spinlock.h>
18#include <linux/bitmap.h>
19#include <linux/cpumask.h>
20#include <linux/mm.h>
21#include <linux/delay.h>
22#include <linux/libfdt.h>
23
24#include <asm/machdep.h>
25#include <asm/prom.h>
26#include <asm/io.h>
27#include <asm/smp.h>
28#include <asm/irq.h>
29#include <asm/errno.h>
30#include <asm/xive.h>
31#include <asm/xive-regs.h>
32#include <asm/hvcall.h>
33#include <asm/svm.h>
34#include <asm/ultravisor.h>
35
36#include "xive-internal.h"
37
38static u32 xive_queue_shift;
39
40struct xive_irq_bitmap {
41 unsigned long *bitmap;
42 unsigned int base;
43 unsigned int count;
44 spinlock_t lock;
45 struct list_head list;
46};
47
48static LIST_HEAD(xive_irq_bitmaps);
49
50static int __init xive_irq_bitmap_add(int base, int count)
51{
52 struct xive_irq_bitmap *xibm;
53
54 xibm = kzalloc(sizeof(*xibm), GFP_KERNEL);
55 if (!xibm)
56 return -ENOMEM;
57
58 spin_lock_init(&xibm->lock);
59 xibm->base = base;
60 xibm->count = count;
61 xibm->bitmap = bitmap_zalloc(xibm->count, GFP_KERNEL);
62 if (!xibm->bitmap) {
63 kfree(xibm);
64 return -ENOMEM;
65 }
66 list_add(&xibm->list, &xive_irq_bitmaps);
67
68 pr_info("Using IRQ range [%x-%x]", xibm->base,
69 xibm->base + xibm->count - 1);
70 return 0;
71}
72
73static void xive_irq_bitmap_remove_all(void)
74{
75 struct xive_irq_bitmap *xibm, *tmp;
76
77 list_for_each_entry_safe(xibm, tmp, &xive_irq_bitmaps, list) {
78 list_del(&xibm->list);
79 bitmap_free(xibm->bitmap);
80 kfree(xibm);
81 }
82}
83
84static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm)
85{
86 int irq;
87
88 irq = find_first_zero_bit(xibm->bitmap, xibm->count);
89 if (irq != xibm->count) {
90 set_bit(irq, xibm->bitmap);
91 irq += xibm->base;
92 } else {
93 irq = -ENOMEM;
94 }
95
96 return irq;
97}
98
99static int xive_irq_bitmap_alloc(void)
100{
101 struct xive_irq_bitmap *xibm;
102 unsigned long flags;
103 int irq = -ENOENT;
104
105 list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
106 spin_lock_irqsave(&xibm->lock, flags);
107 irq = __xive_irq_bitmap_alloc(xibm);
108 spin_unlock_irqrestore(&xibm->lock, flags);
109 if (irq >= 0)
110 break;
111 }
112 return irq;
113}
114
115static void xive_irq_bitmap_free(int irq)
116{
117 unsigned long flags;
118 struct xive_irq_bitmap *xibm;
119
120 list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
121 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) {
122 spin_lock_irqsave(&xibm->lock, flags);
123 clear_bit(irq - xibm->base, xibm->bitmap);
124 spin_unlock_irqrestore(&xibm->lock, flags);
125 break;
126 }
127 }
128}
129
130
131/* Based on the similar routines in RTAS */
132static unsigned int plpar_busy_delay_time(long rc)
133{
134 unsigned int ms = 0;
135
136 if (H_IS_LONG_BUSY(rc)) {
137 ms = get_longbusy_msecs(rc);
138 } else if (rc == H_BUSY) {
139 ms = 10; /* seems appropriate for XIVE hcalls */
140 }
141
142 return ms;
143}
144
145static unsigned int plpar_busy_delay(int rc)
146{
147 unsigned int ms;
148
149 ms = plpar_busy_delay_time(rc);
150 if (ms)
151 mdelay(ms);
152
153 return ms;
154}
155
156/*
157 * Note: this call has a partition wide scope and can take a while to
158 * complete. If it returns H_LONG_BUSY_* it should be retried
159 * periodically.
160 */
161static long plpar_int_reset(unsigned long flags)
162{
163 long rc;
164
165 do {
166 rc = plpar_hcall_norets(H_INT_RESET, flags);
167 } while (plpar_busy_delay(rc));
168
169 if (rc)
170 pr_err("H_INT_RESET failed %ld\n", rc);
171
172 return rc;
173}
174
175static long plpar_int_get_source_info(unsigned long flags,
176 unsigned long lisn,
177 unsigned long *src_flags,
178 unsigned long *eoi_page,
179 unsigned long *trig_page,
180 unsigned long *esb_shift)
181{
182 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
183 long rc;
184
185 do {
186 rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn);
187 } while (plpar_busy_delay(rc));
188
189 if (rc) {
190 pr_err("H_INT_GET_SOURCE_INFO lisn=0x%lx failed %ld\n", lisn, rc);
191 return rc;
192 }
193
194 *src_flags = retbuf[0];
195 *eoi_page = retbuf[1];
196 *trig_page = retbuf[2];
197 *esb_shift = retbuf[3];
198
199 pr_debug("H_INT_GET_SOURCE_INFO lisn=0x%lx flags=0x%lx eoi=0x%lx trig=0x%lx shift=0x%lx\n",
200 lisn, retbuf[0], retbuf[1], retbuf[2], retbuf[3]);
201
202 return 0;
203}
204
205#define XIVE_SRC_SET_EISN (1ull << (63 - 62))
206#define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */
207
208static long plpar_int_set_source_config(unsigned long flags,
209 unsigned long lisn,
210 unsigned long target,
211 unsigned long prio,
212 unsigned long sw_irq)
213{
214 long rc;
215
216
217 pr_debug("H_INT_SET_SOURCE_CONFIG flags=0x%lx lisn=0x%lx target=%ld prio=%ld sw_irq=%ld\n",
218 flags, lisn, target, prio, sw_irq);
219
220
221 do {
222 rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn,
223 target, prio, sw_irq);
224 } while (plpar_busy_delay(rc));
225
226 if (rc) {
227 pr_err("H_INT_SET_SOURCE_CONFIG lisn=0x%lx target=%ld prio=%ld failed %ld\n",
228 lisn, target, prio, rc);
229 return rc;
230 }
231
232 return 0;
233}
234
235static long plpar_int_get_source_config(unsigned long flags,
236 unsigned long lisn,
237 unsigned long *target,
238 unsigned long *prio,
239 unsigned long *sw_irq)
240{
241 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
242 long rc;
243
244 pr_debug("H_INT_GET_SOURCE_CONFIG flags=0x%lx lisn=0x%lx\n", flags, lisn);
245
246 do {
247 rc = plpar_hcall(H_INT_GET_SOURCE_CONFIG, retbuf, flags, lisn,
248 target, prio, sw_irq);
249 } while (plpar_busy_delay(rc));
250
251 if (rc) {
252 pr_err("H_INT_GET_SOURCE_CONFIG lisn=0x%lx failed %ld\n",
253 lisn, rc);
254 return rc;
255 }
256
257 *target = retbuf[0];
258 *prio = retbuf[1];
259 *sw_irq = retbuf[2];
260
261 pr_debug("H_INT_GET_SOURCE_CONFIG target=%ld prio=%ld sw_irq=%ld\n",
262 retbuf[0], retbuf[1], retbuf[2]);
263
264 return 0;
265}
266
267static long plpar_int_get_queue_info(unsigned long flags,
268 unsigned long target,
269 unsigned long priority,
270 unsigned long *esn_page,
271 unsigned long *esn_size)
272{
273 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
274 long rc;
275
276 do {
277 rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target,
278 priority);
279 } while (plpar_busy_delay(rc));
280
281 if (rc) {
282 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n",
283 target, priority, rc);
284 return rc;
285 }
286
287 *esn_page = retbuf[0];
288 *esn_size = retbuf[1];
289
290 pr_debug("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld page=0x%lx size=0x%lx\n",
291 target, priority, retbuf[0], retbuf[1]);
292
293 return 0;
294}
295
296#define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63))
297
298static long plpar_int_set_queue_config(unsigned long flags,
299 unsigned long target,
300 unsigned long priority,
301 unsigned long qpage,
302 unsigned long qsize)
303{
304 long rc;
305
306 pr_debug("H_INT_SET_QUEUE_CONFIG flags=0x%lx target=%ld priority=0x%lx qpage=0x%lx qsize=0x%lx\n",
307 flags, target, priority, qpage, qsize);
308
309 do {
310 rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target,
311 priority, qpage, qsize);
312 } while (plpar_busy_delay(rc));
313
314 if (rc) {
315 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=0x%lx returned %ld\n",
316 target, priority, qpage, rc);
317 return rc;
318 }
319
320 return 0;
321}
322
323static long plpar_int_sync(unsigned long flags, unsigned long lisn)
324{
325 long rc;
326
327 do {
328 rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn);
329 } while (plpar_busy_delay(rc));
330
331 if (rc) {
332 pr_err("H_INT_SYNC lisn=0x%lx returned %ld\n", lisn, rc);
333 return rc;
334 }
335
336 return 0;
337}
338
339#define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))
340
341static long plpar_int_esb(unsigned long flags,
342 unsigned long lisn,
343 unsigned long offset,
344 unsigned long in_data,
345 unsigned long *out_data)
346{
347 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
348 long rc;
349
350 pr_debug("H_INT_ESB flags=0x%lx lisn=0x%lx offset=0x%lx in=0x%lx\n",
351 flags, lisn, offset, in_data);
352
353 do {
354 rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset,
355 in_data);
356 } while (plpar_busy_delay(rc));
357
358 if (rc) {
359 pr_err("H_INT_ESB lisn=0x%lx offset=0x%lx returned %ld\n",
360 lisn, offset, rc);
361 return rc;
362 }
363
364 *out_data = retbuf[0];
365
366 return 0;
367}
368
369static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)
370{
371 unsigned long read_data;
372 long rc;
373
374 rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,
375 lisn, offset, data, &read_data);
376 if (rc)
377 return -1;
378
379 return write ? 0 : read_data;
380}
381
382#define XIVE_SRC_H_INT_ESB (1ull << (63 - 60))
383#define XIVE_SRC_LSI (1ull << (63 - 61))
384#define XIVE_SRC_TRIGGER (1ull << (63 - 62))
385#define XIVE_SRC_STORE_EOI (1ull << (63 - 63))
386
387static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
388{
389 long rc;
390 unsigned long flags;
391 unsigned long eoi_page;
392 unsigned long trig_page;
393 unsigned long esb_shift;
394
395 memset(data, 0, sizeof(*data));
396
397 rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page,
398 &esb_shift);
399 if (rc)
400 return -EINVAL;
401
402 if (flags & XIVE_SRC_H_INT_ESB)
403 data->flags |= XIVE_IRQ_FLAG_H_INT_ESB;
404 if (flags & XIVE_SRC_STORE_EOI)
405 data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
406 if (flags & XIVE_SRC_LSI)
407 data->flags |= XIVE_IRQ_FLAG_LSI;
408 data->eoi_page = eoi_page;
409 data->esb_shift = esb_shift;
410 data->trig_page = trig_page;
411
412 data->hw_irq = hw_irq;
413
414 /*
415 * No chip-id for the sPAPR backend. This has an impact how we
416 * pick a target. See xive_pick_irq_target().
417 */
418 data->src_chip = XIVE_INVALID_CHIP_ID;
419
420 /*
421 * When the H_INT_ESB flag is set, the H_INT_ESB hcall should
422 * be used for interrupt management. Skip the remapping of the
423 * ESB pages which are not available.
424 */
425 if (data->flags & XIVE_IRQ_FLAG_H_INT_ESB)
426 return 0;
427
428 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
429 if (!data->eoi_mmio) {
430 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
431 return -ENOMEM;
432 }
433
434 /* Full function page supports trigger */
435 if (flags & XIVE_SRC_TRIGGER) {
436 data->trig_mmio = data->eoi_mmio;
437 return 0;
438 }
439
440 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
441 if (!data->trig_mmio) {
442 iounmap(data->eoi_mmio);
443 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
444 return -ENOMEM;
445 }
446 return 0;
447}
448
449static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
450{
451 long rc;
452
453 rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target,
454 prio, sw_irq);
455
456 return rc == 0 ? 0 : -ENXIO;
457}
458
459static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
460 u32 *sw_irq)
461{
462 long rc;
463 unsigned long h_target;
464 unsigned long h_prio;
465 unsigned long h_sw_irq;
466
467 rc = plpar_int_get_source_config(0, hw_irq, &h_target, &h_prio,
468 &h_sw_irq);
469
470 *target = h_target;
471 *prio = h_prio;
472 *sw_irq = h_sw_irq;
473
474 return rc == 0 ? 0 : -ENXIO;
475}
476
477/* This can be called multiple time to change a queue configuration */
478static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
479 __be32 *qpage, u32 order)
480{
481 s64 rc = 0;
482 unsigned long esn_page;
483 unsigned long esn_size;
484 u64 flags, qpage_phys;
485
486 /* If there's an actual queue page, clean it */
487 if (order) {
488 if (WARN_ON(!qpage))
489 return -EINVAL;
490 qpage_phys = __pa(qpage);
491 } else {
492 qpage_phys = 0;
493 }
494
495 /* Initialize the rest of the fields */
496 q->msk = order ? ((1u << (order - 2)) - 1) : 0;
497 q->idx = 0;
498 q->toggle = 0;
499
500 rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size);
501 if (rc) {
502 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc,
503 target, prio);
504 rc = -EIO;
505 goto fail;
506 }
507
508 /* TODO: add support for the notification page */
509 q->eoi_phys = esn_page;
510
511 /* Default is to always notify */
512 flags = XIVE_EQ_ALWAYS_NOTIFY;
513
514 /* Configure and enable the queue in HW */
515 rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order);
516 if (rc) {
517 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc,
518 target, prio);
519 rc = -EIO;
520 } else {
521 q->qpage = qpage;
522 if (is_secure_guest())
523 uv_share_page(PHYS_PFN(qpage_phys),
524 1 << xive_alloc_order(order));
525 }
526fail:
527 return rc;
528}
529
530static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc,
531 u8 prio)
532{
533 struct xive_q *q = &xc->queue[prio];
534 __be32 *qpage;
535
536 qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
537 if (IS_ERR(qpage))
538 return PTR_ERR(qpage);
539
540 return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu),
541 q, prio, qpage, xive_queue_shift);
542}
543
544static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
545 u8 prio)
546{
547 struct xive_q *q = &xc->queue[prio];
548 unsigned int alloc_order;
549 long rc;
550 int hw_cpu = get_hard_smp_processor_id(cpu);
551
552 rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0);
553 if (rc)
554 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc,
555 hw_cpu, prio);
556
557 alloc_order = xive_alloc_order(xive_queue_shift);
558 if (is_secure_guest())
559 uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order);
560 free_pages((unsigned long)q->qpage, alloc_order);
561 q->qpage = NULL;
562}
563
564static bool xive_spapr_match(struct device_node *node)
565{
566 /* Ignore cascaded controllers for the moment */
567 return true;
568}
569
570#ifdef CONFIG_SMP
571static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
572{
573 int irq = xive_irq_bitmap_alloc();
574
575 if (irq < 0) {
576 pr_err("Failed to allocate IPI on CPU %d\n", cpu);
577 return -ENXIO;
578 }
579
580 xc->hw_ipi = irq;
581 return 0;
582}
583
584static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
585{
586 if (xc->hw_ipi == XIVE_BAD_IRQ)
587 return;
588
589 xive_irq_bitmap_free(xc->hw_ipi);
590 xc->hw_ipi = XIVE_BAD_IRQ;
591}
592#endif /* CONFIG_SMP */
593
594static void xive_spapr_shutdown(void)
595{
596 plpar_int_reset(0);
597}
598
599/*
600 * Perform an "ack" cycle on the current thread. Grab the pending
601 * active priorities and update the CPPR to the most favored one.
602 */
603static void xive_spapr_update_pending(struct xive_cpu *xc)
604{
605 u8 nsr, cppr;
606 u16 ack;
607
608 /*
609 * Perform the "Acknowledge O/S to Register" cycle.
610 *
611 * Let's speedup the access to the TIMA using the raw I/O
612 * accessor as we don't need the synchronisation routine of
613 * the higher level ones
614 */
615 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG));
616
617 /* Synchronize subsequent queue accesses */
618 mb();
619
620 /*
621 * Grab the CPPR and the "NSR" field which indicates the source
622 * of the interrupt (if any)
623 */
624 cppr = ack & 0xff;
625 nsr = ack >> 8;
626
627 if (nsr & TM_QW1_NSR_EO) {
628 if (cppr == 0xff)
629 return;
630 /* Mark the priority pending */
631 xc->pending_prio |= 1 << cppr;
632
633 /*
634 * A new interrupt should never have a CPPR less favored
635 * than our current one.
636 */
637 if (cppr >= xc->cppr)
638 pr_err("CPU %d odd ack CPPR, got %d at %d\n",
639 smp_processor_id(), cppr, xc->cppr);
640
641 /* Update our idea of what the CPPR is */
642 xc->cppr = cppr;
643 }
644}
645
646static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
647{
648 /* Only some debug on the TIMA settings */
649 pr_debug("(HW value: %08x %08x %08x)\n",
650 in_be32(xive_tima + TM_QW1_OS + TM_WORD0),
651 in_be32(xive_tima + TM_QW1_OS + TM_WORD1),
652 in_be32(xive_tima + TM_QW1_OS + TM_WORD2));
653}
654
655static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
656{
657 /* Nothing to do */;
658}
659
660static void xive_spapr_sync_source(u32 hw_irq)
661{
662 /* Specs are unclear on what this is doing */
663 plpar_int_sync(0, hw_irq);
664}
665
666static int xive_spapr_debug_show(struct seq_file *m, void *private)
667{
668 struct xive_irq_bitmap *xibm;
669 char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
670
671 if (!buf)
672 return -ENOMEM;
673
674 list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
675 memset(buf, 0, PAGE_SIZE);
676 bitmap_print_to_pagebuf(true, buf, xibm->bitmap, xibm->count);
677 seq_printf(m, "bitmap #%d: %s", xibm->count, buf);
678 }
679 kfree(buf);
680
681 return 0;
682}
683
684static const struct xive_ops xive_spapr_ops = {
685 .populate_irq_data = xive_spapr_populate_irq_data,
686 .configure_irq = xive_spapr_configure_irq,
687 .get_irq_config = xive_spapr_get_irq_config,
688 .setup_queue = xive_spapr_setup_queue,
689 .cleanup_queue = xive_spapr_cleanup_queue,
690 .match = xive_spapr_match,
691 .shutdown = xive_spapr_shutdown,
692 .update_pending = xive_spapr_update_pending,
693 .setup_cpu = xive_spapr_setup_cpu,
694 .teardown_cpu = xive_spapr_teardown_cpu,
695 .sync_source = xive_spapr_sync_source,
696 .esb_rw = xive_spapr_esb_rw,
697#ifdef CONFIG_SMP
698 .get_ipi = xive_spapr_get_ipi,
699 .put_ipi = xive_spapr_put_ipi,
700 .debug_show = xive_spapr_debug_show,
701#endif /* CONFIG_SMP */
702 .name = "spapr",
703};
704
705/*
706 * get max priority from "/ibm,plat-res-int-priorities"
707 */
708static bool __init xive_get_max_prio(u8 *max_prio)
709{
710 struct device_node *rootdn;
711 const __be32 *reg;
712 u32 len;
713 int prio, found;
714
715 rootdn = of_find_node_by_path("/");
716 if (!rootdn) {
717 pr_err("not root node found !\n");
718 return false;
719 }
720
721 reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len);
722 of_node_put(rootdn);
723 if (!reg) {
724 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n");
725 return false;
726 }
727
728 if (len % (2 * sizeof(u32)) != 0) {
729 pr_err("invalid 'ibm,plat-res-int-priorities' property\n");
730 return false;
731 }
732
733 /* HW supports priorities in the range [0-7] and 0xFF is a
734 * wildcard priority used to mask. We scan the ranges reserved
735 * by the hypervisor to find the lowest priority we can use.
736 */
737 found = 0xFF;
738 for (prio = 0; prio < 8; prio++) {
739 int reserved = 0;
740 int i;
741
742 for (i = 0; i < len / (2 * sizeof(u32)); i++) {
743 int base = be32_to_cpu(reg[2 * i]);
744 int range = be32_to_cpu(reg[2 * i + 1]);
745
746 if (prio >= base && prio < base + range)
747 reserved++;
748 }
749
750 if (!reserved)
751 found = prio;
752 }
753
754 if (found == 0xFF) {
755 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n");
756 return false;
757 }
758
759 *max_prio = found;
760 return true;
761}
762
763static const u8 *__init get_vec5_feature(unsigned int index)
764{
765 unsigned long root, chosen;
766 int size;
767 const u8 *vec5;
768
769 root = of_get_flat_dt_root();
770 chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
771 if (chosen == -FDT_ERR_NOTFOUND)
772 return NULL;
773
774 vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", &size);
775 if (!vec5)
776 return NULL;
777
778 if (size <= index)
779 return NULL;
780
781 return vec5 + index;
782}
783
784static bool __init xive_spapr_disabled(void)
785{
786 const u8 *vec5_xive;
787
788 vec5_xive = get_vec5_feature(OV5_INDX(OV5_XIVE_SUPPORT));
789 if (vec5_xive) {
790 u8 val;
791
792 val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT);
793 switch (val) {
794 case OV5_FEAT(OV5_XIVE_EITHER):
795 case OV5_FEAT(OV5_XIVE_LEGACY):
796 break;
797 case OV5_FEAT(OV5_XIVE_EXPLOIT):
798 /* Hypervisor only supports XIVE */
799 if (xive_cmdline_disabled)
800 pr_warn("WARNING: Ignoring cmdline option xive=off\n");
801 return false;
802 default:
803 pr_warn("%s: Unknown xive support option: 0x%x\n",
804 __func__, val);
805 break;
806 }
807 }
808
809 return xive_cmdline_disabled;
810}
811
812bool __init xive_spapr_init(void)
813{
814 struct device_node *np;
815 struct resource r;
816 void __iomem *tima;
817 struct property *prop;
818 u8 max_prio;
819 u32 val;
820 u32 len;
821 const __be32 *reg;
822 int i, err;
823
824 if (xive_spapr_disabled())
825 return false;
826
827 pr_devel("%s()\n", __func__);
828 np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe");
829 if (!np) {
830 pr_devel("not found !\n");
831 return false;
832 }
833 pr_devel("Found %s\n", np->full_name);
834
835 /* Resource 1 is the OS ring TIMA */
836 if (of_address_to_resource(np, 1, &r)) {
837 pr_err("Failed to get thread mgmnt area resource\n");
838 goto err_put;
839 }
840 tima = ioremap(r.start, resource_size(&r));
841 if (!tima) {
842 pr_err("Failed to map thread mgmnt area\n");
843 goto err_put;
844 }
845
846 if (!xive_get_max_prio(&max_prio))
847 goto err_unmap;
848
849 /* Feed the IRQ number allocator with the ranges given in the DT */
850 reg = of_get_property(np, "ibm,xive-lisn-ranges", &len);
851 if (!reg) {
852 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n");
853 goto err_unmap;
854 }
855
856 if (len % (2 * sizeof(u32)) != 0) {
857 pr_err("invalid 'ibm,xive-lisn-ranges' property\n");
858 goto err_unmap;
859 }
860
861 for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2) {
862 err = xive_irq_bitmap_add(be32_to_cpu(reg[0]),
863 be32_to_cpu(reg[1]));
864 if (err < 0)
865 goto err_mem_free;
866 }
867
868 /* Iterate the EQ sizes and pick one */
869 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
870 xive_queue_shift = val;
871 if (val == PAGE_SHIFT)
872 break;
873 }
874
875 /* Initialize XIVE core with our backend */
876 if (!xive_core_init(np, &xive_spapr_ops, tima, TM_QW1_OS, max_prio))
877 goto err_mem_free;
878
879 of_node_put(np);
880 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
881 return true;
882
883err_mem_free:
884 xive_irq_bitmap_remove_all();
885err_unmap:
886 iounmap(tima);
887err_put:
888 of_node_put(np);
889 return false;
890}
891
892machine_arch_initcall(pseries, xive_core_debug_init);
1/*
2 * Copyright 2016,2017 IBM Corporation.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#define pr_fmt(fmt) "xive: " fmt
11
12#include <linux/types.h>
13#include <linux/irq.h>
14#include <linux/smp.h>
15#include <linux/interrupt.h>
16#include <linux/init.h>
17#include <linux/of.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20#include <linux/cpumask.h>
21#include <linux/mm.h>
22
23#include <asm/prom.h>
24#include <asm/io.h>
25#include <asm/smp.h>
26#include <asm/irq.h>
27#include <asm/errno.h>
28#include <asm/xive.h>
29#include <asm/xive-regs.h>
30#include <asm/hvcall.h>
31
32#include "xive-internal.h"
33
34static u32 xive_queue_shift;
35
36struct xive_irq_bitmap {
37 unsigned long *bitmap;
38 unsigned int base;
39 unsigned int count;
40 spinlock_t lock;
41 struct list_head list;
42};
43
44static LIST_HEAD(xive_irq_bitmaps);
45
46static int xive_irq_bitmap_add(int base, int count)
47{
48 struct xive_irq_bitmap *xibm;
49
50 xibm = kzalloc(sizeof(*xibm), GFP_ATOMIC);
51 if (!xibm)
52 return -ENOMEM;
53
54 spin_lock_init(&xibm->lock);
55 xibm->base = base;
56 xibm->count = count;
57 xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL);
58 list_add(&xibm->list, &xive_irq_bitmaps);
59
60 pr_info("Using IRQ range [%x-%x]", xibm->base,
61 xibm->base + xibm->count - 1);
62 return 0;
63}
64
65static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm)
66{
67 int irq;
68
69 irq = find_first_zero_bit(xibm->bitmap, xibm->count);
70 if (irq != xibm->count) {
71 set_bit(irq, xibm->bitmap);
72 irq += xibm->base;
73 } else {
74 irq = -ENOMEM;
75 }
76
77 return irq;
78}
79
80static int xive_irq_bitmap_alloc(void)
81{
82 struct xive_irq_bitmap *xibm;
83 unsigned long flags;
84 int irq = -ENOENT;
85
86 list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
87 spin_lock_irqsave(&xibm->lock, flags);
88 irq = __xive_irq_bitmap_alloc(xibm);
89 spin_unlock_irqrestore(&xibm->lock, flags);
90 if (irq >= 0)
91 break;
92 }
93 return irq;
94}
95
96static void xive_irq_bitmap_free(int irq)
97{
98 unsigned long flags;
99 struct xive_irq_bitmap *xibm;
100
101 list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
102 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) {
103 spin_lock_irqsave(&xibm->lock, flags);
104 clear_bit(irq - xibm->base, xibm->bitmap);
105 spin_unlock_irqrestore(&xibm->lock, flags);
106 break;
107 }
108 }
109}
110
111static long plpar_int_get_source_info(unsigned long flags,
112 unsigned long lisn,
113 unsigned long *src_flags,
114 unsigned long *eoi_page,
115 unsigned long *trig_page,
116 unsigned long *esb_shift)
117{
118 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
119 long rc;
120
121 rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn);
122 if (rc) {
123 pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc);
124 return rc;
125 }
126
127 *src_flags = retbuf[0];
128 *eoi_page = retbuf[1];
129 *trig_page = retbuf[2];
130 *esb_shift = retbuf[3];
131
132 pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n",
133 retbuf[0], retbuf[1], retbuf[2], retbuf[3]);
134
135 return 0;
136}
137
138#define XIVE_SRC_SET_EISN (1ull << (63 - 62))
139#define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */
140
141static long plpar_int_set_source_config(unsigned long flags,
142 unsigned long lisn,
143 unsigned long target,
144 unsigned long prio,
145 unsigned long sw_irq)
146{
147 long rc;
148
149
150 pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n",
151 flags, lisn, target, prio, sw_irq);
152
153
154 rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn,
155 target, prio, sw_irq);
156 if (rc) {
157 pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n",
158 lisn, target, prio, rc);
159 return rc;
160 }
161
162 return 0;
163}
164
165static long plpar_int_get_queue_info(unsigned long flags,
166 unsigned long target,
167 unsigned long priority,
168 unsigned long *esn_page,
169 unsigned long *esn_size)
170{
171 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
172 long rc;
173
174 rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target, priority);
175 if (rc) {
176 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n",
177 target, priority, rc);
178 return rc;
179 }
180
181 *esn_page = retbuf[0];
182 *esn_size = retbuf[1];
183
184 pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n",
185 retbuf[0], retbuf[1]);
186
187 return 0;
188}
189
190#define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63))
191
192static long plpar_int_set_queue_config(unsigned long flags,
193 unsigned long target,
194 unsigned long priority,
195 unsigned long qpage,
196 unsigned long qsize)
197{
198 long rc;
199
200 pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n",
201 flags, target, priority, qpage, qsize);
202
203 rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target,
204 priority, qpage, qsize);
205 if (rc) {
206 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n",
207 target, priority, qpage, rc);
208 return rc;
209 }
210
211 return 0;
212}
213
214static long plpar_int_sync(unsigned long flags, unsigned long lisn)
215{
216 long rc;
217
218 rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn);
219 if (rc) {
220 pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc);
221 return rc;
222 }
223
224 return 0;
225}
226
227#define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))
228
229static long plpar_int_esb(unsigned long flags,
230 unsigned long lisn,
231 unsigned long offset,
232 unsigned long in_data,
233 unsigned long *out_data)
234{
235 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
236 long rc;
237
238 pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n",
239 flags, lisn, offset, in_data);
240
241 rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, in_data);
242 if (rc) {
243 pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n",
244 lisn, offset, rc);
245 return rc;
246 }
247
248 *out_data = retbuf[0];
249
250 return 0;
251}
252
253static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)
254{
255 unsigned long read_data;
256 long rc;
257
258 rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,
259 lisn, offset, data, &read_data);
260 if (rc)
261 return -1;
262
263 return write ? 0 : read_data;
264}
265
266#define XIVE_SRC_H_INT_ESB (1ull << (63 - 60))
267#define XIVE_SRC_LSI (1ull << (63 - 61))
268#define XIVE_SRC_TRIGGER (1ull << (63 - 62))
269#define XIVE_SRC_STORE_EOI (1ull << (63 - 63))
270
271static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
272{
273 long rc;
274 unsigned long flags;
275 unsigned long eoi_page;
276 unsigned long trig_page;
277 unsigned long esb_shift;
278
279 memset(data, 0, sizeof(*data));
280
281 rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page,
282 &esb_shift);
283 if (rc)
284 return -EINVAL;
285
286 if (flags & XIVE_SRC_H_INT_ESB)
287 data->flags |= XIVE_IRQ_FLAG_H_INT_ESB;
288 if (flags & XIVE_SRC_STORE_EOI)
289 data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
290 if (flags & XIVE_SRC_LSI)
291 data->flags |= XIVE_IRQ_FLAG_LSI;
292 data->eoi_page = eoi_page;
293 data->esb_shift = esb_shift;
294 data->trig_page = trig_page;
295
296 /*
297 * No chip-id for the sPAPR backend. This has an impact how we
298 * pick a target. See xive_pick_irq_target().
299 */
300 data->src_chip = XIVE_INVALID_CHIP_ID;
301
302 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
303 if (!data->eoi_mmio) {
304 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
305 return -ENOMEM;
306 }
307
308 data->hw_irq = hw_irq;
309
310 /* Full function page supports trigger */
311 if (flags & XIVE_SRC_TRIGGER) {
312 data->trig_mmio = data->eoi_mmio;
313 return 0;
314 }
315
316 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
317 if (!data->trig_mmio) {
318 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
319 return -ENOMEM;
320 }
321 return 0;
322}
323
324static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
325{
326 long rc;
327
328 rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target,
329 prio, sw_irq);
330
331 return rc == 0 ? 0 : -ENXIO;
332}
333
334/* This can be called multiple time to change a queue configuration */
335static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
336 __be32 *qpage, u32 order)
337{
338 s64 rc = 0;
339 unsigned long esn_page;
340 unsigned long esn_size;
341 u64 flags, qpage_phys;
342
343 /* If there's an actual queue page, clean it */
344 if (order) {
345 if (WARN_ON(!qpage))
346 return -EINVAL;
347 qpage_phys = __pa(qpage);
348 } else {
349 qpage_phys = 0;
350 }
351
352 /* Initialize the rest of the fields */
353 q->msk = order ? ((1u << (order - 2)) - 1) : 0;
354 q->idx = 0;
355 q->toggle = 0;
356
357 rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size);
358 if (rc) {
359 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc,
360 target, prio);
361 rc = -EIO;
362 goto fail;
363 }
364
365 /* TODO: add support for the notification page */
366 q->eoi_phys = esn_page;
367
368 /* Default is to always notify */
369 flags = XIVE_EQ_ALWAYS_NOTIFY;
370
371 /* Configure and enable the queue in HW */
372 rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order);
373 if (rc) {
374 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc,
375 target, prio);
376 rc = -EIO;
377 } else {
378 q->qpage = qpage;
379 }
380fail:
381 return rc;
382}
383
384static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc,
385 u8 prio)
386{
387 struct xive_q *q = &xc->queue[prio];
388 __be32 *qpage;
389
390 qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
391 if (IS_ERR(qpage))
392 return PTR_ERR(qpage);
393
394 return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu),
395 q, prio, qpage, xive_queue_shift);
396}
397
398static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
399 u8 prio)
400{
401 struct xive_q *q = &xc->queue[prio];
402 unsigned int alloc_order;
403 long rc;
404 int hw_cpu = get_hard_smp_processor_id(cpu);
405
406 rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0);
407 if (rc)
408 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc,
409 hw_cpu, prio);
410
411 alloc_order = xive_alloc_order(xive_queue_shift);
412 free_pages((unsigned long)q->qpage, alloc_order);
413 q->qpage = NULL;
414}
415
416static bool xive_spapr_match(struct device_node *node)
417{
418 /* Ignore cascaded controllers for the moment */
419 return 1;
420}
421
422#ifdef CONFIG_SMP
423static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
424{
425 int irq = xive_irq_bitmap_alloc();
426
427 if (irq < 0) {
428 pr_err("Failed to allocate IPI on CPU %d\n", cpu);
429 return -ENXIO;
430 }
431
432 xc->hw_ipi = irq;
433 return 0;
434}
435
436static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
437{
438 if (!xc->hw_ipi)
439 return;
440
441 xive_irq_bitmap_free(xc->hw_ipi);
442 xc->hw_ipi = 0;
443}
444#endif /* CONFIG_SMP */
445
446static void xive_spapr_shutdown(void)
447{
448 long rc;
449
450 rc = plpar_hcall_norets(H_INT_RESET, 0);
451 if (rc)
452 pr_err("H_INT_RESET failed %ld\n", rc);
453}
454
455/*
456 * Perform an "ack" cycle on the current thread. Grab the pending
457 * active priorities and update the CPPR to the most favored one.
458 */
459static void xive_spapr_update_pending(struct xive_cpu *xc)
460{
461 u8 nsr, cppr;
462 u16 ack;
463
464 /*
465 * Perform the "Acknowledge O/S to Register" cycle.
466 *
467 * Let's speedup the access to the TIMA using the raw I/O
468 * accessor as we don't need the synchronisation routine of
469 * the higher level ones
470 */
471 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG));
472
473 /* Synchronize subsequent queue accesses */
474 mb();
475
476 /*
477 * Grab the CPPR and the "NSR" field which indicates the source
478 * of the interrupt (if any)
479 */
480 cppr = ack & 0xff;
481 nsr = ack >> 8;
482
483 if (nsr & TM_QW1_NSR_EO) {
484 if (cppr == 0xff)
485 return;
486 /* Mark the priority pending */
487 xc->pending_prio |= 1 << cppr;
488
489 /*
490 * A new interrupt should never have a CPPR less favored
491 * than our current one.
492 */
493 if (cppr >= xc->cppr)
494 pr_err("CPU %d odd ack CPPR, got %d at %d\n",
495 smp_processor_id(), cppr, xc->cppr);
496
497 /* Update our idea of what the CPPR is */
498 xc->cppr = cppr;
499 }
500}
501
502static void xive_spapr_eoi(u32 hw_irq)
503{
504 /* Not used */;
505}
506
507static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
508{
509 /* Only some debug on the TIMA settings */
510 pr_debug("(HW value: %08x %08x %08x)\n",
511 in_be32(xive_tima + TM_QW1_OS + TM_WORD0),
512 in_be32(xive_tima + TM_QW1_OS + TM_WORD1),
513 in_be32(xive_tima + TM_QW1_OS + TM_WORD2));
514}
515
516static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
517{
518 /* Nothing to do */;
519}
520
521static void xive_spapr_sync_source(u32 hw_irq)
522{
523 /* Specs are unclear on what this is doing */
524 plpar_int_sync(0, hw_irq);
525}
526
527static const struct xive_ops xive_spapr_ops = {
528 .populate_irq_data = xive_spapr_populate_irq_data,
529 .configure_irq = xive_spapr_configure_irq,
530 .setup_queue = xive_spapr_setup_queue,
531 .cleanup_queue = xive_spapr_cleanup_queue,
532 .match = xive_spapr_match,
533 .shutdown = xive_spapr_shutdown,
534 .update_pending = xive_spapr_update_pending,
535 .eoi = xive_spapr_eoi,
536 .setup_cpu = xive_spapr_setup_cpu,
537 .teardown_cpu = xive_spapr_teardown_cpu,
538 .sync_source = xive_spapr_sync_source,
539 .esb_rw = xive_spapr_esb_rw,
540#ifdef CONFIG_SMP
541 .get_ipi = xive_spapr_get_ipi,
542 .put_ipi = xive_spapr_put_ipi,
543#endif /* CONFIG_SMP */
544 .name = "spapr",
545};
546
547/*
548 * get max priority from "/ibm,plat-res-int-priorities"
549 */
550static bool xive_get_max_prio(u8 *max_prio)
551{
552 struct device_node *rootdn;
553 const __be32 *reg;
554 u32 len;
555 int prio, found;
556
557 rootdn = of_find_node_by_path("/");
558 if (!rootdn) {
559 pr_err("not root node found !\n");
560 return false;
561 }
562
563 reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len);
564 if (!reg) {
565 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n");
566 return false;
567 }
568
569 if (len % (2 * sizeof(u32)) != 0) {
570 pr_err("invalid 'ibm,plat-res-int-priorities' property\n");
571 return false;
572 }
573
574 /* HW supports priorities in the range [0-7] and 0xFF is a
575 * wildcard priority used to mask. We scan the ranges reserved
576 * by the hypervisor to find the lowest priority we can use.
577 */
578 found = 0xFF;
579 for (prio = 0; prio < 8; prio++) {
580 int reserved = 0;
581 int i;
582
583 for (i = 0; i < len / (2 * sizeof(u32)); i++) {
584 int base = be32_to_cpu(reg[2 * i]);
585 int range = be32_to_cpu(reg[2 * i + 1]);
586
587 if (prio >= base && prio < base + range)
588 reserved++;
589 }
590
591 if (!reserved)
592 found = prio;
593 }
594
595 if (found == 0xFF) {
596 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n");
597 return false;
598 }
599
600 *max_prio = found;
601 return true;
602}
603
604bool __init xive_spapr_init(void)
605{
606 struct device_node *np;
607 struct resource r;
608 void __iomem *tima;
609 struct property *prop;
610 u8 max_prio;
611 u32 val;
612 u32 len;
613 const __be32 *reg;
614 int i;
615
616 if (xive_cmdline_disabled)
617 return false;
618
619 pr_devel("%s()\n", __func__);
620 np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe");
621 if (!np) {
622 pr_devel("not found !\n");
623 return false;
624 }
625 pr_devel("Found %s\n", np->full_name);
626
627 /* Resource 1 is the OS ring TIMA */
628 if (of_address_to_resource(np, 1, &r)) {
629 pr_err("Failed to get thread mgmnt area resource\n");
630 return false;
631 }
632 tima = ioremap(r.start, resource_size(&r));
633 if (!tima) {
634 pr_err("Failed to map thread mgmnt area\n");
635 return false;
636 }
637
638 if (!xive_get_max_prio(&max_prio))
639 return false;
640
641 /* Feed the IRQ number allocator with the ranges given in the DT */
642 reg = of_get_property(np, "ibm,xive-lisn-ranges", &len);
643 if (!reg) {
644 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n");
645 return false;
646 }
647
648 if (len % (2 * sizeof(u32)) != 0) {
649 pr_err("invalid 'ibm,xive-lisn-ranges' property\n");
650 return false;
651 }
652
653 for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2)
654 xive_irq_bitmap_add(be32_to_cpu(reg[0]),
655 be32_to_cpu(reg[1]));
656
657 /* Iterate the EQ sizes and pick one */
658 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
659 xive_queue_shift = val;
660 if (val == PAGE_SHIFT)
661 break;
662 }
663
664 /* Initialize XIVE core with our backend */
665 if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio))
666 return false;
667
668 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
669 return true;
670}