1/*
   2 *  arch/powerpc/kernel/mpic.c
   3 *
   4 *  Driver for interrupt controllers following the OpenPIC standard, the
   5 *  common implementation being IBM's MPIC. This driver also can deal
   6 *  with various broken implementations of this HW.
   7 *
   8 *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
   9 *  Copyright 2010-2012 Freescale Semiconductor, Inc.
  10 *
  11 *  This file is subject to the terms and conditions of the GNU General Public
  12 *  License.  See the file COPYING in the main directory of this archive
  13 *  for more details.
  14 */
  15
  16#undef DEBUG
  17#undef DEBUG_IPI
  18#undef DEBUG_IRQ
  19#undef DEBUG_LOW
  20
  21#include <linux/types.h>
  22#include <linux/kernel.h>
  23#include <linux/init.h>
  24#include <linux/irq.h>
  25#include <linux/smp.h>
  26#include <linux/interrupt.h>
  27#include <linux/spinlock.h>
  28#include <linux/pci.h>
  29#include <linux/slab.h>
  30#include <linux/syscore_ops.h>
  31#include <linux/ratelimit.h>
  32#include <linux/pgtable.h>
  33#include <linux/of_address.h>
  34#include <linux/of_irq.h>
  35
  36#include <asm/ptrace.h>
  37#include <asm/signal.h>
  38#include <asm/io.h>
 
  39#include <asm/irq.h>
  40#include <asm/machdep.h>
  41#include <asm/mpic.h>
  42#include <asm/smp.h>
  43
  44#include "mpic.h"
  45
  46#ifdef DEBUG
  47#define DBG(fmt...) printk(fmt)
  48#else
  49#define DBG(fmt...)
  50#endif
  51
  52struct bus_type mpic_subsys = {
  53	.name = "mpic",
  54	.dev_name = "mpic",
  55};
  56EXPORT_SYMBOL_GPL(mpic_subsys);
  57
  58static struct mpic *mpics;
  59static struct mpic *mpic_primary;
  60static DEFINE_RAW_SPINLOCK(mpic_lock);
  61
  62#ifdef CONFIG_PPC32	/* XXX for now */
  63#ifdef CONFIG_IRQ_ALL_CPUS
  64#define distribute_irqs	(1)
  65#else
  66#define distribute_irqs	(0)
  67#endif
  68#endif
  69
  70#ifdef CONFIG_MPIC_WEIRD
  71static u32 mpic_infos[][MPIC_IDX_END] = {
  72	[0] = {	/* Original OpenPIC compatible MPIC */
  73		MPIC_GREG_BASE,
  74		MPIC_GREG_FEATURE_0,
  75		MPIC_GREG_GLOBAL_CONF_0,
  76		MPIC_GREG_VENDOR_ID,
  77		MPIC_GREG_IPI_VECTOR_PRI_0,
  78		MPIC_GREG_IPI_STRIDE,
  79		MPIC_GREG_SPURIOUS,
  80		MPIC_GREG_TIMER_FREQ,
  81
  82		MPIC_TIMER_BASE,
  83		MPIC_TIMER_STRIDE,
  84		MPIC_TIMER_CURRENT_CNT,
  85		MPIC_TIMER_BASE_CNT,
  86		MPIC_TIMER_VECTOR_PRI,
  87		MPIC_TIMER_DESTINATION,
  88
  89		MPIC_CPU_BASE,
  90		MPIC_CPU_STRIDE,
  91		MPIC_CPU_IPI_DISPATCH_0,
  92		MPIC_CPU_IPI_DISPATCH_STRIDE,
  93		MPIC_CPU_CURRENT_TASK_PRI,
  94		MPIC_CPU_WHOAMI,
  95		MPIC_CPU_INTACK,
  96		MPIC_CPU_EOI,
  97		MPIC_CPU_MCACK,
  98
  99		MPIC_IRQ_BASE,
 100		MPIC_IRQ_STRIDE,
 101		MPIC_IRQ_VECTOR_PRI,
 102		MPIC_VECPRI_VECTOR_MASK,
 103		MPIC_VECPRI_POLARITY_POSITIVE,
 104		MPIC_VECPRI_POLARITY_NEGATIVE,
 105		MPIC_VECPRI_SENSE_LEVEL,
 106		MPIC_VECPRI_SENSE_EDGE,
 107		MPIC_VECPRI_POLARITY_MASK,
 108		MPIC_VECPRI_SENSE_MASK,
 109		MPIC_IRQ_DESTINATION
 110	},
 111	[1] = {	/* Tsi108/109 PIC */
 112		TSI108_GREG_BASE,
 113		TSI108_GREG_FEATURE_0,
 114		TSI108_GREG_GLOBAL_CONF_0,
 115		TSI108_GREG_VENDOR_ID,
 116		TSI108_GREG_IPI_VECTOR_PRI_0,
 117		TSI108_GREG_IPI_STRIDE,
 118		TSI108_GREG_SPURIOUS,
 119		TSI108_GREG_TIMER_FREQ,
 120
 121		TSI108_TIMER_BASE,
 122		TSI108_TIMER_STRIDE,
 123		TSI108_TIMER_CURRENT_CNT,
 124		TSI108_TIMER_BASE_CNT,
 125		TSI108_TIMER_VECTOR_PRI,
 126		TSI108_TIMER_DESTINATION,
 127
 128		TSI108_CPU_BASE,
 129		TSI108_CPU_STRIDE,
 130		TSI108_CPU_IPI_DISPATCH_0,
 131		TSI108_CPU_IPI_DISPATCH_STRIDE,
 132		TSI108_CPU_CURRENT_TASK_PRI,
 133		TSI108_CPU_WHOAMI,
 134		TSI108_CPU_INTACK,
 135		TSI108_CPU_EOI,
 136		TSI108_CPU_MCACK,
 137
 138		TSI108_IRQ_BASE,
 139		TSI108_IRQ_STRIDE,
 140		TSI108_IRQ_VECTOR_PRI,
 141		TSI108_VECPRI_VECTOR_MASK,
 142		TSI108_VECPRI_POLARITY_POSITIVE,
 143		TSI108_VECPRI_POLARITY_NEGATIVE,
 144		TSI108_VECPRI_SENSE_LEVEL,
 145		TSI108_VECPRI_SENSE_EDGE,
 146		TSI108_VECPRI_POLARITY_MASK,
 147		TSI108_VECPRI_SENSE_MASK,
 148		TSI108_IRQ_DESTINATION
 149	},
 150};
 151
 152#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
 153
 154#else /* CONFIG_MPIC_WEIRD */
 155
 156#define MPIC_INFO(name) MPIC_##name
 157
 158#endif /* CONFIG_MPIC_WEIRD */
 159
 160static inline unsigned int mpic_processor_id(struct mpic *mpic)
 161{
 162	unsigned int cpu = 0;
 163
 164	if (!(mpic->flags & MPIC_SECONDARY))
 165		cpu = hard_smp_processor_id();
 166
 167	return cpu;
 168}
 169
 170/*
 171 * Register accessor functions
 172 */
 173
 174
 175static inline u32 _mpic_read(enum mpic_reg_type type,
 176			     struct mpic_reg_bank *rb,
 177			     unsigned int reg)
 178{
 179	switch(type) {
 180#ifdef CONFIG_PPC_DCR
 181	case mpic_access_dcr:
 182		return dcr_read(rb->dhost, reg);
 183#endif
 184	case mpic_access_mmio_be:
 185		return in_be32(rb->base + (reg >> 2));
 186	case mpic_access_mmio_le:
 187	default:
 188		return in_le32(rb->base + (reg >> 2));
 189	}
 190}
 191
 192static inline void _mpic_write(enum mpic_reg_type type,
 193			       struct mpic_reg_bank *rb,
 194 			       unsigned int reg, u32 value)
 195{
 196	switch(type) {
 197#ifdef CONFIG_PPC_DCR
 198	case mpic_access_dcr:
 199		dcr_write(rb->dhost, reg, value);
 200		break;
 201#endif
 202	case mpic_access_mmio_be:
 203		out_be32(rb->base + (reg >> 2), value);
 204		break;
 205	case mpic_access_mmio_le:
 206	default:
 207		out_le32(rb->base + (reg >> 2), value);
 208		break;
 209	}
 210}
 211
 212static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 213{
 214	enum mpic_reg_type type = mpic->reg_type;
 215	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 216			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 217
 218	if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
 219		type = mpic_access_mmio_be;
 220	return _mpic_read(type, &mpic->gregs, offset);
 221}
 222
 223static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
 224{
 225	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 226			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 227
 228	_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
 229}
 230
 231static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
 232{
 233	return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
 234	       (tm & 3) * MPIC_INFO(TIMER_STRIDE);
 235}
 236
 237static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
 238{
 239	unsigned int offset = mpic_tm_offset(mpic, tm) +
 240			      MPIC_INFO(TIMER_VECTOR_PRI);
 241
 242	return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
 243}
 244
 245static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
 246{
 247	unsigned int offset = mpic_tm_offset(mpic, tm) +
 248			      MPIC_INFO(TIMER_VECTOR_PRI);
 249
 250	_mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
 251}
 252
 253static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
 254{
 255	unsigned int cpu = mpic_processor_id(mpic);
 256
 257	return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
 258}
 259
 260static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
 261{
 262	unsigned int cpu = mpic_processor_id(mpic);
 263
 264	_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
 265}
 266
 267static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
 268{
 269	unsigned int	isu = src_no >> mpic->isu_shift;
 270	unsigned int	idx = src_no & mpic->isu_mask;
 271	unsigned int	val;
 272
 273	val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
 274			 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 275#ifdef CONFIG_MPIC_BROKEN_REGREAD
 276	if (reg == 0)
 277		val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
 278			mpic->isu_reg0_shadow[src_no];
 279#endif
 280	return val;
 281}
 282
 283static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 284				   unsigned int reg, u32 value)
 285{
 286	unsigned int	isu = src_no >> mpic->isu_shift;
 287	unsigned int	idx = src_no & mpic->isu_mask;
 288
 289	_mpic_write(mpic->reg_type, &mpic->isus[isu],
 290		    reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
 291
 292#ifdef CONFIG_MPIC_BROKEN_REGREAD
 293	if (reg == 0)
 294		mpic->isu_reg0_shadow[src_no] =
 295			value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
 296#endif
 297}
 298
 299#define mpic_read(b,r)		_mpic_read(mpic->reg_type,&(b),(r))
 300#define mpic_write(b,r,v)	_mpic_write(mpic->reg_type,&(b),(r),(v))
 301#define mpic_ipi_read(i)	_mpic_ipi_read(mpic,(i))
 302#define mpic_ipi_write(i,v)	_mpic_ipi_write(mpic,(i),(v))
 303#define mpic_tm_read(i)		_mpic_tm_read(mpic,(i))
 304#define mpic_tm_write(i,v)	_mpic_tm_write(mpic,(i),(v))
 305#define mpic_cpu_read(i)	_mpic_cpu_read(mpic,(i))
 306#define mpic_cpu_write(i,v)	_mpic_cpu_write(mpic,(i),(v))
 307#define mpic_irq_read(s,r)	_mpic_irq_read(mpic,(s),(r))
 308#define mpic_irq_write(s,r,v)	_mpic_irq_write(mpic,(s),(r),(v))
 309
 310
 311/*
 312 * Low level utility functions
 313 */
 314
 315
 316static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
 317			   struct mpic_reg_bank *rb, unsigned int offset,
 318			   unsigned int size)
 319{
 320	rb->base = ioremap(phys_addr + offset, size);
 321	BUG_ON(rb->base == NULL);
 322}
 323
 324#ifdef CONFIG_PPC_DCR
 325static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
 326			  unsigned int offset, unsigned int size)
 327{
 328	phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
 329	rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
 330	BUG_ON(!DCR_MAP_OK(rb->dhost));
 331}
 332
 333static inline void mpic_map(struct mpic *mpic,
 334			    phys_addr_t phys_addr, struct mpic_reg_bank *rb,
 335			    unsigned int offset, unsigned int size)
 336{
 337	if (mpic->flags & MPIC_USES_DCR)
 338		_mpic_map_dcr(mpic, rb, offset, size);
 339	else
 340		_mpic_map_mmio(mpic, phys_addr, rb, offset, size);
 341}
 342#else /* CONFIG_PPC_DCR */
 343#define mpic_map(m,p,b,o,s)	_mpic_map_mmio(m,p,b,o,s)
 344#endif /* !CONFIG_PPC_DCR */
 345
 346
 347
 348/* Check if we have one of those nice broken MPICs with a flipped endian on
 349 * reads from IPI registers
 350 */
 351static void __init mpic_test_broken_ipi(struct mpic *mpic)
 352{
 353	u32 r;
 354
 355	mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
 356	r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
 357
 358	if (r == swab32(MPIC_VECPRI_MASK)) {
 359		printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
 360		mpic->flags |= MPIC_BROKEN_IPI;
 361	}
 362}
 363
 364#ifdef CONFIG_MPIC_U3_HT_IRQS
 365
 366/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 367 * to force the edge setting on the MPIC and do the ack workaround.
 368 */
 369static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 370{
 371	if (source >= 128 || !mpic->fixups)
 372		return 0;
 373	return mpic->fixups[source].base != NULL;
 374}
 375
 376
 377static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
 378{
 379	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 380
 381	if (fixup->applebase) {
 382		unsigned int soff = (fixup->index >> 3) & ~3;
 383		unsigned int mask = 1U << (fixup->index & 0x1f);
 384		writel(mask, fixup->applebase + soff);
 385	} else {
 386		raw_spin_lock(&mpic->fixup_lock);
 387		writeb(0x11 + 2 * fixup->index, fixup->base + 2);
 388		writel(fixup->data, fixup->base + 4);
 389		raw_spin_unlock(&mpic->fixup_lock);
 390	}
 391}
 392
 393static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 394				      bool level)
 395{
 396	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 397	unsigned long flags;
 398	u32 tmp;
 399
 400	if (fixup->base == NULL)
 401		return;
 402
 403	DBG("startup_ht_interrupt(0x%x) index: %d\n",
 404	    source, fixup->index);
 405	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 406	/* Enable and configure */
 407	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 408	tmp = readl(fixup->base + 4);
 409	tmp &= ~(0x23U);
 410	if (level)
 411		tmp |= 0x22;
 412	writel(tmp, fixup->base + 4);
 413	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 414
 415#ifdef CONFIG_PM
 416	/* use the lowest bit inverted to the actual HW,
 417	 * set if this fixup was enabled, clear otherwise */
 418	mpic->save_data[source].fixup_data = tmp | 1;
 419#endif
 420}
 421
 422static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
 423{
 424	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 425	unsigned long flags;
 426	u32 tmp;
 427
 428	if (fixup->base == NULL)
 429		return;
 430
 431	DBG("shutdown_ht_interrupt(0x%x)\n", source);
 432
 433	/* Disable */
 434	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 435	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 436	tmp = readl(fixup->base + 4);
 437	tmp |= 1;
 438	writel(tmp, fixup->base + 4);
 439	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 440
 441#ifdef CONFIG_PM
 442	/* use the lowest bit inverted to the actual HW,
 443	 * set if this fixup was enabled, clear otherwise */
 444	mpic->save_data[source].fixup_data = tmp & ~1;
 445#endif
 446}
 447
 448#ifdef CONFIG_PCI_MSI
 449static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 450				    unsigned int devfn)
 451{
 452	u8 __iomem *base;
 453	u8 pos, flags;
 454	u64 addr = 0;
 455
 456	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 457	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 458		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 459		if (id == PCI_CAP_ID_HT) {
 460			id = readb(devbase + pos + 3);
 461			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
 462				break;
 463		}
 464	}
 465
 466	if (pos == 0)
 467		return;
 468
 469	base = devbase + pos;
 470
 471	flags = readb(base + HT_MSI_FLAGS);
 472	if (!(flags & HT_MSI_FLAGS_FIXED)) {
 473		addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
 474		addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
 475	}
 476
 477	printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
 478		PCI_SLOT(devfn), PCI_FUNC(devfn),
 479		flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
 480
 481	if (!(flags & HT_MSI_FLAGS_ENABLE))
 482		writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
 483}
 484#else
 485static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 486				    unsigned int devfn)
 487{
 488	return;
 489}
 490#endif
 491
 492static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
 493				    unsigned int devfn, u32 vdid)
 494{
 495	int i, irq, n;
 496	u8 __iomem *base;
 497	u32 tmp;
 498	u8 pos;
 499
 500	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 501	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 502		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 503		if (id == PCI_CAP_ID_HT) {
 504			id = readb(devbase + pos + 3);
 505			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
 506				break;
 507		}
 508	}
 509	if (pos == 0)
 510		return;
 511
 512	base = devbase + pos;
 513	writeb(0x01, base + 2);
 514	n = (readl(base + 4) >> 16) & 0xff;
 515
 516	printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
 517	       " has %d irqs\n",
 518	       devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
 519
 520	for (i = 0; i <= n; i++) {
 521		writeb(0x10 + 2 * i, base + 2);
 522		tmp = readl(base + 4);
 523		irq = (tmp >> 16) & 0xff;
 524		DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
 525		/* mask it , will be unmasked later */
 526		tmp |= 0x1;
 527		writel(tmp, base + 4);
 528		mpic->fixups[irq].index = i;
 529		mpic->fixups[irq].base = base;
 530		/* Apple HT PIC has a non-standard way of doing EOIs */
 531		if ((vdid & 0xffff) == 0x106b)
 532			mpic->fixups[irq].applebase = devbase + 0x60;
 533		else
 534			mpic->fixups[irq].applebase = NULL;
 535		writeb(0x11 + 2 * i, base + 2);
 536		mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
 537	}
 538}
 539
 540
 541static void __init mpic_scan_ht_pics(struct mpic *mpic)
 542{
 543	unsigned int devfn;
 544	u8 __iomem *cfgspace;
 545
 546	printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
 547
 548	/* Allocate fixups array */
 549	mpic->fixups = kcalloc(128, sizeof(*mpic->fixups), GFP_KERNEL);
 550	BUG_ON(mpic->fixups == NULL);
 551
 552	/* Init spinlock */
 553	raw_spin_lock_init(&mpic->fixup_lock);
 554
 555	/* Map U3 config space. We assume all IO-APICs are on the primary bus
 556	 * so we only need to map 64kB.
 557	 */
 558	cfgspace = ioremap(0xf2000000, 0x10000);
 559	BUG_ON(cfgspace == NULL);
 560
 561	/* Now we scan all slots. We do a very quick scan, we read the header
 562	 * type, vendor ID and device ID only, that's plenty enough
 563	 */
 564	for (devfn = 0; devfn < 0x100; devfn++) {
 565		u8 __iomem *devbase = cfgspace + (devfn << 8);
 566		u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
 567		u32 l = readl(devbase + PCI_VENDOR_ID);
 568		u16 s;
 569
 570		DBG("devfn %x, l: %x\n", devfn, l);
 571
 572		/* If no device, skip */
 573		if (l == 0xffffffff || l == 0x00000000 ||
 574		    l == 0x0000ffff || l == 0xffff0000)
 575			goto next;
 576		/* Check if is supports capability lists */
 577		s = readw(devbase + PCI_STATUS);
 578		if (!(s & PCI_STATUS_CAP_LIST))
 579			goto next;
 580
 581		mpic_scan_ht_pic(mpic, devbase, devfn, l);
 582		mpic_scan_ht_msi(mpic, devbase, devfn);
 583
 584	next:
 585		/* next device, if function 0 */
 586		if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
 587			devfn += 7;
 588	}
 589}
 590
 591#else /* CONFIG_MPIC_U3_HT_IRQS */
 592
 593static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 594{
 595	return 0;
 596}
 597
 598static void __init mpic_scan_ht_pics(struct mpic *mpic)
 599{
 600}
 601
 602#endif /* CONFIG_MPIC_U3_HT_IRQS */
 603
 604/* Find an mpic associated with a given linux interrupt */
 605static struct mpic *mpic_find(unsigned int irq)
 606{
 607	if (irq < NR_IRQS_LEGACY)
 608		return NULL;
 609
 610	return irq_get_chip_data(irq);
 611}
 612
 613/* Determine if the linux irq is an IPI */
 614static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
 615{
 616	return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 617}
 618
 619/* Determine if the linux irq is a timer */
 620static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
 621{
 622	return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
 623}
 624
 625/* Convert a cpu mask from logical to physical cpu numbers. */
 626static inline u32 mpic_physmask(u32 cpumask)
 627{
 628	int i;
 629	u32 mask = 0;
 630
 631	for (i = 0; i < min(32, NR_CPUS) && cpu_possible(i); ++i, cpumask >>= 1)
 632		mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
 633	return mask;
 634}
 635
 636#ifdef CONFIG_SMP
 637/* Get the mpic structure from the IPI number */
 638static inline struct mpic * mpic_from_ipi(struct irq_data *d)
 639{
 640	return irq_data_get_irq_chip_data(d);
 641}
 642#endif
 643
 644/* Get the mpic structure from the irq number */
 645static inline struct mpic * mpic_from_irq(unsigned int irq)
 646{
 647	return irq_get_chip_data(irq);
 648}
 649
 650/* Get the mpic structure from the irq data */
 651static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
 652{
 653	return irq_data_get_irq_chip_data(d);
 654}
 655
 656/* Send an EOI */
 657static inline void mpic_eoi(struct mpic *mpic)
 658{
 659	mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
 660}
 661
 662/*
 663 * Linux descriptor level callbacks
 664 */
 665
 666
 667void mpic_unmask_irq(struct irq_data *d)
 668{
 669	unsigned int loops = 100000;
 670	struct mpic *mpic = mpic_from_irq_data(d);
 671	unsigned int src = irqd_to_hwirq(d);
 672
 673	DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
 674
 675	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 676		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
 677		       ~MPIC_VECPRI_MASK);
 678	/* make sure mask gets to controller before we return to user */
 679	do {
 680		if (!loops--) {
 681			printk(KERN_ERR "%s: timeout on hwirq %u\n",
 682			       __func__, src);
 683			break;
 684		}
 685	} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
 686}
 687
 688void mpic_mask_irq(struct irq_data *d)
 689{
 690	unsigned int loops = 100000;
 691	struct mpic *mpic = mpic_from_irq_data(d);
 692	unsigned int src = irqd_to_hwirq(d);
 693
 694	DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
 695
 696	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 697		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
 698		       MPIC_VECPRI_MASK);
 699
 700	/* make sure mask gets to controller before we return to user */
 701	do {
 702		if (!loops--) {
 703			printk(KERN_ERR "%s: timeout on hwirq %u\n",
 704			       __func__, src);
 705			break;
 706		}
 707	} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
 708}
 709
 710void mpic_end_irq(struct irq_data *d)
 711{
 712	struct mpic *mpic = mpic_from_irq_data(d);
 713
 714#ifdef DEBUG_IRQ
 715	DBG("%s: end_irq: %d\n", mpic->name, d->irq);
 716#endif
 717	/* We always EOI on end_irq() even for edge interrupts since that
 718	 * should only lower the priority, the MPIC should have properly
 719	 * latched another edge interrupt coming in anyway
 720	 */
 721
 722	mpic_eoi(mpic);
 723}
 724
 725#ifdef CONFIG_MPIC_U3_HT_IRQS
 726
 727static void mpic_unmask_ht_irq(struct irq_data *d)
 728{
 729	struct mpic *mpic = mpic_from_irq_data(d);
 730	unsigned int src = irqd_to_hwirq(d);
 731
 732	mpic_unmask_irq(d);
 733
 734	if (irqd_is_level_type(d))
 735		mpic_ht_end_irq(mpic, src);
 736}
 737
 738static unsigned int mpic_startup_ht_irq(struct irq_data *d)
 739{
 740	struct mpic *mpic = mpic_from_irq_data(d);
 741	unsigned int src = irqd_to_hwirq(d);
 742
 743	mpic_unmask_irq(d);
 744	mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
 745
 746	return 0;
 747}
 748
 749static void mpic_shutdown_ht_irq(struct irq_data *d)
 750{
 751	struct mpic *mpic = mpic_from_irq_data(d);
 752	unsigned int src = irqd_to_hwirq(d);
 753
 754	mpic_shutdown_ht_interrupt(mpic, src);
 755	mpic_mask_irq(d);
 756}
 757
 758static void mpic_end_ht_irq(struct irq_data *d)
 759{
 760	struct mpic *mpic = mpic_from_irq_data(d);
 761	unsigned int src = irqd_to_hwirq(d);
 762
 763#ifdef DEBUG_IRQ
 764	DBG("%s: end_irq: %d\n", mpic->name, d->irq);
 765#endif
 766	/* We always EOI on end_irq() even for edge interrupts since that
 767	 * should only lower the priority, the MPIC should have properly
 768	 * latched another edge interrupt coming in anyway
 769	 */
 770
 771	if (irqd_is_level_type(d))
 772		mpic_ht_end_irq(mpic, src);
 773	mpic_eoi(mpic);
 774}
 775#endif /* !CONFIG_MPIC_U3_HT_IRQS */
 776
 777#ifdef CONFIG_SMP
 778
 779static void mpic_unmask_ipi(struct irq_data *d)
 780{
 781	struct mpic *mpic = mpic_from_ipi(d);
 782	unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
 783
 784	DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
 785	mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
 786}
 787
 788static void mpic_mask_ipi(struct irq_data *d)
 789{
 790	/* NEVER disable an IPI... that's just plain wrong! */
 791}
 792
 793static void mpic_end_ipi(struct irq_data *d)
 794{
 795	struct mpic *mpic = mpic_from_ipi(d);
 796
 797	/*
 798	 * IPIs are marked IRQ_PER_CPU. This has the side effect of
 799	 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
 800	 * applying to them. We EOI them late to avoid re-entering.
 801	 */
 802	mpic_eoi(mpic);
 803}
 804
 805#endif /* CONFIG_SMP */
 806
 807static void mpic_unmask_tm(struct irq_data *d)
 808{
 809	struct mpic *mpic = mpic_from_irq_data(d);
 810	unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
 811
 812	DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
 813	mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
 814	mpic_tm_read(src);
 815}
 816
 817static void mpic_mask_tm(struct irq_data *d)
 818{
 819	struct mpic *mpic = mpic_from_irq_data(d);
 820	unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
 821
 822	mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
 823	mpic_tm_read(src);
 824}
 825
 826int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 827		      bool force)
 828{
 829	struct mpic *mpic = mpic_from_irq_data(d);
 830	unsigned int src = irqd_to_hwirq(d);
 831
 832	if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
 833		int cpuid = irq_choose_cpu(cpumask);
 834
 835		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 836	} else {
 837		u32 mask = cpumask_bits(cpumask)[0];
 838
 839		mask &= cpumask_bits(cpu_online_mask)[0];
 840
 841		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
 842			       mpic_physmask(mask));
 843	}
 844
 845	return IRQ_SET_MASK_OK;
 846}
 847
 848static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
 849{
 850	/* Now convert sense value */
 851	switch(type & IRQ_TYPE_SENSE_MASK) {
 852	case IRQ_TYPE_EDGE_RISING:
 853		return MPIC_INFO(VECPRI_SENSE_EDGE) |
 854		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 855	case IRQ_TYPE_EDGE_FALLING:
 856	case IRQ_TYPE_EDGE_BOTH:
 857		return MPIC_INFO(VECPRI_SENSE_EDGE) |
 858		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 859	case IRQ_TYPE_LEVEL_HIGH:
 860		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 861		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 862	case IRQ_TYPE_LEVEL_LOW:
 863	default:
 864		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 865		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 866	}
 867}
 868
 869int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 870{
 871	struct mpic *mpic = mpic_from_irq_data(d);
 872	unsigned int src = irqd_to_hwirq(d);
 873	unsigned int vecpri, vold, vnew;
 874
 875	DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
 876	    mpic, d->irq, src, flow_type);
 877
 878	if (src >= mpic->num_sources)
 879		return -EINVAL;
 880
 881	vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 882
 883	/* We don't support "none" type */
 884	if (flow_type == IRQ_TYPE_NONE)
 885		flow_type = IRQ_TYPE_DEFAULT;
 886
 887	/* Default: read HW settings */
 888	if (flow_type == IRQ_TYPE_DEFAULT) {
 889		int vold_ps;
 890
 891		vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
 892				  MPIC_INFO(VECPRI_SENSE_MASK));
 893
 894		if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
 895				MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
 896			flow_type = IRQ_TYPE_EDGE_RISING;
 897		else if	(vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
 898				     MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
 899			flow_type = IRQ_TYPE_EDGE_FALLING;
 900		else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
 901				     MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
 902			flow_type = IRQ_TYPE_LEVEL_HIGH;
 903		else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
 904				     MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
 905			flow_type = IRQ_TYPE_LEVEL_LOW;
 906		else
 907			WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
 908	}
 909
 910	/* Apply to irq desc */
 911	irqd_set_trigger_type(d, flow_type);
 912
 913	/* Apply to HW */
 914	if (mpic_is_ht_interrupt(mpic, src))
 915		vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
 916			MPIC_VECPRI_SENSE_EDGE;
 917	else
 918		vecpri = mpic_type_to_vecpri(mpic, flow_type);
 919
 920	vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
 921			MPIC_INFO(VECPRI_SENSE_MASK));
 922	vnew |= vecpri;
 923	if (vold != vnew)
 924		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 925
 926	return IRQ_SET_MASK_OK_NOCOPY;
 927}
 928
 929void mpic_set_vector(unsigned int virq, unsigned int vector)
 930{
 931	struct mpic *mpic = mpic_from_irq(virq);
 932	unsigned int src = virq_to_hw(virq);
 933	unsigned int vecpri;
 934
 935	DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
 936	    mpic, virq, src, vector);
 937
 938	if (src >= mpic->num_sources)
 939		return;
 940
 941	vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 942	vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
 943	vecpri |= vector;
 944	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
 945}
 946
 947static void mpic_set_destination(unsigned int virq, unsigned int cpuid)
 948{
 949	struct mpic *mpic = mpic_from_irq(virq);
 950	unsigned int src = virq_to_hw(virq);
 951
 952	DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
 953	    mpic, virq, src, cpuid);
 954
 955	if (src >= mpic->num_sources)
 956		return;
 957
 958	mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 959}
 960
 961static struct irq_chip mpic_irq_chip = {
 962	.irq_mask	= mpic_mask_irq,
 963	.irq_unmask	= mpic_unmask_irq,
 964	.irq_eoi	= mpic_end_irq,
 965	.irq_set_type	= mpic_set_irq_type,
 966};
 967
 968#ifdef CONFIG_SMP
 969static const struct irq_chip mpic_ipi_chip = {
 970	.irq_mask	= mpic_mask_ipi,
 971	.irq_unmask	= mpic_unmask_ipi,
 972	.irq_eoi	= mpic_end_ipi,
 973};
 974#endif /* CONFIG_SMP */
 975
 976static struct irq_chip mpic_tm_chip = {
 977	.irq_mask	= mpic_mask_tm,
 978	.irq_unmask	= mpic_unmask_tm,
 979	.irq_eoi	= mpic_end_irq,
 980};
 981
 982#ifdef CONFIG_MPIC_U3_HT_IRQS
 983static const struct irq_chip mpic_irq_ht_chip = {
 984	.irq_startup	= mpic_startup_ht_irq,
 985	.irq_shutdown	= mpic_shutdown_ht_irq,
 986	.irq_mask	= mpic_mask_irq,
 987	.irq_unmask	= mpic_unmask_ht_irq,
 988	.irq_eoi	= mpic_end_ht_irq,
 989	.irq_set_type	= mpic_set_irq_type,
 990};
 991#endif /* CONFIG_MPIC_U3_HT_IRQS */
 992
 993
 994static int mpic_host_match(struct irq_domain *h, struct device_node *node,
 995			   enum irq_domain_bus_token bus_token)
 996{
 997	/* Exact match, unless mpic node is NULL */
 998	struct device_node *of_node = irq_domain_get_of_node(h);
 999	return of_node == NULL || of_node == node;
1000}
1001
1002static int mpic_host_map(struct irq_domain *h, unsigned int virq,
1003			 irq_hw_number_t hw)
1004{
1005	struct mpic *mpic = h->host_data;
1006	struct irq_chip *chip;
1007
1008	DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1009
1010	if (hw == mpic->spurious_vec)
1011		return -EINVAL;
1012	if (mpic->protected && test_bit(hw, mpic->protected)) {
1013		pr_warn("mpic: Mapping of source 0x%x failed, source protected by firmware !\n",
1014			(unsigned int)hw);
1015		return -EPERM;
1016	}
1017
1018#ifdef CONFIG_SMP
1019	else if (hw >= mpic->ipi_vecs[0]) {
1020		WARN_ON(mpic->flags & MPIC_SECONDARY);
1021
1022		DBG("mpic: mapping as IPI\n");
1023		irq_set_chip_data(virq, mpic);
1024		irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1025					 handle_percpu_irq);
1026		return 0;
1027	}
1028#endif /* CONFIG_SMP */
1029
1030	if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1031		WARN_ON(mpic->flags & MPIC_SECONDARY);
1032
1033		DBG("mpic: mapping as timer\n");
1034		irq_set_chip_data(virq, mpic);
1035		irq_set_chip_and_handler(virq, &mpic->hc_tm,
1036					 handle_fasteoi_irq);
1037		return 0;
1038	}
1039
1040	if (mpic_map_error_int(mpic, virq, hw))
1041		return 0;
1042
1043	if (hw >= mpic->num_sources) {
1044		pr_warn("mpic: Mapping of source 0x%x failed, source out of range !\n",
1045			(unsigned int)hw);
1046		return -EINVAL;
1047	}
1048
1049	mpic_msi_reserve_hwirq(mpic, hw);
1050
1051	/* Default chip */
1052	chip = &mpic->hc_irq;
1053
1054#ifdef CONFIG_MPIC_U3_HT_IRQS
1055	/* Check for HT interrupts, override vecpri */
1056	if (mpic_is_ht_interrupt(mpic, hw))
1057		chip = &mpic->hc_ht_irq;
1058#endif /* CONFIG_MPIC_U3_HT_IRQS */
1059
1060	DBG("mpic: mapping to irq chip @%p\n", chip);
1061
1062	irq_set_chip_data(virq, mpic);
1063	irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1064
1065	/* Set default irq type */
1066	irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1067
1068	/* If the MPIC was reset, then all vectors have already been
1069	 * initialized.  Otherwise, a per source lazy initialization
1070	 * is done here.
1071	 */
1072	if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1073		int cpu;
1074
1075		preempt_disable();
1076		cpu = mpic_processor_id(mpic);
1077		preempt_enable();
1078
1079		mpic_set_vector(virq, hw);
1080		mpic_set_destination(virq, cpu);
1081		mpic_irq_set_priority(virq, 8);
1082	}
1083
1084	return 0;
1085}
1086
1087static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1088			   const u32 *intspec, unsigned int intsize,
1089			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1090
1091{
1092	struct mpic *mpic = h->host_data;
1093	static unsigned char map_mpic_senses[4] = {
1094		IRQ_TYPE_EDGE_RISING,
1095		IRQ_TYPE_LEVEL_LOW,
1096		IRQ_TYPE_LEVEL_HIGH,
1097		IRQ_TYPE_EDGE_FALLING,
1098	};
1099
1100	*out_hwirq = intspec[0];
1101	if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1102		/*
1103		 * Freescale MPIC with extended intspec:
1104		 * First two cells are as usual.  Third specifies
1105		 * an "interrupt type".  Fourth is type-specific data.
1106		 *
1107		 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1108		 */
1109		switch (intspec[2]) {
1110		case 0:
1111			break;
1112		case 1:
1113			if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1114				break;
1115
1116			if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1117				return -EINVAL;
1118
1119			*out_hwirq = mpic->err_int_vecs[intspec[3]];
1120
1121			break;
1122		case 2:
1123			if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1124				return -EINVAL;
1125
1126			*out_hwirq = mpic->ipi_vecs[intspec[0]];
1127			break;
1128		case 3:
1129			if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1130				return -EINVAL;
1131
1132			*out_hwirq = mpic->timer_vecs[intspec[0]];
1133			break;
1134		default:
1135			pr_debug("%s: unknown irq type %u\n",
1136				 __func__, intspec[2]);
1137			return -EINVAL;
1138		}
1139
1140		*out_flags = map_mpic_senses[intspec[1] & 3];
1141	} else if (intsize > 1) {
1142		u32 mask = 0x3;
1143
1144		/* Apple invented a new race of encoding on machines with
1145		 * an HT APIC. They encode, among others, the index within
1146		 * the HT APIC. We don't care about it here since thankfully,
1147		 * it appears that they have the APIC already properly
1148		 * configured, and thus our current fixup code that reads the
1149		 * APIC config works fine. However, we still need to mask out
1150		 * bits in the specifier to make sure we only get bit 0 which
1151		 * is the level/edge bit (the only sense bit exposed by Apple),
1152		 * as their bit 1 means something else.
1153		 */
1154		if (machine_is(powermac))
1155			mask = 0x1;
1156		*out_flags = map_mpic_senses[intspec[1] & mask];
1157	} else
1158		*out_flags = IRQ_TYPE_NONE;
1159
1160	DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1161	    intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1162
1163	return 0;
1164}
1165
1166/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1167static void mpic_cascade(struct irq_desc *desc)
1168{
1169	struct irq_chip *chip = irq_desc_get_chip(desc);
1170	struct mpic *mpic = irq_desc_get_handler_data(desc);
1171	unsigned int virq;
1172
1173	BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1174
1175	virq = mpic_get_one_irq(mpic);
1176	if (virq)
1177		generic_handle_irq(virq);
1178
1179	chip->irq_eoi(&desc->irq_data);
1180}
1181
1182static const struct irq_domain_ops mpic_host_ops = {
1183	.match = mpic_host_match,
1184	.map = mpic_host_map,
1185	.xlate = mpic_host_xlate,
1186};
1187
1188static u32 fsl_mpic_get_version(struct mpic *mpic)
1189{
1190	u32 brr1;
1191
1192	if (!(mpic->flags & MPIC_FSL))
1193		return 0;
1194
1195	brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1196			MPIC_FSL_BRR1);
1197
1198	return brr1 & MPIC_FSL_BRR1_VER;
1199}
1200
1201/*
1202 * Exported functions
1203 */
1204
1205u32 fsl_mpic_primary_get_version(void)
1206{
1207	struct mpic *mpic = mpic_primary;
1208
1209	if (mpic)
1210		return fsl_mpic_get_version(mpic);
1211
1212	return 0;
1213}
1214
1215struct mpic * __init mpic_alloc(struct device_node *node,
1216				phys_addr_t phys_addr,
1217				unsigned int flags,
1218				unsigned int isu_size,
1219				unsigned int irq_count,
1220				const char *name)
1221{
1222	int i, psize, intvec_top;
1223	struct mpic *mpic;
1224	u32 greg_feature;
1225	const char *vers;
1226	const u32 *psrc;
1227	u32 last_irq;
1228	u32 fsl_version = 0;
1229
1230	/* Default MPIC search parameters */
1231	static const struct of_device_id __initconst mpic_device_id[] = {
1232		{ .type	      = "open-pic", },
1233		{ .compatible = "open-pic", },
1234		{},
1235	};
1236
1237	/*
1238	 * If we were not passed a device-tree node, then perform the default
1239	 * search for standardized a standardized OpenPIC.
1240	 */
1241	if (node) {
1242		node = of_node_get(node);
1243	} else {
1244		node = of_find_matching_node(NULL, mpic_device_id);
1245		if (!node)
1246			return NULL;
1247	}
1248
1249	/* Pick the physical address from the device tree if unspecified */
1250	if (!phys_addr) {
1251		/* Check if it is DCR-based */
1252		if (of_property_read_bool(node, "dcr-reg")) {
1253			flags |= MPIC_USES_DCR;
1254		} else {
1255			struct resource r;
1256			if (of_address_to_resource(node, 0, &r))
1257				goto err_of_node_put;
1258			phys_addr = r.start;
1259		}
1260	}
1261
1262	/* Read extra device-tree properties into the flags variable */
1263	if (of_property_read_bool(node, "big-endian"))
1264		flags |= MPIC_BIG_ENDIAN;
1265	if (of_property_read_bool(node, "pic-no-reset"))
1266		flags |= MPIC_NO_RESET;
1267	if (of_property_read_bool(node, "single-cpu-affinity"))
1268		flags |= MPIC_SINGLE_DEST_CPU;
1269	if (of_device_is_compatible(node, "fsl,mpic")) {
1270		flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
1271		mpic_irq_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
1272		mpic_tm_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
1273	}
1274
1275	mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1276	if (mpic == NULL)
1277		goto err_of_node_put;
1278
1279	mpic->name = name;
1280	mpic->node = node;
1281	mpic->paddr = phys_addr;
1282	mpic->flags = flags;
1283
1284	mpic->hc_irq = mpic_irq_chip;
1285	mpic->hc_irq.name = name;
1286	if (!(mpic->flags & MPIC_SECONDARY))
1287		mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1288#ifdef CONFIG_MPIC_U3_HT_IRQS
1289	mpic->hc_ht_irq = mpic_irq_ht_chip;
1290	mpic->hc_ht_irq.name = name;
1291	if (!(mpic->flags & MPIC_SECONDARY))
1292		mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1293#endif /* CONFIG_MPIC_U3_HT_IRQS */
1294
1295#ifdef CONFIG_SMP
1296	mpic->hc_ipi = mpic_ipi_chip;
1297	mpic->hc_ipi.name = name;
1298#endif /* CONFIG_SMP */
1299
1300	mpic->hc_tm = mpic_tm_chip;
1301	mpic->hc_tm.name = name;
1302
1303	mpic->num_sources = 0; /* so far */
1304
1305	if (mpic->flags & MPIC_LARGE_VECTORS)
1306		intvec_top = 2047;
1307	else
1308		intvec_top = 255;
1309
1310	mpic->timer_vecs[0] = intvec_top - 12;
1311	mpic->timer_vecs[1] = intvec_top - 11;
1312	mpic->timer_vecs[2] = intvec_top - 10;
1313	mpic->timer_vecs[3] = intvec_top - 9;
1314	mpic->timer_vecs[4] = intvec_top - 8;
1315	mpic->timer_vecs[5] = intvec_top - 7;
1316	mpic->timer_vecs[6] = intvec_top - 6;
1317	mpic->timer_vecs[7] = intvec_top - 5;
1318	mpic->ipi_vecs[0]   = intvec_top - 4;
1319	mpic->ipi_vecs[1]   = intvec_top - 3;
1320	mpic->ipi_vecs[2]   = intvec_top - 2;
1321	mpic->ipi_vecs[3]   = intvec_top - 1;
1322	mpic->spurious_vec  = intvec_top;
1323
1324	/* Look for protected sources */
1325	psrc = of_get_property(mpic->node, "protected-sources", &psize);
1326	if (psrc) {
1327		/* Allocate a bitmap with one bit per interrupt */
1328		mpic->protected = bitmap_zalloc(intvec_top + 1, GFP_KERNEL);
 
1329		BUG_ON(mpic->protected == NULL);
1330		for (i = 0; i < psize/sizeof(u32); i++) {
1331			if (psrc[i] > intvec_top)
1332				continue;
1333			__set_bit(psrc[i], mpic->protected);
1334		}
1335	}
1336
1337#ifdef CONFIG_MPIC_WEIRD
1338	mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1339#endif
1340
1341	/* default register type */
1342	if (mpic->flags & MPIC_BIG_ENDIAN)
1343		mpic->reg_type = mpic_access_mmio_be;
1344	else
1345		mpic->reg_type = mpic_access_mmio_le;
1346
1347	/*
1348	 * An MPIC with a "dcr-reg" property must be accessed that way, but
1349	 * only if the kernel includes DCR support.
1350	 */
1351#ifdef CONFIG_PPC_DCR
1352	if (mpic->flags & MPIC_USES_DCR)
1353		mpic->reg_type = mpic_access_dcr;
1354#else
1355	BUG_ON(mpic->flags & MPIC_USES_DCR);
1356#endif
1357
1358	/* Map the global registers */
1359	mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1360	mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1361
1362	if (mpic->flags & MPIC_FSL) {
1363		int ret;
1364
1365		/*
1366		 * Yes, Freescale really did put global registers in the
1367		 * magic per-cpu area -- and they don't even show up in the
1368		 * non-magic per-cpu copies that this driver normally uses.
1369		 */
1370		mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1371			 MPIC_CPU_THISBASE, 0x1000);
1372
1373		fsl_version = fsl_mpic_get_version(mpic);
1374
1375		/* Error interrupt mask register (EIMR) is required for
1376		 * handling individual device error interrupts. EIMR
1377		 * was added in MPIC version 4.1.
1378		 *
1379		 * Over here we reserve vector number space for error
1380		 * interrupt vectors. This space is stolen from the
1381		 * global vector number space, as in case of ipis
1382		 * and timer interrupts.
1383		 *
1384		 * Available vector space = intvec_top - 13, where 13
1385		 * is the number of vectors which have been consumed by
1386		 * ipis, timer interrupts and spurious.
1387		 */
1388		if (fsl_version >= 0x401) {
1389			ret = mpic_setup_error_int(mpic, intvec_top - 13);
1390			if (ret)
1391				return NULL;
1392		}
1393
1394	}
1395
1396	/*
1397	 * EPR is only available starting with v4.0.  To support
1398	 * platforms that don't know the MPIC version at compile-time,
1399	 * such as qemu-e500, turn off coreint if this MPIC doesn't
1400	 * support it.  Note that we never enable it if it wasn't
1401	 * requested in the first place.
1402	 *
1403	 * This is done outside the MPIC_FSL check, so that we
1404	 * also disable coreint if the MPIC node doesn't have
1405	 * an "fsl,mpic" compatible at all.  This will be the case
1406	 * with device trees generated by older versions of QEMU.
1407	 * fsl_version will be zero if MPIC_FSL is not set.
1408	 */
1409	if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT))
 
1410		ppc_md.get_irq = mpic_get_irq;
 
1411
1412	/* Reset */
1413
1414	/* When using a device-node, reset requests are only honored if the MPIC
1415	 * is allowed to reset.
1416	 */
1417	if (!(mpic->flags & MPIC_NO_RESET)) {
1418		printk(KERN_DEBUG "mpic: Resetting\n");
1419		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1420			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1421			   | MPIC_GREG_GCONF_RESET);
1422		while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1423		       & MPIC_GREG_GCONF_RESET)
1424			mb();
1425	}
1426
1427	/* CoreInt */
1428	if (mpic->flags & MPIC_ENABLE_COREINT)
1429		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1430			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1431			   | MPIC_GREG_GCONF_COREINT);
1432
1433	if (mpic->flags & MPIC_ENABLE_MCK)
1434		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1435			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1436			   | MPIC_GREG_GCONF_MCK);
1437
1438	/*
1439	 * The MPIC driver will crash if there are more cores than we
1440	 * can initialize, so we may as well catch that problem here.
1441	 */
1442	BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1443
1444	/* Map the per-CPU registers */
1445	for_each_possible_cpu(i) {
1446		unsigned int cpu = get_hard_smp_processor_id(i);
1447
1448		mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1449			 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1450			 0x1000);
1451	}
1452
1453	/*
1454	 * Read feature register.  For non-ISU MPICs, num sources as well. On
1455	 * ISU MPICs, sources are counted as ISUs are added
1456	 */
1457	greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1458
1459	/*
1460	 * By default, the last source number comes from the MPIC, but the
1461	 * device-tree and board support code can override it on buggy hw.
1462	 * If we get passed an isu_size (multi-isu MPIC) then we use that
1463	 * as a default instead of the value read from the HW.
1464	 */
1465	last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1466				>> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1467	if (isu_size)
1468		last_irq = isu_size  * MPIC_MAX_ISU - 1;
1469	of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1470	if (irq_count)
1471		last_irq = irq_count - 1;
1472
1473	/* Initialize main ISU if none provided */
1474	if (!isu_size) {
1475		isu_size = last_irq + 1;
1476		mpic->num_sources = isu_size;
1477		mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1478				MPIC_INFO(IRQ_BASE),
1479				MPIC_INFO(IRQ_STRIDE) * isu_size);
1480	}
1481
1482	mpic->isu_size = isu_size;
1483	mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1484	mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1485
1486	mpic->irqhost = irq_domain_add_linear(mpic->node,
1487				       intvec_top,
1488				       &mpic_host_ops, mpic);
1489
1490	/*
1491	 * FIXME: The code leaks the MPIC object and mappings here; this
1492	 * is very unlikely to fail but it ought to be fixed anyways.
1493	 */
1494	if (mpic->irqhost == NULL)
1495		return NULL;
1496
1497	/* Display version */
1498	switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1499	case 1:
1500		vers = "1.0";
1501		break;
1502	case 2:
1503		vers = "1.2";
1504		break;
1505	case 3:
1506		vers = "1.3";
1507		break;
1508	default:
1509		vers = "<unknown>";
1510		break;
1511	}
1512	printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1513	       " max %d CPUs\n",
1514	       name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1515	printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1516	       mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1517
1518	mpic->next = mpics;
1519	mpics = mpic;
1520
1521	if (!(mpic->flags & MPIC_SECONDARY)) {
1522		mpic_primary = mpic;
1523		irq_set_default_host(mpic->irqhost);
1524	}
1525
1526	return mpic;
1527
1528err_of_node_put:
1529	of_node_put(node);
1530	return NULL;
1531}
1532
1533void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1534			    phys_addr_t paddr)
1535{
1536	unsigned int isu_first = isu_num * mpic->isu_size;
1537
1538	BUG_ON(isu_num >= MPIC_MAX_ISU);
1539
1540	mpic_map(mpic,
1541		 paddr, &mpic->isus[isu_num], 0,
1542		 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1543
1544	if ((isu_first + mpic->isu_size) > mpic->num_sources)
1545		mpic->num_sources = isu_first + mpic->isu_size;
1546}
1547
1548void __init mpic_init(struct mpic *mpic)
1549{
1550	int i, cpu;
1551	int num_timers = 4;
1552
1553	BUG_ON(mpic->num_sources == 0);
1554
1555	printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1556
1557	/* Set current processor priority to max */
1558	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1559
1560	if (mpic->flags & MPIC_FSL) {
1561		u32 version = fsl_mpic_get_version(mpic);
1562
1563		/*
1564		 * Timer group B is present at the latest in MPIC 3.1 (e.g.
1565		 * mpc8536).  It is not present in MPIC 2.0 (e.g. mpc8544).
1566		 * I don't know about the status of intermediate versions (or
1567		 * whether they even exist).
1568		 */
1569		if (version >= 0x0301)
1570			num_timers = 8;
1571	}
1572
1573	/* Initialize timers to our reserved vectors and mask them for now */
1574	for (i = 0; i < num_timers; i++) {
1575		unsigned int offset = mpic_tm_offset(mpic, i);
1576
1577		mpic_write(mpic->tmregs,
1578			   offset + MPIC_INFO(TIMER_DESTINATION),
1579			   1 << hard_smp_processor_id());
1580		mpic_write(mpic->tmregs,
1581			   offset + MPIC_INFO(TIMER_VECTOR_PRI),
1582			   MPIC_VECPRI_MASK |
1583			   (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1584			   (mpic->timer_vecs[0] + i));
1585	}
1586
1587	/* Initialize IPIs to our reserved vectors and mark them disabled for now */
1588	mpic_test_broken_ipi(mpic);
1589	for (i = 0; i < 4; i++) {
1590		mpic_ipi_write(i,
1591			       MPIC_VECPRI_MASK |
1592			       (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1593			       (mpic->ipi_vecs[0] + i));
1594	}
1595
1596	/* Do the HT PIC fixups on U3 broken mpic */
1597	DBG("MPIC flags: %x\n", mpic->flags);
1598	if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1599		mpic_scan_ht_pics(mpic);
1600		mpic_u3msi_init(mpic);
1601	}
1602
1603	mpic_pasemi_msi_init(mpic);
1604
1605	cpu = mpic_processor_id(mpic);
1606
1607	if (!(mpic->flags & MPIC_NO_RESET)) {
1608		for (i = 0; i < mpic->num_sources; i++) {
1609			/* start with vector = source number, and masked */
1610			u32 vecpri = MPIC_VECPRI_MASK | i |
1611				(8 << MPIC_VECPRI_PRIORITY_SHIFT);
1612
1613			/* check if protected */
1614			if (mpic->protected && test_bit(i, mpic->protected))
1615				continue;
1616			/* init hw */
1617			mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1618			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1619		}
1620	}
1621
1622	/* Init spurious vector */
1623	mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1624
1625	/* Disable 8259 passthrough, if supported */
1626	if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1627		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1628			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1629			   | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1630
1631	if (mpic->flags & MPIC_NO_BIAS)
1632		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1633			mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1634			| MPIC_GREG_GCONF_NO_BIAS);
1635
1636	/* Set current processor priority to 0 */
1637	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1638
1639#ifdef CONFIG_PM
1640	/* allocate memory to save mpic state */
1641	mpic->save_data = kmalloc_array(mpic->num_sources,
1642				        sizeof(*mpic->save_data),
1643				        GFP_KERNEL);
1644	BUG_ON(mpic->save_data == NULL);
1645#endif
1646
1647	/* Check if this MPIC is chained from a parent interrupt controller */
1648	if (mpic->flags & MPIC_SECONDARY) {
1649		int virq = irq_of_parse_and_map(mpic->node, 0);
1650		if (virq) {
1651			printk(KERN_INFO "%pOF: hooking up to IRQ %d\n",
1652					mpic->node, virq);
1653			irq_set_handler_data(virq, mpic);
1654			irq_set_chained_handler(virq, &mpic_cascade);
1655		}
1656	}
1657
1658	/* FSL mpic error interrupt initialization */
1659	if (mpic->flags & MPIC_FSL_HAS_EIMR)
1660		mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1661}
1662
1663void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1664{
1665	struct mpic *mpic = mpic_find(irq);
1666	unsigned int src = virq_to_hw(irq);
1667	unsigned long flags;
1668	u32 reg;
1669
1670	if (!mpic)
1671		return;
1672
1673	raw_spin_lock_irqsave(&mpic_lock, flags);
1674	if (mpic_is_ipi(mpic, src)) {
1675		reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1676			~MPIC_VECPRI_PRIORITY_MASK;
1677		mpic_ipi_write(src - mpic->ipi_vecs[0],
1678			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1679	} else if (mpic_is_tm(mpic, src)) {
1680		reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1681			~MPIC_VECPRI_PRIORITY_MASK;
1682		mpic_tm_write(src - mpic->timer_vecs[0],
1683			      reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1684	} else {
1685		reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1686			& ~MPIC_VECPRI_PRIORITY_MASK;
1687		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1688			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1689	}
1690	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1691}
1692
1693void mpic_setup_this_cpu(void)
1694{
1695#ifdef CONFIG_SMP
1696	struct mpic *mpic = mpic_primary;
1697	unsigned long flags;
1698	u32 msk = 1 << hard_smp_processor_id();
1699	unsigned int i;
1700
1701	BUG_ON(mpic == NULL);
1702
1703	DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1704
1705	raw_spin_lock_irqsave(&mpic_lock, flags);
1706
1707 	/* let the mpic know we want intrs. default affinity is 0xffffffff
1708	 * until changed via /proc. That's how it's done on x86. If we want
1709	 * it differently, then we should make sure we also change the default
1710	 * values of irq_desc[].affinity in irq.c.
1711 	 */
1712	if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
1713	 	for (i = 0; i < mpic->num_sources ; i++)
1714			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1715				mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1716	}
1717
1718	/* Set current processor priority to 0 */
1719	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1720
1721	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1722#endif /* CONFIG_SMP */
1723}
1724
1725int mpic_cpu_get_priority(void)
1726{
1727	struct mpic *mpic = mpic_primary;
1728
1729	return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1730}
1731
1732void mpic_cpu_set_priority(int prio)
1733{
1734	struct mpic *mpic = mpic_primary;
1735
1736	prio &= MPIC_CPU_TASKPRI_MASK;
1737	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1738}
1739
1740void mpic_teardown_this_cpu(int secondary)
1741{
1742	struct mpic *mpic = mpic_primary;
1743	unsigned long flags;
1744	u32 msk = 1 << hard_smp_processor_id();
1745	unsigned int i;
1746
1747	BUG_ON(mpic == NULL);
1748
1749	DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1750	raw_spin_lock_irqsave(&mpic_lock, flags);
1751
1752	/* let the mpic know we don't want intrs.  */
1753	for (i = 0; i < mpic->num_sources ; i++)
1754		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1755			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1756
1757	/* Set current processor priority to max */
1758	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1759	/* We need to EOI the IPI since not all platforms reset the MPIC
1760	 * on boot and new interrupts wouldn't get delivered otherwise.
1761	 */
1762	mpic_eoi(mpic);
1763
1764	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1765}
1766
1767
1768static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1769{
1770	u32 src;
1771
1772	src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1773#ifdef DEBUG_LOW
1774	DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1775#endif
1776	if (unlikely(src == mpic->spurious_vec)) {
1777		if (mpic->flags & MPIC_SPV_EOI)
1778			mpic_eoi(mpic);
1779		return 0;
1780	}
1781	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1782		printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1783				   mpic->name, (int)src);
1784		mpic_eoi(mpic);
1785		return 0;
1786	}
1787
1788	return irq_linear_revmap(mpic->irqhost, src);
1789}
1790
1791unsigned int mpic_get_one_irq(struct mpic *mpic)
1792{
1793	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1794}
1795
1796unsigned int mpic_get_irq(void)
1797{
1798	struct mpic *mpic = mpic_primary;
1799
1800	BUG_ON(mpic == NULL);
1801
1802	return mpic_get_one_irq(mpic);
1803}
1804
1805unsigned int mpic_get_coreint_irq(void)
1806{
1807#ifdef CONFIG_BOOKE
1808	struct mpic *mpic = mpic_primary;
1809	u32 src;
1810
1811	BUG_ON(mpic == NULL);
1812
1813	src = mfspr(SPRN_EPR);
1814
1815	if (unlikely(src == mpic->spurious_vec)) {
1816		if (mpic->flags & MPIC_SPV_EOI)
1817			mpic_eoi(mpic);
1818		return 0;
1819	}
1820	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1821		printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1822				   mpic->name, (int)src);
1823		return 0;
1824	}
1825
1826	return irq_linear_revmap(mpic->irqhost, src);
1827#else
1828	return 0;
1829#endif
1830}
1831
1832unsigned int mpic_get_mcirq(void)
1833{
1834	struct mpic *mpic = mpic_primary;
1835
1836	BUG_ON(mpic == NULL);
1837
1838	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1839}
1840
1841#ifdef CONFIG_SMP
1842void __init mpic_request_ipis(void)
1843{
1844	struct mpic *mpic = mpic_primary;
1845	int i;
1846	BUG_ON(mpic == NULL);
1847
1848	printk(KERN_INFO "mpic: requesting IPIs...\n");
1849
1850	for (i = 0; i < 4; i++) {
1851		unsigned int vipi = irq_create_mapping(mpic->irqhost,
1852						       mpic->ipi_vecs[0] + i);
1853		if (!vipi) {
1854			printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1855			continue;
1856		}
1857		smp_request_message_ipi(vipi, i);
1858	}
1859}
1860
1861void smp_mpic_message_pass(int cpu, int msg)
1862{
1863	struct mpic *mpic = mpic_primary;
1864	u32 physmask;
1865
1866	BUG_ON(mpic == NULL);
1867
1868	/* make sure we're sending something that translates to an IPI */
1869	if ((unsigned int)msg > 3) {
1870		printk("SMP %d: smp_message_pass: unknown msg %d\n",
1871		       smp_processor_id(), msg);
1872		return;
1873	}
1874
1875#ifdef DEBUG_IPI
1876	DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1877#endif
1878
1879	physmask = 1 << get_hard_smp_processor_id(cpu);
1880
1881	mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1882		       msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1883}
1884
1885void __init smp_mpic_probe(void)
1886{
1887	int nr_cpus;
1888
1889	DBG("smp_mpic_probe()...\n");
1890
1891	nr_cpus = num_possible_cpus();
1892
1893	DBG("nr_cpus: %d\n", nr_cpus);
1894
1895	if (nr_cpus > 1)
1896		mpic_request_ipis();
1897}
1898
1899void smp_mpic_setup_cpu(int cpu)
1900{
1901	mpic_setup_this_cpu();
1902}
1903
1904void mpic_reset_core(int cpu)
1905{
1906	struct mpic *mpic = mpic_primary;
1907	u32 pir;
1908	int cpuid = get_hard_smp_processor_id(cpu);
1909	int i;
1910
1911	/* Set target bit for core reset */
1912	pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1913	pir |= (1 << cpuid);
1914	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1915	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1916
1917	/* Restore target bit after reset complete */
1918	pir &= ~(1 << cpuid);
1919	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1920	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1921
1922	/* Perform 15 EOI on each reset core to clear pending interrupts.
1923	 * This is required for FSL CoreNet based devices */
1924	if (mpic->flags & MPIC_FSL) {
1925		for (i = 0; i < 15; i++) {
1926			_mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1927				      MPIC_CPU_EOI, 0);
1928		}
1929	}
1930}
1931#endif /* CONFIG_SMP */
1932
1933#ifdef CONFIG_PM
1934static void mpic_suspend_one(struct mpic *mpic)
1935{
1936	int i;
1937
1938	for (i = 0; i < mpic->num_sources; i++) {
1939		mpic->save_data[i].vecprio =
1940			mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1941		mpic->save_data[i].dest =
1942			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1943	}
1944}
1945
1946static int mpic_suspend(void)
1947{
1948	struct mpic *mpic = mpics;
1949
1950	while (mpic) {
1951		mpic_suspend_one(mpic);
1952		mpic = mpic->next;
1953	}
1954
1955	return 0;
1956}
1957
1958static void mpic_resume_one(struct mpic *mpic)
1959{
1960	int i;
1961
1962	for (i = 0; i < mpic->num_sources; i++) {
1963		mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1964			       mpic->save_data[i].vecprio);
1965		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1966			       mpic->save_data[i].dest);
1967
1968#ifdef CONFIG_MPIC_U3_HT_IRQS
1969	if (mpic->fixups) {
1970		struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1971
1972		if (fixup->base) {
1973			/* we use the lowest bit in an inverted meaning */
1974			if ((mpic->save_data[i].fixup_data & 1) == 0)
1975				continue;
1976
1977			/* Enable and configure */
1978			writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1979
1980			writel(mpic->save_data[i].fixup_data & ~1,
1981			       fixup->base + 4);
1982		}
1983	}
1984#endif
1985	} /* end for loop */
1986}
1987
1988static void mpic_resume(void)
1989{
1990	struct mpic *mpic = mpics;
1991
1992	while (mpic) {
1993		mpic_resume_one(mpic);
1994		mpic = mpic->next;
1995	}
1996}
1997
1998static struct syscore_ops mpic_syscore_ops = {
1999	.resume = mpic_resume,
2000	.suspend = mpic_suspend,
2001};
2002
2003static int mpic_init_sys(void)
2004{
2005	int rc;
2006
2007	register_syscore_ops(&mpic_syscore_ops);
2008	rc = subsys_system_register(&mpic_subsys, NULL);
2009	if (rc) {
2010		unregister_syscore_ops(&mpic_syscore_ops);
2011		pr_err("mpic: Failed to register subsystem!\n");
2012		return rc;
2013	}
2014
2015	return 0;
2016}
2017
2018device_initcall(mpic_init_sys);
2019#endif