1# SPDX-License-Identifier: GPL-2.0-only
   2config ARM64
   3	def_bool y
   4	select ACPI_APMT if ACPI
   5	select ACPI_CCA_REQUIRED if ACPI
   6	select ACPI_GENERIC_GSI if ACPI
   7	select ACPI_GTDT if ACPI
   8	select ACPI_IORT if ACPI
   9	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
  10	select ACPI_MCFG if (ACPI && PCI)
  11	select ACPI_SPCR_TABLE if ACPI
  12	select ACPI_PPTT if ACPI
  13	select ARCH_HAS_DEBUG_WX
  14	select ARCH_BINFMT_ELF_EXTRA_PHDRS
  15	select ARCH_BINFMT_ELF_STATE
  16	select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
  17	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
  18	select ARCH_ENABLE_MEMORY_HOTPLUG
  19	select ARCH_ENABLE_MEMORY_HOTREMOVE
  20	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
  21	select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
  22	select ARCH_HAS_CACHE_LINE_SIZE
  23	select ARCH_HAS_CURRENT_STACK_POINTER
  24	select ARCH_HAS_DEBUG_VIRTUAL
  25	select ARCH_HAS_DEBUG_VM_PGTABLE
  26	select ARCH_HAS_DMA_PREP_COHERENT
  27	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
  28	select ARCH_HAS_FAST_MULTIPLIER
  29	select ARCH_HAS_FORTIFY_SOURCE
  30	select ARCH_HAS_GCOV_PROFILE_ALL
  31	select ARCH_HAS_GIGANTIC_PAGE
  32	select ARCH_HAS_KCOV
  33	select ARCH_HAS_KEEPINITRD
  34	select ARCH_HAS_MEMBARRIER_SYNC_CORE
  35	select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
  36	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
  37	select ARCH_HAS_PTE_DEVMAP
  38	select ARCH_HAS_PTE_SPECIAL
  39	select ARCH_HAS_HW_PTE_YOUNG
  40	select ARCH_HAS_SETUP_DMA_OPS
  41	select ARCH_HAS_SET_DIRECT_MAP
  42	select ARCH_HAS_SET_MEMORY
  43	select ARCH_STACKWALK
  44	select ARCH_HAS_STRICT_KERNEL_RWX
  45	select ARCH_HAS_STRICT_MODULE_RWX
  46	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
  47	select ARCH_HAS_SYNC_DMA_FOR_CPU
  48	select ARCH_HAS_SYSCALL_WRAPPER
  49	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
  50	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  51	select ARCH_HAS_ZONE_DMA_SET if EXPERT
  52	select ARCH_HAVE_ELF_PROT
  53	select ARCH_HAVE_NMI_SAFE_CMPXCHG
  54	select ARCH_HAVE_TRACE_MMIO_ACCESS
  55	select ARCH_INLINE_READ_LOCK if !PREEMPTION
  56	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
  57	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
  58	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
  59	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
  60	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
  61	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
  62	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
  63	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
  64	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
  65	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
  66	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
  67	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
  68	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
  69	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
  70	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
  71	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
  72	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
  73	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
  74	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
  75	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
  76	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
  77	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
  78	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
  79	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
  80	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
  81	select ARCH_KEEP_MEMBLOCK
  82	select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
  83	select ARCH_USE_CMPXCHG_LOCKREF
  84	select ARCH_USE_GNU_PROPERTY
  85	select ARCH_USE_MEMTEST
  86	select ARCH_USE_QUEUED_RWLOCKS
  87	select ARCH_USE_QUEUED_SPINLOCKS
  88	select ARCH_USE_SYM_ANNOTATIONS
  89	select ARCH_SUPPORTS_DEBUG_PAGEALLOC
  90	select ARCH_SUPPORTS_HUGETLBFS
  91	select ARCH_SUPPORTS_MEMORY_FAILURE
  92	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
  93	select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
  94	select ARCH_SUPPORTS_LTO_CLANG_THIN
  95	select ARCH_SUPPORTS_CFI_CLANG
  96	select ARCH_SUPPORTS_ATOMIC_RMW
  97	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
  98	select ARCH_SUPPORTS_NUMA_BALANCING
  99	select ARCH_SUPPORTS_PAGE_TABLE_CHECK
 100	select ARCH_SUPPORTS_PER_VMA_LOCK
 101	select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH
 102	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
 103	select ARCH_WANT_DEFAULT_BPF_JIT
 104	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
 105	select ARCH_WANT_FRAME_POINTERS
 106	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
 107	select ARCH_WANT_LD_ORPHAN_WARN
 108	select ARCH_WANTS_NO_INSTR
 109	select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
 110	select ARCH_HAS_UBSAN_SANITIZE_ALL
 111	select ARM_AMBA
 112	select ARM_ARCH_TIMER
 113	select ARM_GIC
 114	select AUDIT_ARCH_COMPAT_GENERIC
 115	select ARM_GIC_V2M if PCI
 116	select ARM_GIC_V3
 117	select ARM_GIC_V3_ITS if PCI
 118	select ARM_PSCI_FW
 119	select BUILDTIME_TABLE_SORT
 120	select CLONE_BACKWARDS
 121	select COMMON_CLK
 122	select CPU_PM if (SUSPEND || CPU_IDLE)
 123	select CRC32
 124	select DCACHE_WORD_ACCESS
 125	select DYNAMIC_FTRACE if FUNCTION_TRACER
 126	select DMA_BOUNCE_UNALIGNED_KMALLOC
 127	select DMA_DIRECT_REMAP
 128	select EDAC_SUPPORT
 129	select FRAME_POINTER
 130	select FUNCTION_ALIGNMENT_4B
 131	select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
 132	select GENERIC_ALLOCATOR
 133	select GENERIC_ARCH_TOPOLOGY
 
 134	select GENERIC_CLOCKEVENTS_BROADCAST
 135	select GENERIC_CPU_AUTOPROBE
 136	select GENERIC_CPU_DEVICES
 137	select GENERIC_CPU_VULNERABILITIES
 138	select GENERIC_EARLY_IOREMAP
 139	select GENERIC_IDLE_POLL_SETUP
 140	select GENERIC_IOREMAP
 141	select GENERIC_IRQ_IPI
 142	select GENERIC_IRQ_PROBE
 143	select GENERIC_IRQ_SHOW
 144	select GENERIC_IRQ_SHOW_LEVEL
 145	select GENERIC_LIB_DEVMEM_IS_ALLOWED
 146	select GENERIC_PCI_IOMAP
 147	select GENERIC_PTDUMP
 148	select GENERIC_SCHED_CLOCK
 149	select GENERIC_SMP_IDLE_THREAD
 
 
 150	select GENERIC_TIME_VSYSCALL
 151	select GENERIC_GETTIMEOFDAY
 152	select GENERIC_VDSO_TIME_NS
 153	select HARDIRQS_SW_RESEND
 154	select HAS_IOPORT
 155	select HAVE_MOVE_PMD
 156	select HAVE_MOVE_PUD
 157	select HAVE_PCI
 158	select HAVE_ACPI_APEI if (ACPI && EFI)
 159	select HAVE_ALIGNED_STRUCT_PAGE
 160	select HAVE_ARCH_AUDITSYSCALL
 161	select HAVE_ARCH_BITREVERSE
 162	select HAVE_ARCH_COMPILER_H
 163	select HAVE_ARCH_HUGE_VMALLOC
 164	select HAVE_ARCH_HUGE_VMAP
 165	select HAVE_ARCH_JUMP_LABEL
 166	select HAVE_ARCH_JUMP_LABEL_RELATIVE
 167	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
 168	select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
 169	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
 170	select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
 171	# Some instrumentation may be unsound, hence EXPERT
 172	select HAVE_ARCH_KCSAN if EXPERT
 173	select HAVE_ARCH_KFENCE
 174	select HAVE_ARCH_KGDB
 175	select HAVE_ARCH_MMAP_RND_BITS
 176	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
 177	select HAVE_ARCH_PREL32_RELOCATIONS
 178	select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
 179	select HAVE_ARCH_SECCOMP_FILTER
 180	select HAVE_ARCH_STACKLEAK
 181	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
 182	select HAVE_ARCH_TRACEHOOK
 183	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
 184	select HAVE_ARCH_VMAP_STACK
 185	select HAVE_ARM_SMCCC
 186	select HAVE_ASM_MODVERSIONS
 187	select HAVE_EBPF_JIT
 188	select HAVE_C_RECORDMCOUNT
 
 189	select HAVE_CMPXCHG_DOUBLE
 190	select HAVE_CMPXCHG_LOCAL
 191	select HAVE_CONTEXT_TRACKING_USER
 
 192	select HAVE_DEBUG_KMEMLEAK
 
 193	select HAVE_DMA_CONTIGUOUS
 194	select HAVE_DYNAMIC_FTRACE
 195	select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
 196		if $(cc-option,-fpatchable-function-entry=2)
 197	select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \
 198		if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS
 199	select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
 200		if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
 201		    !CC_OPTIMIZE_FOR_SIZE)
 202	select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
 203		if DYNAMIC_FTRACE_WITH_ARGS
 204	select HAVE_SAMPLE_FTRACE_DIRECT
 205	select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
 206	select HAVE_EFFICIENT_UNALIGNED_ACCESS
 207	select HAVE_FAST_GUP
 208	select HAVE_FTRACE_MCOUNT_RECORD
 209	select HAVE_FUNCTION_TRACER
 210	select HAVE_FUNCTION_ERROR_INJECTION
 211	select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER
 212	select HAVE_FUNCTION_GRAPH_TRACER
 213	select HAVE_GCC_PLUGINS
 214	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \
 215		HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI
 216	select HAVE_HW_BREAKPOINT if PERF_EVENTS
 217	select HAVE_IOREMAP_PROT
 218	select HAVE_IRQ_TIME_ACCOUNTING
 219	select HAVE_KVM
 220	select HAVE_MOD_ARCH_SPECIFIC
 221	select HAVE_NMI
 
 222	select HAVE_PERF_EVENTS
 223	select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI
 224	select HAVE_PERF_REGS
 225	select HAVE_PERF_USER_STACK_DUMP
 226	select HAVE_PREEMPT_DYNAMIC_KEY
 227	select HAVE_REGS_AND_STACK_ACCESS_API
 228	select HAVE_POSIX_CPU_TIMERS_TASK_WORK
 229	select HAVE_FUNCTION_ARG_ACCESS_API
 230	select MMU_GATHER_RCU_TABLE_FREE
 231	select HAVE_RSEQ
 232	select HAVE_STACKPROTECTOR
 233	select HAVE_SYSCALL_TRACEPOINTS
 234	select HAVE_KPROBES
 235	select HAVE_KRETPROBES
 236	select HAVE_GENERIC_VDSO
 237	select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
 238	select IRQ_DOMAIN
 239	select IRQ_FORCED_THREADING
 240	select KASAN_VMALLOC if KASAN
 241	select LOCK_MM_AND_FIND_VMA
 242	select MODULES_USE_ELF_RELA
 243	select NEED_DMA_MAP_STATE
 244	select NEED_SG_DMA_LENGTH
 245	select OF
 246	select OF_EARLY_FLATTREE
 247	select PCI_DOMAINS_GENERIC if PCI
 248	select PCI_ECAM if (ACPI && PCI)
 249	select PCI_SYSCALL if PCI
 250	select POWER_RESET
 251	select POWER_SUPPLY
 
 252	select SPARSE_IRQ
 253	select SWIOTLB
 254	select SYSCTL_EXCEPTION_TRACE
 255	select THREAD_INFO_IN_TASK
 256	select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
 257	select TRACE_IRQFLAGS_SUPPORT
 258	select TRACE_IRQFLAGS_NMI_SUPPORT
 259	select HAVE_SOFTIRQ_ON_OWN_STACK
 260	help
 261	  ARM 64-bit (AArch64) Linux support.
 262
 263config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
 264	def_bool CC_IS_CLANG
 265	# https://github.com/ClangBuiltLinux/linux/issues/1507
 266	depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
 267	select HAVE_DYNAMIC_FTRACE_WITH_ARGS
 268
 269config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
 270	def_bool CC_IS_GCC
 271	depends on $(cc-option,-fpatchable-function-entry=2)
 272	select HAVE_DYNAMIC_FTRACE_WITH_ARGS
 273
 274config 64BIT
 275	def_bool y
 276
 
 
 
 277config MMU
 278	def_bool y
 279
 280config ARM64_PAGE_SHIFT
 281	int
 282	default 16 if ARM64_64K_PAGES
 283	default 14 if ARM64_16K_PAGES
 284	default 12
 285
 286config ARM64_CONT_PTE_SHIFT
 287	int
 288	default 5 if ARM64_64K_PAGES
 289	default 7 if ARM64_16K_PAGES
 290	default 4
 291
 292config ARM64_CONT_PMD_SHIFT
 293	int
 294	default 5 if ARM64_64K_PAGES
 295	default 5 if ARM64_16K_PAGES
 296	default 4
 297
 298config ARCH_MMAP_RND_BITS_MIN
 299	default 14 if ARM64_64K_PAGES
 300	default 16 if ARM64_16K_PAGES
 301	default 18
 302
 303# max bits determined by the following formula:
 304#  VA_BITS - PAGE_SHIFT - 3
 305config ARCH_MMAP_RND_BITS_MAX
 306	default 19 if ARM64_VA_BITS=36
 307	default 24 if ARM64_VA_BITS=39
 308	default 27 if ARM64_VA_BITS=42
 309	default 30 if ARM64_VA_BITS=47
 310	default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
 311	default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
 312	default 33 if ARM64_VA_BITS=48
 313	default 14 if ARM64_64K_PAGES
 314	default 16 if ARM64_16K_PAGES
 315	default 18
 316
 317config ARCH_MMAP_RND_COMPAT_BITS_MIN
 318	default 7 if ARM64_64K_PAGES
 319	default 9 if ARM64_16K_PAGES
 320	default 11
 321
 322config ARCH_MMAP_RND_COMPAT_BITS_MAX
 323	default 16
 324
 325config NO_IOPORT_MAP
 326	def_bool y if !PCI
 327
 328config STACKTRACE_SUPPORT
 329	def_bool y
 330
 331config ILLEGAL_POINTER_VALUE
 332	hex
 333	default 0xdead000000000000
 334
 335config LOCKDEP_SUPPORT
 336	def_bool y
 337
 
 
 
 
 
 
 338config GENERIC_BUG
 339	def_bool y
 340	depends on BUG
 341
 342config GENERIC_BUG_RELATIVE_POINTERS
 343	def_bool y
 344	depends on GENERIC_BUG
 345
 346config GENERIC_HWEIGHT
 347	def_bool y
 348
 349config GENERIC_CSUM
 350	def_bool y
 351
 352config GENERIC_CALIBRATE_DELAY
 353	def_bool y
 354
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 355config SMP
 356	def_bool y
 357
 
 
 
 
 
 
 358config KERNEL_MODE_NEON
 359	def_bool y
 360
 361config FIX_EARLYCON_MEM
 362	def_bool y
 363
 364config PGTABLE_LEVELS
 365	int
 366	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
 367	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 368	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
 369	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 370	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
 371	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
 372
 373config ARCH_SUPPORTS_UPROBES
 374	def_bool y
 375
 376config ARCH_PROC_KCORE_TEXT
 377	def_bool y
 378
 379config BROKEN_GAS_INST
 380	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
 381
 382config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
 383	bool
 384	# Clang's __builtin_return_adddress() strips the PAC since 12.0.0
 385	# https://reviews.llvm.org/D75044
 386	default y if CC_IS_CLANG && (CLANG_VERSION >= 120000)
 387	# GCC's __builtin_return_address() strips the PAC since 11.1.0,
 388	# and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
 389	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891
 390	default y if CC_IS_GCC && (GCC_VERSION >= 110100)
 391	default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
 392	default y if CC_IS_GCC && (GCC_VERSION >=  90400) && (GCC_VERSION < 100000)
 393	default y if CC_IS_GCC && (GCC_VERSION >=  80500) && (GCC_VERSION <  90000)
 394	default n
 395
 396config KASAN_SHADOW_OFFSET
 397	hex
 398	depends on KASAN_GENERIC || KASAN_SW_TAGS
 399	default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
 400	default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
 401	default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
 402	default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
 403	default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
 404	default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
 405	default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
 406	default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
 407	default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
 408	default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
 409	default 0xffffffffffffffff
 410
 411config UNWIND_TABLES
 412	bool
 413
 414source "arch/arm64/Kconfig.platforms"
 415
 416menu "Kernel Features"
 417
 418menu "ARM errata workarounds via the alternatives framework"
 419
 420config AMPERE_ERRATUM_AC03_CPU_38
 421        bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"
 422	default y
 423	help
 424	  This option adds an alternative code sequence to work around Ampere
 425	  erratum AC03_CPU_38 on AmpereOne.
 
 426
 427	  The affected design reports FEAT_HAFDBS as not implemented in
 428	  ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0
 429	  as required by the architecture. The unadvertised HAFDBS
 430	  implementation suffers from an additional erratum where hardware
 431	  A/D updates can occur after a PTE has been marked invalid.
 432
 433	  The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
 434	  which avoids enabling unadvertised hardware Access Flag management
 435	  at stage-2.
 436
 437	  If unsure, say Y.
 
 438
 439config ARM64_WORKAROUND_CLEAN_CACHE
 440	bool
 
 
 
 
 
 441
 442config ARM64_ERRATUM_826319
 443	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 444	default y
 445	select ARM64_WORKAROUND_CLEAN_CACHE
 446	help
 447	  This option adds an alternative code sequence to work around ARM
 448	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 449	  AXI master interface and an L2 cache.
 450
 451	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 452	  and is unable to accept a certain write via this interface, it will
 453	  not progress on read data presented on the read data channel and the
 454	  system can deadlock.
 455
 456	  The workaround promotes data cache clean instructions to
 457	  data cache clean-and-invalidate.
 458	  Please note that this does not necessarily enable the workaround,
 459	  as it depends on the alternative framework, which will only patch
 460	  the kernel if an affected CPU is detected.
 461
 462	  If unsure, say Y.
 463
 464config ARM64_ERRATUM_827319
 465	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 466	default y
 467	select ARM64_WORKAROUND_CLEAN_CACHE
 468	help
 469	  This option adds an alternative code sequence to work around ARM
 470	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 471	  master interface and an L2 cache.
 472
 473	  Under certain conditions this erratum can cause a clean line eviction
 474	  to occur at the same time as another transaction to the same address
 475	  on the AMBA 5 CHI interface, which can cause data corruption if the
 476	  interconnect reorders the two transactions.
 477
 478	  The workaround promotes data cache clean instructions to
 479	  data cache clean-and-invalidate.
 480	  Please note that this does not necessarily enable the workaround,
 481	  as it depends on the alternative framework, which will only patch
 482	  the kernel if an affected CPU is detected.
 483
 484	  If unsure, say Y.
 485
 486config ARM64_ERRATUM_824069
 487	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 488	default y
 489	select ARM64_WORKAROUND_CLEAN_CACHE
 490	help
 491	  This option adds an alternative code sequence to work around ARM
 492	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 493	  to a coherent interconnect.
 494
 495	  If a Cortex-A53 processor is executing a store or prefetch for
 496	  write instruction at the same time as a processor in another
 497	  cluster is executing a cache maintenance operation to the same
 498	  address, then this erratum might cause a clean cache line to be
 499	  incorrectly marked as dirty.
 500
 501	  The workaround promotes data cache clean instructions to
 502	  data cache clean-and-invalidate.
 503	  Please note that this option does not necessarily enable the
 504	  workaround, as it depends on the alternative framework, which will
 505	  only patch the kernel if an affected CPU is detected.
 506
 507	  If unsure, say Y.
 508
 509config ARM64_ERRATUM_819472
 510	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 511	default y
 512	select ARM64_WORKAROUND_CLEAN_CACHE
 513	help
 514	  This option adds an alternative code sequence to work around ARM
 515	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 516	  present when it is connected to a coherent interconnect.
 517
 518	  If the processor is executing a load and store exclusive sequence at
 519	  the same time as a processor in another cluster is executing a cache
 520	  maintenance operation to the same address, then this erratum might
 521	  cause data corruption.
 522
 523	  The workaround promotes data cache clean instructions to
 524	  data cache clean-and-invalidate.
 525	  Please note that this does not necessarily enable the workaround,
 526	  as it depends on the alternative framework, which will only patch
 527	  the kernel if an affected CPU is detected.
 528
 529	  If unsure, say Y.
 530
 531config ARM64_ERRATUM_832075
 532	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 533	default y
 534	help
 535	  This option adds an alternative code sequence to work around ARM
 536	  erratum 832075 on Cortex-A57 parts up to r1p2.
 537
 538	  Affected Cortex-A57 parts might deadlock when exclusive load/store
 539	  instructions to Write-Back memory are mixed with Device loads.
 540
 541	  The workaround is to promote device loads to use Load-Acquire
 542	  semantics.
 543	  Please note that this does not necessarily enable the workaround,
 544	  as it depends on the alternative framework, which will only patch
 545	  the kernel if an affected CPU is detected.
 546
 547	  If unsure, say Y.
 548
 549config ARM64_ERRATUM_834220
 550	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
 551	depends on KVM
 552	default y
 553	help
 554	  This option adds an alternative code sequence to work around ARM
 555	  erratum 834220 on Cortex-A57 parts up to r1p2.
 556
 557	  Affected Cortex-A57 parts might report a Stage 2 translation
 558	  fault as the result of a Stage 1 fault for load crossing a
 559	  page boundary when there is a permission or device memory
 560	  alignment fault at Stage 1 and a translation fault at Stage 2.
 561
 562	  The workaround is to verify that the Stage 1 translation
 563	  doesn't generate a fault before handling the Stage 2 fault.
 564	  Please note that this does not necessarily enable the workaround,
 565	  as it depends on the alternative framework, which will only patch
 566	  the kernel if an affected CPU is detected.
 567
 568	  If unsure, say Y.
 569
 570config ARM64_ERRATUM_1742098
 571	bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
 572	depends on COMPAT
 573	default y
 574	help
 575	  This option removes the AES hwcap for aarch32 user-space to
 576	  workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
 577
 578	  Affected parts may corrupt the AES state if an interrupt is
 579	  taken between a pair of AES instructions. These instructions
 580	  are only present if the cryptography extensions are present.
 581	  All software should have a fallback implementation for CPUs
 582	  that don't implement the cryptography extensions.
 583
 584	  If unsure, say Y.
 585
 586config ARM64_ERRATUM_845719
 587	bool "Cortex-A53: 845719: a load might read incorrect data"
 588	depends on COMPAT
 589	default y
 590	help
 591	  This option adds an alternative code sequence to work around ARM
 592	  erratum 845719 on Cortex-A53 parts up to r0p4.
 593
 594	  When running a compat (AArch32) userspace on an affected Cortex-A53
 595	  part, a load at EL0 from a virtual address that matches the bottom 32
 596	  bits of the virtual address used by a recent load at (AArch64) EL1
 597	  might return incorrect data.
 598
 599	  The workaround is to write the contextidr_el1 register on exception
 600	  return to a 32-bit task.
 601	  Please note that this does not necessarily enable the workaround,
 602	  as it depends on the alternative framework, which will only patch
 603	  the kernel if an affected CPU is detected.
 604
 605	  If unsure, say Y.
 606
 607config ARM64_ERRATUM_843419
 608	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
 609	default y
 
 610	help
 611	  This option links the kernel with '--fix-cortex-a53-843419' and
 612	  enables PLT support to replace certain ADRP instructions, which can
 613	  cause subsequent memory accesses to use an incorrect address on
 614	  Cortex-A53 parts up to r0p4.
 615
 616	  If unsure, say Y.
 617
 618config ARM64_LD_HAS_FIX_ERRATUM_843419
 619	def_bool $(ld-option,--fix-cortex-a53-843419)
 620
 621config ARM64_ERRATUM_1024718
 622	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
 623	default y
 624	help
 625	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
 626
 627	  Affected Cortex-A55 cores (all revisions) could cause incorrect
 628	  update of the hardware dirty bit when the DBM/AP bits are updated
 629	  without a break-before-make. The workaround is to disable the usage
 630	  of hardware DBM locally on the affected cores. CPUs not affected by
 631	  this erratum will continue to use the feature.
 632
 633	  If unsure, say Y.
 634
 635config ARM64_ERRATUM_1418040
 636	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
 637	default y
 638	depends on COMPAT
 639	help
 640	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
 641	  errata 1188873 and 1418040.
 642
 643	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
 644	  cause register corruption when accessing the timer registers
 645	  from AArch32 userspace.
 646
 647	  If unsure, say Y.
 648
 649config ARM64_WORKAROUND_SPECULATIVE_AT
 650	bool
 651
 652config ARM64_ERRATUM_1165522
 653	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 654	default y
 655	select ARM64_WORKAROUND_SPECULATIVE_AT
 656	help
 657	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
 658
 659	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
 660	  corrupted TLBs by speculating an AT instruction during a guest
 661	  context switch.
 662
 663	  If unsure, say Y.
 664
 665config ARM64_ERRATUM_1319367
 666	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 667	default y
 668	select ARM64_WORKAROUND_SPECULATIVE_AT
 669	help
 670	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
 671	  and A72 erratum 1319367
 672
 673	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
 674	  speculating an AT instruction during a guest context switch.
 675
 676	  If unsure, say Y.
 677
 678config ARM64_ERRATUM_1530923
 679	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
 680	default y
 681	select ARM64_WORKAROUND_SPECULATIVE_AT
 682	help
 683	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
 684
 685	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
 686	  corrupted TLBs by speculating an AT instruction during a guest
 687	  context switch.
 688
 689	  If unsure, say Y.
 690
 691config ARM64_WORKAROUND_REPEAT_TLBI
 692	bool
 693
 694config ARM64_ERRATUM_2441007
 695	bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
 696	default y
 697	select ARM64_WORKAROUND_REPEAT_TLBI
 698	help
 699	  This option adds a workaround for ARM Cortex-A55 erratum #2441007.
 700
 701	  Under very rare circumstances, affected Cortex-A55 CPUs
 702	  may not handle a race between a break-before-make sequence on one
 703	  CPU, and another CPU accessing the same page. This could allow a
 704	  store to a page that has been unmapped.
 705
 706	  Work around this by adding the affected CPUs to the list that needs
 707	  TLB sequences to be done twice.
 708
 709	  If unsure, say Y.
 710
 711config ARM64_ERRATUM_1286807
 712	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
 713	default y
 714	select ARM64_WORKAROUND_REPEAT_TLBI
 715	help
 716	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
 717
 718	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
 719	  address for a cacheable mapping of a location is being
 720	  accessed by a core while another core is remapping the virtual
 721	  address to a new physical page using the recommended
 722	  break-before-make sequence, then under very rare circumstances
 723	  TLBI+DSB completes before a read using the translation being
 724	  invalidated has been observed by other observers. The
 725	  workaround repeats the TLBI+DSB operation.
 726
 727config ARM64_ERRATUM_1463225
 728	bool "Cortex-A76: Software Step might prevent interrupt recognition"
 729	default y
 730	help
 731	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
 732
 733	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
 734	  of a system call instruction (SVC) can prevent recognition of
 735	  subsequent interrupts when software stepping is disabled in the
 736	  exception handler of the system call and either kernel debugging
 737	  is enabled or VHE is in use.
 738
 739	  Work around the erratum by triggering a dummy step exception
 740	  when handling a system call from a task that is being stepped
 741	  in a VHE configuration of the kernel.
 742
 743	  If unsure, say Y.
 744
 745config ARM64_ERRATUM_1542419
 746	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
 747	default y
 748	help
 749	  This option adds a workaround for ARM Neoverse-N1 erratum
 750	  1542419.
 751
 752	  Affected Neoverse-N1 cores could execute a stale instruction when
 753	  modified by another CPU. The workaround depends on a firmware
 754	  counterpart.
 755
 756	  Workaround the issue by hiding the DIC feature from EL0. This
 757	  forces user-space to perform cache maintenance.
 758
 759	  If unsure, say Y.
 760
 761config ARM64_ERRATUM_1508412
 762	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
 763	default y
 764	help
 765	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
 766
 767	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
 768	  of a store-exclusive or read of PAR_EL1 and a load with device or
 769	  non-cacheable memory attributes. The workaround depends on a firmware
 770	  counterpart.
 771
 772	  KVM guests must also have the workaround implemented or they can
 773	  deadlock the system.
 774
 775	  Work around the issue by inserting DMB SY barriers around PAR_EL1
 776	  register reads and warning KVM users. The DMB barrier is sufficient
 777	  to prevent a speculative PAR_EL1 read.
 778
 779	  If unsure, say Y.
 780
 781config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
 782	bool
 783
 784config ARM64_ERRATUM_2051678
 785	bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
 786	default y
 787	help
 788	  This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
 789	  Affected Cortex-A510 might not respect the ordering rules for
 790	  hardware update of the page table's dirty bit. The workaround
 791	  is to not enable the feature on affected CPUs.
 792
 793	  If unsure, say Y.
 794
 795config ARM64_ERRATUM_2077057
 796	bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
 797	default y
 798	help
 799	  This option adds the workaround for ARM Cortex-A510 erratum 2077057.
 800	  Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
 801	  expected, but a Pointer Authentication trap is taken instead. The
 802	  erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
 803	  EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
 804
 805	  This can only happen when EL2 is stepping EL1.
 806
 807	  When these conditions occur, the SPSR_EL2 value is unchanged from the
 808	  previous guest entry, and can be restored from the in-memory copy.
 809
 810	  If unsure, say Y.
 811
 812config ARM64_ERRATUM_2658417
 813	bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
 814	default y
 815	help
 816	  This option adds the workaround for ARM Cortex-A510 erratum 2658417.
 817	  Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
 818	  BFMMLA or VMMLA instructions in rare circumstances when a pair of
 819	  A510 CPUs are using shared neon hardware. As the sharing is not
 820	  discoverable by the kernel, hide the BF16 HWCAP to indicate that
 821	  user-space should not be using these instructions.
 822
 823	  If unsure, say Y.
 824
 825config ARM64_ERRATUM_2119858
 826	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
 827	default y
 828	depends on CORESIGHT_TRBE
 829	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
 830	help
 831	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
 832
 833	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
 834	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
 835	  the event of a WRAP event.
 836
 837	  Work around the issue by always making sure we move the TRBPTR_EL1 by
 838	  256 bytes before enabling the buffer and filling the first 256 bytes of
 839	  the buffer with ETM ignore packets upon disabling.
 840
 841	  If unsure, say Y.
 842
 843config ARM64_ERRATUM_2139208
 844	bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
 845	default y
 846	depends on CORESIGHT_TRBE
 847	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
 848	help
 849	  This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
 850
 851	  Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
 852	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
 853	  the event of a WRAP event.
 854
 855	  Work around the issue by always making sure we move the TRBPTR_EL1 by
 856	  256 bytes before enabling the buffer and filling the first 256 bytes of
 857	  the buffer with ETM ignore packets upon disabling.
 858
 859	  If unsure, say Y.
 860
 861config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
 862	bool
 863
 864config ARM64_ERRATUM_2054223
 865	bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
 866	default y
 867	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
 868	help
 869	  Enable workaround for ARM Cortex-A710 erratum 2054223
 870
 871	  Affected cores may fail to flush the trace data on a TSB instruction, when
 872	  the PE is in trace prohibited state. This will cause losing a few bytes
 873	  of the trace cached.
 874
 875	  Workaround is to issue two TSB consecutively on affected cores.
 876
 877	  If unsure, say Y.
 878
 879config ARM64_ERRATUM_2067961
 880	bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
 881	default y
 882	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
 883	help
 884	  Enable workaround for ARM Neoverse-N2 erratum 2067961
 885
 886	  Affected cores may fail to flush the trace data on a TSB instruction, when
 887	  the PE is in trace prohibited state. This will cause losing a few bytes
 888	  of the trace cached.
 889
 890	  Workaround is to issue two TSB consecutively on affected cores.
 891
 892	  If unsure, say Y.
 893
 894config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
 895	bool
 896
 897config ARM64_ERRATUM_2253138
 898	bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
 899	depends on CORESIGHT_TRBE
 900	default y
 901	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
 902	help
 903	  This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
 904
 905	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
 906	  for TRBE. Under some conditions, the TRBE might generate a write to the next
 907	  virtually addressed page following the last page of the TRBE address space
 908	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
 909
 910	  Work around this in the driver by always making sure that there is a
 911	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
 912
 913	  If unsure, say Y.
 914
 915config ARM64_ERRATUM_2224489
 916	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
 917	depends on CORESIGHT_TRBE
 918	default y
 919	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
 920	help
 921	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
 922
 923	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
 924	  for TRBE. Under some conditions, the TRBE might generate a write to the next
 925	  virtually addressed page following the last page of the TRBE address space
 926	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
 927
 928	  Work around this in the driver by always making sure that there is a
 929	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
 930
 931	  If unsure, say Y.
 932
 933config ARM64_ERRATUM_2441009
 934	bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
 935	default y
 936	select ARM64_WORKAROUND_REPEAT_TLBI
 937	help
 938	  This option adds a workaround for ARM Cortex-A510 erratum #2441009.
 939
 940	  Under very rare circumstances, affected Cortex-A510 CPUs
 941	  may not handle a race between a break-before-make sequence on one
 942	  CPU, and another CPU accessing the same page. This could allow a
 943	  store to a page that has been unmapped.
 944
 945	  Work around this by adding the affected CPUs to the list that needs
 946	  TLB sequences to be done twice.
 947
 948	  If unsure, say Y.
 949
 950config ARM64_ERRATUM_2064142
 951	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
 952	depends on CORESIGHT_TRBE
 953	default y
 954	help
 955	  This option adds the workaround for ARM Cortex-A510 erratum 2064142.
 956
 957	  Affected Cortex-A510 core might fail to write into system registers after the
 958	  TRBE has been disabled. Under some conditions after the TRBE has been disabled
 959	  writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
 960	  and TRBTRG_EL1 will be ignored and will not be effected.
 961
 962	  Work around this in the driver by executing TSB CSYNC and DSB after collection
 963	  is stopped and before performing a system register write to one of the affected
 964	  registers.
 965
 966	  If unsure, say Y.
 967
 968config ARM64_ERRATUM_2038923
 969	bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
 970	depends on CORESIGHT_TRBE
 971	default y
 972	help
 973	  This option adds the workaround for ARM Cortex-A510 erratum 2038923.
 974
 975	  Affected Cortex-A510 core might cause an inconsistent view on whether trace is
 976	  prohibited within the CPU. As a result, the trace buffer or trace buffer state
 977	  might be corrupted. This happens after TRBE buffer has been enabled by setting
 978	  TRBLIMITR_EL1.E, followed by just a single context synchronization event before
 979	  execution changes from a context, in which trace is prohibited to one where it
 980	  isn't, or vice versa. In these mentioned conditions, the view of whether trace
 981	  is prohibited is inconsistent between parts of the CPU, and the trace buffer or
 982	  the trace buffer state might be corrupted.
 983
 984	  Work around this in the driver by preventing an inconsistent view of whether the
 985	  trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
 986	  change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
 987	  two ISB instructions if no ERET is to take place.
 988
 989	  If unsure, say Y.
 990
 991config ARM64_ERRATUM_1902691
 992	bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
 993	depends on CORESIGHT_TRBE
 994	default y
 995	help
 996	  This option adds the workaround for ARM Cortex-A510 erratum 1902691.
 997
 998	  Affected Cortex-A510 core might cause trace data corruption, when being written
 999	  into the memory. Effectively TRBE is broken and hence cannot be used to capture
1000	  trace data.
1001
1002	  Work around this problem in the driver by just preventing TRBE initialization on
1003	  affected cpus. The firmware must have disabled the access to TRBE for the kernel
1004	  on such implementations. This will cover the kernel for any firmware that doesn't
1005	  do this already.
1006
1007	  If unsure, say Y.
1008
1009config ARM64_ERRATUM_2457168
1010	bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1011	depends on ARM64_AMU_EXTN
1012	default y
1013	help
1014	  This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1015
1016	  The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
1017	  as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1018	  incorrectly giving a significantly higher output value.
1019
1020	  Work around this problem by returning 0 when reading the affected counter in
1021	  key locations that results in disabling all users of this counter. This effect
1022	  is the same to firmware disabling affected counters.
1023
1024	  If unsure, say Y.
1025
1026config ARM64_ERRATUM_2645198
1027	bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1028	default y
1029	help
1030	  This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1031
1032	  If a Cortex-A715 cpu sees a page mapping permissions change from executable
1033	  to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1034	  next instruction abort caused by permission fault.
1035
1036	  Only user-space does executable to non-executable permission transition via
1037	  mprotect() system call. Workaround the problem by doing a break-before-make
1038	  TLB invalidation, for all changes to executable user space mappings.
1039
1040	  If unsure, say Y.
1041
1042config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1043	bool
1044
1045config ARM64_ERRATUM_2966298
1046	bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1047	select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1048	default y
1049	help
1050	  This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1051
1052	  On an affected Cortex-A520 core, a speculatively executed unprivileged
1053	  load might leak data from a privileged level via a cache side channel.
1054
1055	  Work around this problem by executing a TLBI before returning to EL0.
1056
1057	  If unsure, say Y.
1058
1059config ARM64_ERRATUM_3117295
1060	bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1061	select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1062	default y
1063	help
1064	  This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1065
1066	  On an affected Cortex-A510 core, a speculatively executed unprivileged
1067	  load might leak data from a privileged level via a cache side channel.
1068
1069	  Work around this problem by executing a TLBI before returning to EL0.
1070
1071	  If unsure, say Y.
1072
1073config CAVIUM_ERRATUM_22375
1074	bool "Cavium erratum 22375, 24313"
1075	default y
1076	help
1077	  Enable workaround for errata 22375 and 24313.
1078
1079	  This implements two gicv3-its errata workarounds for ThunderX. Both
1080	  with a small impact affecting only ITS table allocation.
1081
1082	    erratum 22375: only alloc 8MB table size
1083	    erratum 24313: ignore memory access type
1084
1085	  The fixes are in ITS initialization and basically ignore memory access
1086	  type and table size provided by the TYPER and BASER registers.
1087
1088	  If unsure, say Y.
1089
1090config CAVIUM_ERRATUM_23144
1091	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1092	depends on NUMA
1093	default y
1094	help
1095	  ITS SYNC command hang for cross node io and collections/cpu mapping.
1096
1097	  If unsure, say Y.
1098
1099config CAVIUM_ERRATUM_23154
1100	bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1101	default y
1102	help
1103	  The ThunderX GICv3 implementation requires a modified version for
1104	  reading the IAR status to ensure data synchronization
1105	  (access to icc_iar1_el1 is not sync'ed before and after).
1106
1107	  It also suffers from erratum 38545 (also present on Marvell's
1108	  OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1109	  spuriously presented to the CPU interface.
1110
1111	  If unsure, say Y.
1112
1113config CAVIUM_ERRATUM_27456
1114	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1115	default y
1116	help
1117	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1118	  instructions may cause the icache to become corrupted if it
1119	  contains data for a non-current ASID.  The fix is to
1120	  invalidate the icache when changing the mm context.
1121
1122	  If unsure, say Y.
1123
1124config CAVIUM_ERRATUM_30115
1125	bool "Cavium erratum 30115: Guest may disable interrupts in host"
1126	default y
1127	help
1128	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1129	  1.2, and T83 Pass 1.0, KVM guest execution may disable
1130	  interrupts in host. Trapping both GICv3 group-0 and group-1
1131	  accesses sidesteps the issue.
1132
1133	  If unsure, say Y.
1134
1135config CAVIUM_TX2_ERRATUM_219
1136	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1137	default y
1138	help
1139	  On Cavium ThunderX2, a load, store or prefetch instruction between a
1140	  TTBR update and the corresponding context synchronizing operation can
1141	  cause a spurious Data Abort to be delivered to any hardware thread in
1142	  the CPU core.
1143
1144	  Work around the issue by avoiding the problematic code sequence and
1145	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1146	  trap handler performs the corresponding register access, skips the
1147	  instruction and ensures context synchronization by virtue of the
1148	  exception return.
1149
1150	  If unsure, say Y.
1151
1152config FUJITSU_ERRATUM_010001
1153	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1154	default y
1155	help
1156	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1157	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1158	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
1159	  This fault occurs under a specific hardware condition when a
1160	  load/store instruction performs an address translation using:
1161	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1162	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1163	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1164	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1165
1166	  The workaround is to ensure these bits are clear in TCR_ELx.
1167	  The workaround only affects the Fujitsu-A64FX.
1168
1169	  If unsure, say Y.
1170
1171config HISILICON_ERRATUM_161600802
1172	bool "Hip07 161600802: Erroneous redistributor VLPI base"
1173	default y
1174	help
1175	  The HiSilicon Hip07 SoC uses the wrong redistributor base
1176	  when issued ITS commands such as VMOVP and VMAPP, and requires
1177	  a 128kB offset to be applied to the target address in this commands.
1178
1179	  If unsure, say Y.
1180
1181config QCOM_FALKOR_ERRATUM_1003
1182	bool "Falkor E1003: Incorrect translation due to ASID change"
1183	default y
1184	help
1185	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1186	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1187	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
1188	  then only for entries in the walk cache, since the leaf translation
1189	  is unchanged. Work around the erratum by invalidating the walk cache
1190	  entries for the trampoline before entering the kernel proper.
1191
1192config QCOM_FALKOR_ERRATUM_1009
1193	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1194	default y
1195	select ARM64_WORKAROUND_REPEAT_TLBI
1196	help
1197	  On Falkor v1, the CPU may prematurely complete a DSB following a
1198	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1199	  one more time to fix the issue.
1200
1201	  If unsure, say Y.
1202
1203config QCOM_QDF2400_ERRATUM_0065
1204	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1205	default y
1206	help
1207	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1208	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1209	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1210
1211	  If unsure, say Y.
1212
1213config QCOM_FALKOR_ERRATUM_E1041
1214	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1215	default y
1216	help
1217	  Falkor CPU may speculatively fetch instructions from an improper
1218	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
1219	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1220
1221	  If unsure, say Y.
1222
1223config NVIDIA_CARMEL_CNP_ERRATUM
1224	bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1225	default y
1226	help
1227	  If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1228	  invalidate shared TLB entries installed by a different core, as it would
1229	  on standard ARM cores.
1230
1231	  If unsure, say Y.
1232
1233config ROCKCHIP_ERRATUM_3588001
1234	bool "Rockchip 3588001: GIC600 can not support shareability attributes"
1235	default y
1236	help
1237	  The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1238	  This means, that its sharability feature may not be used, even though it
1239	  is supported by the IP itself.
1240
1241	  If unsure, say Y.
1242
1243config SOCIONEXT_SYNQUACER_PREITS
1244	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1245	default y
1246	help
1247	  Socionext Synquacer SoCs implement a separate h/w block to generate
1248	  MSI doorbell writes with non-zero values for the device ID.
1249
1250	  If unsure, say Y.
1251
1252endmenu # "ARM errata workarounds via the alternatives framework"
1253
1254choice
1255	prompt "Page size"
1256	default ARM64_4K_PAGES
1257	help
1258	  Page size (translation granule) configuration.
1259
1260config ARM64_4K_PAGES
1261	bool "4KB"
1262	help
1263	  This feature enables 4KB pages support.
1264
1265config ARM64_16K_PAGES
1266	bool "16KB"
1267	help
1268	  The system will use 16KB pages support. AArch32 emulation
1269	  requires applications compiled with 16K (or a multiple of 16K)
1270	  aligned segments.
1271
1272config ARM64_64K_PAGES
1273	bool "64KB"
1274	help
1275	  This feature enables 64KB pages support (4KB by default)
1276	  allowing only two levels of page tables and faster TLB
1277	  look-up. AArch32 emulation requires applications compiled
1278	  with 64K aligned segments.
1279
1280endchoice
1281
1282choice
1283	prompt "Virtual address space size"
1284	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1285	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1286	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1287	help
1288	  Allows choosing one of multiple possible virtual address
1289	  space sizes. The level of translation table is determined by
1290	  a combination of page size and virtual address space size.
1291
1292config ARM64_VA_BITS_36
1293	bool "36-bit" if EXPERT
1294	depends on ARM64_16K_PAGES
1295
1296config ARM64_VA_BITS_39
1297	bool "39-bit"
1298	depends on ARM64_4K_PAGES
1299
1300config ARM64_VA_BITS_42
1301	bool "42-bit"
1302	depends on ARM64_64K_PAGES
1303
1304config ARM64_VA_BITS_47
1305	bool "47-bit"
1306	depends on ARM64_16K_PAGES
1307
1308config ARM64_VA_BITS_48
1309	bool "48-bit"
1310
1311config ARM64_VA_BITS_52
1312	bool "52-bit"
1313	depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1314	help
1315	  Enable 52-bit virtual addressing for userspace when explicitly
1316	  requested via a hint to mmap(). The kernel will also use 52-bit
1317	  virtual addresses for its own mappings (provided HW support for
1318	  this feature is available, otherwise it reverts to 48-bit).
1319
1320	  NOTE: Enabling 52-bit virtual addressing in conjunction with
1321	  ARMv8.3 Pointer Authentication will result in the PAC being
1322	  reduced from 7 bits to 3 bits, which may have a significant
1323	  impact on its susceptibility to brute-force attacks.
1324
1325	  If unsure, select 48-bit virtual addressing instead.
1326
1327endchoice
1328
1329config ARM64_FORCE_52BIT
1330	bool "Force 52-bit virtual addresses for userspace"
1331	depends on ARM64_VA_BITS_52 && EXPERT
1332	help
1333	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
1334	  to maintain compatibility with older software by providing 48-bit VAs
1335	  unless a hint is supplied to mmap.
1336
1337	  This configuration option disables the 48-bit compatibility logic, and
1338	  forces all userspace addresses to be 52-bit on HW that supports it. One
1339	  should only enable this configuration option for stress testing userspace
1340	  memory management code. If unsure say N here.
1341
1342config ARM64_VA_BITS
1343	int
1344	default 36 if ARM64_VA_BITS_36
1345	default 39 if ARM64_VA_BITS_39
1346	default 42 if ARM64_VA_BITS_42
1347	default 47 if ARM64_VA_BITS_47
1348	default 48 if ARM64_VA_BITS_48
1349	default 52 if ARM64_VA_BITS_52
1350
1351choice
1352	prompt "Physical address space size"
1353	default ARM64_PA_BITS_48
1354	help
1355	  Choose the maximum physical address range that the kernel will
1356	  support.
1357
1358config ARM64_PA_BITS_48
1359	bool "48-bit"
1360
1361config ARM64_PA_BITS_52
1362	bool "52-bit (ARMv8.2)"
1363	depends on ARM64_64K_PAGES
1364	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1365	help
1366	  Enable support for a 52-bit physical address space, introduced as
1367	  part of the ARMv8.2-LPA extension.
1368
1369	  With this enabled, the kernel will also continue to work on CPUs that
1370	  do not support ARMv8.2-LPA, but with some added memory overhead (and
1371	  minor performance overhead).
1372
1373endchoice
1374
1375config ARM64_PA_BITS
1376	int
1377	default 48 if ARM64_PA_BITS_48
1378	default 52 if ARM64_PA_BITS_52
1379
1380choice
1381	prompt "Endianness"
1382	default CPU_LITTLE_ENDIAN
1383	help
1384	  Select the endianness of data accesses performed by the CPU. Userspace
1385	  applications will need to be compiled and linked for the endianness
1386	  that is selected here.
1387
1388config CPU_BIG_ENDIAN
1389	bool "Build big-endian kernel"
1390	depends on !LD_IS_LLD || LLD_VERSION >= 130000
1391	# https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1392	depends on AS_IS_GNU || AS_VERSION >= 150000
1393	help
1394	  Say Y if you plan on running a kernel with a big-endian userspace.
1395
1396config CPU_LITTLE_ENDIAN
1397	bool "Build little-endian kernel"
1398	help
1399	  Say Y if you plan on running a kernel with a little-endian userspace.
1400	  This is usually the case for distributions targeting arm64.
1401
1402endchoice
1403
1404config SCHED_MC
1405	bool "Multi-core scheduler support"
1406	help
1407	  Multi-core scheduler support improves the CPU scheduler's decision
1408	  making when dealing with multi-core CPU chips at a cost of slightly
1409	  increased overhead in some places. If unsure say N here.
1410
1411config SCHED_CLUSTER
1412	bool "Cluster scheduler support"
1413	help
1414	  Cluster scheduler support improves the CPU scheduler's decision
1415	  making when dealing with machines that have clusters of CPUs.
1416	  Cluster usually means a couple of CPUs which are placed closely
1417	  by sharing mid-level caches, last-level cache tags or internal
1418	  busses.
1419
1420config SCHED_SMT
1421	bool "SMT scheduler support"
1422	help
1423	  Improves the CPU scheduler's decision making when dealing with
1424	  MultiThreading at a cost of slightly increased overhead in some
1425	  places. If unsure say N here.
1426
1427config NR_CPUS
1428	int "Maximum number of CPUs (2-4096)"
1429	range 2 4096
1430	default "256"
 
1431
1432config HOTPLUG_CPU
1433	bool "Support for hot-pluggable CPUs"
1434	select GENERIC_IRQ_MIGRATION
1435	help
1436	  Say Y here to experiment with turning CPUs off and on.  CPUs
1437	  can be controlled through /sys/devices/system/cpu.
1438
1439# Common NUMA Features
1440config NUMA
1441	bool "NUMA Memory Allocation and Scheduler Support"
1442	select GENERIC_ARCH_NUMA
1443	select ACPI_NUMA if ACPI
1444	select OF_NUMA
1445	select HAVE_SETUP_PER_CPU_AREA
1446	select NEED_PER_CPU_EMBED_FIRST_CHUNK
1447	select NEED_PER_CPU_PAGE_FIRST_CHUNK
1448	select USE_PERCPU_NUMA_NODE_ID
1449	help
1450	  Enable NUMA (Non-Uniform Memory Access) support.
1451
1452	  The kernel will try to allocate memory used by a CPU on the
1453	  local memory of the CPU and add some more
1454	  NUMA awareness to the kernel.
1455
1456config NODES_SHIFT
1457	int "Maximum NUMA Nodes (as a power of 2)"
1458	range 1 10
1459	default "4"
1460	depends on NUMA
1461	help
1462	  Specify the maximum number of NUMA Nodes available on the target
1463	  system.  Increases memory reserved to accommodate various tables.
1464
1465source "kernel/Kconfig.hz"
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1466
1467config ARCH_SPARSEMEM_ENABLE
1468	def_bool y
1469	select SPARSEMEM_VMEMMAP_ENABLE
1470	select SPARSEMEM_VMEMMAP
 
 
 
 
 
 
 
 
1471
1472config HW_PERF_EVENTS
1473	def_bool y
1474	depends on ARM_PMU
1475
1476# Supported by clang >= 7.0 or GCC >= 12.0.0
1477config CC_HAVE_SHADOW_CALL_STACK
1478	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1479
1480config PARAVIRT
1481	bool "Enable paravirtualization code"
1482	help
1483	  This changes the kernel so it can modify itself when it is run
1484	  under a hypervisor, potentially improving performance significantly
1485	  over full virtualization.
1486
1487config PARAVIRT_TIME_ACCOUNTING
1488	bool "Paravirtual steal time accounting"
1489	select PARAVIRT
 
1490	help
1491	  Select this option to enable fine granularity task steal time
1492	  accounting. Time spent executing other tasks in parallel with
1493	  the current vCPU is discounted from the vCPU power. To account for
1494	  that, there can be a small performance impact.
1495
1496	  If in doubt, say N here.
1497
1498config ARCH_SUPPORTS_KEXEC
1499	def_bool PM_SLEEP_SMP
1500
1501config ARCH_SUPPORTS_KEXEC_FILE
1502	def_bool y
1503
1504config ARCH_SELECTS_KEXEC_FILE
1505	def_bool y
1506	depends on KEXEC_FILE
1507	select HAVE_IMA_KEXEC if IMA
1508
1509config ARCH_SUPPORTS_KEXEC_SIG
1510	def_bool y
1511
1512config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG
1513	def_bool y
1514
1515config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG
1516	def_bool y
1517
1518config ARCH_SUPPORTS_CRASH_DUMP
1519	def_bool y
1520
1521config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
1522	def_bool CRASH_CORE
1523
1524config TRANS_TABLE
1525	def_bool y
1526	depends on HIBERNATION || KEXEC_CORE
1527
1528config XEN_DOM0
1529	def_bool y
1530	depends on XEN
1531
1532config XEN
1533	bool "Xen guest support on ARM64"
1534	depends on ARM64 && OF
1535	select SWIOTLB_XEN
1536	select PARAVIRT
1537	help
1538	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1539
1540# include/linux/mmzone.h requires the following to be true:
1541#
1542#   MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1543#
1544# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1545#
1546#     | SECTION_SIZE_BITS |  PAGE_SHIFT  |  max MAX_PAGE_ORDER  |  default MAX_PAGE_ORDER |
1547# ----+-------------------+--------------+----------------------+-------------------------+
1548# 4K  |       27          |      12      |       15             |         10              |
1549# 16K |       27          |      14      |       13             |         11              |
1550# 64K |       29          |      16      |       13             |         13              |
1551config ARCH_FORCE_MAX_ORDER
1552	int
1553	default "13" if ARM64_64K_PAGES
1554	default "11" if ARM64_16K_PAGES
1555	default "10"
1556	help
1557	  The kernel page allocator limits the size of maximal physically
1558	  contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1559	  defines the maximal power of two of number of pages that can be
1560	  allocated as a single contiguous block. This option allows
1561	  overriding the default setting when ability to allocate very
1562	  large blocks of physically contiguous memory is required.
1563
1564	  The maximal size of allocation cannot exceed the size of the
1565	  section, so the value of MAX_PAGE_ORDER should satisfy
 
 
 
 
1566
1567	    MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1568
1569	  Don't change if unsure.
1570
1571config UNMAP_KERNEL_AT_EL0
1572	bool "Unmap kernel when running in userspace (KPTI)" if EXPERT
1573	default y
1574	help
1575	  Speculation attacks against some high-performance processors can
1576	  be used to bypass MMU permission checks and leak kernel data to
1577	  userspace. This can be defended against by unmapping the kernel
1578	  when running in userspace, mapping it back in on exception entry
1579	  via a trampoline page in the vector table.
1580
1581	  If unsure, say Y.
1582
1583config MITIGATE_SPECTRE_BRANCH_HISTORY
1584	bool "Mitigate Spectre style attacks against branch history" if EXPERT
1585	default y
1586	help
1587	  Speculation attacks against some high-performance processors can
1588	  make use of branch history to influence future speculation.
1589	  When taking an exception from user-space, a sequence of branches
1590	  or a firmware call overwrites the branch history.
1591
1592config RODATA_FULL_DEFAULT_ENABLED
1593	bool "Apply r/o permissions of VM areas also to their linear aliases"
1594	default y
1595	help
1596	  Apply read-only attributes of VM areas to the linear alias of
1597	  the backing pages as well. This prevents code or read-only data
1598	  from being modified (inadvertently or intentionally) via another
1599	  mapping of the same memory page. This additional enhancement can
1600	  be turned off at runtime by passing rodata=[off|on] (and turned on
1601	  with rodata=full if this option is set to 'n')
1602
1603	  This requires the linear region to be mapped down to pages,
1604	  which may adversely affect performance in some cases.
1605
1606config ARM64_SW_TTBR0_PAN
1607	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1608	help
1609	  Enabling this option prevents the kernel from accessing
1610	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1611	  zeroed area and reserved ASID. The user access routines
1612	  restore the valid TTBR0_EL1 temporarily.
1613
1614config ARM64_TAGGED_ADDR_ABI
1615	bool "Enable the tagged user addresses syscall ABI"
1616	default y
1617	help
1618	  When this option is enabled, user applications can opt in to a
1619	  relaxed ABI via prctl() allowing tagged addresses to be passed
1620	  to system calls as pointer arguments. For details, see
1621	  Documentation/arch/arm64/tagged-address-abi.rst.
1622
1623menuconfig COMPAT
1624	bool "Kernel support for 32-bit EL0"
1625	depends on ARM64_4K_PAGES || EXPERT
1626	select HAVE_UID16
1627	select OLD_SIGSUSPEND3
1628	select COMPAT_OLD_SIGACTION
1629	help
1630	  This option enables support for a 32-bit EL0 running under a 64-bit
1631	  kernel at EL1. AArch32-specific components such as system calls,
1632	  the user helper functions, VFP support and the ptrace interface are
1633	  handled appropriately by the kernel.
1634
1635	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1636	  that you will only be able to execute AArch32 binaries that were compiled
1637	  with page size aligned segments.
1638
1639	  If you want to execute 32-bit userspace applications, say Y.
1640
1641if COMPAT
1642
1643config KUSER_HELPERS
1644	bool "Enable kuser helpers page for 32-bit applications"
1645	default y
1646	help
1647	  Warning: disabling this option may break 32-bit user programs.
1648
1649	  Provide kuser helpers to compat tasks. The kernel provides
1650	  helper code to userspace in read only form at a fixed location
1651	  to allow userspace to be independent of the CPU type fitted to
1652	  the system. This permits binaries to be run on ARMv4 through
1653	  to ARMv8 without modification.
1654
1655	  See Documentation/arch/arm/kernel_user_helpers.rst for details.
1656
1657	  However, the fixed address nature of these helpers can be used
1658	  by ROP (return orientated programming) authors when creating
1659	  exploits.
1660
1661	  If all of the binaries and libraries which run on your platform
1662	  are built specifically for your platform, and make no use of
1663	  these helpers, then you can turn this option off to hinder
1664	  such exploits. However, in that case, if a binary or library
1665	  relying on those helpers is run, it will not function correctly.
1666
1667	  Say N here only if you are absolutely certain that you do not
1668	  need these helpers; otherwise, the safe option is to say Y.
1669
1670config COMPAT_VDSO
1671	bool "Enable vDSO for 32-bit applications"
1672	depends on !CPU_BIG_ENDIAN
1673	depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1674	select GENERIC_COMPAT_VDSO
1675	default y
1676	help
1677	  Place in the process address space of 32-bit applications an
1678	  ELF shared object providing fast implementations of gettimeofday
1679	  and clock_gettime.
1680
1681	  You must have a 32-bit build of glibc 2.22 or later for programs
1682	  to seamlessly take advantage of this.
1683
1684config THUMB2_COMPAT_VDSO
1685	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1686	depends on COMPAT_VDSO
1687	default y
1688	help
1689	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1690	  otherwise with '-marm'.
 
 
 
 
 
 
 
1691
1692config COMPAT_ALIGNMENT_FIXUPS
1693	bool "Fix up misaligned multi-word loads and stores in user space"
1694
1695menuconfig ARMV8_DEPRECATED
1696	bool "Emulate deprecated/obsolete ARMv8 instructions"
 
1697	depends on SYSCTL
1698	help
1699	  Legacy software support may require certain instructions
1700	  that have been deprecated or obsoleted in the architecture.
1701
1702	  Enable this config to enable selective emulation of these
1703	  features.
1704
1705	  If unsure, say Y
1706
1707if ARMV8_DEPRECATED
1708
1709config SWP_EMULATION
1710	bool "Emulate SWP/SWPB instructions"
1711	help
1712	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1713	  they are always undefined. Say Y here to enable software
1714	  emulation of these instructions for userspace using LDXR/STXR.
1715	  This feature can be controlled at runtime with the abi.swp
1716	  sysctl which is disabled by default.
1717
1718	  In some older versions of glibc [<=2.8] SWP is used during futex
1719	  trylock() operations with the assumption that the code will not
1720	  be preempted. This invalid assumption may be more likely to fail
1721	  with SWP emulation enabled, leading to deadlock of the user
1722	  application.
1723
1724	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1725	  on an external transaction monitoring block called a global
1726	  monitor to maintain update atomicity. If your system does not
1727	  implement a global monitor, this option can cause programs that
1728	  perform SWP operations to uncached memory to deadlock.
1729
1730	  If unsure, say Y
1731
1732config CP15_BARRIER_EMULATION
1733	bool "Emulate CP15 Barrier instructions"
1734	help
1735	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1736	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1737	  strongly recommended to use the ISB, DSB, and DMB
1738	  instructions instead.
1739
1740	  Say Y here to enable software emulation of these
1741	  instructions for AArch32 userspace code. When this option is
1742	  enabled, CP15 barrier usage is traced which can help
1743	  identify software that needs updating. This feature can be
1744	  controlled at runtime with the abi.cp15_barrier sysctl.
1745
1746	  If unsure, say Y
1747
1748config SETEND_EMULATION
1749	bool "Emulate SETEND instruction"
1750	help
1751	  The SETEND instruction alters the data-endianness of the
1752	  AArch32 EL0, and is deprecated in ARMv8.
1753
1754	  Say Y here to enable software emulation of the instruction
1755	  for AArch32 userspace code. This feature can be controlled
1756	  at runtime with the abi.setend sysctl.
1757
1758	  Note: All the cpus on the system must have mixed endian support at EL0
1759	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1760	  endian - is hotplugged in after this feature has been enabled, there could
1761	  be unexpected results in the applications.
1762
1763	  If unsure, say Y
1764endif # ARMV8_DEPRECATED
1765
1766endif # COMPAT
 
 
 
 
 
 
1767
1768menu "ARMv8.1 architectural features"
1769
1770config ARM64_HW_AFDBM
1771	bool "Support for hardware updates of the Access and Dirty page flags"
1772	default y
1773	help
1774	  The ARMv8.1 architecture extensions introduce support for
1775	  hardware updates of the access and dirty information in page
1776	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1777	  capable processors, accesses to pages with PTE_AF cleared will
1778	  set this bit instead of raising an access flag fault.
1779	  Similarly, writes to read-only pages with the DBM bit set will
1780	  clear the read-only bit (AP[2]) instead of raising a
1781	  permission fault.
1782
1783	  Kernels built with this configuration option enabled continue
1784	  to work on pre-ARMv8.1 hardware and the performance impact is
1785	  minimal. If unsure, say Y.
1786
1787config ARM64_PAN
1788	bool "Enable support for Privileged Access Never (PAN)"
1789	default y
1790	help
1791	  Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1792	  prevents the kernel or hypervisor from accessing user-space (EL0)
1793	  memory directly.
1794
1795	  Choosing this option will cause any unprotected (not using
1796	  copy_to_user et al) memory access to fail with a permission fault.
1797
1798	  The feature is detected at runtime, and will remain as a 'nop'
1799	  instruction if the cpu does not implement the feature.
1800
1801config AS_HAS_LSE_ATOMICS
1802	def_bool $(as-instr,.arch_extension lse)
1803
1804config ARM64_LSE_ATOMICS
1805	bool
1806	default ARM64_USE_LSE_ATOMICS
1807	depends on AS_HAS_LSE_ATOMICS
1808
1809config ARM64_USE_LSE_ATOMICS
1810	bool "Atomic instructions"
1811	default y
1812	help
1813	  As part of the Large System Extensions, ARMv8.1 introduces new
1814	  atomic instructions that are designed specifically to scale in
1815	  very large systems.
1816
1817	  Say Y here to make use of these instructions for the in-kernel
1818	  atomic routines. This incurs a small overhead on CPUs that do
1819	  not support these instructions and requires the kernel to be
1820	  built with binutils >= 2.25 in order for the new instructions
1821	  to be used.
1822
1823endmenu # "ARMv8.1 architectural features"
 
 
 
 
 
 
 
1824
1825menu "ARMv8.2 architectural features"
 
 
1826
1827config AS_HAS_ARMV8_2
1828	def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1829
1830config AS_HAS_SHA3
1831	def_bool $(as-instr,.arch armv8.2-a+sha3)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1832
1833config ARM64_PMEM
1834	bool "Enable support for persistent memory"
1835	select ARCH_HAS_PMEM_API
1836	select ARCH_HAS_UACCESS_FLUSHCACHE
1837	help
1838	  Say Y to enable support for the persistent memory API based on the
1839	  ARMv8.2 DCPoP feature.
1840
1841	  The feature is detected at runtime, and the kernel will use DC CVAC
1842	  operations if DC CVAP is not supported (following the behaviour of
1843	  DC CVAP itself if the system does not define a point of persistence).
1844
1845config ARM64_RAS_EXTN
1846	bool "Enable support for RAS CPU Extensions"
1847	default y
1848	help
1849	  CPUs that support the Reliability, Availability and Serviceability
1850	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1851	  errors, classify them and report them to software.
1852
1853	  On CPUs with these extensions system software can use additional
1854	  barriers to determine if faults are pending and read the
1855	  classification from a new set of registers.
1856
1857	  Selecting this feature will allow the kernel to use these barriers
1858	  and access the new registers if the system supports the extension.
1859	  Platform RAS features may additionally depend on firmware support.
1860
1861config ARM64_CNP
1862	bool "Enable support for Common Not Private (CNP) translations"
1863	default y
1864	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1865	help
1866	  Common Not Private (CNP) allows translation table entries to
1867	  be shared between different PEs in the same inner shareable
1868	  domain, so the hardware can use this fact to optimise the
1869	  caching of such entries in the TLB.
1870
1871	  Selecting this option allows the CNP feature to be detected
1872	  at runtime, and does not affect PEs that do not implement
1873	  this feature.
1874
1875endmenu # "ARMv8.2 architectural features"
1876
1877menu "ARMv8.3 architectural features"
1878
1879config ARM64_PTR_AUTH
1880	bool "Enable support for pointer authentication"
1881	default y
1882	help
1883	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1884	  instructions for signing and authenticating pointers against secret
1885	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1886	  and other attacks.
1887
1888	  This option enables these instructions at EL0 (i.e. for userspace).
1889	  Choosing this option will cause the kernel to initialise secret keys
1890	  for each process at exec() time, with these keys being
1891	  context-switched along with the process.
1892
1893	  The feature is detected at runtime. If the feature is not present in
1894	  hardware it will not be advertised to userspace/KVM guest nor will it
1895	  be enabled.
1896
1897	  If the feature is present on the boot CPU but not on a late CPU, then
1898	  the late CPU will be parked. Also, if the boot CPU does not have
1899	  address auth and the late CPU has then the late CPU will still boot
1900	  but with the feature disabled. On such a system, this option should
1901	  not be selected.
1902
1903config ARM64_PTR_AUTH_KERNEL
1904	bool "Use pointer authentication for kernel"
1905	default y
1906	depends on ARM64_PTR_AUTH
1907	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1908	# Modern compilers insert a .note.gnu.property section note for PAC
1909	# which is only understood by binutils starting with version 2.33.1.
1910	depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1911	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1912	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1913	help
1914	  If the compiler supports the -mbranch-protection or
1915	  -msign-return-address flag (e.g. GCC 7 or later), then this option
1916	  will cause the kernel itself to be compiled with return address
1917	  protection. In this case, and if the target hardware is known to
1918	  support pointer authentication, then CONFIG_STACKPROTECTOR can be
1919	  disabled with minimal loss of protection.
1920
1921	  This feature works with FUNCTION_GRAPH_TRACER option only if
1922	  DYNAMIC_FTRACE_WITH_ARGS is enabled.
1923
1924config CC_HAS_BRANCH_PROT_PAC_RET
1925	# GCC 9 or later, clang 8 or later
1926	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1927
1928config CC_HAS_SIGN_RETURN_ADDRESS
1929	# GCC 7, 8
1930	def_bool $(cc-option,-msign-return-address=all)
1931
1932config AS_HAS_ARMV8_3
1933	def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1934
1935config AS_HAS_CFI_NEGATE_RA_STATE
1936	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1937
1938config AS_HAS_LDAPR
1939	def_bool $(as-instr,.arch_extension rcpc)
1940
1941endmenu # "ARMv8.3 architectural features"
1942
1943menu "ARMv8.4 architectural features"
1944
1945config ARM64_AMU_EXTN
1946	bool "Enable support for the Activity Monitors Unit CPU extension"
1947	default y
1948	help
1949	  The activity monitors extension is an optional extension introduced
1950	  by the ARMv8.4 CPU architecture. This enables support for version 1
1951	  of the activity monitors architecture, AMUv1.
1952
1953	  To enable the use of this extension on CPUs that implement it, say Y.
1954
1955	  Note that for architectural reasons, firmware _must_ implement AMU
1956	  support when running on CPUs that present the activity monitors
1957	  extension. The required support is present in:
1958	    * Version 1.5 and later of the ARM Trusted Firmware
1959
1960	  For kernels that have this configuration enabled but boot with broken
1961	  firmware, you may need to say N here until the firmware is fixed.
1962	  Otherwise you may experience firmware panics or lockups when
1963	  accessing the counter registers. Even if you are not observing these
1964	  symptoms, the values returned by the register reads might not
1965	  correctly reflect reality. Most commonly, the value read will be 0,
1966	  indicating that the counter is not enabled.
1967
1968config AS_HAS_ARMV8_4
1969	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1970
1971config ARM64_TLB_RANGE
1972	bool "Enable support for tlbi range feature"
1973	default y
1974	depends on AS_HAS_ARMV8_4
1975	help
1976	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1977	  range of input addresses.
1978
1979	  The feature introduces new assembly instructions, and they were
1980	  support when binutils >= 2.30.
1981
1982endmenu # "ARMv8.4 architectural features"
1983
1984menu "ARMv8.5 architectural features"
1985
1986config AS_HAS_ARMV8_5
1987	def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1988
1989config ARM64_BTI
1990	bool "Branch Target Identification support"
1991	default y
1992	help
1993	  Branch Target Identification (part of the ARMv8.5 Extensions)
1994	  provides a mechanism to limit the set of locations to which computed
1995	  branch instructions such as BR or BLR can jump.
1996
1997	  To make use of BTI on CPUs that support it, say Y.
1998
1999	  BTI is intended to provide complementary protection to other control
2000	  flow integrity protection mechanisms, such as the Pointer
2001	  authentication mechanism provided as part of the ARMv8.3 Extensions.
2002	  For this reason, it does not make sense to enable this option without
2003	  also enabling support for pointer authentication.  Thus, when
2004	  enabling this option you should also select ARM64_PTR_AUTH=y.
2005
2006	  Userspace binaries must also be specifically compiled to make use of
2007	  this mechanism.  If you say N here or the hardware does not support
2008	  BTI, such binaries can still run, but you get no additional
2009	  enforcement of branch destinations.
2010
2011config ARM64_BTI_KERNEL
2012	bool "Use Branch Target Identification for kernel"
2013	default y
2014	depends on ARM64_BTI
2015	depends on ARM64_PTR_AUTH_KERNEL
2016	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
2017	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
2018	depends on !CC_IS_GCC || GCC_VERSION >= 100100
2019	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
2020	depends on !CC_IS_GCC
2021	# https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
2022	depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
2023	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
2024	help
2025	  Build the kernel with Branch Target Identification annotations
2026	  and enable enforcement of this for kernel code. When this option
2027	  is enabled and the system supports BTI all kernel code including
2028	  modular code must have BTI enabled.
2029
2030config CC_HAS_BRANCH_PROT_PAC_RET_BTI
2031	# GCC 9 or later, clang 8 or later
2032	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2033
2034config ARM64_E0PD
2035	bool "Enable support for E0PD"
2036	default y
2037	help
2038	  E0PD (part of the ARMv8.5 extensions) allows us to ensure
2039	  that EL0 accesses made via TTBR1 always fault in constant time,
2040	  providing similar benefits to KASLR as those provided by KPTI, but
2041	  with lower overhead and without disrupting legitimate access to
2042	  kernel memory such as SPE.
2043
2044	  This option enables E0PD for TTBR1 where available.
2045
2046config ARM64_AS_HAS_MTE
2047	# Initial support for MTE went in binutils 2.32.0, checked with
2048	# ".arch armv8.5-a+memtag" below. However, this was incomplete
2049	# as a late addition to the final architecture spec (LDGM/STGM)
2050	# is only supported in the newer 2.32.x and 2.33 binutils
2051	# versions, hence the extra "stgm" instruction check below.
2052	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2053
2054config ARM64_MTE
2055	bool "Memory Tagging Extension support"
2056	default y
2057	depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2058	depends on AS_HAS_ARMV8_5
2059	depends on AS_HAS_LSE_ATOMICS
2060	# Required for tag checking in the uaccess routines
2061	depends on ARM64_PAN
2062	select ARCH_HAS_SUBPAGE_FAULTS
2063	select ARCH_USES_HIGH_VMA_FLAGS
2064	select ARCH_USES_PG_ARCH_X
2065	help
2066	  Memory Tagging (part of the ARMv8.5 Extensions) provides
2067	  architectural support for run-time, always-on detection of
2068	  various classes of memory error to aid with software debugging
2069	  to eliminate vulnerabilities arising from memory-unsafe
2070	  languages.
2071
2072	  This option enables the support for the Memory Tagging
2073	  Extension at EL0 (i.e. for userspace).
2074
2075	  Selecting this option allows the feature to be detected at
2076	  runtime. Any secondary CPU not implementing this feature will
2077	  not be allowed a late bring-up.
2078
2079	  Userspace binaries that want to use this feature must
2080	  explicitly opt in. The mechanism for the userspace is
2081	  described in:
2082
2083	  Documentation/arch/arm64/memory-tagging-extension.rst.
2084
2085endmenu # "ARMv8.5 architectural features"
2086
2087menu "ARMv8.7 architectural features"
2088
2089config ARM64_EPAN
2090	bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2091	default y
2092	depends on ARM64_PAN
2093	help
2094	  Enhanced Privileged Access Never (EPAN) allows Privileged
2095	  Access Never to be used with Execute-only mappings.
2096
2097	  The feature is detected at runtime, and will remain disabled
2098	  if the cpu does not implement the feature.
2099endmenu # "ARMv8.7 architectural features"
2100
2101config ARM64_SVE
2102	bool "ARM Scalable Vector Extension support"
2103	default y
2104	help
2105	  The Scalable Vector Extension (SVE) is an extension to the AArch64
2106	  execution state which complements and extends the SIMD functionality
2107	  of the base architecture to support much larger vectors and to enable
2108	  additional vectorisation opportunities.
2109
2110	  To enable use of this extension on CPUs that implement it, say Y.
2111
2112	  On CPUs that support the SVE2 extensions, this option will enable
2113	  those too.
2114
2115	  Note that for architectural reasons, firmware _must_ implement SVE
2116	  support when running on SVE capable hardware.  The required support
2117	  is present in:
2118
2119	    * version 1.5 and later of the ARM Trusted Firmware
2120	    * the AArch64 boot wrapper since commit 5e1261e08abf
2121	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
2122
2123	  For other firmware implementations, consult the firmware documentation
2124	  or vendor.
2125
2126	  If you need the kernel to boot on SVE-capable hardware with broken
2127	  firmware, you may need to say N here until you get your firmware
2128	  fixed.  Otherwise, you may experience firmware panics or lockups when
2129	  booting the kernel.  If unsure and you are not observing these
2130	  symptoms, you should assume that it is safe to say Y.
2131
2132config ARM64_SME
2133	bool "ARM Scalable Matrix Extension support"
2134	default y
2135	depends on ARM64_SVE
2136	help
2137	  The Scalable Matrix Extension (SME) is an extension to the AArch64
2138	  execution state which utilises a substantial subset of the SVE
2139	  instruction set, together with the addition of new architectural
2140	  register state capable of holding two dimensional matrix tiles to
2141	  enable various matrix operations.
2142
2143config ARM64_PSEUDO_NMI
2144	bool "Support for NMI-like interrupts"
2145	select ARM_GIC_V3
2146	help
2147	  Adds support for mimicking Non-Maskable Interrupts through the use of
2148	  GIC interrupt priority. This support requires version 3 or later of
2149	  ARM GIC.
2150
2151	  This high priority configuration for interrupts needs to be
2152	  explicitly enabled by setting the kernel parameter
2153	  "irqchip.gicv3_pseudo_nmi" to 1.
2154
2155	  If unsure, say N
2156
2157if ARM64_PSEUDO_NMI
2158config ARM64_DEBUG_PRIORITY_MASKING
2159	bool "Debug interrupt priority masking"
2160	help
2161	  This adds runtime checks to functions enabling/disabling
2162	  interrupts when using priority masking. The additional checks verify
2163	  the validity of ICC_PMR_EL1 when calling concerned functions.
2164
2165	  If unsure, say N
2166endif # ARM64_PSEUDO_NMI
2167
2168config RELOCATABLE
2169	bool "Build a relocatable kernel image" if EXPERT
2170	select ARCH_HAS_RELR
2171	default y
2172	help
2173	  This builds the kernel as a Position Independent Executable (PIE),
2174	  which retains all relocation metadata required to relocate the
2175	  kernel binary at runtime to a different virtual address than the
2176	  address it was linked at.
2177	  Since AArch64 uses the RELA relocation format, this requires a
2178	  relocation pass at runtime even if the kernel is loaded at the
2179	  same address it was linked at.
2180
2181config RANDOMIZE_BASE
2182	bool "Randomize the address of the kernel image"
 
2183	select RELOCATABLE
2184	help
2185	  Randomizes the virtual address at which the kernel image is
2186	  loaded, as a security feature that deters exploit attempts
2187	  relying on knowledge of the location of kernel internals.
2188
2189	  It is the bootloader's job to provide entropy, by passing a
2190	  random u64 value in /chosen/kaslr-seed at kernel entry.
2191
2192	  When booting via the UEFI stub, it will invoke the firmware's
2193	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2194	  to the kernel proper. In addition, it will randomise the physical
2195	  location of the kernel Image as well.
2196
2197	  If unsure, say N.
2198
2199config RANDOMIZE_MODULE_REGION_FULL
2200	bool "Randomize the module region over a 2 GB range"
2201	depends on RANDOMIZE_BASE
2202	default y
2203	help
2204	  Randomizes the location of the module region inside a 2 GB window
2205	  covering the core kernel. This way, it is less likely for modules
2206	  to leak information about the location of core kernel data structures
2207	  but it does imply that function calls between modules and the core
2208	  kernel will need to be resolved via veneers in the module PLT.
2209
2210	  When this option is not set, the module region will be randomized over
2211	  a limited range that contains the [_stext, _etext] interval of the
2212	  core kernel, so branch relocations are almost always in range unless
2213	  the region is exhausted. In this particular case of region
2214	  exhaustion, modules might be able to fall back to a larger 2GB area.
2215
2216config CC_HAVE_STACKPROTECTOR_SYSREG
2217	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2218
2219config STACKPROTECTOR_PER_TASK
2220	def_bool y
2221	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2222
2223config UNWIND_PATCH_PAC_INTO_SCS
2224	bool "Enable shadow call stack dynamically using code patching"
2225	# needs Clang with https://reviews.llvm.org/D111780 incorporated
2226	depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2227	depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2228	depends on SHADOW_CALL_STACK
2229	select UNWIND_TABLES
2230	select DYNAMIC_SCS
2231
2232endmenu # "Kernel Features"
2233
2234menu "Boot options"
2235
2236config ARM64_ACPI_PARKING_PROTOCOL
2237	bool "Enable support for the ARM64 ACPI parking protocol"
2238	depends on ACPI
2239	help
2240	  Enable support for the ARM64 ACPI parking protocol. If disabled
2241	  the kernel will not allow booting through the ARM64 ACPI parking
2242	  protocol even if the corresponding data is present in the ACPI
2243	  MADT table.
2244
2245config CMDLINE
2246	string "Default kernel command string"
2247	default ""
2248	help
2249	  Provide a set of default command-line options at build time by
2250	  entering them here. As a minimum, you should specify the the
2251	  root device (e.g. root=/dev/nfs).
2252
2253choice
2254	prompt "Kernel command line type" if CMDLINE != ""
2255	default CMDLINE_FROM_BOOTLOADER
2256	help
2257	  Choose how the kernel will handle the provided default kernel
2258	  command line string.
2259
2260config CMDLINE_FROM_BOOTLOADER
2261	bool "Use bootloader kernel arguments if available"
2262	help
2263	  Uses the command-line options passed by the boot loader. If
2264	  the boot loader doesn't provide any, the default kernel command
2265	  string provided in CMDLINE will be used.
2266
2267config CMDLINE_FORCE
2268	bool "Always use the default kernel command string"
2269	help
2270	  Always use the default kernel command string, even if the boot
2271	  loader passes other arguments to the kernel.
2272	  This is useful if you cannot or don't want to change the
2273	  command-line options your boot loader passes to the kernel.
2274
2275endchoice
2276
2277config EFI_STUB
2278	bool
2279
2280config EFI
2281	bool "UEFI runtime support"
2282	depends on OF && !CPU_BIG_ENDIAN
2283	depends on KERNEL_MODE_NEON
2284	select ARCH_SUPPORTS_ACPI
2285	select LIBFDT
2286	select UCS2_STRING
2287	select EFI_PARAMS_FROM_FDT
2288	select EFI_RUNTIME_WRAPPERS
2289	select EFI_STUB
2290	select EFI_GENERIC_STUB
2291	imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2292	default y
2293	help
2294	  This option provides support for runtime services provided
2295	  by UEFI firmware (such as non-volatile variables, realtime
2296	  clock, and platform reset). A UEFI stub is also provided to
2297	  allow the kernel to be booted as an EFI application. This
2298	  is only useful on systems that have UEFI firmware.
2299
2300config DMI
2301	bool "Enable support for SMBIOS (DMI) tables"
2302	depends on EFI
2303	default y
2304	help
2305	  This enables SMBIOS/DMI feature for systems.
2306
2307	  This option is only useful on systems that have UEFI firmware.
2308	  However, even with this option, the resultant kernel should
2309	  continue to boot on existing non-UEFI platforms.
2310
2311endmenu # "Boot options"
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2312
2313menu "Power management options"
2314
2315source "kernel/power/Kconfig"
2316
2317config ARCH_HIBERNATION_POSSIBLE
2318	def_bool y
2319	depends on CPU_PM
2320
2321config ARCH_HIBERNATION_HEADER
2322	def_bool y
2323	depends on HIBERNATION
2324
2325config ARCH_SUSPEND_POSSIBLE
2326	def_bool y
2327
2328endmenu # "Power management options"
2329
2330menu "CPU Power Management"
2331
2332source "drivers/cpuidle/Kconfig"
2333
2334source "drivers/cpufreq/Kconfig"
2335
2336endmenu # "CPU Power Management"
 
 
 
 
 
 
2337
2338source "drivers/acpi/Kconfig"
2339
 
 
2340source "arch/arm64/kvm/Kconfig"
2341