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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * intel TCO Watchdog Driver
4 *
5 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
6 *
7 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
8 * provide warranty for any of this software. This material is
9 * provided "AS-IS" and at no charge.
10 *
11 * The TCO watchdog is implemented in the following I/O controller hubs:
12 * (See the intel documentation on http://developer.intel.com.)
13 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
14 * document number 290687-002, 298242-027: 82801BA (ICH2)
15 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
16 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
17 * document number 290744-001, 290745-025: 82801DB (ICH4)
18 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
19 * document number 273599-001, 273645-002: 82801E (C-ICH)
20 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
21 * document number 300641-004, 300884-013: 6300ESB
22 * document number 301473-002, 301474-026: 82801F (ICH6)
23 * document number 313082-001, 313075-006: 631xESB, 632xESB
24 * document number 307013-003, 307014-024: 82801G (ICH7)
25 * document number 322896-001, 322897-001: NM10
26 * document number 313056-003, 313057-017: 82801H (ICH8)
27 * document number 316972-004, 316973-012: 82801I (ICH9)
28 * document number 319973-002, 319974-002: 82801J (ICH10)
29 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
30 * document number 320066-003, 320257-008: EP80597 (IICH)
31 * document number 324645-001, 324646-001: Cougar Point (CPT)
32 * document number TBD : Patsburg (PBG)
33 * document number TBD : DH89xxCC
34 * document number TBD : Panther Point
35 * document number TBD : Lynx Point
36 * document number TBD : Lynx Point-LP
37 */
38
39/*
40 * Includes, defines, variables, module parameters, ...
41 */
42
43/* Module and version information */
44#define DRV_NAME "iTCO_wdt"
45#define DRV_VERSION "1.11"
46
47/* Includes */
48#include <linux/acpi.h> /* For ACPI support */
49#include <linux/bits.h> /* For BIT() */
50#include <linux/module.h> /* For module specific items */
51#include <linux/moduleparam.h> /* For new moduleparam's */
52#include <linux/types.h> /* For standard types (like size_t) */
53#include <linux/errno.h> /* For the -ENODEV/... values */
54#include <linux/kernel.h> /* For printk/panic/... */
55#include <linux/watchdog.h> /* For the watchdog specific items */
56#include <linux/init.h> /* For __init/__exit/... */
57#include <linux/fs.h> /* For file operations */
58#include <linux/platform_device.h> /* For platform_driver framework */
59#include <linux/pci.h> /* For pci functions */
60#include <linux/ioport.h> /* For io-port access */
61#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
62#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
63#include <linux/io.h> /* For inb/outb/... */
64#include <linux/platform_data/itco_wdt.h>
65#include <linux/mfd/intel_pmc_bxt.h>
66
67#include "iTCO_vendor.h"
68
69/* Address definitions for the TCO */
70/* TCO base address */
71#define TCOBASE(p) ((p)->tco_res->start)
72/* SMI Control and Enable Register */
73#define SMI_EN(p) ((p)->smi_res->start)
74
75#define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
76#define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
77#define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
78#define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
79#define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
80#define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
81#define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
82#define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
83#define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
84
85/* internal variables */
86struct iTCO_wdt_private {
87 struct watchdog_device wddev;
88
89 /* TCO version/generation */
90 unsigned int iTCO_version;
91 struct resource *tco_res;
92 struct resource *smi_res;
93 /*
94 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
95 * or memory-mapped PMC register bit 4 (TCO version 3).
96 */
97 unsigned long __iomem *gcs_pmc;
98 /* the lock for io operations */
99 spinlock_t io_lock;
100 /* the PCI-device */
101 struct pci_dev *pci_dev;
102 /* whether or not the watchdog has been suspended */
103 bool suspended;
104 /* no reboot API private data */
105 void *no_reboot_priv;
106 /* no reboot update function pointer */
107 int (*update_no_reboot_bit)(void *p, bool set);
108};
109
110/* module parameters */
111#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
112static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
113module_param(heartbeat, int, 0);
114MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
115 "5..76 (TCO v1) or 3..614 (TCO v2), default="
116 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
117
118static bool nowayout = WATCHDOG_NOWAYOUT;
119module_param(nowayout, bool, 0);
120MODULE_PARM_DESC(nowayout,
121 "Watchdog cannot be stopped once started (default="
122 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
123
124static int turn_SMI_watchdog_clear_off = 1;
125module_param(turn_SMI_watchdog_clear_off, int, 0);
126MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
127 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
128
129/*
130 * Some TCO specific functions
131 */
132
133/*
134 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
135 * every 0.6 seconds. v3's internal timer is stored as seconds (some
136 * datasheets incorrectly state 0.6 seconds).
137 */
138static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
139 int secs)
140{
141 return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
142}
143
144static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
145 int ticks)
146{
147 return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
148}
149
150static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
151{
152 u32 enable_bit;
153
154 switch (p->iTCO_version) {
155 case 5:
156 case 3:
157 enable_bit = 0x00000010;
158 break;
159 case 2:
160 enable_bit = 0x00000020;
161 break;
162 case 4:
163 case 1:
164 default:
165 enable_bit = 0x00000002;
166 break;
167 }
168
169 return enable_bit;
170}
171
172static int update_no_reboot_bit_def(void *priv, bool set)
173{
174 return 0;
175}
176
177static int update_no_reboot_bit_pci(void *priv, bool set)
178{
179 struct iTCO_wdt_private *p = priv;
180 u32 val32 = 0, newval32 = 0;
181
182 pci_read_config_dword(p->pci_dev, 0xd4, &val32);
183 if (set)
184 val32 |= no_reboot_bit(p);
185 else
186 val32 &= ~no_reboot_bit(p);
187 pci_write_config_dword(p->pci_dev, 0xd4, val32);
188 pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
189
190 /* make sure the update is successful */
191 if (val32 != newval32)
192 return -EIO;
193
194 return 0;
195}
196
197static int update_no_reboot_bit_mem(void *priv, bool set)
198{
199 struct iTCO_wdt_private *p = priv;
200 u32 val32 = 0, newval32 = 0;
201
202 val32 = readl(p->gcs_pmc);
203 if (set)
204 val32 |= no_reboot_bit(p);
205 else
206 val32 &= ~no_reboot_bit(p);
207 writel(val32, p->gcs_pmc);
208 newval32 = readl(p->gcs_pmc);
209
210 /* make sure the update is successful */
211 if (val32 != newval32)
212 return -EIO;
213
214 return 0;
215}
216
217static int update_no_reboot_bit_cnt(void *priv, bool set)
218{
219 struct iTCO_wdt_private *p = priv;
220 u16 val, newval;
221
222 val = inw(TCO1_CNT(p));
223 if (set)
224 val |= BIT(0);
225 else
226 val &= ~BIT(0);
227 outw(val, TCO1_CNT(p));
228 newval = inw(TCO1_CNT(p));
229
230 /* make sure the update is successful */
231 return val != newval ? -EIO : 0;
232}
233
234static int update_no_reboot_bit_pmc(void *priv, bool set)
235{
236 struct intel_pmc_dev *pmc = priv;
237 u32 bits = PMC_CFG_NO_REBOOT_EN;
238 u32 value = set ? bits : 0;
239
240 return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value);
241}
242
243static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
244 struct platform_device *pdev,
245 struct itco_wdt_platform_data *pdata)
246{
247 if (pdata->no_reboot_use_pmc) {
248 struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent);
249
250 p->update_no_reboot_bit = update_no_reboot_bit_pmc;
251 p->no_reboot_priv = pmc;
252 return;
253 }
254
255 if (p->iTCO_version >= 6)
256 p->update_no_reboot_bit = update_no_reboot_bit_cnt;
257 else if (p->iTCO_version >= 2)
258 p->update_no_reboot_bit = update_no_reboot_bit_mem;
259 else if (p->iTCO_version == 1)
260 p->update_no_reboot_bit = update_no_reboot_bit_pci;
261 else
262 p->update_no_reboot_bit = update_no_reboot_bit_def;
263
264 p->no_reboot_priv = p;
265}
266
267static int iTCO_wdt_start(struct watchdog_device *wd_dev)
268{
269 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
270 unsigned int val;
271
272 spin_lock(&p->io_lock);
273
274 iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
275
276 /* disable chipset's NO_REBOOT bit */
277 if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
278 spin_unlock(&p->io_lock);
279 dev_err(wd_dev->parent, "failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
280 return -EIO;
281 }
282
283 /* Force the timer to its reload value by writing to the TCO_RLD
284 register */
285 if (p->iTCO_version >= 2)
286 outw(0x01, TCO_RLD(p));
287 else if (p->iTCO_version == 1)
288 outb(0x01, TCO_RLD(p));
289
290 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
291 val = inw(TCO1_CNT(p));
292 val &= 0xf7ff;
293 outw(val, TCO1_CNT(p));
294 val = inw(TCO1_CNT(p));
295 spin_unlock(&p->io_lock);
296
297 if (val & 0x0800)
298 return -1;
299 return 0;
300}
301
302static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
303{
304 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
305 unsigned int val;
306
307 spin_lock(&p->io_lock);
308
309 iTCO_vendor_pre_stop(p->smi_res);
310
311 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
312 val = inw(TCO1_CNT(p));
313 val |= 0x0800;
314 outw(val, TCO1_CNT(p));
315 val = inw(TCO1_CNT(p));
316
317 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
318 p->update_no_reboot_bit(p->no_reboot_priv, true);
319
320 spin_unlock(&p->io_lock);
321
322 if ((val & 0x0800) == 0)
323 return -1;
324 return 0;
325}
326
327static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
328{
329 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
330
331 spin_lock(&p->io_lock);
332
333 /* Reload the timer by writing to the TCO Timer Counter register */
334 if (p->iTCO_version >= 2) {
335 outw(0x01, TCO_RLD(p));
336 } else if (p->iTCO_version == 1) {
337 /* Reset the timeout status bit so that the timer
338 * needs to count down twice again before rebooting */
339 outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
340
341 outb(0x01, TCO_RLD(p));
342 }
343
344 spin_unlock(&p->io_lock);
345 return 0;
346}
347
348static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
349{
350 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
351 unsigned int val16;
352 unsigned char val8;
353 unsigned int tmrval;
354
355 tmrval = seconds_to_ticks(p, t);
356
357 /* For TCO v1 the timer counts down twice before rebooting */
358 if (p->iTCO_version == 1)
359 tmrval /= 2;
360
361 /* from the specs: */
362 /* "Values of 0h-3h are ignored and should not be attempted" */
363 if (tmrval < 0x04)
364 return -EINVAL;
365 if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
366 (p->iTCO_version == 1 && tmrval > 0x03f))
367 return -EINVAL;
368
369 /* Write new heartbeat to watchdog */
370 if (p->iTCO_version >= 2) {
371 spin_lock(&p->io_lock);
372 val16 = inw(TCOv2_TMR(p));
373 val16 &= 0xfc00;
374 val16 |= tmrval;
375 outw(val16, TCOv2_TMR(p));
376 val16 = inw(TCOv2_TMR(p));
377 spin_unlock(&p->io_lock);
378
379 if ((val16 & 0x3ff) != tmrval)
380 return -EINVAL;
381 } else if (p->iTCO_version == 1) {
382 spin_lock(&p->io_lock);
383 val8 = inb(TCOv1_TMR(p));
384 val8 &= 0xc0;
385 val8 |= (tmrval & 0xff);
386 outb(val8, TCOv1_TMR(p));
387 val8 = inb(TCOv1_TMR(p));
388 spin_unlock(&p->io_lock);
389
390 if ((val8 & 0x3f) != tmrval)
391 return -EINVAL;
392 }
393
394 wd_dev->timeout = t;
395 return 0;
396}
397
398static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
399{
400 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
401 unsigned int val16;
402 unsigned char val8;
403 unsigned int time_left = 0;
404
405 /* read the TCO Timer */
406 if (p->iTCO_version >= 2) {
407 spin_lock(&p->io_lock);
408 val16 = inw(TCO_RLD(p));
409 val16 &= 0x3ff;
410 spin_unlock(&p->io_lock);
411
412 time_left = ticks_to_seconds(p, val16);
413 } else if (p->iTCO_version == 1) {
414 spin_lock(&p->io_lock);
415 val8 = inb(TCO_RLD(p));
416 val8 &= 0x3f;
417 if (!(inw(TCO1_STS(p)) & 0x0008))
418 val8 += (inb(TCOv1_TMR(p)) & 0x3f);
419 spin_unlock(&p->io_lock);
420
421 time_left = ticks_to_seconds(p, val8);
422 }
423 return time_left;
424}
425
426/* Returns true if the watchdog was running */
427static bool iTCO_wdt_set_running(struct iTCO_wdt_private *p)
428{
429 u16 val;
430
431 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled */
432 val = inw(TCO1_CNT(p));
433 if (!(val & BIT(11))) {
434 set_bit(WDOG_HW_RUNNING, &p->wddev.status);
435 return true;
436 }
437 return false;
438}
439
440/*
441 * Kernel Interfaces
442 */
443
444static struct watchdog_info ident = {
445 .options = WDIOF_SETTIMEOUT |
446 WDIOF_KEEPALIVEPING |
447 WDIOF_MAGICCLOSE,
448 .identity = DRV_NAME,
449};
450
451static const struct watchdog_ops iTCO_wdt_ops = {
452 .owner = THIS_MODULE,
453 .start = iTCO_wdt_start,
454 .stop = iTCO_wdt_stop,
455 .ping = iTCO_wdt_ping,
456 .set_timeout = iTCO_wdt_set_timeout,
457 .get_timeleft = iTCO_wdt_get_timeleft,
458};
459
460/*
461 * Init & exit routines
462 */
463
464static int iTCO_wdt_probe(struct platform_device *pdev)
465{
466 struct device *dev = &pdev->dev;
467 struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
468 struct iTCO_wdt_private *p;
469 unsigned long val32;
470 int ret;
471
472 if (!pdata)
473 return -ENODEV;
474
475 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
476 if (!p)
477 return -ENOMEM;
478
479 spin_lock_init(&p->io_lock);
480
481 p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
482 if (!p->tco_res)
483 return -ENODEV;
484
485 p->iTCO_version = pdata->version;
486 p->pci_dev = to_pci_dev(dev->parent);
487
488 p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
489 if (p->smi_res) {
490 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
491 if (!devm_request_region(dev, p->smi_res->start,
492 resource_size(p->smi_res),
493 pdev->name)) {
494 dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
495 (u64)SMI_EN(p));
496 return -EBUSY;
497 }
498 } else if (iTCO_vendorsupport ||
499 turn_SMI_watchdog_clear_off >= p->iTCO_version) {
500 dev_err(dev, "SMI I/O resource is missing\n");
501 return -ENODEV;
502 }
503
504 iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata);
505
506 /*
507 * Get the Memory-Mapped GCS or PMC register, we need it for the
508 * NO_REBOOT flag (TCO v2 and v3).
509 */
510 if (p->iTCO_version >= 2 && p->iTCO_version < 6 &&
511 !pdata->no_reboot_use_pmc) {
512 p->gcs_pmc = devm_platform_ioremap_resource(pdev, ICH_RES_MEM_GCS_PMC);
513 if (IS_ERR(p->gcs_pmc))
514 return PTR_ERR(p->gcs_pmc);
515 }
516
517 /* Check chipset's NO_REBOOT bit */
518 if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
519 iTCO_vendor_check_noreboot_on()) {
520 dev_info(dev, "unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
521 return -ENODEV; /* Cannot reset NO_REBOOT bit */
522 }
523
524 if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
525 /*
526 * Bit 13: TCO_EN -> 0
527 * Disables TCO logic generating an SMI#
528 */
529 val32 = inl(SMI_EN(p));
530 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
531 outl(val32, SMI_EN(p));
532 }
533
534 if (!devm_request_region(dev, p->tco_res->start,
535 resource_size(p->tco_res),
536 pdev->name)) {
537 dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
538 (u64)TCOBASE(p));
539 return -EBUSY;
540 }
541
542 dev_info(dev, "Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
543 pdata->name, pdata->version, (u64)TCOBASE(p));
544
545 /* Clear out the (probably old) status */
546 switch (p->iTCO_version) {
547 case 6:
548 case 5:
549 case 4:
550 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
551 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
552 break;
553 case 3:
554 outl(0x20008, TCO1_STS(p));
555 break;
556 case 2:
557 case 1:
558 default:
559 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
560 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
561 outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
562 break;
563 }
564
565 ident.firmware_version = p->iTCO_version;
566 p->wddev.info = &ident,
567 p->wddev.ops = &iTCO_wdt_ops,
568 p->wddev.bootstatus = 0;
569 p->wddev.timeout = WATCHDOG_TIMEOUT;
570 watchdog_set_nowayout(&p->wddev, nowayout);
571 p->wddev.parent = dev;
572
573 watchdog_set_drvdata(&p->wddev, p);
574 platform_set_drvdata(pdev, p);
575
576 if (!iTCO_wdt_set_running(p)) {
577 /*
578 * If the watchdog was not running set NO_REBOOT now to
579 * prevent later reboots.
580 */
581 p->update_no_reboot_bit(p->no_reboot_priv, true);
582 }
583
584 /* Check that the heartbeat value is within it's range;
585 if not reset to the default */
586 if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
587 iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
588 dev_info(dev, "timeout value out of range, using %d\n",
589 WATCHDOG_TIMEOUT);
590 }
591
592 watchdog_stop_on_reboot(&p->wddev);
593 watchdog_stop_on_unregister(&p->wddev);
594 ret = devm_watchdog_register_device(dev, &p->wddev);
595 if (ret != 0) {
596 dev_err(dev, "cannot register watchdog device (err=%d)\n", ret);
597 return ret;
598 }
599
600 dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
601 heartbeat, nowayout);
602
603 return 0;
604}
605
606/*
607 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
608 * the watchdog cannot be pinged while in that state. In ACPI sleep states the
609 * watchdog is stopped by the platform firmware.
610 */
611
612#ifdef CONFIG_ACPI
613static inline bool __maybe_unused need_suspend(void)
614{
615 return acpi_target_system_state() == ACPI_STATE_S0;
616}
617#else
618static inline bool __maybe_unused need_suspend(void) { return true; }
619#endif
620
621static int __maybe_unused iTCO_wdt_suspend_noirq(struct device *dev)
622{
623 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
624 int ret = 0;
625
626 p->suspended = false;
627 if (watchdog_active(&p->wddev) && need_suspend()) {
628 ret = iTCO_wdt_stop(&p->wddev);
629 if (!ret)
630 p->suspended = true;
631 }
632 return ret;
633}
634
635static int __maybe_unused iTCO_wdt_resume_noirq(struct device *dev)
636{
637 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
638
639 if (p->suspended)
640 iTCO_wdt_start(&p->wddev);
641
642 return 0;
643}
644
645static const struct dev_pm_ops iTCO_wdt_pm = {
646 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(iTCO_wdt_suspend_noirq,
647 iTCO_wdt_resume_noirq)
648};
649
650static struct platform_driver iTCO_wdt_driver = {
651 .probe = iTCO_wdt_probe,
652 .driver = {
653 .name = DRV_NAME,
654 .pm = &iTCO_wdt_pm,
655 },
656};
657
658module_platform_driver(iTCO_wdt_driver);
659
660MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
661MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
662MODULE_VERSION(DRV_VERSION);
663MODULE_LICENSE("GPL");
664MODULE_ALIAS("platform:" DRV_NAME);
1/*
2 * intel TCO Watchdog Driver
3 *
4 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 322896-001, 322897-001: NM10
30 * document number 313056-003, 313057-017: 82801H (ICH8)
31 * document number 316972-004, 316973-012: 82801I (ICH9)
32 * document number 319973-002, 319974-002: 82801J (ICH10)
33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
34 * document number 320066-003, 320257-008: EP80597 (IICH)
35 * document number 324645-001, 324646-001: Cougar Point (CPT)
36 * document number TBD : Patsburg (PBG)
37 * document number TBD : DH89xxCC
38 * document number TBD : Panther Point
39 * document number TBD : Lynx Point
40 * document number TBD : Lynx Point-LP
41 */
42
43/*
44 * Includes, defines, variables, module parameters, ...
45 */
46
47#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
48
49/* Module and version information */
50#define DRV_NAME "iTCO_wdt"
51#define DRV_VERSION "1.11"
52
53/* Includes */
54#include <linux/acpi.h> /* For ACPI support */
55#include <linux/module.h> /* For module specific items */
56#include <linux/moduleparam.h> /* For new moduleparam's */
57#include <linux/types.h> /* For standard types (like size_t) */
58#include <linux/errno.h> /* For the -ENODEV/... values */
59#include <linux/kernel.h> /* For printk/panic/... */
60#include <linux/watchdog.h> /* For the watchdog specific items */
61#include <linux/init.h> /* For __init/__exit/... */
62#include <linux/fs.h> /* For file operations */
63#include <linux/platform_device.h> /* For platform_driver framework */
64#include <linux/pci.h> /* For pci functions */
65#include <linux/ioport.h> /* For io-port access */
66#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
67#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
68#include <linux/io.h> /* For inb/outb/... */
69#include <linux/platform_data/itco_wdt.h>
70
71#include "iTCO_vendor.h"
72
73/* Address definitions for the TCO */
74/* TCO base address */
75#define TCOBASE (iTCO_wdt_private.tco_res->start)
76/* SMI Control and Enable Register */
77#define SMI_EN (iTCO_wdt_private.smi_res->start)
78
79#define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
80#define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
81#define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
82#define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
83#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
84#define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
85#define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
86#define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
87#define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
88
89/* internal variables */
90static struct { /* this is private data for the iTCO_wdt device */
91 /* TCO version/generation */
92 unsigned int iTCO_version;
93 struct resource *tco_res;
94 struct resource *smi_res;
95 /*
96 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
97 * or memory-mapped PMC register bit 4 (TCO version 3).
98 */
99 struct resource *gcs_pmc_res;
100 unsigned long __iomem *gcs_pmc;
101 /* the lock for io operations */
102 spinlock_t io_lock;
103 struct platform_device *dev;
104 /* the PCI-device */
105 struct pci_dev *pdev;
106 /* whether or not the watchdog has been suspended */
107 bool suspended;
108} iTCO_wdt_private;
109
110/* module parameters */
111#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
112static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
113module_param(heartbeat, int, 0);
114MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
115 "5..76 (TCO v1) or 3..614 (TCO v2), default="
116 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
117
118static bool nowayout = WATCHDOG_NOWAYOUT;
119module_param(nowayout, bool, 0);
120MODULE_PARM_DESC(nowayout,
121 "Watchdog cannot be stopped once started (default="
122 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
123
124static int turn_SMI_watchdog_clear_off = 1;
125module_param(turn_SMI_watchdog_clear_off, int, 0);
126MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
127 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
128
129/*
130 * Some TCO specific functions
131 */
132
133/*
134 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
135 * every 0.6 seconds. v3's internal timer is stored as seconds (some
136 * datasheets incorrectly state 0.6 seconds).
137 */
138static inline unsigned int seconds_to_ticks(int secs)
139{
140 return iTCO_wdt_private.iTCO_version == 3 ? secs : (secs * 10) / 6;
141}
142
143static inline unsigned int ticks_to_seconds(int ticks)
144{
145 return iTCO_wdt_private.iTCO_version == 3 ? ticks : (ticks * 6) / 10;
146}
147
148static inline u32 no_reboot_bit(void)
149{
150 u32 enable_bit;
151
152 switch (iTCO_wdt_private.iTCO_version) {
153 case 5:
154 case 3:
155 enable_bit = 0x00000010;
156 break;
157 case 2:
158 enable_bit = 0x00000020;
159 break;
160 case 4:
161 case 1:
162 default:
163 enable_bit = 0x00000002;
164 break;
165 }
166
167 return enable_bit;
168}
169
170static void iTCO_wdt_set_NO_REBOOT_bit(void)
171{
172 u32 val32;
173
174 /* Set the NO_REBOOT bit: this disables reboots */
175 if (iTCO_wdt_private.iTCO_version >= 2) {
176 val32 = readl(iTCO_wdt_private.gcs_pmc);
177 val32 |= no_reboot_bit();
178 writel(val32, iTCO_wdt_private.gcs_pmc);
179 } else if (iTCO_wdt_private.iTCO_version == 1) {
180 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
181 val32 |= no_reboot_bit();
182 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
183 }
184}
185
186static int iTCO_wdt_unset_NO_REBOOT_bit(void)
187{
188 u32 enable_bit = no_reboot_bit();
189 u32 val32 = 0;
190
191 /* Unset the NO_REBOOT bit: this enables reboots */
192 if (iTCO_wdt_private.iTCO_version >= 2) {
193 val32 = readl(iTCO_wdt_private.gcs_pmc);
194 val32 &= ~enable_bit;
195 writel(val32, iTCO_wdt_private.gcs_pmc);
196
197 val32 = readl(iTCO_wdt_private.gcs_pmc);
198 } else if (iTCO_wdt_private.iTCO_version == 1) {
199 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
200 val32 &= ~enable_bit;
201 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
202
203 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
204 }
205
206 if (val32 & enable_bit)
207 return -EIO;
208
209 return 0;
210}
211
212static int iTCO_wdt_start(struct watchdog_device *wd_dev)
213{
214 unsigned int val;
215
216 spin_lock(&iTCO_wdt_private.io_lock);
217
218 iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout);
219
220 /* disable chipset's NO_REBOOT bit */
221 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
222 spin_unlock(&iTCO_wdt_private.io_lock);
223 pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
224 return -EIO;
225 }
226
227 /* Force the timer to its reload value by writing to the TCO_RLD
228 register */
229 if (iTCO_wdt_private.iTCO_version >= 2)
230 outw(0x01, TCO_RLD);
231 else if (iTCO_wdt_private.iTCO_version == 1)
232 outb(0x01, TCO_RLD);
233
234 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
235 val = inw(TCO1_CNT);
236 val &= 0xf7ff;
237 outw(val, TCO1_CNT);
238 val = inw(TCO1_CNT);
239 spin_unlock(&iTCO_wdt_private.io_lock);
240
241 if (val & 0x0800)
242 return -1;
243 return 0;
244}
245
246static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
247{
248 unsigned int val;
249
250 spin_lock(&iTCO_wdt_private.io_lock);
251
252 iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res);
253
254 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
255 val = inw(TCO1_CNT);
256 val |= 0x0800;
257 outw(val, TCO1_CNT);
258 val = inw(TCO1_CNT);
259
260 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
261 iTCO_wdt_set_NO_REBOOT_bit();
262
263 spin_unlock(&iTCO_wdt_private.io_lock);
264
265 if ((val & 0x0800) == 0)
266 return -1;
267 return 0;
268}
269
270static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
271{
272 spin_lock(&iTCO_wdt_private.io_lock);
273
274 iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout);
275
276 /* Reload the timer by writing to the TCO Timer Counter register */
277 if (iTCO_wdt_private.iTCO_version >= 2) {
278 outw(0x01, TCO_RLD);
279 } else if (iTCO_wdt_private.iTCO_version == 1) {
280 /* Reset the timeout status bit so that the timer
281 * needs to count down twice again before rebooting */
282 outw(0x0008, TCO1_STS); /* write 1 to clear bit */
283
284 outb(0x01, TCO_RLD);
285 }
286
287 spin_unlock(&iTCO_wdt_private.io_lock);
288 return 0;
289}
290
291static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
292{
293 unsigned int val16;
294 unsigned char val8;
295 unsigned int tmrval;
296
297 tmrval = seconds_to_ticks(t);
298
299 /* For TCO v1 the timer counts down twice before rebooting */
300 if (iTCO_wdt_private.iTCO_version == 1)
301 tmrval /= 2;
302
303 /* from the specs: */
304 /* "Values of 0h-3h are ignored and should not be attempted" */
305 if (tmrval < 0x04)
306 return -EINVAL;
307 if (((iTCO_wdt_private.iTCO_version >= 2) && (tmrval > 0x3ff)) ||
308 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
309 return -EINVAL;
310
311 iTCO_vendor_pre_set_heartbeat(tmrval);
312
313 /* Write new heartbeat to watchdog */
314 if (iTCO_wdt_private.iTCO_version >= 2) {
315 spin_lock(&iTCO_wdt_private.io_lock);
316 val16 = inw(TCOv2_TMR);
317 val16 &= 0xfc00;
318 val16 |= tmrval;
319 outw(val16, TCOv2_TMR);
320 val16 = inw(TCOv2_TMR);
321 spin_unlock(&iTCO_wdt_private.io_lock);
322
323 if ((val16 & 0x3ff) != tmrval)
324 return -EINVAL;
325 } else if (iTCO_wdt_private.iTCO_version == 1) {
326 spin_lock(&iTCO_wdt_private.io_lock);
327 val8 = inb(TCOv1_TMR);
328 val8 &= 0xc0;
329 val8 |= (tmrval & 0xff);
330 outb(val8, TCOv1_TMR);
331 val8 = inb(TCOv1_TMR);
332 spin_unlock(&iTCO_wdt_private.io_lock);
333
334 if ((val8 & 0x3f) != tmrval)
335 return -EINVAL;
336 }
337
338 wd_dev->timeout = t;
339 return 0;
340}
341
342static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
343{
344 unsigned int val16;
345 unsigned char val8;
346 unsigned int time_left = 0;
347
348 /* read the TCO Timer */
349 if (iTCO_wdt_private.iTCO_version >= 2) {
350 spin_lock(&iTCO_wdt_private.io_lock);
351 val16 = inw(TCO_RLD);
352 val16 &= 0x3ff;
353 spin_unlock(&iTCO_wdt_private.io_lock);
354
355 time_left = ticks_to_seconds(val16);
356 } else if (iTCO_wdt_private.iTCO_version == 1) {
357 spin_lock(&iTCO_wdt_private.io_lock);
358 val8 = inb(TCO_RLD);
359 val8 &= 0x3f;
360 if (!(inw(TCO1_STS) & 0x0008))
361 val8 += (inb(TCOv1_TMR) & 0x3f);
362 spin_unlock(&iTCO_wdt_private.io_lock);
363
364 time_left = ticks_to_seconds(val8);
365 }
366 return time_left;
367}
368
369/*
370 * Kernel Interfaces
371 */
372
373static const struct watchdog_info ident = {
374 .options = WDIOF_SETTIMEOUT |
375 WDIOF_KEEPALIVEPING |
376 WDIOF_MAGICCLOSE,
377 .firmware_version = 0,
378 .identity = DRV_NAME,
379};
380
381static const struct watchdog_ops iTCO_wdt_ops = {
382 .owner = THIS_MODULE,
383 .start = iTCO_wdt_start,
384 .stop = iTCO_wdt_stop,
385 .ping = iTCO_wdt_ping,
386 .set_timeout = iTCO_wdt_set_timeout,
387 .get_timeleft = iTCO_wdt_get_timeleft,
388};
389
390static struct watchdog_device iTCO_wdt_watchdog_dev = {
391 .info = &ident,
392 .ops = &iTCO_wdt_ops,
393};
394
395/*
396 * Init & exit routines
397 */
398
399static void iTCO_wdt_cleanup(void)
400{
401 /* Stop the timer before we leave */
402 if (!nowayout)
403 iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
404
405 /* Deregister */
406 watchdog_unregister_device(&iTCO_wdt_watchdog_dev);
407
408 /* release resources */
409 release_region(iTCO_wdt_private.tco_res->start,
410 resource_size(iTCO_wdt_private.tco_res));
411 release_region(iTCO_wdt_private.smi_res->start,
412 resource_size(iTCO_wdt_private.smi_res));
413 if (iTCO_wdt_private.iTCO_version >= 2) {
414 iounmap(iTCO_wdt_private.gcs_pmc);
415 release_mem_region(iTCO_wdt_private.gcs_pmc_res->start,
416 resource_size(iTCO_wdt_private.gcs_pmc_res));
417 }
418
419 iTCO_wdt_private.tco_res = NULL;
420 iTCO_wdt_private.smi_res = NULL;
421 iTCO_wdt_private.gcs_pmc_res = NULL;
422 iTCO_wdt_private.gcs_pmc = NULL;
423}
424
425static int iTCO_wdt_probe(struct platform_device *dev)
426{
427 int ret = -ENODEV;
428 unsigned long val32;
429 struct itco_wdt_platform_data *pdata = dev_get_platdata(&dev->dev);
430
431 if (!pdata)
432 goto out;
433
434 spin_lock_init(&iTCO_wdt_private.io_lock);
435
436 iTCO_wdt_private.tco_res =
437 platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
438 if (!iTCO_wdt_private.tco_res)
439 goto out;
440
441 iTCO_wdt_private.smi_res =
442 platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
443 if (!iTCO_wdt_private.smi_res)
444 goto out;
445
446 iTCO_wdt_private.iTCO_version = pdata->version;
447 iTCO_wdt_private.dev = dev;
448 iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent);
449
450 /*
451 * Get the Memory-Mapped GCS or PMC register, we need it for the
452 * NO_REBOOT flag (TCO v2 and v3).
453 */
454 if (iTCO_wdt_private.iTCO_version >= 2) {
455 iTCO_wdt_private.gcs_pmc_res = platform_get_resource(dev,
456 IORESOURCE_MEM,
457 ICH_RES_MEM_GCS_PMC);
458
459 if (!iTCO_wdt_private.gcs_pmc_res)
460 goto out;
461
462 if (!request_mem_region(iTCO_wdt_private.gcs_pmc_res->start,
463 resource_size(iTCO_wdt_private.gcs_pmc_res), dev->name)) {
464 ret = -EBUSY;
465 goto out;
466 }
467 iTCO_wdt_private.gcs_pmc = ioremap(iTCO_wdt_private.gcs_pmc_res->start,
468 resource_size(iTCO_wdt_private.gcs_pmc_res));
469 if (!iTCO_wdt_private.gcs_pmc) {
470 ret = -EIO;
471 goto unreg_gcs_pmc;
472 }
473 }
474
475 /* Check chipset's NO_REBOOT bit */
476 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
477 pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
478 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
479 goto unmap_gcs_pmc;
480 }
481
482 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
483 iTCO_wdt_set_NO_REBOOT_bit();
484
485 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
486 if (!request_region(iTCO_wdt_private.smi_res->start,
487 resource_size(iTCO_wdt_private.smi_res), dev->name)) {
488 pr_err("I/O address 0x%04llx already in use, device disabled\n",
489 (u64)SMI_EN);
490 ret = -EBUSY;
491 goto unmap_gcs_pmc;
492 }
493 if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
494 /*
495 * Bit 13: TCO_EN -> 0
496 * Disables TCO logic generating an SMI#
497 */
498 val32 = inl(SMI_EN);
499 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
500 outl(val32, SMI_EN);
501 }
502
503 if (!request_region(iTCO_wdt_private.tco_res->start,
504 resource_size(iTCO_wdt_private.tco_res), dev->name)) {
505 pr_err("I/O address 0x%04llx already in use, device disabled\n",
506 (u64)TCOBASE);
507 ret = -EBUSY;
508 goto unreg_smi;
509 }
510
511 pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
512 pdata->name, pdata->version, (u64)TCOBASE);
513
514 /* Clear out the (probably old) status */
515 switch (iTCO_wdt_private.iTCO_version) {
516 case 5:
517 case 4:
518 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
519 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
520 break;
521 case 3:
522 outl(0x20008, TCO1_STS);
523 break;
524 case 2:
525 case 1:
526 default:
527 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
528 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
529 outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
530 break;
531 }
532
533 iTCO_wdt_watchdog_dev.bootstatus = 0;
534 iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT;
535 watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout);
536 iTCO_wdt_watchdog_dev.parent = &dev->dev;
537
538 /* Make sure the watchdog is not running */
539 iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
540
541 /* Check that the heartbeat value is within it's range;
542 if not reset to the default */
543 if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) {
544 iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT);
545 pr_info("timeout value out of range, using %d\n",
546 WATCHDOG_TIMEOUT);
547 }
548
549 ret = watchdog_register_device(&iTCO_wdt_watchdog_dev);
550 if (ret != 0) {
551 pr_err("cannot register watchdog device (err=%d)\n", ret);
552 goto unreg_tco;
553 }
554
555 pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
556 heartbeat, nowayout);
557
558 return 0;
559
560unreg_tco:
561 release_region(iTCO_wdt_private.tco_res->start,
562 resource_size(iTCO_wdt_private.tco_res));
563unreg_smi:
564 release_region(iTCO_wdt_private.smi_res->start,
565 resource_size(iTCO_wdt_private.smi_res));
566unmap_gcs_pmc:
567 if (iTCO_wdt_private.iTCO_version >= 2)
568 iounmap(iTCO_wdt_private.gcs_pmc);
569unreg_gcs_pmc:
570 if (iTCO_wdt_private.iTCO_version >= 2)
571 release_mem_region(iTCO_wdt_private.gcs_pmc_res->start,
572 resource_size(iTCO_wdt_private.gcs_pmc_res));
573out:
574 iTCO_wdt_private.tco_res = NULL;
575 iTCO_wdt_private.smi_res = NULL;
576 iTCO_wdt_private.gcs_pmc_res = NULL;
577 iTCO_wdt_private.gcs_pmc = NULL;
578
579 return ret;
580}
581
582static int iTCO_wdt_remove(struct platform_device *dev)
583{
584 if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res)
585 iTCO_wdt_cleanup();
586
587 return 0;
588}
589
590static void iTCO_wdt_shutdown(struct platform_device *dev)
591{
592 iTCO_wdt_stop(NULL);
593}
594
595#ifdef CONFIG_PM_SLEEP
596/*
597 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
598 * the watchdog cannot be pinged while in that state. In ACPI sleep states the
599 * watchdog is stopped by the platform firmware.
600 */
601
602#ifdef CONFIG_ACPI
603static inline bool need_suspend(void)
604{
605 return acpi_target_system_state() == ACPI_STATE_S0;
606}
607#else
608static inline bool need_suspend(void) { return true; }
609#endif
610
611static int iTCO_wdt_suspend_noirq(struct device *dev)
612{
613 int ret = 0;
614
615 iTCO_wdt_private.suspended = false;
616 if (watchdog_active(&iTCO_wdt_watchdog_dev) && need_suspend()) {
617 ret = iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
618 if (!ret)
619 iTCO_wdt_private.suspended = true;
620 }
621 return ret;
622}
623
624static int iTCO_wdt_resume_noirq(struct device *dev)
625{
626 if (iTCO_wdt_private.suspended)
627 iTCO_wdt_start(&iTCO_wdt_watchdog_dev);
628
629 return 0;
630}
631
632static const struct dev_pm_ops iTCO_wdt_pm = {
633 .suspend_noirq = iTCO_wdt_suspend_noirq,
634 .resume_noirq = iTCO_wdt_resume_noirq,
635};
636
637#define ITCO_WDT_PM_OPS (&iTCO_wdt_pm)
638#else
639#define ITCO_WDT_PM_OPS NULL
640#endif /* CONFIG_PM_SLEEP */
641
642static struct platform_driver iTCO_wdt_driver = {
643 .probe = iTCO_wdt_probe,
644 .remove = iTCO_wdt_remove,
645 .shutdown = iTCO_wdt_shutdown,
646 .driver = {
647 .name = DRV_NAME,
648 .pm = ITCO_WDT_PM_OPS,
649 },
650};
651
652static int __init iTCO_wdt_init_module(void)
653{
654 int err;
655
656 pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
657
658 err = platform_driver_register(&iTCO_wdt_driver);
659 if (err)
660 return err;
661
662 return 0;
663}
664
665static void __exit iTCO_wdt_cleanup_module(void)
666{
667 platform_driver_unregister(&iTCO_wdt_driver);
668 pr_info("Watchdog Module Unloaded\n");
669}
670
671module_init(iTCO_wdt_init_module);
672module_exit(iTCO_wdt_cleanup_module);
673
674MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
675MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
676MODULE_VERSION(DRV_VERSION);
677MODULE_LICENSE("GPL");
678MODULE_ALIAS("platform:" DRV_NAME);