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1#ifndef __LINUX_FOTG210_H
2#define __LINUX_FOTG210_H
3
4#include <linux/usb/ehci-dbgp.h>
5
6/* definitions used for the EHCI driver */
7
8/*
9 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
10 * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
11 * the host controller implementation.
12 *
13 * To facilitate the strongest possible byte-order checking from "sparse"
14 * and so on, we use __leXX unless that's not practical.
15 */
16#define __hc32 __le32
17#define __hc16 __le16
18
19/* statistics can be kept for tuning/monitoring */
20struct fotg210_stats {
21 /* irq usage */
22 unsigned long normal;
23 unsigned long error;
24 unsigned long iaa;
25 unsigned long lost_iaa;
26
27 /* termination of urbs from core */
28 unsigned long complete;
29 unsigned long unlink;
30};
31
32/* fotg210_hcd->lock guards shared data against other CPUs:
33 * fotg210_hcd: async, unlink, periodic (and shadow), ...
34 * usb_host_endpoint: hcpriv
35 * fotg210_qh: qh_next, qtd_list
36 * fotg210_qtd: qtd_list
37 *
38 * Also, hold this lock when talking to HC registers or
39 * when updating hw_* fields in shared qh/qtd/... structures.
40 */
41
42#define FOTG210_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
43
44/*
45 * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
46 * controller may be doing DMA. Lower values mean there's no DMA.
47 */
48enum fotg210_rh_state {
49 FOTG210_RH_HALTED,
50 FOTG210_RH_SUSPENDED,
51 FOTG210_RH_RUNNING,
52 FOTG210_RH_STOPPING
53};
54
55/*
56 * Timer events, ordered by increasing delay length.
57 * Always update event_delays_ns[] and event_handlers[] (defined in
58 * ehci-timer.c) in parallel with this list.
59 */
60enum fotg210_hrtimer_event {
61 FOTG210_HRTIMER_POLL_ASS, /* Poll for async schedule off */
62 FOTG210_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
63 FOTG210_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
64 FOTG210_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
65 FOTG210_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
66 FOTG210_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
67 FOTG210_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
68 FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
69 FOTG210_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
70 FOTG210_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
71 FOTG210_HRTIMER_NUM_EVENTS /* Must come last */
72};
73#define FOTG210_HRTIMER_NO_EVENT 99
74
75struct fotg210_hcd { /* one per controller */
76 /* timing support */
77 enum fotg210_hrtimer_event next_hrtimer_event;
78 unsigned enabled_hrtimer_events;
79 ktime_t hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
80 struct hrtimer hrtimer;
81
82 int PSS_poll_count;
83 int ASS_poll_count;
84 int died_poll_count;
85
86 /* glue to PCI and HCD framework */
87 struct fotg210_caps __iomem *caps;
88 struct fotg210_regs __iomem *regs;
89 struct ehci_dbg_port __iomem *debug;
90
91 __u32 hcs_params; /* cached register copy */
92 spinlock_t lock;
93 enum fotg210_rh_state rh_state;
94
95 /* general schedule support */
96 bool scanning:1;
97 bool need_rescan:1;
98 bool intr_unlinking:1;
99 bool async_unlinking:1;
100 bool shutdown:1;
101 struct fotg210_qh *qh_scan_next;
102
103 /* async schedule support */
104 struct fotg210_qh *async;
105 struct fotg210_qh *dummy; /* For AMD quirk use */
106 struct fotg210_qh *async_unlink;
107 struct fotg210_qh *async_unlink_last;
108 struct fotg210_qh *async_iaa;
109 unsigned async_unlink_cycle;
110 unsigned async_count; /* async activity count */
111
112 /* periodic schedule support */
113#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
114 unsigned periodic_size;
115 __hc32 *periodic; /* hw periodic table */
116 dma_addr_t periodic_dma;
117 struct list_head intr_qh_list;
118 unsigned i_thresh; /* uframes HC might cache */
119
120 union fotg210_shadow *pshadow; /* mirror hw periodic table */
121 struct fotg210_qh *intr_unlink;
122 struct fotg210_qh *intr_unlink_last;
123 unsigned intr_unlink_cycle;
124 unsigned now_frame; /* frame from HC hardware */
125 unsigned next_frame; /* scan periodic, start here */
126 unsigned intr_count; /* intr activity count */
127 unsigned isoc_count; /* isoc activity count */
128 unsigned periodic_count; /* periodic activity count */
129 /* max periodic time per uframe */
130 unsigned uframe_periodic_max;
131
132
133 /* list of itds completed while now_frame was still active */
134 struct list_head cached_itd_list;
135 struct fotg210_itd *last_itd_to_free;
136
137 /* per root hub port */
138 unsigned long reset_done[FOTG210_MAX_ROOT_PORTS];
139
140 /* bit vectors (one bit per port)
141 * which ports were already suspended at the start of a bus suspend
142 */
143 unsigned long bus_suspended;
144
145 /* which ports are edicated to the companion controller */
146 unsigned long companion_ports;
147
148 /* which ports are owned by the companion during a bus suspend */
149 unsigned long owned_ports;
150
151 /* which ports have the change-suspend feature turned on */
152 unsigned long port_c_suspend;
153
154 /* which ports are suspended */
155 unsigned long suspended_ports;
156
157 /* which ports have started to resume */
158 unsigned long resuming_ports;
159
160 /* per-HC memory pools (could be per-bus, but ...) */
161 struct dma_pool *qh_pool; /* qh per active urb */
162 struct dma_pool *qtd_pool; /* one or more per qh */
163 struct dma_pool *itd_pool; /* itd per iso urb */
164
165 unsigned random_frame;
166 unsigned long next_statechange;
167 ktime_t last_periodic_enable;
168 u32 command;
169
170 /* SILICON QUIRKS */
171 unsigned need_io_watchdog:1;
172 unsigned fs_i_thresh:1; /* Intel iso scheduling */
173
174 u8 sbrn; /* packed release number */
175
176 /* irq statistics */
177#ifdef FOTG210_STATS
178 struct fotg210_stats stats;
179# define COUNT(x) ((x)++)
180#else
181# define COUNT(x)
182#endif
183
184 /* debug files */
185 struct dentry *debug_dir;
186};
187
188/* convert between an HCD pointer and the corresponding FOTG210_HCD */
189static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
190{
191 return (struct fotg210_hcd *)(hcd->hcd_priv);
192}
193static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
194{
195 return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
196}
197
198/*-------------------------------------------------------------------------*/
199
200/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
201
202/* Section 2.2 Host Controller Capability Registers */
203struct fotg210_caps {
204 /* these fields are specified as 8 and 16 bit registers,
205 * but some hosts can't perform 8 or 16 bit PCI accesses.
206 * some hosts treat caplength and hciversion as parts of a 32-bit
207 * register, others treat them as two separate registers, this
208 * affects the memory map for big endian controllers.
209 */
210 u32 hc_capbase;
211#define HC_LENGTH(fotg210, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
212 (fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
213#define HC_VERSION(fotg210, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
214 (fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
215 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
216#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
217
218 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
219#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
220#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
221 u8 portroute[8]; /* nibbles for routing - offset 0xC */
222};
223
224
225/* Section 2.3 Host Controller Operational Registers */
226struct fotg210_regs {
227
228 /* USBCMD: offset 0x00 */
229 u32 command;
230
231/* EHCI 1.1 addendum */
232/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
233#define CMD_PARK (1<<11) /* enable "park" on async qh */
234#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
235#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
236#define CMD_ASE (1<<5) /* async schedule enable */
237#define CMD_PSE (1<<4) /* periodic schedule enable */
238/* 3:2 is periodic frame list size */
239#define CMD_RESET (1<<1) /* reset HC not bus */
240#define CMD_RUN (1<<0) /* start/stop HC */
241
242 /* USBSTS: offset 0x04 */
243 u32 status;
244#define STS_ASS (1<<15) /* Async Schedule Status */
245#define STS_PSS (1<<14) /* Periodic Schedule Status */
246#define STS_RECL (1<<13) /* Reclamation */
247#define STS_HALT (1<<12) /* Not running (any reason) */
248/* some bits reserved */
249 /* these STS_* flags are also intr_enable bits (USBINTR) */
250#define STS_IAA (1<<5) /* Interrupted on async advance */
251#define STS_FATAL (1<<4) /* such as some PCI access errors */
252#define STS_FLR (1<<3) /* frame list rolled over */
253#define STS_PCD (1<<2) /* port change detect */
254#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
255#define STS_INT (1<<0) /* "normal" completion (short, ...) */
256
257 /* USBINTR: offset 0x08 */
258 u32 intr_enable;
259
260 /* FRINDEX: offset 0x0C */
261 u32 frame_index; /* current microframe number */
262 /* CTRLDSSEGMENT: offset 0x10 */
263 u32 segment; /* address bits 63:32 if needed */
264 /* PERIODICLISTBASE: offset 0x14 */
265 u32 frame_list; /* points to periodic list */
266 /* ASYNCLISTADDR: offset 0x18 */
267 u32 async_next; /* address of next async queue head */
268
269 u32 reserved1;
270 /* PORTSC: offset 0x20 */
271 u32 port_status;
272/* 31:23 reserved */
273#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
274#define PORT_RESET (1<<8) /* reset port */
275#define PORT_SUSPEND (1<<7) /* suspend port */
276#define PORT_RESUME (1<<6) /* resume it */
277#define PORT_PEC (1<<3) /* port enable change */
278#define PORT_PE (1<<2) /* port enable */
279#define PORT_CSC (1<<1) /* connect status change */
280#define PORT_CONNECT (1<<0) /* device connected */
281#define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
282 u32 reserved2[19];
283
284 /* OTGCSR: offet 0x70 */
285 u32 otgcsr;
286#define OTGCSR_HOST_SPD_TYP (3 << 22)
287#define OTGCSR_A_BUS_DROP (1 << 5)
288#define OTGCSR_A_BUS_REQ (1 << 4)
289
290 /* OTGISR: offset 0x74 */
291 u32 otgisr;
292#define OTGISR_OVC (1 << 10)
293
294 u32 reserved3[15];
295
296 /* GMIR: offset 0xB4 */
297 u32 gmir;
298#define GMIR_INT_POLARITY (1 << 3) /*Active High*/
299#define GMIR_MHC_INT (1 << 2)
300#define GMIR_MOTG_INT (1 << 1)
301#define GMIR_MDEV_INT (1 << 0)
302};
303
304/*-------------------------------------------------------------------------*/
305
306#define QTD_NEXT(fotg210, dma) cpu_to_hc32(fotg210, (u32)dma)
307
308/*
309 * EHCI Specification 0.95 Section 3.5
310 * QTD: describe data transfer components (buffer, direction, ...)
311 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
312 *
313 * These are associated only with "QH" (Queue Head) structures,
314 * used with control, bulk, and interrupt transfers.
315 */
316struct fotg210_qtd {
317 /* first part defined by EHCI spec */
318 __hc32 hw_next; /* see EHCI 3.5.1 */
319 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
320 __hc32 hw_token; /* see EHCI 3.5.3 */
321#define QTD_TOGGLE (1 << 31) /* data toggle */
322#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
323#define QTD_IOC (1 << 15) /* interrupt on complete */
324#define QTD_CERR(tok) (((tok)>>10) & 0x3)
325#define QTD_PID(tok) (((tok)>>8) & 0x3)
326#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
327#define QTD_STS_HALT (1 << 6) /* halted on error */
328#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
329#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
330#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
331#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
332#define QTD_STS_STS (1 << 1) /* split transaction state */
333#define QTD_STS_PING (1 << 0) /* issue PING? */
334
335#define ACTIVE_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
336#define HALT_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_HALT)
337#define STATUS_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_STS)
338
339 __hc32 hw_buf[5]; /* see EHCI 3.5.4 */
340 __hc32 hw_buf_hi[5]; /* Appendix B */
341
342 /* the rest is HCD-private */
343 dma_addr_t qtd_dma; /* qtd address */
344 struct list_head qtd_list; /* sw qtd list */
345 struct urb *urb; /* qtd's urb */
346 size_t length; /* length of buffer */
347} __aligned(32);
348
349/* mask NakCnt+T in qh->hw_alt_next */
350#define QTD_MASK(fotg210) cpu_to_hc32(fotg210, ~0x1f)
351
352#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
353
354/*-------------------------------------------------------------------------*/
355
356/* type tag from {qh,itd,fstn}->hw_next */
357#define Q_NEXT_TYPE(fotg210, dma) ((dma) & cpu_to_hc32(fotg210, 3 << 1))
358
359/*
360 * Now the following defines are not converted using the
361 * cpu_to_le32() macro anymore, since we have to support
362 * "dynamic" switching between be and le support, so that the driver
363 * can be used on one system with SoC EHCI controller using big-endian
364 * descriptors as well as a normal little-endian PCI EHCI controller.
365 */
366/* values for that type tag */
367#define Q_TYPE_ITD (0 << 1)
368#define Q_TYPE_QH (1 << 1)
369#define Q_TYPE_SITD (2 << 1)
370#define Q_TYPE_FSTN (3 << 1)
371
372/* next async queue entry, or pointer to interrupt/periodic QH */
373#define QH_NEXT(fotg210, dma) \
374 (cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
375
376/* for periodic/async schedules and qtd lists, mark end of list */
377#define FOTG210_LIST_END(fotg210) \
378 cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
379
380/*
381 * Entries in periodic shadow table are pointers to one of four kinds
382 * of data structure. That's dictated by the hardware; a type tag is
383 * encoded in the low bits of the hardware's periodic schedule. Use
384 * Q_NEXT_TYPE to get the tag.
385 *
386 * For entries in the async schedule, the type tag always says "qh".
387 */
388union fotg210_shadow {
389 struct fotg210_qh *qh; /* Q_TYPE_QH */
390 struct fotg210_itd *itd; /* Q_TYPE_ITD */
391 struct fotg210_fstn *fstn; /* Q_TYPE_FSTN */
392 __hc32 *hw_next; /* (all types) */
393 void *ptr;
394};
395
396/*-------------------------------------------------------------------------*/
397
398/*
399 * EHCI Specification 0.95 Section 3.6
400 * QH: describes control/bulk/interrupt endpoints
401 * See Fig 3-7 "Queue Head Structure Layout".
402 *
403 * These appear in both the async and (for interrupt) periodic schedules.
404 */
405
406/* first part defined by EHCI spec */
407struct fotg210_qh_hw {
408 __hc32 hw_next; /* see EHCI 3.6.1 */
409 __hc32 hw_info1; /* see EHCI 3.6.2 */
410#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
411#define QH_HEAD (1 << 15) /* Head of async reclamation list */
412#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
413#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
414#define QH_LOW_SPEED (1 << 12)
415#define QH_FULL_SPEED (0 << 12)
416#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
417 __hc32 hw_info2; /* see EHCI 3.6.2 */
418#define QH_SMASK 0x000000ff
419#define QH_CMASK 0x0000ff00
420#define QH_HUBADDR 0x007f0000
421#define QH_HUBPORT 0x3f800000
422#define QH_MULT 0xc0000000
423 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
424
425 /* qtd overlay (hardware parts of a struct fotg210_qtd) */
426 __hc32 hw_qtd_next;
427 __hc32 hw_alt_next;
428 __hc32 hw_token;
429 __hc32 hw_buf[5];
430 __hc32 hw_buf_hi[5];
431} __aligned(32);
432
433struct fotg210_qh {
434 struct fotg210_qh_hw *hw; /* Must come first */
435 /* the rest is HCD-private */
436 dma_addr_t qh_dma; /* address of qh */
437 union fotg210_shadow qh_next; /* ptr to qh; or periodic */
438 struct list_head qtd_list; /* sw qtd list */
439 struct list_head intr_node; /* list of intr QHs */
440 struct fotg210_qtd *dummy;
441 struct fotg210_qh *unlink_next; /* next on unlink list */
442
443 unsigned unlink_cycle;
444
445 u8 needs_rescan; /* Dequeue during giveback */
446 u8 qh_state;
447#define QH_STATE_LINKED 1 /* HC sees this */
448#define QH_STATE_UNLINK 2 /* HC may still see this */
449#define QH_STATE_IDLE 3 /* HC doesn't see this */
450#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
451#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
452
453 u8 xacterrs; /* XactErr retry counter */
454#define QH_XACTERR_MAX 32 /* XactErr retry limit */
455
456 /* periodic schedule info */
457 u8 usecs; /* intr bandwidth */
458 u8 gap_uf; /* uframes split/csplit gap */
459 u8 c_usecs; /* ... split completion bw */
460 u16 tt_usecs; /* tt downstream bandwidth */
461 unsigned short period; /* polling interval */
462 unsigned short start; /* where polling starts */
463#define NO_FRAME ((unsigned short)~0) /* pick new start */
464
465 struct usb_device *dev; /* access to TT */
466 unsigned is_out:1; /* bulk or intr OUT */
467 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
468};
469
470/*-------------------------------------------------------------------------*/
471
472/* description of one iso transaction (up to 3 KB data if highspeed) */
473struct fotg210_iso_packet {
474 /* These will be copied to iTD when scheduling */
475 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
476 __hc32 transaction; /* itd->hw_transaction[i] |= */
477 u8 cross; /* buf crosses pages */
478 /* for full speed OUT splits */
479 u32 buf1;
480};
481
482/* temporary schedule data for packets from iso urbs (both speeds)
483 * each packet is one logical usb transaction to the device (not TT),
484 * beginning at stream->next_uframe
485 */
486struct fotg210_iso_sched {
487 struct list_head td_list;
488 unsigned span;
489 struct fotg210_iso_packet packet[0];
490};
491
492/*
493 * fotg210_iso_stream - groups all (s)itds for this endpoint.
494 * acts like a qh would, if EHCI had them for ISO.
495 */
496struct fotg210_iso_stream {
497 /* first field matches fotg210_hq, but is NULL */
498 struct fotg210_qh_hw *hw;
499
500 u8 bEndpointAddress;
501 u8 highspeed;
502 struct list_head td_list; /* queued itds */
503 struct list_head free_list; /* list of unused itds */
504 struct usb_device *udev;
505 struct usb_host_endpoint *ep;
506
507 /* output of (re)scheduling */
508 int next_uframe;
509 __hc32 splits;
510
511 /* the rest is derived from the endpoint descriptor,
512 * trusting urb->interval == f(epdesc->bInterval) and
513 * including the extra info for hw_bufp[0..2]
514 */
515 u8 usecs, c_usecs;
516 u16 interval;
517 u16 tt_usecs;
518 u16 maxp;
519 u16 raw_mask;
520 unsigned bandwidth;
521
522 /* This is used to initialize iTD's hw_bufp fields */
523 __hc32 buf0;
524 __hc32 buf1;
525 __hc32 buf2;
526
527 /* this is used to initialize sITD's tt info */
528 __hc32 address;
529};
530
531/*-------------------------------------------------------------------------*/
532
533/*
534 * EHCI Specification 0.95 Section 3.3
535 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
536 *
537 * Schedule records for high speed iso xfers
538 */
539struct fotg210_itd {
540 /* first part defined by EHCI spec */
541 __hc32 hw_next; /* see EHCI 3.3.1 */
542 __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */
543#define FOTG210_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
544#define FOTG210_ISOC_BUF_ERR (1<<30) /* Data buffer error */
545#define FOTG210_ISOC_BABBLE (1<<29) /* babble detected */
546#define FOTG210_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
547#define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
548#define FOTG210_ITD_IOC (1 << 15) /* interrupt on complete */
549
550#define ITD_ACTIVE(fotg210) cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
551
552 __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
553 __hc32 hw_bufp_hi[7]; /* Appendix B */
554
555 /* the rest is HCD-private */
556 dma_addr_t itd_dma; /* for this itd */
557 union fotg210_shadow itd_next; /* ptr to periodic q entry */
558
559 struct urb *urb;
560 struct fotg210_iso_stream *stream; /* endpoint's queue */
561 struct list_head itd_list; /* list of stream's itds */
562
563 /* any/all hw_transactions here may be used by that urb */
564 unsigned frame; /* where scheduled */
565 unsigned pg;
566 unsigned index[8]; /* in urb->iso_frame_desc */
567} __aligned(32);
568
569/*-------------------------------------------------------------------------*/
570
571/*
572 * EHCI Specification 0.96 Section 3.7
573 * Periodic Frame Span Traversal Node (FSTN)
574 *
575 * Manages split interrupt transactions (using TT) that span frame boundaries
576 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
577 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
578 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
579 */
580struct fotg210_fstn {
581 __hc32 hw_next; /* any periodic q entry */
582 __hc32 hw_prev; /* qh or FOTG210_LIST_END */
583
584 /* the rest is HCD-private */
585 dma_addr_t fstn_dma;
586 union fotg210_shadow fstn_next; /* ptr to periodic q entry */
587} __aligned(32);
588
589/*-------------------------------------------------------------------------*/
590
591/* Prepare the PORTSC wakeup flags during controller suspend/resume */
592
593#define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
594 fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup)
595
596#define fotg210_prepare_ports_for_controller_resume(fotg210) \
597 fotg210_adjust_port_wakeup_flags(fotg210, false, false)
598
599/*-------------------------------------------------------------------------*/
600
601/*
602 * Some EHCI controllers have a Transaction Translator built into the
603 * root hub. This is a non-standard feature. Each controller will need
604 * to add code to the following inline functions, and call them as
605 * needed (mostly in root hub code).
606 */
607
608static inline unsigned int
609fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
610{
611 return (readl(&fotg210->regs->otgcsr)
612 & OTGCSR_HOST_SPD_TYP) >> 22;
613}
614
615/* Returns the speed of a device attached to a port on the root hub. */
616static inline unsigned int
617fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
618{
619 switch (fotg210_get_speed(fotg210, portsc)) {
620 case 0:
621 return 0;
622 case 1:
623 return USB_PORT_STAT_LOW_SPEED;
624 case 2:
625 default:
626 return USB_PORT_STAT_HIGH_SPEED;
627 }
628}
629
630/*-------------------------------------------------------------------------*/
631
632#define fotg210_has_fsl_portno_bug(e) (0)
633
634/*
635 * While most USB host controllers implement their registers in
636 * little-endian format, a minority (celleb companion chip) implement
637 * them in big endian format.
638 *
639 * This attempts to support either format at compile time without a
640 * runtime penalty, or both formats with the additional overhead
641 * of checking a flag bit.
642 *
643 */
644
645#define fotg210_big_endian_mmio(e) 0
646#define fotg210_big_endian_capbase(e) 0
647
648static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
649 __u32 __iomem *regs)
650{
651 return readl(regs);
652}
653
654static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
655 const unsigned int val, __u32 __iomem *regs)
656{
657 writel(val, regs);
658}
659
660/* cpu to fotg210 */
661static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
662{
663 return cpu_to_le32(x);
664}
665
666/* fotg210 to cpu */
667static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
668{
669 return le32_to_cpu(x);
670}
671
672static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
673 const __hc32 *x)
674{
675 return le32_to_cpup(x);
676}
677
678/*-------------------------------------------------------------------------*/
679
680static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
681{
682 return fotg210_readl(fotg210, &fotg210->regs->frame_index);
683}
684
685#define fotg210_itdlen(urb, desc, t) ({ \
686 usb_pipein((urb)->pipe) ? \
687 (desc)->length - FOTG210_ITD_LENGTH(t) : \
688 FOTG210_ITD_LENGTH(t); \
689})
690/*-------------------------------------------------------------------------*/
691
692#endif /* __LINUX_FOTG210_H */