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1/*
2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2009 - 2013 NVIDIA Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 */
18
19#include <linux/clk.h>
20#include <linux/dma-mapping.h>
21#include <linux/err.h>
22#include <linux/gpio.h>
23#include <linux/io.h>
24#include <linux/irq.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_gpio.h>
29#include <linux/platform_device.h>
30#include <linux/pm_runtime.h>
31#include <linux/reset.h>
32#include <linux/slab.h>
33#include <linux/usb/ehci_def.h>
34#include <linux/usb/tegra_usb_phy.h>
35#include <linux/usb.h>
36#include <linux/usb/hcd.h>
37#include <linux/usb/otg.h>
38
39#include "ehci.h"
40
41#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
42
43#define TEGRA_USB_DMA_ALIGN 32
44
45#define DRIVER_DESC "Tegra EHCI driver"
46#define DRV_NAME "tegra-ehci"
47
48static struct hc_driver __read_mostly tegra_ehci_hc_driver;
49static bool usb1_reset_attempted;
50
51struct tegra_ehci_soc_config {
52 bool has_hostpc;
53};
54
55struct tegra_ehci_hcd {
56 struct tegra_usb_phy *phy;
57 struct clk *clk;
58 struct reset_control *rst;
59 int port_resuming;
60 bool needs_double_reset;
61 enum tegra_usb_phy_port_speed port_speed;
62};
63
64/*
65 * The 1st USB controller contains some UTMI pad registers that are global for
66 * all the controllers on the chip. Those registers are also cleared when
67 * reset is asserted to the 1st controller. This means that the 1st controller
68 * can only be reset when no other controlled has finished probing. So we'll
69 * reset the 1st controller before doing any other setup on any of the
70 * controllers, and then never again.
71 *
72 * Since this is a PHY issue, the Tegra PHY driver should probably be doing
73 * the resetting of the USB controllers. But to keep compatibility with old
74 * device trees that don't have reset phandles in the PHYs, do it here.
75 * Those old DTs will be vulnerable to total USB breakage if the 1st EHCI
76 * device isn't the first one to finish probing, so warn them.
77 */
78static int tegra_reset_usb_controller(struct platform_device *pdev)
79{
80 struct device_node *phy_np;
81 struct usb_hcd *hcd = platform_get_drvdata(pdev);
82 struct tegra_ehci_hcd *tegra =
83 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
84 bool has_utmi_pad_registers = false;
85
86 phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
87 if (!phy_np)
88 return -ENOENT;
89
90 if (of_property_read_bool(phy_np, "nvidia,has-utmi-pad-registers"))
91 has_utmi_pad_registers = true;
92
93 if (!usb1_reset_attempted) {
94 struct reset_control *usb1_reset;
95
96 if (!has_utmi_pad_registers)
97 usb1_reset = of_reset_control_get(phy_np, "utmi-pads");
98 else
99 usb1_reset = tegra->rst;
100
101 if (IS_ERR(usb1_reset)) {
102 dev_warn(&pdev->dev,
103 "can't get utmi-pads reset from the PHY\n");
104 dev_warn(&pdev->dev,
105 "continuing, but please update your DT\n");
106 } else {
107 reset_control_assert(usb1_reset);
108 udelay(1);
109 reset_control_deassert(usb1_reset);
110
111 if (!has_utmi_pad_registers)
112 reset_control_put(usb1_reset);
113 }
114
115 usb1_reset_attempted = true;
116 }
117
118 if (!has_utmi_pad_registers) {
119 reset_control_assert(tegra->rst);
120 udelay(1);
121 reset_control_deassert(tegra->rst);
122 }
123
124 of_node_put(phy_np);
125
126 return 0;
127}
128
129static int tegra_ehci_internal_port_reset(
130 struct ehci_hcd *ehci,
131 u32 __iomem *portsc_reg
132)
133{
134 u32 temp;
135 unsigned long flags;
136 int retval = 0;
137 int i, tries;
138 u32 saved_usbintr;
139
140 spin_lock_irqsave(&ehci->lock, flags);
141 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
142 /* disable USB interrupt */
143 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
144 spin_unlock_irqrestore(&ehci->lock, flags);
145
146 /*
147 * Here we have to do Port Reset at most twice for
148 * Port Enable bit to be set.
149 */
150 for (i = 0; i < 2; i++) {
151 temp = ehci_readl(ehci, portsc_reg);
152 temp |= PORT_RESET;
153 ehci_writel(ehci, temp, portsc_reg);
154 mdelay(10);
155 temp &= ~PORT_RESET;
156 ehci_writel(ehci, temp, portsc_reg);
157 mdelay(1);
158 tries = 100;
159 do {
160 mdelay(1);
161 /*
162 * Up to this point, Port Enable bit is
163 * expected to be set after 2 ms waiting.
164 * USB1 usually takes extra 45 ms, for safety,
165 * we take 100 ms as timeout.
166 */
167 temp = ehci_readl(ehci, portsc_reg);
168 } while (!(temp & PORT_PE) && tries--);
169 if (temp & PORT_PE)
170 break;
171 }
172 if (i == 2)
173 retval = -ETIMEDOUT;
174
175 /*
176 * Clear Connect Status Change bit if it's set.
177 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
178 */
179 if (temp & PORT_CSC)
180 ehci_writel(ehci, PORT_CSC, portsc_reg);
181
182 /*
183 * Write to clear any interrupt status bits that might be set
184 * during port reset.
185 */
186 temp = ehci_readl(ehci, &ehci->regs->status);
187 ehci_writel(ehci, temp, &ehci->regs->status);
188
189 /* restore original interrupt enable bits */
190 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
191 return retval;
192}
193
194static int tegra_ehci_hub_control(
195 struct usb_hcd *hcd,
196 u16 typeReq,
197 u16 wValue,
198 u16 wIndex,
199 char *buf,
200 u16 wLength
201)
202{
203 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
204 struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
205 u32 __iomem *status_reg;
206 u32 temp;
207 unsigned long flags;
208 int retval = 0;
209
210 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
211
212 spin_lock_irqsave(&ehci->lock, flags);
213
214 if (typeReq == GetPortStatus) {
215 temp = ehci_readl(ehci, status_reg);
216 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
217 /* Resume completed, re-enable disconnect detection */
218 tegra->port_resuming = 0;
219 tegra_usb_phy_postresume(hcd->usb_phy);
220 }
221 }
222
223 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
224 temp = ehci_readl(ehci, status_reg);
225 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
226 retval = -EPIPE;
227 goto done;
228 }
229
230 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
231 temp |= PORT_WKDISC_E | PORT_WKOC_E;
232 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
233
234 /*
235 * If a transaction is in progress, there may be a delay in
236 * suspending the port. Poll until the port is suspended.
237 */
238 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
239 PORT_SUSPEND, 5000))
240 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
241
242 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
243 goto done;
244 }
245
246 /* For USB1 port we need to issue Port Reset twice internally */
247 if (tegra->needs_double_reset &&
248 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
249 spin_unlock_irqrestore(&ehci->lock, flags);
250 return tegra_ehci_internal_port_reset(ehci, status_reg);
251 }
252
253 /*
254 * Tegra host controller will time the resume operation to clear the bit
255 * when the port control state switches to HS or FS Idle. This behavior
256 * is different from EHCI where the host controller driver is required
257 * to set this bit to a zero after the resume duration is timed in the
258 * driver.
259 */
260 else if (typeReq == ClearPortFeature &&
261 wValue == USB_PORT_FEAT_SUSPEND) {
262 temp = ehci_readl(ehci, status_reg);
263 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
264 retval = -EPIPE;
265 goto done;
266 }
267
268 if (!(temp & PORT_SUSPEND))
269 goto done;
270
271 /* Disable disconnect detection during port resume */
272 tegra_usb_phy_preresume(hcd->usb_phy);
273
274 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
275
276 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
277 /* start resume signalling */
278 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
279 set_bit(wIndex-1, &ehci->resuming_ports);
280
281 spin_unlock_irqrestore(&ehci->lock, flags);
282 msleep(20);
283 spin_lock_irqsave(&ehci->lock, flags);
284
285 /* Poll until the controller clears RESUME and SUSPEND */
286 if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
287 pr_err("%s: timeout waiting for RESUME\n", __func__);
288 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
289 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
290
291 ehci->reset_done[wIndex-1] = 0;
292 clear_bit(wIndex-1, &ehci->resuming_ports);
293
294 tegra->port_resuming = 1;
295 goto done;
296 }
297
298 spin_unlock_irqrestore(&ehci->lock, flags);
299
300 /* Handle the hub control events here */
301 return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
302
303done:
304 spin_unlock_irqrestore(&ehci->lock, flags);
305 return retval;
306}
307
308struct dma_aligned_buffer {
309 void *kmalloc_ptr;
310 void *old_xfer_buffer;
311 u8 data[0];
312};
313
314static void free_dma_aligned_buffer(struct urb *urb)
315{
316 struct dma_aligned_buffer *temp;
317 size_t length;
318
319 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
320 return;
321
322 temp = container_of(urb->transfer_buffer,
323 struct dma_aligned_buffer, data);
324
325 if (usb_urb_dir_in(urb)) {
326 if (usb_pipeisoc(urb->pipe))
327 length = urb->transfer_buffer_length;
328 else
329 length = urb->actual_length;
330
331 memcpy(temp->old_xfer_buffer, temp->data, length);
332 }
333 urb->transfer_buffer = temp->old_xfer_buffer;
334 kfree(temp->kmalloc_ptr);
335
336 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
337}
338
339static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
340{
341 struct dma_aligned_buffer *temp, *kmalloc_ptr;
342 size_t kmalloc_size;
343
344 if (urb->num_sgs || urb->sg ||
345 urb->transfer_buffer_length == 0 ||
346 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
347 return 0;
348
349 /* Allocate a buffer with enough padding for alignment */
350 kmalloc_size = urb->transfer_buffer_length +
351 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
352
353 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
354 if (!kmalloc_ptr)
355 return -ENOMEM;
356
357 /* Position our struct dma_aligned_buffer such that data is aligned */
358 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
359 temp->kmalloc_ptr = kmalloc_ptr;
360 temp->old_xfer_buffer = urb->transfer_buffer;
361 if (usb_urb_dir_out(urb))
362 memcpy(temp->data, urb->transfer_buffer,
363 urb->transfer_buffer_length);
364 urb->transfer_buffer = temp->data;
365
366 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
367
368 return 0;
369}
370
371static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
372 gfp_t mem_flags)
373{
374 int ret;
375
376 ret = alloc_dma_aligned_buffer(urb, mem_flags);
377 if (ret)
378 return ret;
379
380 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
381 if (ret)
382 free_dma_aligned_buffer(urb);
383
384 return ret;
385}
386
387static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
388{
389 usb_hcd_unmap_urb_for_dma(hcd, urb);
390 free_dma_aligned_buffer(urb);
391}
392
393static const struct tegra_ehci_soc_config tegra30_soc_config = {
394 .has_hostpc = true,
395};
396
397static const struct tegra_ehci_soc_config tegra20_soc_config = {
398 .has_hostpc = false,
399};
400
401static const struct of_device_id tegra_ehci_of_match[] = {
402 { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
403 { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
404 { },
405};
406
407static int tegra_ehci_probe(struct platform_device *pdev)
408{
409 const struct of_device_id *match;
410 const struct tegra_ehci_soc_config *soc_config;
411 struct resource *res;
412 struct usb_hcd *hcd;
413 struct ehci_hcd *ehci;
414 struct tegra_ehci_hcd *tegra;
415 int err = 0;
416 int irq;
417 struct usb_phy *u_phy;
418
419 match = of_match_device(tegra_ehci_of_match, &pdev->dev);
420 if (!match) {
421 dev_err(&pdev->dev, "Error: No device match found\n");
422 return -ENODEV;
423 }
424 soc_config = match->data;
425
426 /* Right now device-tree probed devices don't get dma_mask set.
427 * Since shared usb code relies on it, set it here for now.
428 * Once we have dma capability bindings this can go away.
429 */
430 err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
431 if (err)
432 return err;
433
434 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
435 dev_name(&pdev->dev));
436 if (!hcd) {
437 dev_err(&pdev->dev, "Unable to create HCD\n");
438 return -ENOMEM;
439 }
440 platform_set_drvdata(pdev, hcd);
441 ehci = hcd_to_ehci(hcd);
442 tegra = (struct tegra_ehci_hcd *)ehci->priv;
443
444 hcd->has_tt = 1;
445
446 tegra->clk = devm_clk_get(&pdev->dev, NULL);
447 if (IS_ERR(tegra->clk)) {
448 dev_err(&pdev->dev, "Can't get ehci clock\n");
449 err = PTR_ERR(tegra->clk);
450 goto cleanup_hcd_create;
451 }
452
453 tegra->rst = devm_reset_control_get(&pdev->dev, "usb");
454 if (IS_ERR(tegra->rst)) {
455 dev_err(&pdev->dev, "Can't get ehci reset\n");
456 err = PTR_ERR(tegra->rst);
457 goto cleanup_hcd_create;
458 }
459
460 err = clk_prepare_enable(tegra->clk);
461 if (err)
462 goto cleanup_hcd_create;
463
464 err = tegra_reset_usb_controller(pdev);
465 if (err)
466 goto cleanup_clk_en;
467
468 u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
469 if (IS_ERR(u_phy)) {
470 err = -EPROBE_DEFER;
471 goto cleanup_clk_en;
472 }
473 hcd->usb_phy = u_phy;
474
475 tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
476 "nvidia,needs-double-reset");
477
478 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
479 hcd->regs = devm_ioremap_resource(&pdev->dev, res);
480 if (IS_ERR(hcd->regs)) {
481 err = PTR_ERR(hcd->regs);
482 goto cleanup_clk_en;
483 }
484 hcd->rsrc_start = res->start;
485 hcd->rsrc_len = resource_size(res);
486
487 ehci->caps = hcd->regs + 0x100;
488 ehci->has_hostpc = soc_config->has_hostpc;
489
490 err = usb_phy_init(hcd->usb_phy);
491 if (err) {
492 dev_err(&pdev->dev, "Failed to initialize phy\n");
493 goto cleanup_clk_en;
494 }
495
496 u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
497 GFP_KERNEL);
498 if (!u_phy->otg) {
499 err = -ENOMEM;
500 goto cleanup_phy;
501 }
502 u_phy->otg->host = hcd_to_bus(hcd);
503
504 err = usb_phy_set_suspend(hcd->usb_phy, 0);
505 if (err) {
506 dev_err(&pdev->dev, "Failed to power on the phy\n");
507 goto cleanup_phy;
508 }
509
510 irq = platform_get_irq(pdev, 0);
511 if (!irq) {
512 dev_err(&pdev->dev, "Failed to get IRQ\n");
513 err = -ENODEV;
514 goto cleanup_phy;
515 }
516
517 otg_set_host(u_phy->otg, &hcd->self);
518
519 err = usb_add_hcd(hcd, irq, IRQF_SHARED);
520 if (err) {
521 dev_err(&pdev->dev, "Failed to add USB HCD\n");
522 goto cleanup_otg_set_host;
523 }
524 device_wakeup_enable(hcd->self.controller);
525
526 return err;
527
528cleanup_otg_set_host:
529 otg_set_host(u_phy->otg, NULL);
530cleanup_phy:
531 usb_phy_shutdown(hcd->usb_phy);
532cleanup_clk_en:
533 clk_disable_unprepare(tegra->clk);
534cleanup_hcd_create:
535 usb_put_hcd(hcd);
536 return err;
537}
538
539static int tegra_ehci_remove(struct platform_device *pdev)
540{
541 struct usb_hcd *hcd = platform_get_drvdata(pdev);
542 struct tegra_ehci_hcd *tegra =
543 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
544
545 otg_set_host(hcd->usb_phy->otg, NULL);
546
547 usb_phy_shutdown(hcd->usb_phy);
548 usb_remove_hcd(hcd);
549
550 clk_disable_unprepare(tegra->clk);
551
552 usb_put_hcd(hcd);
553
554 return 0;
555}
556
557static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
558{
559 struct usb_hcd *hcd = platform_get_drvdata(pdev);
560
561 if (hcd->driver->shutdown)
562 hcd->driver->shutdown(hcd);
563}
564
565static struct platform_driver tegra_ehci_driver = {
566 .probe = tegra_ehci_probe,
567 .remove = tegra_ehci_remove,
568 .shutdown = tegra_ehci_hcd_shutdown,
569 .driver = {
570 .name = DRV_NAME,
571 .of_match_table = tegra_ehci_of_match,
572 }
573};
574
575static int tegra_ehci_reset(struct usb_hcd *hcd)
576{
577 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
578 int retval;
579 int txfifothresh;
580
581 retval = ehci_setup(hcd);
582 if (retval)
583 return retval;
584
585 /*
586 * We should really pull this value out of tegra_ehci_soc_config, but
587 * to avoid needing access to it, make use of the fact that Tegra20 is
588 * the only one so far that needs a value of 10, and Tegra20 is the
589 * only one which doesn't set has_hostpc.
590 */
591 txfifothresh = ehci->has_hostpc ? 0x10 : 10;
592 ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
593
594 return 0;
595}
596
597static const struct ehci_driver_overrides tegra_overrides __initconst = {
598 .extra_priv_size = sizeof(struct tegra_ehci_hcd),
599 .reset = tegra_ehci_reset,
600};
601
602static int __init ehci_tegra_init(void)
603{
604 if (usb_disabled())
605 return -ENODEV;
606
607 pr_info(DRV_NAME ": " DRIVER_DESC "\n");
608
609 ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
610
611 /*
612 * The Tegra HW has some unusual quirks, which require Tegra-specific
613 * workarounds. We override certain hc_driver functions here to
614 * achieve that. We explicitly do not enhance ehci_driver_overrides to
615 * allow this more easily, since this is an unusual case, and we don't
616 * want to encourage others to override these functions by making it
617 * too easy.
618 */
619
620 tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
621 tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
622 tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
623
624 return platform_driver_register(&tegra_ehci_driver);
625}
626module_init(ehci_tegra_init);
627
628static void __exit ehci_tegra_cleanup(void)
629{
630 platform_driver_unregister(&tegra_ehci_driver);
631}
632module_exit(ehci_tegra_cleanup);
633
634MODULE_DESCRIPTION(DRIVER_DESC);
635MODULE_LICENSE("GPL");
636MODULE_ALIAS("platform:" DRV_NAME);
637MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);