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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9
10/*
11 * This file contains a module version of the ioc4 serial driver. This
12 * includes all the support functions needed (support functions, etc.)
13 * and the serial driver itself.
14 */
15#include <linux/errno.h>
16#include <linux/tty.h>
17#include <linux/tty_flip.h>
18#include <linux/serial.h>
19#include <linux/circ_buf.h>
20#include <linux/serial_reg.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/ioc4.h>
24#include <linux/serial_core.h>
25#include <linux/slab.h>
26
27/*
28 * interesting things about the ioc4
29 */
30
31#define IOC4_NUM_SERIAL_PORTS 4 /* max ports per card */
32#define IOC4_NUM_CARDS 8 /* max cards per partition */
33
34#define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \
35 (_n == 1) ? (IOC4_SIO_IR_S1) : \
36 (_n == 2) ? (IOC4_SIO_IR_S2) : \
37 (IOC4_SIO_IR_S3)
38
39#define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
40 (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
41 (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
42 (IOC4_OTHER_IR_S3_MEMERR)
43
44
45/*
46 * All IOC4 registers are 32 bits wide.
47 */
48
49/*
50 * PCI Memory Space Map
51 */
52#define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */
53#define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
54#define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
55#define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
56#define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
57#define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
58#define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
59
60/* Interrupt types */
61#define IOC4_SIO_INTR_TYPE 0
62#define IOC4_OTHER_INTR_TYPE 1
63#define IOC4_NUM_INTR_TYPES 2
64
65/* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */
66#define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */
67#define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */
68#define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */
69#define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */
70#define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */
71#define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */
72#define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */
73#define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */
74#define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */
75#define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */
76#define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */
77#define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */
78#define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */
79#define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */
80#define IOC4_SIO_IR_S1_INT 0x00004000 /* */
81#define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */
82#define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */
83#define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */
84#define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */
85#define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */
86#define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */
87#define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */
88#define IOC4_SIO_IR_S2_INT 0x00400000 /* */
89#define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */
90#define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */
91#define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */
92#define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */
93#define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */
94#define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */
95#define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */
96#define IOC4_SIO_IR_S3_INT 0x40000000 /* */
97#define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */
98
99/* Per device interrupt masks */
100#define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
101 IOC4_SIO_IR_S0_RX_FULL | \
102 IOC4_SIO_IR_S0_RX_HIGH | \
103 IOC4_SIO_IR_S0_RX_TIMER | \
104 IOC4_SIO_IR_S0_DELTA_DCD | \
105 IOC4_SIO_IR_S0_DELTA_CTS | \
106 IOC4_SIO_IR_S0_INT | \
107 IOC4_SIO_IR_S0_TX_EXPLICIT)
108#define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
109 IOC4_SIO_IR_S1_RX_FULL | \
110 IOC4_SIO_IR_S1_RX_HIGH | \
111 IOC4_SIO_IR_S1_RX_TIMER | \
112 IOC4_SIO_IR_S1_DELTA_DCD | \
113 IOC4_SIO_IR_S1_DELTA_CTS | \
114 IOC4_SIO_IR_S1_INT | \
115 IOC4_SIO_IR_S1_TX_EXPLICIT)
116#define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
117 IOC4_SIO_IR_S2_RX_FULL | \
118 IOC4_SIO_IR_S2_RX_HIGH | \
119 IOC4_SIO_IR_S2_RX_TIMER | \
120 IOC4_SIO_IR_S2_DELTA_DCD | \
121 IOC4_SIO_IR_S2_DELTA_CTS | \
122 IOC4_SIO_IR_S2_INT | \
123 IOC4_SIO_IR_S2_TX_EXPLICIT)
124#define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
125 IOC4_SIO_IR_S3_RX_FULL | \
126 IOC4_SIO_IR_S3_RX_HIGH | \
127 IOC4_SIO_IR_S3_RX_TIMER | \
128 IOC4_SIO_IR_S3_DELTA_DCD | \
129 IOC4_SIO_IR_S3_DELTA_CTS | \
130 IOC4_SIO_IR_S3_INT | \
131 IOC4_SIO_IR_S3_TX_EXPLICIT)
132
133/* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */
134#define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */
135#define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */
136#define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */
137#define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */
138#define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */
139#define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */
140#define IOC4_OTHER_IR_KBD_INT 0x00000040 /* Keyboard/mouse */
141#define IOC4_OTHER_IR_RESERVED 0x007fff80 /* Reserved */
142#define IOC4_OTHER_IR_RT_INT 0x00800000 /* INT_OUT section output */
143#define IOC4_OTHER_IR_GEN_INT 0xff000000 /* Generic pins */
144
145#define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \
146 IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR)
147
148/* Bitmasks for IOC4_SIO_CR */
149#define IOC4_SIO_CR_CMD_PULSE_SHIFT 0 /* byte bus strobe shift */
150#define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
151#define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
152#define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
153#define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
154#define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
155#define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
156#define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
157#define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
158#define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among
159 serial ports (ro) */
160/* Defs for some of the generic I/O pins */
161#define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0
162 mode sel */
163#define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1
164 mode sel */
165#define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2
166 mode sel */
167#define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3
168 mode sel */
169
170#define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling
171 uart 0 mode select */
172#define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling
173 uart 1 mode select */
174#define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling
175 uart 2 mode select */
176#define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling
177 uart 3 mode select */
178
179/* Bitmasks for serial RX status byte */
180#define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */
181#define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */
182#define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */
183#define IOC4_RXSB_BREAK 0x08 /* Break character */
184#define IOC4_RXSB_CTS 0x10 /* State of CTS */
185#define IOC4_RXSB_DCD 0x20 /* State of DCD */
186#define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */
187#define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR
188 * & BREAK valid */
189
190/* Bitmasks for serial TX control byte */
191#define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */
192#define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */
193#define IOC4_TXCB_VALID 0x40 /* Byte is valid */
194#define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control reg */
195#define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */
196
197/* Bitmasks for IOC4_SBBR_L */
198#define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
199
200/* Bitmasks for IOC4_SSCR_<3:0> */
201#define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */
202#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
203#define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */
204#define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */
205#define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */
206#define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */
207#define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */
208#define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */
209#define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */
210#define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */
211#define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */
212
213/* All producer/comsumer pointers are the same bitfield */
214#define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */
215#define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */
216#define IOC4_PROD_CONS_PTR_OFF 3
217
218/* Bitmasks for IOC4_SRCIR_<3:0> */
219#define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */
220
221/* Bitmasks for IOC4_SHADOW_<3:0> */
222#define IOC4_SHADOW_DR 0x00000001 /* Data ready */
223#define IOC4_SHADOW_OE 0x00000002 /* Overrun error */
224#define IOC4_SHADOW_PE 0x00000004 /* Parity error */
225#define IOC4_SHADOW_FE 0x00000008 /* Framing error */
226#define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */
227#define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */
228#define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */
229#define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */
230#define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */
231#define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */
232#define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */
233#define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */
234#define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */
235#define IOC4_SHADOW_RTS 0x02000000 /* Request to send */
236#define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
237#define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
238#define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */
239
240/* Bitmasks for IOC4_SRTR_<3:0> */
241#define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */
242#define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */
243#define IOC4_SRTR_CNT_VAL_SHIFT 16
244#define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */
245
246/* Serial port register map used for DMA and PIO serial I/O */
247struct ioc4_serialregs {
248 uint32_t sscr;
249 uint32_t stpir;
250 uint32_t stcir;
251 uint32_t srpir;
252 uint32_t srcir;
253 uint32_t srtr;
254 uint32_t shadow;
255};
256
257/* IOC4 UART register map */
258struct ioc4_uartregs {
259 char i4u_lcr;
260 union {
261 char iir; /* read only */
262 char fcr; /* write only */
263 } u3;
264 union {
265 char ier; /* DLAB == 0 */
266 char dlm; /* DLAB == 1 */
267 } u2;
268 union {
269 char rbr; /* read only, DLAB == 0 */
270 char thr; /* write only, DLAB == 0 */
271 char dll; /* DLAB == 1 */
272 } u1;
273 char i4u_scr;
274 char i4u_msr;
275 char i4u_lsr;
276 char i4u_mcr;
277};
278
279/* short names */
280#define i4u_dll u1.dll
281#define i4u_ier u2.ier
282#define i4u_dlm u2.dlm
283#define i4u_fcr u3.fcr
284
285/* Serial port registers used for DMA serial I/O */
286struct ioc4_serial {
287 uint32_t sbbr01_l;
288 uint32_t sbbr01_h;
289 uint32_t sbbr23_l;
290 uint32_t sbbr23_h;
291
292 struct ioc4_serialregs port_0;
293 struct ioc4_serialregs port_1;
294 struct ioc4_serialregs port_2;
295 struct ioc4_serialregs port_3;
296 struct ioc4_uartregs uart_0;
297 struct ioc4_uartregs uart_1;
298 struct ioc4_uartregs uart_2;
299 struct ioc4_uartregs uart_3;
300};
301
302/* UART clock speed */
303#define IOC4_SER_XIN_CLK_66 66666667
304#define IOC4_SER_XIN_CLK_33 33333333
305
306#define IOC4_W_IES 0
307#define IOC4_W_IEC 1
308
309typedef void ioc4_intr_func_f(void *, uint32_t);
310typedef ioc4_intr_func_f *ioc4_intr_func_t;
311
312static unsigned int Num_of_ioc4_cards;
313
314/* defining this will get you LOTS of great debug info */
315//#define DEBUG_INTERRUPTS
316#define DPRINT_CONFIG(_x...) ;
317//#define DPRINT_CONFIG(_x...) printk _x
318
319/* number of characters left in xmit buffer before we ask for more */
320#define WAKEUP_CHARS 256
321
322/* number of characters we want to transmit to the lower level at a time */
323#define IOC4_MAX_CHARS 256
324#define IOC4_FIFO_CHARS 255
325
326/* Device name we're using */
327#define DEVICE_NAME_RS232 "ttyIOC"
328#define DEVICE_NAME_RS422 "ttyAIOC"
329#define DEVICE_MAJOR 204
330#define DEVICE_MINOR_RS232 50
331#define DEVICE_MINOR_RS422 84
332
333
334/* register offsets */
335#define IOC4_SERIAL_OFFSET 0x300
336
337/* flags for next_char_state */
338#define NCS_BREAK 0x1
339#define NCS_PARITY 0x2
340#define NCS_FRAMING 0x4
341#define NCS_OVERRUN 0x8
342
343/* cause we need SOME parameters ... */
344#define MIN_BAUD_SUPPORTED 1200
345#define MAX_BAUD_SUPPORTED 115200
346
347/* protocol types supported */
348#define PROTO_RS232 3
349#define PROTO_RS422 7
350
351/* Notification types */
352#define N_DATA_READY 0x01
353#define N_OUTPUT_LOWAT 0x02
354#define N_BREAK 0x04
355#define N_PARITY_ERROR 0x08
356#define N_FRAMING_ERROR 0x10
357#define N_OVERRUN_ERROR 0x20
358#define N_DDCD 0x40
359#define N_DCTS 0x80
360
361#define N_ALL_INPUT (N_DATA_READY | N_BREAK | \
362 N_PARITY_ERROR | N_FRAMING_ERROR | \
363 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
364
365#define N_ALL_OUTPUT N_OUTPUT_LOWAT
366
367#define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
368
369#define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \
370 N_PARITY_ERROR | N_FRAMING_ERROR | \
371 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
372
373#define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16))
374#define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
375
376/* Some masks */
377#define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
378 | UART_LCR_WLEN7 | UART_LCR_WLEN8)
379#define LCR_MASK_STOP_BITS (UART_LCR_STOP)
380
381#define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb)
382#define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw)
383
384/* Default to 4k buffers */
385#ifdef IOC4_1K_BUFFERS
386#define RING_BUF_SIZE 1024
387#define IOC4_BUF_SIZE_BIT 0
388#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
389#else
390#define RING_BUF_SIZE 4096
391#define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
392#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
393#endif
394
395#define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
396
397/*
398 * This is the entry saved by the driver - one per card
399 */
400
401#define UART_PORT_MIN 0
402#define UART_PORT_RS232 UART_PORT_MIN
403#define UART_PORT_RS422 1
404#define UART_PORT_COUNT 2 /* one for each mode */
405
406struct ioc4_control {
407 int ic_irq;
408 struct {
409 /* uart ports are allocated here - 1 for rs232, 1 for rs422 */
410 struct uart_port icp_uart_port[UART_PORT_COUNT];
411 /* Handy reference material */
412 struct ioc4_port *icp_port;
413 } ic_port[IOC4_NUM_SERIAL_PORTS];
414 struct ioc4_soft *ic_soft;
415};
416
417/*
418 * per-IOC4 data structure
419 */
420#define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t))
421struct ioc4_soft {
422 struct ioc4_misc_regs __iomem *is_ioc4_misc_addr;
423 struct ioc4_serial __iomem *is_ioc4_serial_addr;
424
425 /* Each interrupt type has an entry in the array */
426 struct ioc4_intr_type {
427
428 /*
429 * Each in-use entry in this array contains at least
430 * one nonzero bit in sd_bits; no two entries in this
431 * array have overlapping sd_bits values.
432 */
433 struct ioc4_intr_info {
434 uint32_t sd_bits;
435 ioc4_intr_func_f *sd_intr;
436 void *sd_info;
437 } is_intr_info[MAX_IOC4_INTR_ENTS];
438
439 /* Number of entries active in the above array */
440 atomic_t is_num_intrs;
441 } is_intr_type[IOC4_NUM_INTR_TYPES];
442
443 /* is_ir_lock must be held while
444 * modifying sio_ie values, so
445 * we can be sure that sio_ie is
446 * not changing when we read it
447 * along with sio_ir.
448 */
449 spinlock_t is_ir_lock; /* SIO_IE[SC] mod lock */
450};
451
452/* Local port info for each IOC4 serial ports */
453struct ioc4_port {
454 struct uart_port *ip_port; /* current active port ptr */
455 /* Ptrs for all ports */
456 struct uart_port *ip_all_ports[UART_PORT_COUNT];
457 /* Back ptrs for this port */
458 struct ioc4_control *ip_control;
459 struct pci_dev *ip_pdev;
460 struct ioc4_soft *ip_ioc4_soft;
461
462 /* pci mem addresses */
463 struct ioc4_misc_regs __iomem *ip_mem;
464 struct ioc4_serial __iomem *ip_serial;
465 struct ioc4_serialregs __iomem *ip_serial_regs;
466 struct ioc4_uartregs __iomem *ip_uart_regs;
467
468 /* Ring buffer page for this port */
469 dma_addr_t ip_dma_ringbuf;
470 /* vaddr of ring buffer */
471 struct ring_buffer *ip_cpu_ringbuf;
472
473 /* Rings for this port */
474 struct ring *ip_inring;
475 struct ring *ip_outring;
476
477 /* Hook to port specific values */
478 struct hooks *ip_hooks;
479
480 spinlock_t ip_lock;
481
482 /* Various rx/tx parameters */
483 int ip_baud;
484 int ip_tx_lowat;
485 int ip_rx_timeout;
486
487 /* Copy of notification bits */
488 int ip_notify;
489
490 /* Shadow copies of various registers so we don't need to PIO
491 * read them constantly
492 */
493 uint32_t ip_ienb; /* Enabled interrupts */
494 uint32_t ip_sscr;
495 uint32_t ip_tx_prod;
496 uint32_t ip_rx_cons;
497 int ip_pci_bus_speed;
498 unsigned char ip_flags;
499};
500
501/* tx low water mark. We need to notify the driver whenever tx is getting
502 * close to empty so it can refill the tx buffer and keep things going.
503 * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll
504 * have no trouble getting in more chars in time (I certainly hope so).
505 */
506#define TX_LOWAT_LATENCY 1000
507#define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
508#define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
509
510/* Flags per port */
511#define INPUT_HIGH 0x01
512#define DCD_ON 0x02
513#define LOWAT_WRITTEN 0x04
514#define READ_ABORTED 0x08
515#define PORT_ACTIVE 0x10
516#define PORT_INACTIVE 0 /* This is the value when "off" */
517
518
519/* Since each port has different register offsets and bitmasks
520 * for everything, we'll store those that we need in tables so we
521 * don't have to be constantly checking the port we are dealing with.
522 */
523struct hooks {
524 uint32_t intr_delta_dcd;
525 uint32_t intr_delta_cts;
526 uint32_t intr_tx_mt;
527 uint32_t intr_rx_timer;
528 uint32_t intr_rx_high;
529 uint32_t intr_tx_explicit;
530 uint32_t intr_dma_error;
531 uint32_t intr_clear;
532 uint32_t intr_all;
533 int rs422_select_pin;
534};
535
536static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = {
537 /* Values for port 0 */
538 {
539 IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS,
540 IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER,
541 IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT,
542 IOC4_OTHER_IR_S0_MEMERR,
543 (IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL |
544 IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER |
545 IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS |
546 IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT),
547 IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN,
548 },
549
550 /* Values for port 1 */
551 {
552 IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS,
553 IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER,
554 IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT,
555 IOC4_OTHER_IR_S1_MEMERR,
556 (IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL |
557 IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER |
558 IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS |
559 IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT),
560 IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN,
561 },
562
563 /* Values for port 2 */
564 {
565 IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS,
566 IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER,
567 IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT,
568 IOC4_OTHER_IR_S2_MEMERR,
569 (IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL |
570 IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER |
571 IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS |
572 IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT),
573 IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN,
574 },
575
576 /* Values for port 3 */
577 {
578 IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS,
579 IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER,
580 IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT,
581 IOC4_OTHER_IR_S3_MEMERR,
582 (IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL |
583 IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER |
584 IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS |
585 IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT),
586 IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN,
587 }
588};
589
590/* A ring buffer entry */
591struct ring_entry {
592 union {
593 struct {
594 uint32_t alldata;
595 uint32_t allsc;
596 } all;
597 struct {
598 char data[4]; /* data bytes */
599 char sc[4]; /* status/control */
600 } s;
601 } u;
602};
603
604/* Test the valid bits in any of the 4 sc chars using "allsc" member */
605#define RING_ANY_VALID \
606 ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
607
608#define ring_sc u.s.sc
609#define ring_data u.s.data
610#define ring_allsc u.all.allsc
611
612/* Number of entries per ring buffer. */
613#define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
614
615/* An individual ring */
616struct ring {
617 struct ring_entry entries[ENTRIES_PER_RING];
618};
619
620/* The whole enchilada */
621struct ring_buffer {
622 struct ring TX_0_OR_2;
623 struct ring RX_0_OR_2;
624 struct ring TX_1_OR_3;
625 struct ring RX_1_OR_3;
626};
627
628/* Get a ring from a port struct */
629#define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
630
631/* Infinite loop detection.
632 */
633#define MAXITER 10000000
634
635/* Prototypes */
636static void receive_chars(struct uart_port *);
637static void handle_intr(void *arg, uint32_t sio_ir);
638
639/*
640 * port_is_active - determines if this port is currently active
641 * @port: ptr to soft struct for this port
642 * @uart_port: uart port to test for
643 */
644static inline int port_is_active(struct ioc4_port *port,
645 struct uart_port *uart_port)
646{
647 if (port) {
648 if ((port->ip_flags & PORT_ACTIVE)
649 && (port->ip_port == uart_port))
650 return 1;
651 }
652 return 0;
653}
654
655
656/**
657 * write_ireg - write the interrupt regs
658 * @ioc4_soft: ptr to soft struct for this port
659 * @val: value to write
660 * @which: which register
661 * @type: which ireg set
662 */
663static inline void
664write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type)
665{
666 struct ioc4_misc_regs __iomem *mem = ioc4_soft->is_ioc4_misc_addr;
667 unsigned long flags;
668
669 spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags);
670
671 switch (type) {
672 case IOC4_SIO_INTR_TYPE:
673 switch (which) {
674 case IOC4_W_IES:
675 writel(val, &mem->sio_ies.raw);
676 break;
677
678 case IOC4_W_IEC:
679 writel(val, &mem->sio_iec.raw);
680 break;
681 }
682 break;
683
684 case IOC4_OTHER_INTR_TYPE:
685 switch (which) {
686 case IOC4_W_IES:
687 writel(val, &mem->other_ies.raw);
688 break;
689
690 case IOC4_W_IEC:
691 writel(val, &mem->other_iec.raw);
692 break;
693 }
694 break;
695
696 default:
697 break;
698 }
699 spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags);
700}
701
702/**
703 * set_baud - Baud rate setting code
704 * @port: port to set
705 * @baud: baud rate to use
706 */
707static int set_baud(struct ioc4_port *port, int baud)
708{
709 int actual_baud;
710 int diff;
711 int lcr;
712 unsigned short divisor;
713 struct ioc4_uartregs __iomem *uart;
714
715 divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed);
716 if (!divisor)
717 return 1;
718 actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed);
719
720 diff = actual_baud - baud;
721 if (diff < 0)
722 diff = -diff;
723
724 /* If we're within 1%, we've found a match */
725 if (diff * 100 > actual_baud)
726 return 1;
727
728 uart = port->ip_uart_regs;
729 lcr = readb(&uart->i4u_lcr);
730 writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr);
731 writeb((unsigned char)divisor, &uart->i4u_dll);
732 writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm);
733 writeb(lcr, &uart->i4u_lcr);
734 return 0;
735}
736
737
738/**
739 * get_ioc4_port - given a uart port, return the control structure
740 * @port: uart port
741 * @set: set this port as current
742 */
743static struct ioc4_port *get_ioc4_port(struct uart_port *the_port, int set)
744{
745 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
746 struct ioc4_control *control = idd->idd_serial_data;
747 struct ioc4_port *port;
748 int port_num, port_type;
749
750 if (control) {
751 for ( port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS;
752 port_num++ ) {
753 port = control->ic_port[port_num].icp_port;
754 if (!port)
755 continue;
756 for (port_type = UART_PORT_MIN;
757 port_type < UART_PORT_COUNT;
758 port_type++) {
759 if (the_port == port->ip_all_ports
760 [port_type]) {
761 /* set local copy */
762 if (set) {
763 port->ip_port = the_port;
764 }
765 return port;
766 }
767 }
768 }
769 }
770 return NULL;
771}
772
773/* The IOC4 hardware provides no atomic way to determine if interrupts
774 * are pending since two reads are required to do so. The handler must
775 * read the SIO_IR and the SIO_IES, and take the logical and of the
776 * two. When this value is zero, all interrupts have been serviced and
777 * the handler may return.
778 *
779 * This has the unfortunate "hole" that, if some other CPU or
780 * some other thread or some higher level interrupt manages to
781 * modify SIO_IE between our reads of SIO_IR and SIO_IE, we may
782 * think we have observed SIO_IR&SIO_IE==0 when in fact this
783 * condition never really occurred.
784 *
785 * To solve this, we use a simple spinlock that must be held
786 * whenever modifying SIO_IE; holding this lock while observing
787 * both SIO_IR and SIO_IE guarantees that we do not falsely
788 * conclude that no enabled interrupts are pending.
789 */
790
791static inline uint32_t
792pending_intrs(struct ioc4_soft *soft, int type)
793{
794 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
795 unsigned long flag;
796 uint32_t intrs = 0;
797
798 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
799 || (type == IOC4_OTHER_INTR_TYPE)));
800
801 spin_lock_irqsave(&soft->is_ir_lock, flag);
802
803 switch (type) {
804 case IOC4_SIO_INTR_TYPE:
805 intrs = readl(&mem->sio_ir.raw) & readl(&mem->sio_ies.raw);
806 break;
807
808 case IOC4_OTHER_INTR_TYPE:
809 intrs = readl(&mem->other_ir.raw) & readl(&mem->other_ies.raw);
810
811 /* Don't process any ATA interrupte */
812 intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
813 break;
814
815 default:
816 break;
817 }
818 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
819 return intrs;
820}
821
822/**
823 * port_init - Initialize the sio and ioc4 hardware for a given port
824 * called per port from attach...
825 * @port: port to initialize
826 */
827static int inline port_init(struct ioc4_port *port)
828{
829 uint32_t sio_cr;
830 struct hooks *hooks = port->ip_hooks;
831 struct ioc4_uartregs __iomem *uart;
832
833 /* Idle the IOC4 serial interface */
834 writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
835
836 /* Wait until any pending bus activity for this port has ceased */
837 do
838 sio_cr = readl(&port->ip_mem->sio_cr.raw);
839 while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE));
840
841 /* Finish reset sequence */
842 writel(0, &port->ip_serial_regs->sscr);
843
844 /* Once RESET is done, reload cached tx_prod and rx_cons values
845 * and set rings to empty by making prod == cons
846 */
847 port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
848 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
849 port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
850 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
851
852 /* Disable interrupts for this 16550 */
853 uart = port->ip_uart_regs;
854 writeb(0, &uart->i4u_lcr);
855 writeb(0, &uart->i4u_ier);
856
857 /* Set the default baud */
858 set_baud(port, port->ip_baud);
859
860 /* Set line control to 8 bits no parity */
861 writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr);
862 /* UART_LCR_STOP == 1 stop */
863
864 /* Enable the FIFOs */
865 writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr);
866 /* then reset 16550 FIFOs */
867 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
868 &uart->i4u_fcr);
869
870 /* Clear modem control register */
871 writeb(0, &uart->i4u_mcr);
872
873 /* Clear deltas in modem status register */
874 readb(&uart->i4u_msr);
875
876 /* Only do this once per port pair */
877 if (port->ip_hooks == &hooks_array[0]
878 || port->ip_hooks == &hooks_array[2]) {
879 unsigned long ring_pci_addr;
880 uint32_t __iomem *sbbr_l;
881 uint32_t __iomem *sbbr_h;
882
883 if (port->ip_hooks == &hooks_array[0]) {
884 sbbr_l = &port->ip_serial->sbbr01_l;
885 sbbr_h = &port->ip_serial->sbbr01_h;
886 } else {
887 sbbr_l = &port->ip_serial->sbbr23_l;
888 sbbr_h = &port->ip_serial->sbbr23_h;
889 }
890
891 ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
892 DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
893 __func__, ring_pci_addr));
894
895 writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
896 writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l);
897 }
898
899 /* Set the receive timeout value to 10 msec */
900 writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr);
901
902 /* Set rx threshold, enable DMA */
903 /* Set high water mark at 3/4 of full ring */
904 port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
905 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
906
907 /* Disable and clear all serial related interrupt bits */
908 write_ireg(port->ip_ioc4_soft, hooks->intr_clear,
909 IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
910 port->ip_ienb &= ~hooks->intr_clear;
911 writel(hooks->intr_clear, &port->ip_mem->sio_ir.raw);
912 return 0;
913}
914
915/**
916 * handle_dma_error_intr - service any pending DMA error interrupts for the
917 * given port - 2nd level called via sd_intr
918 * @arg: handler arg
919 * @other_ir: ioc4regs
920 */
921static void handle_dma_error_intr(void *arg, uint32_t other_ir)
922{
923 struct ioc4_port *port = (struct ioc4_port *)arg;
924 struct hooks *hooks = port->ip_hooks;
925 unsigned long flags;
926
927 spin_lock_irqsave(&port->ip_lock, flags);
928
929 /* ACK the interrupt */
930 writel(hooks->intr_dma_error, &port->ip_mem->other_ir.raw);
931
932 if (readl(&port->ip_mem->pci_err_addr_l.raw) & IOC4_PCI_ERR_ADDR_VLD) {
933 printk(KERN_ERR
934 "PCI error address is 0x%llx, "
935 "master is serial port %c %s\n",
936 (((uint64_t)readl(&port->ip_mem->pci_err_addr_h)
937 << 32)
938 | readl(&port->ip_mem->pci_err_addr_l.raw))
939 & IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' +
940 ((char)(readl(&port->ip_mem->pci_err_addr_l.raw) &
941 IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1),
942 (readl(&port->ip_mem->pci_err_addr_l.raw)
943 & IOC4_PCI_ERR_ADDR_MST_TYP_MSK)
944 ? "RX" : "TX");
945
946 if (readl(&port->ip_mem->pci_err_addr_l.raw)
947 & IOC4_PCI_ERR_ADDR_MUL_ERR) {
948 printk(KERN_ERR
949 "Multiple errors occurred\n");
950 }
951 }
952 spin_unlock_irqrestore(&port->ip_lock, flags);
953
954 /* Re-enable DMA error interrupts */
955 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES,
956 IOC4_OTHER_INTR_TYPE);
957}
958
959/**
960 * intr_connect - interrupt connect function
961 * @soft: soft struct for this card
962 * @type: interrupt type
963 * @intrbits: bit pattern to set
964 * @intr: handler function
965 * @info: handler arg
966 */
967static void
968intr_connect(struct ioc4_soft *soft, int type,
969 uint32_t intrbits, ioc4_intr_func_f * intr, void *info)
970{
971 int i;
972 struct ioc4_intr_info *intr_ptr;
973
974 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
975 || (type == IOC4_OTHER_INTR_TYPE)));
976
977 i = atomic_inc_return(&soft-> is_intr_type[type].is_num_intrs) - 1;
978 BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0)));
979
980 /* Save off the lower level interrupt handler */
981 intr_ptr = &soft->is_intr_type[type].is_intr_info[i];
982 intr_ptr->sd_bits = intrbits;
983 intr_ptr->sd_intr = intr;
984 intr_ptr->sd_info = info;
985}
986
987/**
988 * ioc4_intr - Top level IOC4 interrupt handler.
989 * @irq: irq value
990 * @arg: handler arg
991 */
992
993static irqreturn_t ioc4_intr(int irq, void *arg)
994{
995 struct ioc4_soft *soft;
996 uint32_t this_ir, this_mir;
997 int xx, num_intrs = 0;
998 int intr_type;
999 int handled = 0;
1000 struct ioc4_intr_info *intr_info;
1001
1002 soft = arg;
1003 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
1004 num_intrs = (int)atomic_read(
1005 &soft->is_intr_type[intr_type].is_num_intrs);
1006
1007 this_mir = this_ir = pending_intrs(soft, intr_type);
1008
1009 /* Farm out the interrupt to the various drivers depending on
1010 * which interrupt bits are set.
1011 */
1012 for (xx = 0; xx < num_intrs; xx++) {
1013 intr_info = &soft->is_intr_type[intr_type].is_intr_info[xx];
1014 this_mir = this_ir & intr_info->sd_bits;
1015 if (this_mir) {
1016 /* Disable owned interrupts, call handler */
1017 handled++;
1018 write_ireg(soft, intr_info->sd_bits, IOC4_W_IEC,
1019 intr_type);
1020 intr_info->sd_intr(intr_info->sd_info, this_mir);
1021 this_ir &= ~this_mir;
1022 }
1023 }
1024 }
1025#ifdef DEBUG_INTERRUPTS
1026 {
1027 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
1028 unsigned long flag;
1029
1030 spin_lock_irqsave(&soft->is_ir_lock, flag);
1031 printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x "
1032 "other_ir 0x%x other_ies 0x%x mask 0x%x\n",
1033 __func__, __LINE__,
1034 (void *)mem, readl(&mem->sio_ir.raw),
1035 readl(&mem->sio_ies.raw),
1036 readl(&mem->other_ir.raw),
1037 readl(&mem->other_ies.raw),
1038 IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
1039 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
1040 }
1041#endif
1042 return handled ? IRQ_HANDLED : IRQ_NONE;
1043}
1044
1045/**
1046 * ioc4_attach_local - Device initialization.
1047 * Called at *_attach() time for each
1048 * IOC4 with serial ports in the system.
1049 * @idd: Master module data for this IOC4
1050 */
1051static int inline ioc4_attach_local(struct ioc4_driver_data *idd)
1052{
1053 struct ioc4_port *port;
1054 struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
1055 int port_number;
1056 uint16_t ioc4_revid_min = 62;
1057 uint16_t ioc4_revid;
1058 struct pci_dev *pdev = idd->idd_pdev;
1059 struct ioc4_control* control = idd->idd_serial_data;
1060 struct ioc4_soft *soft = control->ic_soft;
1061 void __iomem *ioc4_misc = idd->idd_misc_regs;
1062 void __iomem *ioc4_serial = soft->is_ioc4_serial_addr;
1063
1064 /* IOC4 firmware must be at least rev 62 */
1065 pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
1066
1067 printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid);
1068 if (ioc4_revid < ioc4_revid_min) {
1069 printk(KERN_WARNING
1070 "IOC4 serial not supported on firmware rev %d, "
1071 "please upgrade to rev %d or higher\n",
1072 ioc4_revid, ioc4_revid_min);
1073 return -EPERM;
1074 }
1075 BUG_ON(ioc4_misc == NULL);
1076 BUG_ON(ioc4_serial == NULL);
1077
1078 /* Create port structures for each port */
1079 for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS;
1080 port_number++) {
1081 port = kzalloc(sizeof(struct ioc4_port), GFP_KERNEL);
1082 if (!port) {
1083 printk(KERN_WARNING
1084 "IOC4 serial memory not available for port\n");
1085 goto free;
1086 }
1087 spin_lock_init(&port->ip_lock);
1088
1089 /* we need to remember the previous ones, to point back to
1090 * them farther down - setting up the ring buffers.
1091 */
1092 ports[port_number] = port;
1093
1094 /* Allocate buffers and jumpstart the hardware. */
1095 control->ic_port[port_number].icp_port = port;
1096 port->ip_ioc4_soft = soft;
1097 port->ip_pdev = pdev;
1098 port->ip_ienb = 0;
1099 /* Use baud rate calculations based on detected PCI
1100 * bus speed. Simply test whether the PCI clock is
1101 * running closer to 66MHz or 33MHz.
1102 */
1103 if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) {
1104 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66;
1105 } else {
1106 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33;
1107 }
1108 port->ip_baud = 9600;
1109 port->ip_control = control;
1110 port->ip_mem = ioc4_misc;
1111 port->ip_serial = ioc4_serial;
1112
1113 /* point to the right hook */
1114 port->ip_hooks = &hooks_array[port_number];
1115
1116 /* Get direct hooks to the serial regs and uart regs
1117 * for this port
1118 */
1119 switch (port_number) {
1120 case 0:
1121 port->ip_serial_regs = &(port->ip_serial->port_0);
1122 port->ip_uart_regs = &(port->ip_serial->uart_0);
1123 break;
1124 case 1:
1125 port->ip_serial_regs = &(port->ip_serial->port_1);
1126 port->ip_uart_regs = &(port->ip_serial->uart_1);
1127 break;
1128 case 2:
1129 port->ip_serial_regs = &(port->ip_serial->port_2);
1130 port->ip_uart_regs = &(port->ip_serial->uart_2);
1131 break;
1132 default:
1133 case 3:
1134 port->ip_serial_regs = &(port->ip_serial->port_3);
1135 port->ip_uart_regs = &(port->ip_serial->uart_3);
1136 break;
1137 }
1138
1139 /* ring buffers are 1 to a pair of ports */
1140 if (port_number && (port_number & 1)) {
1141 /* odd use the evens buffer */
1142 port->ip_dma_ringbuf =
1143 ports[port_number - 1]->ip_dma_ringbuf;
1144 port->ip_cpu_ringbuf =
1145 ports[port_number - 1]->ip_cpu_ringbuf;
1146 port->ip_inring = RING(port, RX_1_OR_3);
1147 port->ip_outring = RING(port, TX_1_OR_3);
1148
1149 } else {
1150 if (port->ip_dma_ringbuf == 0) {
1151 port->ip_cpu_ringbuf = pci_alloc_consistent
1152 (pdev, TOTAL_RING_BUF_SIZE,
1153 &port->ip_dma_ringbuf);
1154
1155 }
1156 BUG_ON(!((((int64_t)port->ip_dma_ringbuf) &
1157 (TOTAL_RING_BUF_SIZE - 1)) == 0));
1158 DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1159 "ip_dma_ringbuf 0x%p\n",
1160 __func__,
1161 (void *)port->ip_cpu_ringbuf,
1162 (void *)port->ip_dma_ringbuf));
1163 port->ip_inring = RING(port, RX_0_OR_2);
1164 port->ip_outring = RING(port, TX_0_OR_2);
1165 }
1166 DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1167 __func__,
1168 port_number, (void *)port, (void *)control));
1169 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1170 (void *)port->ip_serial_regs,
1171 (void *)port->ip_uart_regs));
1172
1173 /* Initialize the hardware for IOC4 */
1174 port_init(port);
1175
1176 DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1177 "outring 0x%p\n",
1178 __func__,
1179 port_number, (void *)port,
1180 (void *)port->ip_inring,
1181 (void *)port->ip_outring));
1182
1183 /* Attach interrupt handlers */
1184 intr_connect(soft, IOC4_SIO_INTR_TYPE,
1185 GET_SIO_IR(port_number),
1186 handle_intr, port);
1187
1188 intr_connect(soft, IOC4_OTHER_INTR_TYPE,
1189 GET_OTHER_IR(port_number),
1190 handle_dma_error_intr, port);
1191 }
1192 return 0;
1193
1194free:
1195 while (port_number)
1196 kfree(ports[--port_number]);
1197 return -ENOMEM;
1198}
1199
1200/**
1201 * enable_intrs - enable interrupts
1202 * @port: port to enable
1203 * @mask: mask to use
1204 */
1205static void enable_intrs(struct ioc4_port *port, uint32_t mask)
1206{
1207 struct hooks *hooks = port->ip_hooks;
1208
1209 if ((port->ip_ienb & mask) != mask) {
1210 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES,
1211 IOC4_SIO_INTR_TYPE);
1212 port->ip_ienb |= mask;
1213 }
1214
1215 if (port->ip_ienb)
1216 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1217 IOC4_W_IES, IOC4_OTHER_INTR_TYPE);
1218}
1219
1220/**
1221 * local_open - local open a port
1222 * @port: port to open
1223 */
1224static inline int local_open(struct ioc4_port *port)
1225{
1226 int spiniter = 0;
1227
1228 port->ip_flags = PORT_ACTIVE;
1229
1230 /* Pause the DMA interface if necessary */
1231 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1232 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1233 &port->ip_serial_regs->sscr);
1234 while((readl(&port->ip_serial_regs-> sscr)
1235 & IOC4_SSCR_PAUSE_STATE) == 0) {
1236 spiniter++;
1237 if (spiniter > MAXITER) {
1238 port->ip_flags = PORT_INACTIVE;
1239 return -1;
1240 }
1241 }
1242 }
1243
1244 /* Reset the input fifo. If the uart received chars while the port
1245 * was closed and DMA is not enabled, the uart may have a bunch of
1246 * chars hanging around in its rx fifo which will not be discarded
1247 * by rclr in the upper layer. We must get rid of them here.
1248 */
1249 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1250 &port->ip_uart_regs->i4u_fcr);
1251
1252 writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr);
1253 /* UART_LCR_STOP == 1 stop */
1254
1255 /* Re-enable DMA, set default threshold to intr whenever there is
1256 * data available.
1257 */
1258 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1259 port->ip_sscr |= 1; /* default threshold */
1260
1261 /* Plug in the new sscr. This implicitly clears the DMA_PAUSE
1262 * flag if it was set above
1263 */
1264 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1265 port->ip_tx_lowat = 1;
1266 return 0;
1267}
1268
1269/**
1270 * set_rx_timeout - Set rx timeout and threshold values.
1271 * @port: port to use
1272 * @timeout: timeout value in ticks
1273 */
1274static inline int set_rx_timeout(struct ioc4_port *port, int timeout)
1275{
1276 int threshold;
1277
1278 port->ip_rx_timeout = timeout;
1279
1280 /* Timeout is in ticks. Let's figure out how many chars we
1281 * can receive at the current baud rate in that interval
1282 * and set the rx threshold to that amount. There are 4 chars
1283 * per ring entry, so we'll divide the number of chars that will
1284 * arrive in timeout by 4.
1285 * So .... timeout * baud / 10 / HZ / 4, with HZ = 100.
1286 */
1287 threshold = timeout * port->ip_baud / 4000;
1288 if (threshold == 0)
1289 threshold = 1; /* otherwise we'll intr all the time! */
1290
1291 if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD)
1292 return 1;
1293
1294 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1295 port->ip_sscr |= threshold;
1296
1297 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1298
1299 /* Now set the rx timeout to the given value
1300 * again timeout * IOC4_SRTR_HZ / HZ
1301 */
1302 timeout = timeout * IOC4_SRTR_HZ / 100;
1303 if (timeout > IOC4_SRTR_CNT)
1304 timeout = IOC4_SRTR_CNT;
1305
1306 writel(timeout, &port->ip_serial_regs->srtr);
1307 return 0;
1308}
1309
1310/**
1311 * config_port - config the hardware
1312 * @port: port to config
1313 * @baud: baud rate for the port
1314 * @byte_size: data size
1315 * @stop_bits: number of stop bits
1316 * @parenb: parity enable ?
1317 * @parodd: odd parity ?
1318 */
1319static inline int
1320config_port(struct ioc4_port *port,
1321 int baud, int byte_size, int stop_bits, int parenb, int parodd)
1322{
1323 char lcr, sizebits;
1324 int spiniter = 0;
1325
1326 DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1327 __func__, baud, byte_size, stop_bits, parenb, parodd));
1328
1329 if (set_baud(port, baud))
1330 return 1;
1331
1332 switch (byte_size) {
1333 case 5:
1334 sizebits = UART_LCR_WLEN5;
1335 break;
1336 case 6:
1337 sizebits = UART_LCR_WLEN6;
1338 break;
1339 case 7:
1340 sizebits = UART_LCR_WLEN7;
1341 break;
1342 case 8:
1343 sizebits = UART_LCR_WLEN8;
1344 break;
1345 default:
1346 return 1;
1347 }
1348
1349 /* Pause the DMA interface if necessary */
1350 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1351 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1352 &port->ip_serial_regs->sscr);
1353 while((readl(&port->ip_serial_regs->sscr)
1354 & IOC4_SSCR_PAUSE_STATE) == 0) {
1355 spiniter++;
1356 if (spiniter > MAXITER)
1357 return -1;
1358 }
1359 }
1360
1361 /* Clear relevant fields in lcr */
1362 lcr = readb(&port->ip_uart_regs->i4u_lcr);
1363 lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
1364 UART_LCR_PARITY | LCR_MASK_STOP_BITS);
1365
1366 /* Set byte size in lcr */
1367 lcr |= sizebits;
1368
1369 /* Set parity */
1370 if (parenb) {
1371 lcr |= UART_LCR_PARITY;
1372 if (!parodd)
1373 lcr |= UART_LCR_EPAR;
1374 }
1375
1376 /* Set stop bits */
1377 if (stop_bits)
1378 lcr |= UART_LCR_STOP /* 2 stop bits */ ;
1379
1380 writeb(lcr, &port->ip_uart_regs->i4u_lcr);
1381
1382 /* Re-enable the DMA interface if necessary */
1383 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1384 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1385 }
1386 port->ip_baud = baud;
1387
1388 /* When we get within this number of ring entries of filling the
1389 * entire ring on tx, place an EXPLICIT intr to generate a lowat
1390 * notification when output has drained.
1391 */
1392 port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
1393 if (port->ip_tx_lowat == 0)
1394 port->ip_tx_lowat = 1;
1395
1396 set_rx_timeout(port, 2);
1397
1398 return 0;
1399}
1400
1401/**
1402 * do_write - Write bytes to the port. Returns the number of bytes
1403 * actually written. Called from transmit_chars
1404 * @port: port to use
1405 * @buf: the stuff to write
1406 * @len: how many bytes in 'buf'
1407 */
1408static inline int do_write(struct ioc4_port *port, char *buf, int len)
1409{
1410 int prod_ptr, cons_ptr, total = 0;
1411 struct ring *outring;
1412 struct ring_entry *entry;
1413 struct hooks *hooks = port->ip_hooks;
1414
1415 BUG_ON(!(len >= 0));
1416
1417 prod_ptr = port->ip_tx_prod;
1418 cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
1419 outring = port->ip_outring;
1420
1421 /* Maintain a 1-entry red-zone. The ring buffer is full when
1422 * (cons - prod) % ring_size is 1. Rather than do this subtraction
1423 * in the body of the loop, I'll do it now.
1424 */
1425 cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
1426
1427 /* Stuff the bytes into the output */
1428 while ((prod_ptr != cons_ptr) && (len > 0)) {
1429 int xx;
1430
1431 /* Get 4 bytes (one ring entry) at a time */
1432 entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
1433
1434 /* Invalidate all entries */
1435 entry->ring_allsc = 0;
1436
1437 /* Copy in some bytes */
1438 for (xx = 0; (xx < 4) && (len > 0); xx++) {
1439 entry->ring_data[xx] = *buf++;
1440 entry->ring_sc[xx] = IOC4_TXCB_VALID;
1441 len--;
1442 total++;
1443 }
1444
1445 /* If we are within some small threshold of filling up the
1446 * entire ring buffer, we must place an EXPLICIT intr here
1447 * to generate a lowat interrupt in case we subsequently
1448 * really do fill up the ring and the caller goes to sleep.
1449 * No need to place more than one though.
1450 */
1451 if (!(port->ip_flags & LOWAT_WRITTEN) &&
1452 ((cons_ptr - prod_ptr) & PROD_CONS_MASK)
1453 <= port->ip_tx_lowat
1454 * (int)sizeof(struct ring_entry)) {
1455 port->ip_flags |= LOWAT_WRITTEN;
1456 entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE;
1457 }
1458
1459 /* Go on to next entry */
1460 prod_ptr += sizeof(struct ring_entry);
1461 prod_ptr &= PROD_CONS_MASK;
1462 }
1463
1464 /* If we sent something, start DMA if necessary */
1465 if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
1466 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1467 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1468 }
1469
1470 /* Store the new producer pointer. If tx is disabled, we stuff the
1471 * data into the ring buffer, but we don't actually start tx.
1472 */
1473 if (!uart_tx_stopped(port->ip_port)) {
1474 writel(prod_ptr, &port->ip_serial_regs->stpir);
1475
1476 /* If we are now transmitting, enable tx_mt interrupt so we
1477 * can disable DMA if necessary when the tx finishes.
1478 */
1479 if (total > 0)
1480 enable_intrs(port, hooks->intr_tx_mt);
1481 }
1482 port->ip_tx_prod = prod_ptr;
1483 return total;
1484}
1485
1486/**
1487 * disable_intrs - disable interrupts
1488 * @port: port to enable
1489 * @mask: mask to use
1490 */
1491static void disable_intrs(struct ioc4_port *port, uint32_t mask)
1492{
1493 struct hooks *hooks = port->ip_hooks;
1494
1495 if (port->ip_ienb & mask) {
1496 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC,
1497 IOC4_SIO_INTR_TYPE);
1498 port->ip_ienb &= ~mask;
1499 }
1500
1501 if (!port->ip_ienb)
1502 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1503 IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
1504}
1505
1506/**
1507 * set_notification - Modify event notification
1508 * @port: port to use
1509 * @mask: events mask
1510 * @set_on: set ?
1511 */
1512static int set_notification(struct ioc4_port *port, int mask, int set_on)
1513{
1514 struct hooks *hooks = port->ip_hooks;
1515 uint32_t intrbits, sscrbits;
1516
1517 BUG_ON(!mask);
1518
1519 intrbits = sscrbits = 0;
1520
1521 if (mask & N_DATA_READY)
1522 intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
1523 if (mask & N_OUTPUT_LOWAT)
1524 intrbits |= hooks->intr_tx_explicit;
1525 if (mask & N_DDCD) {
1526 intrbits |= hooks->intr_delta_dcd;
1527 sscrbits |= IOC4_SSCR_RX_RING_DCD;
1528 }
1529 if (mask & N_DCTS)
1530 intrbits |= hooks->intr_delta_cts;
1531
1532 if (set_on) {
1533 enable_intrs(port, intrbits);
1534 port->ip_notify |= mask;
1535 port->ip_sscr |= sscrbits;
1536 } else {
1537 disable_intrs(port, intrbits);
1538 port->ip_notify &= ~mask;
1539 port->ip_sscr &= ~sscrbits;
1540 }
1541
1542 /* We require DMA if either DATA_READY or DDCD notification is
1543 * currently requested. If neither of these is requested and
1544 * there is currently no tx in progress, DMA may be disabled.
1545 */
1546 if (port->ip_notify & (N_DATA_READY | N_DDCD))
1547 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1548 else if (!(port->ip_ienb & hooks->intr_tx_mt))
1549 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1550
1551 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1552 return 0;
1553}
1554
1555/**
1556 * set_mcr - set the master control reg
1557 * @the_port: port to use
1558 * @mask1: mcr mask
1559 * @mask2: shadow mask
1560 */
1561static inline int set_mcr(struct uart_port *the_port,
1562 int mask1, int mask2)
1563{
1564 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1565 uint32_t shadow;
1566 int spiniter = 0;
1567 char mcr;
1568
1569 if (!port)
1570 return -1;
1571
1572 /* Pause the DMA interface if necessary */
1573 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1574 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1575 &port->ip_serial_regs->sscr);
1576 while ((readl(&port->ip_serial_regs->sscr)
1577 & IOC4_SSCR_PAUSE_STATE) == 0) {
1578 spiniter++;
1579 if (spiniter > MAXITER)
1580 return -1;
1581 }
1582 }
1583 shadow = readl(&port->ip_serial_regs->shadow);
1584 mcr = (shadow & 0xff000000) >> 24;
1585
1586 /* Set new value */
1587 mcr |= mask1;
1588 shadow |= mask2;
1589
1590 writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1591 writel(shadow, &port->ip_serial_regs->shadow);
1592
1593 /* Re-enable the DMA interface if necessary */
1594 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1595 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1596 }
1597 return 0;
1598}
1599
1600/**
1601 * ioc4_set_proto - set the protocol for the port
1602 * @port: port to use
1603 * @proto: protocol to use
1604 */
1605static int ioc4_set_proto(struct ioc4_port *port, int proto)
1606{
1607 struct hooks *hooks = port->ip_hooks;
1608
1609 switch (proto) {
1610 case PROTO_RS232:
1611 /* Clear the appropriate GIO pin */
1612 writel(0, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1613 break;
1614
1615 case PROTO_RS422:
1616 /* Set the appropriate GIO pin */
1617 writel(1, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1618 break;
1619
1620 default:
1621 return 1;
1622 }
1623 return 0;
1624}
1625
1626/**
1627 * transmit_chars - upper level write, called with ip_lock
1628 * @the_port: port to write
1629 */
1630static void transmit_chars(struct uart_port *the_port)
1631{
1632 int xmit_count, tail, head;
1633 int result;
1634 char *start;
1635 struct tty_struct *tty;
1636 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1637 struct uart_state *state;
1638
1639 if (!the_port)
1640 return;
1641 if (!port)
1642 return;
1643
1644 state = the_port->state;
1645 tty = state->port.tty;
1646
1647 if (uart_circ_empty(&state->xmit) || uart_tx_stopped(the_port)) {
1648 /* Nothing to do or hw stopped */
1649 set_notification(port, N_ALL_OUTPUT, 0);
1650 return;
1651 }
1652
1653 head = state->xmit.head;
1654 tail = state->xmit.tail;
1655 start = (char *)&state->xmit.buf[tail];
1656
1657 /* write out all the data or until the end of the buffer */
1658 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
1659 if (xmit_count > 0) {
1660 result = do_write(port, start, xmit_count);
1661 if (result > 0) {
1662 /* booking */
1663 xmit_count -= result;
1664 the_port->icount.tx += result;
1665 /* advance the pointers */
1666 tail += result;
1667 tail &= UART_XMIT_SIZE - 1;
1668 state->xmit.tail = tail;
1669 start = (char *)&state->xmit.buf[tail];
1670 }
1671 }
1672 if (uart_circ_chars_pending(&state->xmit) < WAKEUP_CHARS)
1673 uart_write_wakeup(the_port);
1674
1675 if (uart_circ_empty(&state->xmit)) {
1676 set_notification(port, N_OUTPUT_LOWAT, 0);
1677 } else {
1678 set_notification(port, N_OUTPUT_LOWAT, 1);
1679 }
1680}
1681
1682/**
1683 * ioc4_change_speed - change the speed of the port
1684 * @the_port: port to change
1685 * @new_termios: new termios settings
1686 * @old_termios: old termios settings
1687 */
1688static void
1689ioc4_change_speed(struct uart_port *the_port,
1690 struct ktermios *new_termios, struct ktermios *old_termios)
1691{
1692 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1693 int baud, bits;
1694 unsigned cflag, iflag;
1695 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
1696 struct uart_state *state = the_port->state;
1697
1698 cflag = new_termios->c_cflag;
1699 iflag = new_termios->c_iflag;
1700
1701 switch (cflag & CSIZE) {
1702 case CS5:
1703 new_data = 5;
1704 bits = 7;
1705 break;
1706 case CS6:
1707 new_data = 6;
1708 bits = 8;
1709 break;
1710 case CS7:
1711 new_data = 7;
1712 bits = 9;
1713 break;
1714 case CS8:
1715 new_data = 8;
1716 bits = 10;
1717 break;
1718 default:
1719 /* cuz we always need a default ... */
1720 new_data = 5;
1721 bits = 7;
1722 break;
1723 }
1724 if (cflag & CSTOPB) {
1725 bits++;
1726 new_stop = 1;
1727 }
1728 if (cflag & PARENB) {
1729 bits++;
1730 new_parity_enable = 1;
1731 if (cflag & PARODD)
1732 new_parity = 1;
1733 }
1734 baud = uart_get_baud_rate(the_port, new_termios, old_termios,
1735 MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
1736 DPRINT_CONFIG(("%s: returned baud %d\n", __func__, baud));
1737
1738 /* default is 9600 */
1739 if (!baud)
1740 baud = 9600;
1741
1742 if (!the_port->fifosize)
1743 the_port->fifosize = IOC4_FIFO_CHARS;
1744 the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10));
1745 the_port->timeout += HZ / 50; /* Add .02 seconds of slop */
1746
1747 the_port->ignore_status_mask = N_ALL_INPUT;
1748
1749 state->port.low_latency = 1;
1750
1751 if (iflag & IGNPAR)
1752 the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1753 | N_FRAMING_ERROR);
1754 if (iflag & IGNBRK) {
1755 the_port->ignore_status_mask &= ~N_BREAK;
1756 if (iflag & IGNPAR)
1757 the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1758 }
1759 if (!(cflag & CREAD)) {
1760 /* ignore everything */
1761 the_port->ignore_status_mask &= ~N_DATA_READY;
1762 }
1763
1764 if (cflag & CRTSCTS) {
1765 port->ip_sscr |= IOC4_SSCR_HFC_EN;
1766 }
1767 else {
1768 port->ip_sscr &= ~IOC4_SSCR_HFC_EN;
1769 }
1770 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1771
1772 /* Set the configuration and proper notification call */
1773 DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1774 "config_port(baud %d data %d stop %d p enable %d parity %d),"
1775 " notification 0x%x\n",
1776 __func__, (void *)port, cflag, baud, new_data, new_stop,
1777 new_parity_enable, new_parity, the_port->ignore_status_mask));
1778
1779 if ((config_port(port, baud, /* baud */
1780 new_data, /* byte size */
1781 new_stop, /* stop bits */
1782 new_parity_enable, /* set parity */
1783 new_parity)) >= 0) { /* parity 1==odd */
1784 set_notification(port, the_port->ignore_status_mask, 1);
1785 }
1786}
1787
1788/**
1789 * ic4_startup_local - Start up the serial port - returns >= 0 if no errors
1790 * @the_port: Port to operate on
1791 */
1792static inline int ic4_startup_local(struct uart_port *the_port)
1793{
1794 struct ioc4_port *port;
1795 struct uart_state *state;
1796
1797 if (!the_port)
1798 return -1;
1799
1800 port = get_ioc4_port(the_port, 0);
1801 if (!port)
1802 return -1;
1803
1804 state = the_port->state;
1805
1806 local_open(port);
1807
1808 /* set the protocol - mapbase has the port type */
1809 ioc4_set_proto(port, the_port->mapbase);
1810
1811 /* set the speed of the serial port */
1812 ioc4_change_speed(the_port, &state->port.tty->termios,
1813 (struct ktermios *)0);
1814
1815 return 0;
1816}
1817
1818/*
1819 * ioc4_cb_output_lowat - called when the output low water mark is hit
1820 * @the_port: port to output
1821 */
1822static void ioc4_cb_output_lowat(struct uart_port *the_port)
1823{
1824 unsigned long pflags;
1825
1826 /* ip_lock is set on the call here */
1827 if (the_port) {
1828 spin_lock_irqsave(&the_port->lock, pflags);
1829 transmit_chars(the_port);
1830 spin_unlock_irqrestore(&the_port->lock, pflags);
1831 }
1832}
1833
1834/**
1835 * handle_intr - service any interrupts for the given port - 2nd level
1836 * called via sd_intr
1837 * @arg: handler arg
1838 * @sio_ir: ioc4regs
1839 */
1840static void handle_intr(void *arg, uint32_t sio_ir)
1841{
1842 struct ioc4_port *port = (struct ioc4_port *)arg;
1843 struct hooks *hooks = port->ip_hooks;
1844 unsigned int rx_high_rd_aborted = 0;
1845 unsigned long flags;
1846 struct uart_port *the_port;
1847 int loop_counter;
1848
1849 /* Possible race condition here: The tx_mt interrupt bit may be
1850 * cleared without the intervention of the interrupt handler,
1851 * e.g. by a write. If the top level interrupt handler reads a
1852 * tx_mt, then some other processor does a write, starting up
1853 * output, then we come in here, see the tx_mt and stop DMA, the
1854 * output started by the other processor will hang. Thus we can
1855 * only rely on tx_mt being legitimate if it is read while the
1856 * port lock is held. Therefore this bit must be ignored in the
1857 * passed in interrupt mask which was read by the top level
1858 * interrupt handler since the port lock was not held at the time
1859 * it was read. We can only rely on this bit being accurate if it
1860 * is read while the port lock is held. So we'll clear it for now,
1861 * and reload it later once we have the port lock.
1862 */
1863 sio_ir &= ~(hooks->intr_tx_mt);
1864
1865 spin_lock_irqsave(&port->ip_lock, flags);
1866
1867 loop_counter = MAXITER; /* to avoid hangs */
1868
1869 do {
1870 uint32_t shadow;
1871
1872 if ( loop_counter-- <= 0 ) {
1873 printk(KERN_WARNING "IOC4 serial: "
1874 "possible hang condition/"
1875 "port stuck on interrupt.\n");
1876 break;
1877 }
1878
1879 /* Handle a DCD change */
1880 if (sio_ir & hooks->intr_delta_dcd) {
1881 /* ACK the interrupt */
1882 writel(hooks->intr_delta_dcd,
1883 &port->ip_mem->sio_ir.raw);
1884
1885 shadow = readl(&port->ip_serial_regs->shadow);
1886
1887 if ((port->ip_notify & N_DDCD)
1888 && (shadow & IOC4_SHADOW_DCD)
1889 && (port->ip_port)) {
1890 the_port = port->ip_port;
1891 the_port->icount.dcd = 1;
1892 wake_up_interruptible
1893 (&the_port->state->port.delta_msr_wait);
1894 } else if ((port->ip_notify & N_DDCD)
1895 && !(shadow & IOC4_SHADOW_DCD)) {
1896 /* Flag delta DCD/no DCD */
1897 port->ip_flags |= DCD_ON;
1898 }
1899 }
1900
1901 /* Handle a CTS change */
1902 if (sio_ir & hooks->intr_delta_cts) {
1903 /* ACK the interrupt */
1904 writel(hooks->intr_delta_cts,
1905 &port->ip_mem->sio_ir.raw);
1906
1907 shadow = readl(&port->ip_serial_regs->shadow);
1908
1909 if ((port->ip_notify & N_DCTS)
1910 && (port->ip_port)) {
1911 the_port = port->ip_port;
1912 the_port->icount.cts =
1913 (shadow & IOC4_SHADOW_CTS) ? 1 : 0;
1914 wake_up_interruptible
1915 (&the_port->state->port.delta_msr_wait);
1916 }
1917 }
1918
1919 /* rx timeout interrupt. Must be some data available. Put this
1920 * before the check for rx_high since servicing this condition
1921 * may cause that condition to clear.
1922 */
1923 if (sio_ir & hooks->intr_rx_timer) {
1924 /* ACK the interrupt */
1925 writel(hooks->intr_rx_timer,
1926 &port->ip_mem->sio_ir.raw);
1927
1928 if ((port->ip_notify & N_DATA_READY)
1929 && (port->ip_port)) {
1930 /* ip_lock is set on call here */
1931 receive_chars(port->ip_port);
1932 }
1933 }
1934
1935 /* rx high interrupt. Must be after rx_timer. */
1936 else if (sio_ir & hooks->intr_rx_high) {
1937 /* Data available, notify upper layer */
1938 if ((port->ip_notify & N_DATA_READY)
1939 && port->ip_port) {
1940 /* ip_lock is set on call here */
1941 receive_chars(port->ip_port);
1942 }
1943
1944 /* We can't ACK this interrupt. If receive_chars didn't
1945 * cause the condition to clear, we'll have to disable
1946 * the interrupt until the data is drained.
1947 * If the read was aborted, don't disable the interrupt
1948 * as this may cause us to hang indefinitely. An
1949 * aborted read generally means that this interrupt
1950 * hasn't been delivered to the cpu yet anyway, even
1951 * though we see it as asserted when we read the sio_ir.
1952 */
1953 if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) {
1954 if ((port->ip_flags & READ_ABORTED) == 0) {
1955 port->ip_ienb &= ~hooks->intr_rx_high;
1956 port->ip_flags |= INPUT_HIGH;
1957 } else {
1958 rx_high_rd_aborted++;
1959 }
1960 }
1961 }
1962
1963 /* We got a low water interrupt: notify upper layer to
1964 * send more data. Must come before tx_mt since servicing
1965 * this condition may cause that condition to clear.
1966 */
1967 if (sio_ir & hooks->intr_tx_explicit) {
1968 port->ip_flags &= ~LOWAT_WRITTEN;
1969
1970 /* ACK the interrupt */
1971 writel(hooks->intr_tx_explicit,
1972 &port->ip_mem->sio_ir.raw);
1973
1974 if (port->ip_notify & N_OUTPUT_LOWAT)
1975 ioc4_cb_output_lowat(port->ip_port);
1976 }
1977
1978 /* Handle tx_mt. Must come after tx_explicit. */
1979 else if (sio_ir & hooks->intr_tx_mt) {
1980 /* If we are expecting a lowat notification
1981 * and we get to this point it probably means that for
1982 * some reason the tx_explicit didn't work as expected
1983 * (that can legitimately happen if the output buffer is
1984 * filled up in just the right way).
1985 * So send the notification now.
1986 */
1987 if (port->ip_notify & N_OUTPUT_LOWAT) {
1988 ioc4_cb_output_lowat(port->ip_port);
1989
1990 /* We need to reload the sio_ir since the lowat
1991 * call may have caused another write to occur,
1992 * clearing the tx_mt condition.
1993 */
1994 sio_ir = PENDING(port);
1995 }
1996
1997 /* If the tx_mt condition still persists even after the
1998 * lowat call, we've got some work to do.
1999 */
2000 if (sio_ir & hooks->intr_tx_mt) {
2001
2002 /* If we are not currently expecting DMA input,
2003 * and the transmitter has just gone idle,
2004 * there is no longer any reason for DMA, so
2005 * disable it.
2006 */
2007 if (!(port->ip_notify
2008 & (N_DATA_READY | N_DDCD))) {
2009 BUG_ON(!(port->ip_sscr
2010 & IOC4_SSCR_DMA_EN));
2011 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2012 writel(port->ip_sscr,
2013 &port->ip_serial_regs->sscr);
2014 }
2015
2016 /* Prevent infinite tx_mt interrupt */
2017 port->ip_ienb &= ~hooks->intr_tx_mt;
2018 }
2019 }
2020 sio_ir = PENDING(port);
2021
2022 /* if the read was aborted and only hooks->intr_rx_high,
2023 * clear hooks->intr_rx_high, so we do not loop forever.
2024 */
2025
2026 if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
2027 sio_ir &= ~hooks->intr_rx_high;
2028 }
2029 } while (sio_ir & hooks->intr_all);
2030
2031 spin_unlock_irqrestore(&port->ip_lock, flags);
2032
2033 /* Re-enable interrupts before returning from interrupt handler.
2034 * Getting interrupted here is okay. It'll just v() our semaphore, and
2035 * we'll come through the loop again.
2036 */
2037
2038 write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES,
2039 IOC4_SIO_INTR_TYPE);
2040}
2041
2042/*
2043 * ioc4_cb_post_ncs - called for some basic errors
2044 * @port: port to use
2045 * @ncs: event
2046 */
2047static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs)
2048{
2049 struct uart_icount *icount;
2050
2051 icount = &the_port->icount;
2052
2053 if (ncs & NCS_BREAK)
2054 icount->brk++;
2055 if (ncs & NCS_FRAMING)
2056 icount->frame++;
2057 if (ncs & NCS_OVERRUN)
2058 icount->overrun++;
2059 if (ncs & NCS_PARITY)
2060 icount->parity++;
2061}
2062
2063/**
2064 * do_read - Read in bytes from the port. Return the number of bytes
2065 * actually read.
2066 * @the_port: port to use
2067 * @buf: place to put the stuff we read
2068 * @len: how big 'buf' is
2069 */
2070
2071static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2072 int len)
2073{
2074 int prod_ptr, cons_ptr, total;
2075 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2076 struct ring *inring;
2077 struct ring_entry *entry;
2078 struct hooks *hooks;
2079 int byte_num;
2080 char *sc;
2081 int loop_counter;
2082
2083 BUG_ON(!(len >= 0));
2084 BUG_ON(!port);
2085 hooks = port->ip_hooks;
2086
2087 /* There is a nasty timing issue in the IOC4. When the rx_timer
2088 * expires or the rx_high condition arises, we take an interrupt.
2089 * At some point while servicing the interrupt, we read bytes from
2090 * the ring buffer and re-arm the rx_timer. However the rx_timer is
2091 * not started until the first byte is received *after* it is armed,
2092 * and any bytes pending in the rx construction buffers are not drained
2093 * to memory until either there are 4 bytes available or the rx_timer
2094 * expires. This leads to a potential situation where data is left
2095 * in the construction buffers forever - 1 to 3 bytes were received
2096 * after the interrupt was generated but before the rx_timer was
2097 * re-armed. At that point as long as no subsequent bytes are received
2098 * the timer will never be started and the bytes will remain in the
2099 * construction buffer forever. The solution is to execute a DRAIN
2100 * command after rearming the timer. This way any bytes received before
2101 * the DRAIN will be drained to memory, and any bytes received after
2102 * the DRAIN will start the TIMER and be drained when it expires.
2103 * Luckily, this only needs to be done when the DMA buffer is empty
2104 * since there is no requirement that this function return all
2105 * available data as long as it returns some.
2106 */
2107 /* Re-arm the timer */
2108 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
2109
2110 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
2111 cons_ptr = port->ip_rx_cons;
2112
2113 if (prod_ptr == cons_ptr) {
2114 int reset_dma = 0;
2115
2116 /* Input buffer appears empty, do a flush. */
2117
2118 /* DMA must be enabled for this to work. */
2119 if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
2120 port->ip_sscr |= IOC4_SSCR_DMA_EN;
2121 reset_dma = 1;
2122 }
2123
2124 /* Potential race condition: we must reload the srpir after
2125 * issuing the drain command, otherwise we could think the rx
2126 * buffer is empty, then take a very long interrupt, and when
2127 * we come back it's full and we wait forever for the drain to
2128 * complete.
2129 */
2130 writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN,
2131 &port->ip_serial_regs->sscr);
2132 prod_ptr = readl(&port->ip_serial_regs->srpir)
2133 & PROD_CONS_MASK;
2134
2135 /* We must not wait for the DRAIN to complete unless there are
2136 * at least 8 bytes (2 ring entries) available to receive the
2137 * data otherwise the DRAIN will never complete and we'll
2138 * deadlock here.
2139 * In fact, to make things easier, I'll just ignore the flush if
2140 * there is any data at all now available.
2141 */
2142 if (prod_ptr == cons_ptr) {
2143 loop_counter = 0;
2144 while (readl(&port->ip_serial_regs->sscr) &
2145 IOC4_SSCR_RX_DRAIN) {
2146 loop_counter++;
2147 if (loop_counter > MAXITER)
2148 return -1;
2149 }
2150
2151 /* SIGH. We have to reload the prod_ptr *again* since
2152 * the drain may have caused it to change
2153 */
2154 prod_ptr = readl(&port->ip_serial_regs->srpir)
2155 & PROD_CONS_MASK;
2156 }
2157 if (reset_dma) {
2158 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2159 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
2160 }
2161 }
2162 inring = port->ip_inring;
2163 port->ip_flags &= ~READ_ABORTED;
2164
2165 total = 0;
2166 loop_counter = 0xfffff; /* to avoid hangs */
2167
2168 /* Grab bytes from the hardware */
2169 while ((prod_ptr != cons_ptr) && (len > 0)) {
2170 entry = (struct ring_entry *)((caddr_t)inring + cons_ptr);
2171
2172 if ( loop_counter-- <= 0 ) {
2173 printk(KERN_WARNING "IOC4 serial: "
2174 "possible hang condition/"
2175 "port stuck on read.\n");
2176 break;
2177 }
2178
2179 /* According to the producer pointer, this ring entry
2180 * must contain some data. But if the PIO happened faster
2181 * than the DMA, the data may not be available yet, so let's
2182 * wait until it arrives.
2183 */
2184 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2185 /* Indicate the read is aborted so we don't disable
2186 * the interrupt thinking that the consumer is
2187 * congested.
2188 */
2189 port->ip_flags |= READ_ABORTED;
2190 len = 0;
2191 break;
2192 }
2193
2194 /* Load the bytes/status out of the ring entry */
2195 for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
2196 sc = &(entry->ring_sc[byte_num]);
2197
2198 /* Check for change in modem state or overrun */
2199 if ((*sc & IOC4_RXSB_MODEM_VALID)
2200 && (port->ip_notify & N_DDCD)) {
2201 /* Notify upper layer if DCD dropped */
2202
2203 if ((port->ip_flags & DCD_ON)
2204 && !(*sc & IOC4_RXSB_DCD)) {
2205
2206 /* If we have already copied some data,
2207 * return it. We'll pick up the carrier
2208 * drop on the next pass. That way we
2209 * don't throw away the data that has
2210 * already been copied back to
2211 * the caller's buffer.
2212 */
2213 if (total > 0) {
2214 len = 0;
2215 break;
2216 }
2217 port->ip_flags &= ~DCD_ON;
2218
2219 /* Turn off this notification so the
2220 * carrier drop protocol won't see it
2221 * again when it does a read.
2222 */
2223 *sc &= ~IOC4_RXSB_MODEM_VALID;
2224
2225 /* To keep things consistent, we need
2226 * to update the consumer pointer so
2227 * the next reader won't come in and
2228 * try to read the same ring entries
2229 * again. This must be done here before
2230 * the dcd change.
2231 */
2232
2233 if ((entry->ring_allsc & RING_ANY_VALID)
2234 == 0) {
2235 cons_ptr += (int)sizeof
2236 (struct ring_entry);
2237 cons_ptr &= PROD_CONS_MASK;
2238 }
2239 writel(cons_ptr,
2240 &port->ip_serial_regs->srcir);
2241 port->ip_rx_cons = cons_ptr;
2242
2243 /* Notify upper layer of carrier drop */
2244 if ((port->ip_notify & N_DDCD)
2245 && port->ip_port) {
2246 the_port->icount.dcd = 0;
2247 wake_up_interruptible
2248 (&the_port->state->
2249 port.delta_msr_wait);
2250 }
2251
2252 /* If we had any data to return, we
2253 * would have returned it above.
2254 */
2255 return 0;
2256 }
2257 }
2258 if (*sc & IOC4_RXSB_MODEM_VALID) {
2259 /* Notify that an input overrun occurred */
2260 if ((*sc & IOC4_RXSB_OVERRUN)
2261 && (port->ip_notify & N_OVERRUN_ERROR)) {
2262 ioc4_cb_post_ncs(the_port, NCS_OVERRUN);
2263 }
2264 /* Don't look at this byte again */
2265 *sc &= ~IOC4_RXSB_MODEM_VALID;
2266 }
2267
2268 /* Check for valid data or RX errors */
2269 if ((*sc & IOC4_RXSB_DATA_VALID) &&
2270 ((*sc & (IOC4_RXSB_PAR_ERR
2271 | IOC4_RXSB_FRAME_ERR
2272 | IOC4_RXSB_BREAK))
2273 && (port->ip_notify & (N_PARITY_ERROR
2274 | N_FRAMING_ERROR
2275 | N_BREAK)))) {
2276 /* There is an error condition on the next byte.
2277 * If we have already transferred some bytes,
2278 * we'll stop here. Otherwise if this is the
2279 * first byte to be read, we'll just transfer
2280 * it alone after notifying the
2281 * upper layer of its status.
2282 */
2283 if (total > 0) {
2284 len = 0;
2285 break;
2286 } else {
2287 if ((*sc & IOC4_RXSB_PAR_ERR) &&
2288 (port->ip_notify & N_PARITY_ERROR)) {
2289 ioc4_cb_post_ncs(the_port,
2290 NCS_PARITY);
2291 }
2292 if ((*sc & IOC4_RXSB_FRAME_ERR) &&
2293 (port->ip_notify & N_FRAMING_ERROR)){
2294 ioc4_cb_post_ncs(the_port,
2295 NCS_FRAMING);
2296 }
2297 if ((*sc & IOC4_RXSB_BREAK)
2298 && (port->ip_notify & N_BREAK)) {
2299 ioc4_cb_post_ncs
2300 (the_port,
2301 NCS_BREAK);
2302 }
2303 len = 1;
2304 }
2305 }
2306 if (*sc & IOC4_RXSB_DATA_VALID) {
2307 *sc &= ~IOC4_RXSB_DATA_VALID;
2308 *buf = entry->ring_data[byte_num];
2309 buf++;
2310 len--;
2311 total++;
2312 }
2313 }
2314
2315 /* If we used up this entry entirely, go on to the next one,
2316 * otherwise we must have run out of buffer space, so
2317 * leave the consumer pointer here for the next read in case
2318 * there are still unread bytes in this entry.
2319 */
2320 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2321 cons_ptr += (int)sizeof(struct ring_entry);
2322 cons_ptr &= PROD_CONS_MASK;
2323 }
2324 }
2325
2326 /* Update consumer pointer and re-arm rx timer interrupt */
2327 writel(cons_ptr, &port->ip_serial_regs->srcir);
2328 port->ip_rx_cons = cons_ptr;
2329
2330 /* If we have now dipped below the rx high water mark and we have
2331 * rx_high interrupt turned off, we can now turn it back on again.
2332 */
2333 if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
2334 & PROD_CONS_MASK) < ((port->ip_sscr &
2335 IOC4_SSCR_RX_THRESHOLD)
2336 << IOC4_PROD_CONS_PTR_OFF))) {
2337 port->ip_flags &= ~INPUT_HIGH;
2338 enable_intrs(port, hooks->intr_rx_high);
2339 }
2340 return total;
2341}
2342
2343/**
2344 * receive_chars - upper level read. Called with ip_lock.
2345 * @the_port: port to read from
2346 */
2347static void receive_chars(struct uart_port *the_port)
2348{
2349 unsigned char ch[IOC4_MAX_CHARS];
2350 int read_count, request_count = IOC4_MAX_CHARS;
2351 struct uart_icount *icount;
2352 struct uart_state *state = the_port->state;
2353 unsigned long pflags;
2354
2355 /* Make sure all the pointers are "good" ones */
2356 if (!state)
2357 return;
2358
2359 spin_lock_irqsave(&the_port->lock, pflags);
2360
2361 request_count = tty_buffer_request_room(&state->port, IOC4_MAX_CHARS);
2362
2363 if (request_count > 0) {
2364 icount = &the_port->icount;
2365 read_count = do_read(the_port, ch, request_count);
2366 if (read_count > 0) {
2367 tty_insert_flip_string(&state->port, ch, read_count);
2368 icount->rx += read_count;
2369 }
2370 }
2371
2372 spin_unlock_irqrestore(&the_port->lock, pflags);
2373
2374 tty_flip_buffer_push(&state->port);
2375}
2376
2377/**
2378 * ic4_type - What type of console are we?
2379 * @port: Port to operate with (we ignore since we only have one port)
2380 *
2381 */
2382static const char *ic4_type(struct uart_port *the_port)
2383{
2384 if (the_port->mapbase == PROTO_RS232)
2385 return "SGI IOC4 Serial [rs232]";
2386 else
2387 return "SGI IOC4 Serial [rs422]";
2388}
2389
2390/**
2391 * ic4_tx_empty - Is the transmitter empty?
2392 * @port: Port to operate on
2393 *
2394 */
2395static unsigned int ic4_tx_empty(struct uart_port *the_port)
2396{
2397 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2398 unsigned int ret = 0;
2399
2400 if (port_is_active(port, the_port)) {
2401 if (readl(&port->ip_serial_regs->shadow) & IOC4_SHADOW_TEMT)
2402 ret = TIOCSER_TEMT;
2403 }
2404 return ret;
2405}
2406
2407/**
2408 * ic4_stop_tx - stop the transmitter
2409 * @port: Port to operate on
2410 *
2411 */
2412static void ic4_stop_tx(struct uart_port *the_port)
2413{
2414 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2415
2416 if (port_is_active(port, the_port))
2417 set_notification(port, N_OUTPUT_LOWAT, 0);
2418}
2419
2420/**
2421 * null_void_function -
2422 * @port: Port to operate on
2423 *
2424 */
2425static void null_void_function(struct uart_port *the_port)
2426{
2427}
2428
2429/**
2430 * ic4_shutdown - shut down the port - free irq and disable
2431 * @port: Port to shut down
2432 *
2433 */
2434static void ic4_shutdown(struct uart_port *the_port)
2435{
2436 unsigned long port_flags;
2437 struct ioc4_port *port;
2438 struct uart_state *state;
2439
2440 port = get_ioc4_port(the_port, 0);
2441 if (!port)
2442 return;
2443
2444 state = the_port->state;
2445 port->ip_port = NULL;
2446
2447 wake_up_interruptible(&state->port.delta_msr_wait);
2448
2449 if (state->port.tty)
2450 set_bit(TTY_IO_ERROR, &state->port.tty->flags);
2451
2452 spin_lock_irqsave(&the_port->lock, port_flags);
2453 set_notification(port, N_ALL, 0);
2454 port->ip_flags = PORT_INACTIVE;
2455 spin_unlock_irqrestore(&the_port->lock, port_flags);
2456}
2457
2458/**
2459 * ic4_set_mctrl - set control lines (dtr, rts, etc)
2460 * @port: Port to operate on
2461 * @mctrl: Lines to set/unset
2462 *
2463 */
2464static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2465{
2466 unsigned char mcr = 0;
2467 struct ioc4_port *port;
2468
2469 port = get_ioc4_port(the_port, 0);
2470 if (!port_is_active(port, the_port))
2471 return;
2472
2473 if (mctrl & TIOCM_RTS)
2474 mcr |= UART_MCR_RTS;
2475 if (mctrl & TIOCM_DTR)
2476 mcr |= UART_MCR_DTR;
2477 if (mctrl & TIOCM_OUT1)
2478 mcr |= UART_MCR_OUT1;
2479 if (mctrl & TIOCM_OUT2)
2480 mcr |= UART_MCR_OUT2;
2481 if (mctrl & TIOCM_LOOP)
2482 mcr |= UART_MCR_LOOP;
2483
2484 set_mcr(the_port, mcr, IOC4_SHADOW_DTR);
2485}
2486
2487/**
2488 * ic4_get_mctrl - get control line info
2489 * @port: port to operate on
2490 *
2491 */
2492static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2493{
2494 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2495 uint32_t shadow;
2496 unsigned int ret = 0;
2497
2498 if (!port_is_active(port, the_port))
2499 return 0;
2500
2501 shadow = readl(&port->ip_serial_regs->shadow);
2502 if (shadow & IOC4_SHADOW_DCD)
2503 ret |= TIOCM_CAR;
2504 if (shadow & IOC4_SHADOW_DR)
2505 ret |= TIOCM_DSR;
2506 if (shadow & IOC4_SHADOW_CTS)
2507 ret |= TIOCM_CTS;
2508 return ret;
2509}
2510
2511/**
2512 * ic4_start_tx - Start transmitter, flush any output
2513 * @port: Port to operate on
2514 *
2515 */
2516static void ic4_start_tx(struct uart_port *the_port)
2517{
2518 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2519
2520 if (port_is_active(port, the_port)) {
2521 set_notification(port, N_OUTPUT_LOWAT, 1);
2522 enable_intrs(port, port->ip_hooks->intr_tx_mt);
2523 }
2524}
2525
2526/**
2527 * ic4_break_ctl - handle breaks
2528 * @port: Port to operate on
2529 * @break_state: Break state
2530 *
2531 */
2532static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2533{
2534}
2535
2536/**
2537 * ic4_startup - Start up the serial port
2538 * @port: Port to operate on
2539 *
2540 */
2541static int ic4_startup(struct uart_port *the_port)
2542{
2543 int retval;
2544 struct ioc4_port *port;
2545 struct ioc4_control *control;
2546 struct uart_state *state;
2547 unsigned long port_flags;
2548
2549 if (!the_port)
2550 return -ENODEV;
2551 port = get_ioc4_port(the_port, 1);
2552 if (!port)
2553 return -ENODEV;
2554 state = the_port->state;
2555
2556 control = port->ip_control;
2557 if (!control) {
2558 port->ip_port = NULL;
2559 return -ENODEV;
2560 }
2561
2562 /* Start up the serial port */
2563 spin_lock_irqsave(&the_port->lock, port_flags);
2564 retval = ic4_startup_local(the_port);
2565 spin_unlock_irqrestore(&the_port->lock, port_flags);
2566 return retval;
2567}
2568
2569/**
2570 * ic4_set_termios - set termios stuff
2571 * @port: port to operate on
2572 * @termios: New settings
2573 * @termios: Old
2574 *
2575 */
2576static void
2577ic4_set_termios(struct uart_port *the_port,
2578 struct ktermios *termios, struct ktermios *old_termios)
2579{
2580 unsigned long port_flags;
2581
2582 spin_lock_irqsave(&the_port->lock, port_flags);
2583 ioc4_change_speed(the_port, termios, old_termios);
2584 spin_unlock_irqrestore(&the_port->lock, port_flags);
2585}
2586
2587/**
2588 * ic4_request_port - allocate resources for port - no op....
2589 * @port: port to operate on
2590 *
2591 */
2592static int ic4_request_port(struct uart_port *port)
2593{
2594 return 0;
2595}
2596
2597/* Associate the uart functions above - given to serial core */
2598
2599static struct uart_ops ioc4_ops = {
2600 .tx_empty = ic4_tx_empty,
2601 .set_mctrl = ic4_set_mctrl,
2602 .get_mctrl = ic4_get_mctrl,
2603 .stop_tx = ic4_stop_tx,
2604 .start_tx = ic4_start_tx,
2605 .stop_rx = null_void_function,
2606 .break_ctl = ic4_break_ctl,
2607 .startup = ic4_startup,
2608 .shutdown = ic4_shutdown,
2609 .set_termios = ic4_set_termios,
2610 .type = ic4_type,
2611 .release_port = null_void_function,
2612 .request_port = ic4_request_port,
2613};
2614
2615/*
2616 * Boot-time initialization code
2617 */
2618
2619static struct uart_driver ioc4_uart_rs232 = {
2620 .owner = THIS_MODULE,
2621 .driver_name = "ioc4_serial_rs232",
2622 .dev_name = DEVICE_NAME_RS232,
2623 .major = DEVICE_MAJOR,
2624 .minor = DEVICE_MINOR_RS232,
2625 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2626};
2627
2628static struct uart_driver ioc4_uart_rs422 = {
2629 .owner = THIS_MODULE,
2630 .driver_name = "ioc4_serial_rs422",
2631 .dev_name = DEVICE_NAME_RS422,
2632 .major = DEVICE_MAJOR,
2633 .minor = DEVICE_MINOR_RS422,
2634 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2635};
2636
2637
2638/**
2639 * ioc4_serial_remove_one - detach function
2640 *
2641 * @idd: IOC4 master module data for this IOC4
2642 */
2643
2644static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2645{
2646 int port_num, port_type;
2647 struct ioc4_control *control;
2648 struct uart_port *the_port;
2649 struct ioc4_port *port;
2650 struct ioc4_soft *soft;
2651
2652 /* If serial driver did not attach, don't try to detach */
2653 control = idd->idd_serial_data;
2654 if (!control)
2655 return 0;
2656
2657 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2658 for (port_type = UART_PORT_MIN;
2659 port_type < UART_PORT_COUNT;
2660 port_type++) {
2661 the_port = &control->ic_port[port_num].icp_uart_port
2662 [port_type];
2663 if (the_port) {
2664 switch (port_type) {
2665 case UART_PORT_RS422:
2666 uart_remove_one_port(&ioc4_uart_rs422,
2667 the_port);
2668 break;
2669 default:
2670 case UART_PORT_RS232:
2671 uart_remove_one_port(&ioc4_uart_rs232,
2672 the_port);
2673 break;
2674 }
2675 }
2676 }
2677 port = control->ic_port[port_num].icp_port;
2678 /* we allocate in pairs */
2679 if (!(port_num & 1) && port) {
2680 pci_free_consistent(port->ip_pdev,
2681 TOTAL_RING_BUF_SIZE,
2682 port->ip_cpu_ringbuf,
2683 port->ip_dma_ringbuf);
2684 kfree(port);
2685 }
2686 }
2687 soft = control->ic_soft;
2688 if (soft) {
2689 free_irq(control->ic_irq, soft);
2690 if (soft->is_ioc4_serial_addr) {
2691 iounmap(soft->is_ioc4_serial_addr);
2692 release_mem_region((unsigned long)
2693 soft->is_ioc4_serial_addr,
2694 sizeof(struct ioc4_serial));
2695 }
2696 kfree(soft);
2697 }
2698 kfree(control);
2699 idd->idd_serial_data = NULL;
2700
2701 return 0;
2702}
2703
2704
2705/**
2706 * ioc4_serial_core_attach_rs232 - register with serial core
2707 * This is done during pci probing
2708 * @pdev: handle for this card
2709 */
2710static inline int
2711ioc4_serial_core_attach(struct pci_dev *pdev, int port_type)
2712{
2713 struct ioc4_port *port;
2714 struct uart_port *the_port;
2715 struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2716 struct ioc4_control *control = idd->idd_serial_data;
2717 int port_num;
2718 int port_type_idx;
2719 struct uart_driver *u_driver;
2720
2721
2722 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2723 __func__, pdev, (void *)control));
2724
2725 if (!control)
2726 return -ENODEV;
2727
2728 port_type_idx = (port_type == PROTO_RS232) ? UART_PORT_RS232
2729 : UART_PORT_RS422;
2730
2731 u_driver = (port_type == PROTO_RS232) ? &ioc4_uart_rs232
2732 : &ioc4_uart_rs422;
2733
2734 /* once around for each port on this card */
2735 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2736 the_port = &control->ic_port[port_num].icp_uart_port
2737 [port_type_idx];
2738 port = control->ic_port[port_num].icp_port;
2739 port->ip_all_ports[port_type_idx] = the_port;
2740
2741 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p : type %s\n",
2742 __func__, (void *)the_port,
2743 (void *)port,
2744 port_type == PROTO_RS232 ? "rs232" : "rs422"));
2745
2746 /* membase, iobase and mapbase just need to be non-0 */
2747 the_port->membase = (unsigned char __iomem *)1;
2748 the_port->iobase = (pdev->bus->number << 16) | port_num;
2749 the_port->line = (Num_of_ioc4_cards << 2) | port_num;
2750 the_port->mapbase = port_type;
2751 the_port->type = PORT_16550A;
2752 the_port->fifosize = IOC4_FIFO_CHARS;
2753 the_port->ops = &ioc4_ops;
2754 the_port->irq = control->ic_irq;
2755 the_port->dev = &pdev->dev;
2756 spin_lock_init(&the_port->lock);
2757 if (uart_add_one_port(u_driver, the_port) < 0) {
2758 printk(KERN_WARNING
2759 "%s: unable to add port %d bus %d\n",
2760 __func__, the_port->line, pdev->bus->number);
2761 } else {
2762 DPRINT_CONFIG(
2763 ("IOC4 serial port %d irq = %d, bus %d\n",
2764 the_port->line, the_port->irq, pdev->bus->number));
2765 }
2766 }
2767 return 0;
2768}
2769
2770/**
2771 * ioc4_serial_attach_one - register attach function
2772 * called per card found from IOC4 master module.
2773 * @idd: Master module data for this IOC4
2774 */
2775static int
2776ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2777{
2778 unsigned long tmp_addr1;
2779 struct ioc4_serial __iomem *serial;
2780 struct ioc4_soft *soft;
2781 struct ioc4_control *control;
2782 int ret = 0;
2783
2784
2785 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, idd->idd_pdev,
2786 idd->idd_pci_id));
2787
2788 /* PCI-RT does not bring out serial connections.
2789 * Do not attach to this particular IOC4.
2790 */
2791 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
2792 return 0;
2793
2794 /* request serial registers */
2795 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
2796
2797 if (!request_mem_region(tmp_addr1, sizeof(struct ioc4_serial),
2798 "sioc4_uart")) {
2799 printk(KERN_WARNING
2800 "ioc4 (%p): unable to get request region for "
2801 "uart space\n", (void *)idd->idd_pdev);
2802 ret = -ENODEV;
2803 goto out1;
2804 }
2805 serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial));
2806 if (!serial) {
2807 printk(KERN_WARNING
2808 "ioc4 (%p) : unable to remap ioc4 serial register\n",
2809 (void *)idd->idd_pdev);
2810 ret = -ENODEV;
2811 goto out2;
2812 }
2813 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2814 __func__, (void *)idd->idd_misc_regs,
2815 (void *)serial));
2816
2817 /* Get memory for the new card */
2818 control = kzalloc(sizeof(struct ioc4_control), GFP_KERNEL);
2819
2820 if (!control) {
2821 printk(KERN_WARNING "ioc4_attach_one"
2822 ": unable to get memory for the IOC4\n");
2823 ret = -ENOMEM;
2824 goto out2;
2825 }
2826 idd->idd_serial_data = control;
2827
2828 /* Allocate the soft structure */
2829 soft = kzalloc(sizeof(struct ioc4_soft), GFP_KERNEL);
2830 if (!soft) {
2831 printk(KERN_WARNING
2832 "ioc4 (%p): unable to get memory for the soft struct\n",
2833 (void *)idd->idd_pdev);
2834 ret = -ENOMEM;
2835 goto out3;
2836 }
2837
2838 spin_lock_init(&soft->is_ir_lock);
2839 soft->is_ioc4_misc_addr = idd->idd_misc_regs;
2840 soft->is_ioc4_serial_addr = serial;
2841
2842 /* Init the IOC4 */
2843 writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT,
2844 &idd->idd_misc_regs->sio_cr.raw);
2845
2846 /* Enable serial port mode select generic PIO pins as outputs */
2847 writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL
2848 | IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL,
2849 &idd->idd_misc_regs->gpcr_s.raw);
2850
2851 /* Clear and disable all serial interrupts */
2852 write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
2853 writel(~0, &idd->idd_misc_regs->sio_ir.raw);
2854 write_ireg(soft, IOC4_OTHER_IR_SER_MEMERR, IOC4_W_IEC,
2855 IOC4_OTHER_INTR_TYPE);
2856 writel(IOC4_OTHER_IR_SER_MEMERR, &idd->idd_misc_regs->other_ir.raw);
2857 control->ic_soft = soft;
2858
2859 /* Hook up interrupt handler */
2860 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, IRQF_SHARED,
2861 "sgi-ioc4serial", soft)) {
2862 control->ic_irq = idd->idd_pdev->irq;
2863 } else {
2864 printk(KERN_WARNING
2865 "%s : request_irq fails for IRQ 0x%x\n ",
2866 __func__, idd->idd_pdev->irq);
2867 }
2868 ret = ioc4_attach_local(idd);
2869 if (ret)
2870 goto out4;
2871
2872 /* register port with the serial core - 1 rs232, 1 rs422 */
2873
2874 ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS232);
2875 if (ret)
2876 goto out4;
2877
2878 ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS422);
2879 if (ret)
2880 goto out5;
2881
2882 Num_of_ioc4_cards++;
2883
2884 return ret;
2885
2886 /* error exits that give back resources */
2887out5:
2888 ioc4_serial_remove_one(idd);
2889 return ret;
2890out4:
2891 kfree(soft);
2892out3:
2893 kfree(control);
2894out2:
2895 if (serial)
2896 iounmap(serial);
2897 release_mem_region(tmp_addr1, sizeof(struct ioc4_serial));
2898out1:
2899
2900 return ret;
2901}
2902
2903
2904static struct ioc4_submodule ioc4_serial_submodule = {
2905 .is_name = "IOC4_serial",
2906 .is_owner = THIS_MODULE,
2907 .is_probe = ioc4_serial_attach_one,
2908 .is_remove = ioc4_serial_remove_one,
2909};
2910
2911/**
2912 * ioc4_serial_init - module init
2913 */
2914static int __init ioc4_serial_init(void)
2915{
2916 int ret;
2917
2918 /* register with serial core */
2919 if ((ret = uart_register_driver(&ioc4_uart_rs232)) < 0) {
2920 printk(KERN_WARNING
2921 "%s: Couldn't register rs232 IOC4 serial driver\n",
2922 __func__);
2923 goto out;
2924 }
2925 if ((ret = uart_register_driver(&ioc4_uart_rs422)) < 0) {
2926 printk(KERN_WARNING
2927 "%s: Couldn't register rs422 IOC4 serial driver\n",
2928 __func__);
2929 goto out_uart_rs232;
2930 }
2931
2932 /* register with IOC4 main module */
2933 ret = ioc4_register_submodule(&ioc4_serial_submodule);
2934 if (ret)
2935 goto out_uart_rs422;
2936 return 0;
2937
2938out_uart_rs422:
2939 uart_unregister_driver(&ioc4_uart_rs422);
2940out_uart_rs232:
2941 uart_unregister_driver(&ioc4_uart_rs232);
2942out:
2943 return ret;
2944}
2945
2946static void __exit ioc4_serial_exit(void)
2947{
2948 ioc4_unregister_submodule(&ioc4_serial_submodule);
2949 uart_unregister_driver(&ioc4_uart_rs232);
2950 uart_unregister_driver(&ioc4_uart_rs422);
2951}
2952
2953late_initcall(ioc4_serial_init); /* Call only after tty init is done */
2954module_exit(ioc4_serial_exit);
2955
2956MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2957MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2958MODULE_LICENSE("GPL");