1/*
  2 *  Driver for CPM (SCC/SMC) serial ports
  3 *
  4 *  Copyright (C) 2004 Freescale Semiconductor, Inc.
  5 *
  6 *  2006 (c) MontaVista Software, Inc.
  7 *	Vitaly Bordug <vbordug@ru.mvista.com>
  8 *
  9 * This file is licensed under the terms of the GNU General Public License
 10 * version 2. This program is licensed "as is" without any warranty of any
 11 * kind, whether express or implied.
 12 *
 13 */
 14#ifndef CPM_UART_H
 15#define CPM_UART_H
 16
 17#include <linux/platform_device.h>
 18#include <linux/fs_uart_pd.h>
 19
 20#if defined(CONFIG_CPM2)
 21#include "cpm_uart_cpm2.h"
 22#elif defined(CONFIG_CPM1)
 23#include "cpm_uart_cpm1.h"
 24#endif
 25
 26#define SERIAL_CPM_MAJOR	204
 27#define SERIAL_CPM_MINOR	46
 28
 29#define IS_SMC(pinfo)		(pinfo->flags & FLAG_SMC)
 30#define IS_DISCARDING(pinfo)	(pinfo->flags & FLAG_DISCARDING)
 31#define FLAG_DISCARDING	0x00000004	/* when set, don't discard */
 32#define FLAG_SMC	0x00000002
 33#define FLAG_CONSOLE	0x00000001
 34
 35#define UART_SMC1	fsid_smc1_uart
 36#define UART_SMC2	fsid_smc2_uart
 37#define UART_SCC1	fsid_scc1_uart
 38#define UART_SCC2	fsid_scc2_uart
 39#define UART_SCC3	fsid_scc3_uart
 40#define UART_SCC4	fsid_scc4_uart
 41
 42#define UART_NR		fs_uart_nr
 43
 44#define RX_NUM_FIFO	4
 45#define RX_BUF_SIZE	32
 46#define TX_NUM_FIFO	4
 47#define TX_BUF_SIZE	32
 48
 49#define SCC_WAIT_CLOSING 100
 50
 51#define GPIO_CTS	0
 52#define GPIO_RTS	1
 53#define GPIO_DCD	2
 54#define GPIO_DSR	3
 55#define GPIO_DTR	4
 56#define GPIO_RI		5
 57
 58#define NUM_GPIOS	(GPIO_RI+1)
 59
 60struct uart_cpm_port {
 61	struct uart_port	port;
 62	u16			rx_nrfifos;
 63	u16			rx_fifosize;
 64	u16			tx_nrfifos;
 65	u16			tx_fifosize;
 66	smc_t __iomem		*smcp;
 67	smc_uart_t __iomem	*smcup;
 68	scc_t __iomem		*sccp;
 69	scc_uart_t __iomem	*sccup;
 70	cbd_t __iomem		*rx_bd_base;
 71	cbd_t __iomem		*rx_cur;
 72	cbd_t __iomem		*tx_bd_base;
 73	cbd_t __iomem		*tx_cur;
 74	unsigned char		*tx_buf;
 75	unsigned char		*rx_buf;
 76	u32			flags;
 77	struct clk		*clk;
 78	u8			brg;
 79	uint			 dp_addr;
 80	void			*mem_addr;
 81	dma_addr_t		 dma_addr;
 82	u32			mem_size;
 83	/* wait on close if needed */
 84	int			wait_closing;
 85	/* value to combine with opcode to form cpm command */
 86	u32			command;
 87	int			gpios[NUM_GPIOS];
 88};
 89
 90extern int cpm_uart_nr;
 91extern struct uart_cpm_port cpm_uart_ports[UART_NR];
 92
 93/* these are located in their respective files */
 94void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd);
 95void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
 96				struct device_node *np);
 97void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram);
 98int cpm_uart_init_portdesc(void);
 99int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con);
100void cpm_uart_freebuf(struct uart_cpm_port *pinfo);
101
102void smc1_lineif(struct uart_cpm_port *pinfo);
103void smc2_lineif(struct uart_cpm_port *pinfo);
104void scc1_lineif(struct uart_cpm_port *pinfo);
105void scc2_lineif(struct uart_cpm_port *pinfo);
106void scc3_lineif(struct uart_cpm_port *pinfo);
107void scc4_lineif(struct uart_cpm_port *pinfo);
108
109/*
110   virtual to phys transtalion
111*/
112static inline unsigned long cpu2cpm_addr(void *addr,
113                                         struct uart_cpm_port *pinfo)
114{
115	int offset;
116	u32 val = (u32)addr;
117	u32 mem = (u32)pinfo->mem_addr;
118	/* sane check */
119	if (likely(val >= mem && val < mem + pinfo->mem_size)) {
120		offset = val - mem;
121		return pinfo->dma_addr + offset;
122	}
123	/* something nasty happened */
124	BUG();
125	return 0;
126}
127
128static inline void *cpm2cpu_addr(unsigned long addr,
129                                 struct uart_cpm_port *pinfo)
130{
131	int offset;
132	u32 val = addr;
133	u32 dma = (u32)pinfo->dma_addr;
134	/* sane check */
135	if (likely(val >= dma && val < dma + pinfo->mem_size)) {
136		offset = val - dma;
137		return pinfo->mem_addr + offset;
138	}
139	/* something nasty happened */
140	BUG();
141	return NULL;
142}
143
144
145#endif /* CPM_UART_H */