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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 * Copyright (C) 2010 ST-Ericsson SA
10 *
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
17 */
18
19#include <linux/module.h>
20#include <linux/ioport.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/platform_device.h>
24#include <linux/sysrq.h>
25#include <linux/device.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/serial_core.h>
29#include <linux/serial.h>
30#include <linux/amba/bus.h>
31#include <linux/amba/serial.h>
32#include <linux/clk.h>
33#include <linux/slab.h>
34#include <linux/dmaengine.h>
35#include <linux/dma-mapping.h>
36#include <linux/scatterlist.h>
37#include <linux/delay.h>
38#include <linux/types.h>
39#include <linux/of.h>
40#include <linux/pinctrl/consumer.h>
41#include <linux/sizes.h>
42#include <linux/io.h>
43#include <linux/acpi.h>
44
45#define UART_NR 14
46
47#define SERIAL_AMBA_MAJOR 204
48#define SERIAL_AMBA_MINOR 64
49#define SERIAL_AMBA_NR UART_NR
50
51#define AMBA_ISR_PASS_LIMIT 256
52
53#define UART_DR_ERROR (UART011_DR_OE | UART011_DR_BE | UART011_DR_PE | UART011_DR_FE)
54#define UART_DUMMY_DR_RX BIT(16)
55
56enum {
57 REG_DR,
58 REG_ST_DMAWM,
59 REG_ST_TIMEOUT,
60 REG_FR,
61 REG_LCRH_RX,
62 REG_LCRH_TX,
63 REG_IBRD,
64 REG_FBRD,
65 REG_CR,
66 REG_IFLS,
67 REG_IMSC,
68 REG_RIS,
69 REG_MIS,
70 REG_ICR,
71 REG_DMACR,
72 REG_ST_XFCR,
73 REG_ST_XON1,
74 REG_ST_XON2,
75 REG_ST_XOFF1,
76 REG_ST_XOFF2,
77 REG_ST_ITCR,
78 REG_ST_ITIP,
79 REG_ST_ABCR,
80 REG_ST_ABIMSC,
81
82 /* The size of the array - must be last */
83 REG_ARRAY_SIZE,
84};
85
86static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
87 [REG_DR] = UART01x_DR,
88 [REG_FR] = UART01x_FR,
89 [REG_LCRH_RX] = UART011_LCRH,
90 [REG_LCRH_TX] = UART011_LCRH,
91 [REG_IBRD] = UART011_IBRD,
92 [REG_FBRD] = UART011_FBRD,
93 [REG_CR] = UART011_CR,
94 [REG_IFLS] = UART011_IFLS,
95 [REG_IMSC] = UART011_IMSC,
96 [REG_RIS] = UART011_RIS,
97 [REG_MIS] = UART011_MIS,
98 [REG_ICR] = UART011_ICR,
99 [REG_DMACR] = UART011_DMACR,
100};
101
102/* There is by now at least one vendor with differing details, so handle it */
103struct vendor_data {
104 const u16 *reg_offset;
105 unsigned int ifls;
106 unsigned int fr_busy;
107 unsigned int fr_dsr;
108 unsigned int fr_cts;
109 unsigned int fr_ri;
110 unsigned int inv_fr;
111 bool access_32b;
112 bool oversampling;
113 bool dma_threshold;
114 bool cts_event_workaround;
115 bool always_enabled;
116 bool fixed_options;
117
118 unsigned int (*get_fifosize)(struct amba_device *dev);
119};
120
121static unsigned int get_fifosize_arm(struct amba_device *dev)
122{
123 return amba_rev(dev) < 3 ? 16 : 32;
124}
125
126static struct vendor_data vendor_arm = {
127 .reg_offset = pl011_std_offsets,
128 .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8,
129 .fr_busy = UART01x_FR_BUSY,
130 .fr_dsr = UART01x_FR_DSR,
131 .fr_cts = UART01x_FR_CTS,
132 .fr_ri = UART011_FR_RI,
133 .oversampling = false,
134 .dma_threshold = false,
135 .cts_event_workaround = false,
136 .always_enabled = false,
137 .fixed_options = false,
138 .get_fifosize = get_fifosize_arm,
139};
140
141static const struct vendor_data vendor_sbsa = {
142 .reg_offset = pl011_std_offsets,
143 .fr_busy = UART01x_FR_BUSY,
144 .fr_dsr = UART01x_FR_DSR,
145 .fr_cts = UART01x_FR_CTS,
146 .fr_ri = UART011_FR_RI,
147 .access_32b = true,
148 .oversampling = false,
149 .dma_threshold = false,
150 .cts_event_workaround = false,
151 .always_enabled = true,
152 .fixed_options = true,
153};
154
155#ifdef CONFIG_ACPI_SPCR_TABLE
156static const struct vendor_data vendor_qdt_qdf2400_e44 = {
157 .reg_offset = pl011_std_offsets,
158 .fr_busy = UART011_FR_TXFE,
159 .fr_dsr = UART01x_FR_DSR,
160 .fr_cts = UART01x_FR_CTS,
161 .fr_ri = UART011_FR_RI,
162 .inv_fr = UART011_FR_TXFE,
163 .access_32b = true,
164 .oversampling = false,
165 .dma_threshold = false,
166 .cts_event_workaround = false,
167 .always_enabled = true,
168 .fixed_options = true,
169};
170#endif
171
172static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
173 [REG_DR] = UART01x_DR,
174 [REG_ST_DMAWM] = ST_UART011_DMAWM,
175 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
176 [REG_FR] = UART01x_FR,
177 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
178 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
179 [REG_IBRD] = UART011_IBRD,
180 [REG_FBRD] = UART011_FBRD,
181 [REG_CR] = UART011_CR,
182 [REG_IFLS] = UART011_IFLS,
183 [REG_IMSC] = UART011_IMSC,
184 [REG_RIS] = UART011_RIS,
185 [REG_MIS] = UART011_MIS,
186 [REG_ICR] = UART011_ICR,
187 [REG_DMACR] = UART011_DMACR,
188 [REG_ST_XFCR] = ST_UART011_XFCR,
189 [REG_ST_XON1] = ST_UART011_XON1,
190 [REG_ST_XON2] = ST_UART011_XON2,
191 [REG_ST_XOFF1] = ST_UART011_XOFF1,
192 [REG_ST_XOFF2] = ST_UART011_XOFF2,
193 [REG_ST_ITCR] = ST_UART011_ITCR,
194 [REG_ST_ITIP] = ST_UART011_ITIP,
195 [REG_ST_ABCR] = ST_UART011_ABCR,
196 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
197};
198
199static unsigned int get_fifosize_st(struct amba_device *dev)
200{
201 return 64;
202}
203
204static struct vendor_data vendor_st = {
205 .reg_offset = pl011_st_offsets,
206 .ifls = UART011_IFLS_RX_HALF | UART011_IFLS_TX_HALF,
207 .fr_busy = UART01x_FR_BUSY,
208 .fr_dsr = UART01x_FR_DSR,
209 .fr_cts = UART01x_FR_CTS,
210 .fr_ri = UART011_FR_RI,
211 .oversampling = true,
212 .dma_threshold = true,
213 .cts_event_workaround = true,
214 .always_enabled = false,
215 .fixed_options = false,
216 .get_fifosize = get_fifosize_st,
217};
218
219/* Deals with DMA transactions */
220
221struct pl011_dmabuf {
222 dma_addr_t dma;
223 size_t len;
224 char *buf;
225};
226
227struct pl011_dmarx_data {
228 struct dma_chan *chan;
229 struct completion complete;
230 bool use_buf_b;
231 struct pl011_dmabuf dbuf_a;
232 struct pl011_dmabuf dbuf_b;
233 dma_cookie_t cookie;
234 bool running;
235 struct timer_list timer;
236 unsigned int last_residue;
237 unsigned long last_jiffies;
238 bool auto_poll_rate;
239 unsigned int poll_rate;
240 unsigned int poll_timeout;
241};
242
243struct pl011_dmatx_data {
244 struct dma_chan *chan;
245 dma_addr_t dma;
246 size_t len;
247 char *buf;
248 bool queued;
249};
250
251/*
252 * We wrap our port structure around the generic uart_port.
253 */
254struct uart_amba_port {
255 struct uart_port port;
256 const u16 *reg_offset;
257 struct clk *clk;
258 const struct vendor_data *vendor;
259 unsigned int dmacr; /* dma control reg */
260 unsigned int im; /* interrupt mask */
261 unsigned int old_status;
262 unsigned int fifosize; /* vendor-specific */
263 unsigned int fixed_baud; /* vendor-set fixed baud rate */
264 char type[12];
265 bool rs485_tx_started;
266 unsigned int rs485_tx_drain_interval; /* usecs */
267#ifdef CONFIG_DMA_ENGINE
268 /* DMA stuff */
269 bool using_tx_dma;
270 bool using_rx_dma;
271 struct pl011_dmarx_data dmarx;
272 struct pl011_dmatx_data dmatx;
273 bool dma_probed;
274#endif
275};
276
277static unsigned int pl011_tx_empty(struct uart_port *port);
278
279static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
280 unsigned int reg)
281{
282 return uap->reg_offset[reg];
283}
284
285static unsigned int pl011_read(const struct uart_amba_port *uap,
286 unsigned int reg)
287{
288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
289
290 return (uap->port.iotype == UPIO_MEM32) ?
291 readl_relaxed(addr) : readw_relaxed(addr);
292}
293
294static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
295 unsigned int reg)
296{
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
298
299 if (uap->port.iotype == UPIO_MEM32)
300 writel_relaxed(val, addr);
301 else
302 writew_relaxed(val, addr);
303}
304
305/*
306 * Reads up to 256 characters from the FIFO or until it's empty and
307 * inserts them into the TTY layer. Returns the number of characters
308 * read from the FIFO.
309 */
310static int pl011_fifo_to_tty(struct uart_amba_port *uap)
311{
312 unsigned int ch, fifotaken;
313 int sysrq;
314 u16 status;
315 u8 flag;
316
317 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
318 status = pl011_read(uap, REG_FR);
319 if (status & UART01x_FR_RXFE)
320 break;
321
322 /* Take chars from the FIFO and update status */
323 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
324 flag = TTY_NORMAL;
325 uap->port.icount.rx++;
326
327 if (unlikely(ch & UART_DR_ERROR)) {
328 if (ch & UART011_DR_BE) {
329 ch &= ~(UART011_DR_FE | UART011_DR_PE);
330 uap->port.icount.brk++;
331 if (uart_handle_break(&uap->port))
332 continue;
333 } else if (ch & UART011_DR_PE) {
334 uap->port.icount.parity++;
335 } else if (ch & UART011_DR_FE) {
336 uap->port.icount.frame++;
337 }
338 if (ch & UART011_DR_OE)
339 uap->port.icount.overrun++;
340
341 ch &= uap->port.read_status_mask;
342
343 if (ch & UART011_DR_BE)
344 flag = TTY_BREAK;
345 else if (ch & UART011_DR_PE)
346 flag = TTY_PARITY;
347 else if (ch & UART011_DR_FE)
348 flag = TTY_FRAME;
349 }
350
351 uart_port_unlock(&uap->port);
352 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
353 uart_port_lock(&uap->port);
354
355 if (!sysrq)
356 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
357 }
358
359 return fifotaken;
360}
361
362/*
363 * All the DMA operation mode stuff goes inside this ifdef.
364 * This assumes that you have a generic DMA device interface,
365 * no custom DMA interfaces are supported.
366 */
367#ifdef CONFIG_DMA_ENGINE
368
369#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
370
371static int pl011_dmabuf_init(struct dma_chan *chan, struct pl011_dmabuf *db,
372 enum dma_data_direction dir)
373{
374 db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE,
375 &db->dma, GFP_KERNEL);
376 if (!db->buf)
377 return -ENOMEM;
378 db->len = PL011_DMA_BUFFER_SIZE;
379
380 return 0;
381}
382
383static void pl011_dmabuf_free(struct dma_chan *chan, struct pl011_dmabuf *db,
384 enum dma_data_direction dir)
385{
386 if (db->buf) {
387 dma_free_coherent(chan->device->dev,
388 PL011_DMA_BUFFER_SIZE, db->buf, db->dma);
389 }
390}
391
392static void pl011_dma_probe(struct uart_amba_port *uap)
393{
394 /* DMA is the sole user of the platform data right now */
395 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
396 struct device *dev = uap->port.dev;
397 struct dma_slave_config tx_conf = {
398 .dst_addr = uap->port.mapbase +
399 pl011_reg_to_offset(uap, REG_DR),
400 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
401 .direction = DMA_MEM_TO_DEV,
402 .dst_maxburst = uap->fifosize >> 1,
403 .device_fc = false,
404 };
405 struct dma_chan *chan;
406 dma_cap_mask_t mask;
407
408 uap->dma_probed = true;
409 chan = dma_request_chan(dev, "tx");
410 if (IS_ERR(chan)) {
411 if (PTR_ERR(chan) == -EPROBE_DEFER) {
412 uap->dma_probed = false;
413 return;
414 }
415
416 /* We need platform data */
417 if (!plat || !plat->dma_filter) {
418 dev_dbg(uap->port.dev, "no DMA platform data\n");
419 return;
420 }
421
422 /* Try to acquire a generic DMA engine slave TX channel */
423 dma_cap_zero(mask);
424 dma_cap_set(DMA_SLAVE, mask);
425
426 chan = dma_request_channel(mask, plat->dma_filter,
427 plat->dma_tx_param);
428 if (!chan) {
429 dev_err(uap->port.dev, "no TX DMA channel!\n");
430 return;
431 }
432 }
433
434 dmaengine_slave_config(chan, &tx_conf);
435 uap->dmatx.chan = chan;
436
437 dev_info(uap->port.dev, "DMA channel TX %s\n",
438 dma_chan_name(uap->dmatx.chan));
439
440 /* Optionally make use of an RX channel as well */
441 chan = dma_request_chan(dev, "rx");
442
443 if (IS_ERR(chan) && plat && plat->dma_rx_param) {
444 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
445
446 if (!chan) {
447 dev_err(uap->port.dev, "no RX DMA channel!\n");
448 return;
449 }
450 }
451
452 if (!IS_ERR(chan)) {
453 struct dma_slave_config rx_conf = {
454 .src_addr = uap->port.mapbase +
455 pl011_reg_to_offset(uap, REG_DR),
456 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
457 .direction = DMA_DEV_TO_MEM,
458 .src_maxburst = uap->fifosize >> 2,
459 .device_fc = false,
460 };
461 struct dma_slave_caps caps;
462
463 /*
464 * Some DMA controllers provide information on their capabilities.
465 * If the controller does, check for suitable residue processing
466 * otherwise assime all is well.
467 */
468 if (dma_get_slave_caps(chan, &caps) == 0) {
469 if (caps.residue_granularity ==
470 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
471 dma_release_channel(chan);
472 dev_info(uap->port.dev,
473 "RX DMA disabled - no residue processing\n");
474 return;
475 }
476 }
477 dmaengine_slave_config(chan, &rx_conf);
478 uap->dmarx.chan = chan;
479
480 uap->dmarx.auto_poll_rate = false;
481 if (plat && plat->dma_rx_poll_enable) {
482 /* Set poll rate if specified. */
483 if (plat->dma_rx_poll_rate) {
484 uap->dmarx.auto_poll_rate = false;
485 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
486 } else {
487 /*
488 * 100 ms defaults to poll rate if not
489 * specified. This will be adjusted with
490 * the baud rate at set_termios.
491 */
492 uap->dmarx.auto_poll_rate = true;
493 uap->dmarx.poll_rate = 100;
494 }
495 /* 3 secs defaults poll_timeout if not specified. */
496 if (plat->dma_rx_poll_timeout)
497 uap->dmarx.poll_timeout =
498 plat->dma_rx_poll_timeout;
499 else
500 uap->dmarx.poll_timeout = 3000;
501 } else if (!plat && dev->of_node) {
502 uap->dmarx.auto_poll_rate =
503 of_property_read_bool(dev->of_node, "auto-poll");
504 if (uap->dmarx.auto_poll_rate) {
505 u32 x;
506
507 if (of_property_read_u32(dev->of_node, "poll-rate-ms", &x) == 0)
508 uap->dmarx.poll_rate = x;
509 else
510 uap->dmarx.poll_rate = 100;
511 if (of_property_read_u32(dev->of_node, "poll-timeout-ms", &x) == 0)
512 uap->dmarx.poll_timeout = x;
513 else
514 uap->dmarx.poll_timeout = 3000;
515 }
516 }
517 dev_info(uap->port.dev, "DMA channel RX %s\n",
518 dma_chan_name(uap->dmarx.chan));
519 }
520}
521
522static void pl011_dma_remove(struct uart_amba_port *uap)
523{
524 if (uap->dmatx.chan)
525 dma_release_channel(uap->dmatx.chan);
526 if (uap->dmarx.chan)
527 dma_release_channel(uap->dmarx.chan);
528}
529
530/* Forward declare these for the refill routine */
531static int pl011_dma_tx_refill(struct uart_amba_port *uap);
532static void pl011_start_tx_pio(struct uart_amba_port *uap);
533
534/*
535 * The current DMA TX buffer has been sent.
536 * Try to queue up another DMA buffer.
537 */
538static void pl011_dma_tx_callback(void *data)
539{
540 struct uart_amba_port *uap = data;
541 struct pl011_dmatx_data *dmatx = &uap->dmatx;
542 unsigned long flags;
543 u16 dmacr;
544
545 uart_port_lock_irqsave(&uap->port, &flags);
546 if (uap->dmatx.queued)
547 dma_unmap_single(dmatx->chan->device->dev, dmatx->dma,
548 dmatx->len, DMA_TO_DEVICE);
549
550 dmacr = uap->dmacr;
551 uap->dmacr = dmacr & ~UART011_TXDMAE;
552 pl011_write(uap->dmacr, uap, REG_DMACR);
553
554 /*
555 * If TX DMA was disabled, it means that we've stopped the DMA for
556 * some reason (eg, XOFF received, or we want to send an X-char.)
557 *
558 * Note: we need to be careful here of a potential race between DMA
559 * and the rest of the driver - if the driver disables TX DMA while
560 * a TX buffer completing, we must update the tx queued status to
561 * get further refills (hence we check dmacr).
562 */
563 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
564 uart_circ_empty(&uap->port.state->xmit)) {
565 uap->dmatx.queued = false;
566 uart_port_unlock_irqrestore(&uap->port, flags);
567 return;
568 }
569
570 if (pl011_dma_tx_refill(uap) <= 0)
571 /*
572 * We didn't queue a DMA buffer for some reason, but we
573 * have data pending to be sent. Re-enable the TX IRQ.
574 */
575 pl011_start_tx_pio(uap);
576
577 uart_port_unlock_irqrestore(&uap->port, flags);
578}
579
580/*
581 * Try to refill the TX DMA buffer.
582 * Locking: called with port lock held and IRQs disabled.
583 * Returns:
584 * 1 if we queued up a TX DMA buffer.
585 * 0 if we didn't want to handle this by DMA
586 * <0 on error
587 */
588static int pl011_dma_tx_refill(struct uart_amba_port *uap)
589{
590 struct pl011_dmatx_data *dmatx = &uap->dmatx;
591 struct dma_chan *chan = dmatx->chan;
592 struct dma_device *dma_dev = chan->device;
593 struct dma_async_tx_descriptor *desc;
594 struct circ_buf *xmit = &uap->port.state->xmit;
595 unsigned int count;
596
597 /*
598 * Try to avoid the overhead involved in using DMA if the
599 * transaction fits in the first half of the FIFO, by using
600 * the standard interrupt handling. This ensures that we
601 * issue a uart_write_wakeup() at the appropriate time.
602 */
603 count = uart_circ_chars_pending(xmit);
604 if (count < (uap->fifosize >> 1)) {
605 uap->dmatx.queued = false;
606 return 0;
607 }
608
609 /*
610 * Bodge: don't send the last character by DMA, as this
611 * will prevent XON from notifying us to restart DMA.
612 */
613 count -= 1;
614
615 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
616 if (count > PL011_DMA_BUFFER_SIZE)
617 count = PL011_DMA_BUFFER_SIZE;
618
619 if (xmit->tail < xmit->head) {
620 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
621 } else {
622 size_t first = UART_XMIT_SIZE - xmit->tail;
623 size_t second;
624
625 if (first > count)
626 first = count;
627 second = count - first;
628
629 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
630 if (second)
631 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
632 }
633
634 dmatx->len = count;
635 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count,
636 DMA_TO_DEVICE);
637 if (dmatx->dma == DMA_MAPPING_ERROR) {
638 uap->dmatx.queued = false;
639 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
640 return -EBUSY;
641 }
642
643 desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV,
644 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
645 if (!desc) {
646 dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE);
647 uap->dmatx.queued = false;
648 /*
649 * If DMA cannot be used right now, we complete this
650 * transaction via IRQ and let the TTY layer retry.
651 */
652 dev_dbg(uap->port.dev, "TX DMA busy\n");
653 return -EBUSY;
654 }
655
656 /* Some data to go along to the callback */
657 desc->callback = pl011_dma_tx_callback;
658 desc->callback_param = uap;
659
660 /* All errors should happen at prepare time */
661 dmaengine_submit(desc);
662
663 /* Fire the DMA transaction */
664 dma_dev->device_issue_pending(chan);
665
666 uap->dmacr |= UART011_TXDMAE;
667 pl011_write(uap->dmacr, uap, REG_DMACR);
668 uap->dmatx.queued = true;
669
670 /*
671 * Now we know that DMA will fire, so advance the ring buffer
672 * with the stuff we just dispatched.
673 */
674 uart_xmit_advance(&uap->port, count);
675
676 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
677 uart_write_wakeup(&uap->port);
678
679 return 1;
680}
681
682/*
683 * We received a transmit interrupt without a pending X-char but with
684 * pending characters.
685 * Locking: called with port lock held and IRQs disabled.
686 * Returns:
687 * false if we want to use PIO to transmit
688 * true if we queued a DMA buffer
689 */
690static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
691{
692 if (!uap->using_tx_dma)
693 return false;
694
695 /*
696 * If we already have a TX buffer queued, but received a
697 * TX interrupt, it will be because we've just sent an X-char.
698 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
699 */
700 if (uap->dmatx.queued) {
701 uap->dmacr |= UART011_TXDMAE;
702 pl011_write(uap->dmacr, uap, REG_DMACR);
703 uap->im &= ~UART011_TXIM;
704 pl011_write(uap->im, uap, REG_IMSC);
705 return true;
706 }
707
708 /*
709 * We don't have a TX buffer queued, so try to queue one.
710 * If we successfully queued a buffer, mask the TX IRQ.
711 */
712 if (pl011_dma_tx_refill(uap) > 0) {
713 uap->im &= ~UART011_TXIM;
714 pl011_write(uap->im, uap, REG_IMSC);
715 return true;
716 }
717 return false;
718}
719
720/*
721 * Stop the DMA transmit (eg, due to received XOFF).
722 * Locking: called with port lock held and IRQs disabled.
723 */
724static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
725{
726 if (uap->dmatx.queued) {
727 uap->dmacr &= ~UART011_TXDMAE;
728 pl011_write(uap->dmacr, uap, REG_DMACR);
729 }
730}
731
732/*
733 * Try to start a DMA transmit, or in the case of an XON/OFF
734 * character queued for send, try to get that character out ASAP.
735 * Locking: called with port lock held and IRQs disabled.
736 * Returns:
737 * false if we want the TX IRQ to be enabled
738 * true if we have a buffer queued
739 */
740static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
741{
742 u16 dmacr;
743
744 if (!uap->using_tx_dma)
745 return false;
746
747 if (!uap->port.x_char) {
748 /* no X-char, try to push chars out in DMA mode */
749 bool ret = true;
750
751 if (!uap->dmatx.queued) {
752 if (pl011_dma_tx_refill(uap) > 0) {
753 uap->im &= ~UART011_TXIM;
754 pl011_write(uap->im, uap, REG_IMSC);
755 } else {
756 ret = false;
757 }
758 } else if (!(uap->dmacr & UART011_TXDMAE)) {
759 uap->dmacr |= UART011_TXDMAE;
760 pl011_write(uap->dmacr, uap, REG_DMACR);
761 }
762 return ret;
763 }
764
765 /*
766 * We have an X-char to send. Disable DMA to prevent it loading
767 * the TX fifo, and then see if we can stuff it into the FIFO.
768 */
769 dmacr = uap->dmacr;
770 uap->dmacr &= ~UART011_TXDMAE;
771 pl011_write(uap->dmacr, uap, REG_DMACR);
772
773 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
774 /*
775 * No space in the FIFO, so enable the transmit interrupt
776 * so we know when there is space. Note that once we've
777 * loaded the character, we should just re-enable DMA.
778 */
779 return false;
780 }
781
782 pl011_write(uap->port.x_char, uap, REG_DR);
783 uap->port.icount.tx++;
784 uap->port.x_char = 0;
785
786 /* Success - restore the DMA state */
787 uap->dmacr = dmacr;
788 pl011_write(dmacr, uap, REG_DMACR);
789
790 return true;
791}
792
793/*
794 * Flush the transmit buffer.
795 * Locking: called with port lock held and IRQs disabled.
796 */
797static void pl011_dma_flush_buffer(struct uart_port *port)
798__releases(&uap->port.lock)
799__acquires(&uap->port.lock)
800{
801 struct uart_amba_port *uap =
802 container_of(port, struct uart_amba_port, port);
803
804 if (!uap->using_tx_dma)
805 return;
806
807 dmaengine_terminate_async(uap->dmatx.chan);
808
809 if (uap->dmatx.queued) {
810 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma,
811 uap->dmatx.len, DMA_TO_DEVICE);
812 uap->dmatx.queued = false;
813 uap->dmacr &= ~UART011_TXDMAE;
814 pl011_write(uap->dmacr, uap, REG_DMACR);
815 }
816}
817
818static void pl011_dma_rx_callback(void *data);
819
820static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
821{
822 struct dma_chan *rxchan = uap->dmarx.chan;
823 struct pl011_dmarx_data *dmarx = &uap->dmarx;
824 struct dma_async_tx_descriptor *desc;
825 struct pl011_dmabuf *dbuf;
826
827 if (!rxchan)
828 return -EIO;
829
830 /* Start the RX DMA job */
831 dbuf = uap->dmarx.use_buf_b ?
832 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
833 desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len,
834 DMA_DEV_TO_MEM,
835 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
836 /*
837 * If the DMA engine is busy and cannot prepare a
838 * channel, no big deal, the driver will fall back
839 * to interrupt mode as a result of this error code.
840 */
841 if (!desc) {
842 uap->dmarx.running = false;
843 dmaengine_terminate_all(rxchan);
844 return -EBUSY;
845 }
846
847 /* Some data to go along to the callback */
848 desc->callback = pl011_dma_rx_callback;
849 desc->callback_param = uap;
850 dmarx->cookie = dmaengine_submit(desc);
851 dma_async_issue_pending(rxchan);
852
853 uap->dmacr |= UART011_RXDMAE;
854 pl011_write(uap->dmacr, uap, REG_DMACR);
855 uap->dmarx.running = true;
856
857 uap->im &= ~UART011_RXIM;
858 pl011_write(uap->im, uap, REG_IMSC);
859
860 return 0;
861}
862
863/*
864 * This is called when either the DMA job is complete, or
865 * the FIFO timeout interrupt occurred. This must be called
866 * with the port spinlock uap->port.lock held.
867 */
868static void pl011_dma_rx_chars(struct uart_amba_port *uap,
869 u32 pending, bool use_buf_b,
870 bool readfifo)
871{
872 struct tty_port *port = &uap->port.state->port;
873 struct pl011_dmabuf *dbuf = use_buf_b ?
874 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
875 int dma_count = 0;
876 u32 fifotaken = 0; /* only used for vdbg() */
877
878 struct pl011_dmarx_data *dmarx = &uap->dmarx;
879 int dmataken = 0;
880
881 if (uap->dmarx.poll_rate) {
882 /* The data can be taken by polling */
883 dmataken = dbuf->len - dmarx->last_residue;
884 /* Recalculate the pending size */
885 if (pending >= dmataken)
886 pending -= dmataken;
887 }
888
889 /* Pick the remain data from the DMA */
890 if (pending) {
891 /*
892 * First take all chars in the DMA pipe, then look in the FIFO.
893 * Note that tty_insert_flip_buf() tries to take as many chars
894 * as it can.
895 */
896 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, pending);
897
898 uap->port.icount.rx += dma_count;
899 if (dma_count < pending)
900 dev_warn(uap->port.dev,
901 "couldn't insert all characters (TTY is full?)\n");
902 }
903
904 /* Reset the last_residue for Rx DMA poll */
905 if (uap->dmarx.poll_rate)
906 dmarx->last_residue = dbuf->len;
907
908 /*
909 * Only continue with trying to read the FIFO if all DMA chars have
910 * been taken first.
911 */
912 if (dma_count == pending && readfifo) {
913 /* Clear any error flags */
914 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
915 UART011_FEIS, uap, REG_ICR);
916
917 /*
918 * If we read all the DMA'd characters, and we had an
919 * incomplete buffer, that could be due to an rx error, or
920 * maybe we just timed out. Read any pending chars and check
921 * the error status.
922 *
923 * Error conditions will only occur in the FIFO, these will
924 * trigger an immediate interrupt and stop the DMA job, so we
925 * will always find the error in the FIFO, never in the DMA
926 * buffer.
927 */
928 fifotaken = pl011_fifo_to_tty(uap);
929 }
930
931 dev_vdbg(uap->port.dev,
932 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
933 dma_count, fifotaken);
934 tty_flip_buffer_push(port);
935}
936
937static void pl011_dma_rx_irq(struct uart_amba_port *uap)
938{
939 struct pl011_dmarx_data *dmarx = &uap->dmarx;
940 struct dma_chan *rxchan = dmarx->chan;
941 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?
942 &dmarx->dbuf_b : &dmarx->dbuf_a;
943 size_t pending;
944 struct dma_tx_state state;
945 enum dma_status dmastat;
946
947 /*
948 * Pause the transfer so we can trust the current counter,
949 * do this before we pause the PL011 block, else we may
950 * overflow the FIFO.
951 */
952 if (dmaengine_pause(rxchan))
953 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
954 dmastat = rxchan->device->device_tx_status(rxchan,
955 dmarx->cookie, &state);
956 if (dmastat != DMA_PAUSED)
957 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
958
959 /* Disable RX DMA - incoming data will wait in the FIFO */
960 uap->dmacr &= ~UART011_RXDMAE;
961 pl011_write(uap->dmacr, uap, REG_DMACR);
962 uap->dmarx.running = false;
963
964 pending = dbuf->len - state.residue;
965 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
966 /* Then we terminate the transfer - we now know our residue */
967 dmaengine_terminate_all(rxchan);
968
969 /*
970 * This will take the chars we have so far and insert
971 * into the framework.
972 */
973 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
974
975 /* Switch buffer & re-trigger DMA job */
976 dmarx->use_buf_b = !dmarx->use_buf_b;
977 if (pl011_dma_rx_trigger_dma(uap)) {
978 dev_dbg(uap->port.dev,
979 "could not retrigger RX DMA job fall back to interrupt mode\n");
980 uap->im |= UART011_RXIM;
981 pl011_write(uap->im, uap, REG_IMSC);
982 }
983}
984
985static void pl011_dma_rx_callback(void *data)
986{
987 struct uart_amba_port *uap = data;
988 struct pl011_dmarx_data *dmarx = &uap->dmarx;
989 struct dma_chan *rxchan = dmarx->chan;
990 bool lastbuf = dmarx->use_buf_b;
991 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?
992 &dmarx->dbuf_b : &dmarx->dbuf_a;
993 size_t pending;
994 struct dma_tx_state state;
995 int ret;
996
997 /*
998 * This completion interrupt occurs typically when the
999 * RX buffer is totally stuffed but no timeout has yet
1000 * occurred. When that happens, we just want the RX
1001 * routine to flush out the secondary DMA buffer while
1002 * we immediately trigger the next DMA job.
1003 */
1004 uart_port_lock_irq(&uap->port);
1005 /*
1006 * Rx data can be taken by the UART interrupts during
1007 * the DMA irq handler. So we check the residue here.
1008 */
1009 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1010 pending = dbuf->len - state.residue;
1011 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1012 /* Then we terminate the transfer - we now know our residue */
1013 dmaengine_terminate_all(rxchan);
1014
1015 uap->dmarx.running = false;
1016 dmarx->use_buf_b = !lastbuf;
1017 ret = pl011_dma_rx_trigger_dma(uap);
1018
1019 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1020 uart_port_unlock_irq(&uap->port);
1021 /*
1022 * Do this check after we picked the DMA chars so we don't
1023 * get some IRQ immediately from RX.
1024 */
1025 if (ret) {
1026 dev_dbg(uap->port.dev,
1027 "could not retrigger RX DMA job fall back to interrupt mode\n");
1028 uap->im |= UART011_RXIM;
1029 pl011_write(uap->im, uap, REG_IMSC);
1030 }
1031}
1032
1033/*
1034 * Stop accepting received characters, when we're shutting down or
1035 * suspending this port.
1036 * Locking: called with port lock held and IRQs disabled.
1037 */
1038static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1039{
1040 if (!uap->using_rx_dma)
1041 return;
1042
1043 /* FIXME. Just disable the DMA enable */
1044 uap->dmacr &= ~UART011_RXDMAE;
1045 pl011_write(uap->dmacr, uap, REG_DMACR);
1046}
1047
1048/*
1049 * Timer handler for Rx DMA polling.
1050 * Every polling, It checks the residue in the dma buffer and transfer
1051 * data to the tty. Also, last_residue is updated for the next polling.
1052 */
1053static void pl011_dma_rx_poll(struct timer_list *t)
1054{
1055 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1056 struct tty_port *port = &uap->port.state->port;
1057 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1058 struct dma_chan *rxchan = uap->dmarx.chan;
1059 unsigned long flags;
1060 unsigned int dmataken = 0;
1061 unsigned int size = 0;
1062 struct pl011_dmabuf *dbuf;
1063 int dma_count;
1064 struct dma_tx_state state;
1065
1066 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
1067 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1068 if (likely(state.residue < dmarx->last_residue)) {
1069 dmataken = dbuf->len - dmarx->last_residue;
1070 size = dmarx->last_residue - state.residue;
1071 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken,
1072 size);
1073 if (dma_count == size)
1074 dmarx->last_residue = state.residue;
1075 dmarx->last_jiffies = jiffies;
1076 }
1077 tty_flip_buffer_push(port);
1078
1079 /*
1080 * If no data is received in poll_timeout, the driver will fall back
1081 * to interrupt mode. We will retrigger DMA at the first interrupt.
1082 */
1083 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1084 > uap->dmarx.poll_timeout) {
1085 uart_port_lock_irqsave(&uap->port, &flags);
1086 pl011_dma_rx_stop(uap);
1087 uap->im |= UART011_RXIM;
1088 pl011_write(uap->im, uap, REG_IMSC);
1089 uart_port_unlock_irqrestore(&uap->port, flags);
1090
1091 uap->dmarx.running = false;
1092 dmaengine_terminate_all(rxchan);
1093 del_timer(&uap->dmarx.timer);
1094 } else {
1095 mod_timer(&uap->dmarx.timer,
1096 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1097 }
1098}
1099
1100static void pl011_dma_startup(struct uart_amba_port *uap)
1101{
1102 int ret;
1103
1104 if (!uap->dma_probed)
1105 pl011_dma_probe(uap);
1106
1107 if (!uap->dmatx.chan)
1108 return;
1109
1110 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1111 if (!uap->dmatx.buf) {
1112 uap->port.fifosize = uap->fifosize;
1113 return;
1114 }
1115
1116 uap->dmatx.len = PL011_DMA_BUFFER_SIZE;
1117
1118 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1119 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1120 uap->using_tx_dma = true;
1121
1122 if (!uap->dmarx.chan)
1123 goto skip_rx;
1124
1125 /* Allocate and map DMA RX buffers */
1126 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1127 DMA_FROM_DEVICE);
1128 if (ret) {
1129 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1130 "RX buffer A", ret);
1131 goto skip_rx;
1132 }
1133
1134 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b,
1135 DMA_FROM_DEVICE);
1136 if (ret) {
1137 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1138 "RX buffer B", ret);
1139 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1140 DMA_FROM_DEVICE);
1141 goto skip_rx;
1142 }
1143
1144 uap->using_rx_dma = true;
1145
1146skip_rx:
1147 /* Turn on DMA error (RX/TX will be enabled on demand) */
1148 uap->dmacr |= UART011_DMAONERR;
1149 pl011_write(uap->dmacr, uap, REG_DMACR);
1150
1151 /*
1152 * ST Micro variants has some specific dma burst threshold
1153 * compensation. Set this to 16 bytes, so burst will only
1154 * be issued above/below 16 bytes.
1155 */
1156 if (uap->vendor->dma_threshold)
1157 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1158 uap, REG_ST_DMAWM);
1159
1160 if (uap->using_rx_dma) {
1161 if (pl011_dma_rx_trigger_dma(uap))
1162 dev_dbg(uap->port.dev,
1163 "could not trigger initial RX DMA job, fall back to interrupt mode\n");
1164 if (uap->dmarx.poll_rate) {
1165 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1166 mod_timer(&uap->dmarx.timer,
1167 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1168 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1169 uap->dmarx.last_jiffies = jiffies;
1170 }
1171 }
1172}
1173
1174static void pl011_dma_shutdown(struct uart_amba_port *uap)
1175{
1176 if (!(uap->using_tx_dma || uap->using_rx_dma))
1177 return;
1178
1179 /* Disable RX and TX DMA */
1180 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1181 cpu_relax();
1182
1183 uart_port_lock_irq(&uap->port);
1184 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1185 pl011_write(uap->dmacr, uap, REG_DMACR);
1186 uart_port_unlock_irq(&uap->port);
1187
1188 if (uap->using_tx_dma) {
1189 /* In theory, this should already be done by pl011_dma_flush_buffer */
1190 dmaengine_terminate_all(uap->dmatx.chan);
1191 if (uap->dmatx.queued) {
1192 dma_unmap_single(uap->dmatx.chan->device->dev,
1193 uap->dmatx.dma, uap->dmatx.len,
1194 DMA_TO_DEVICE);
1195 uap->dmatx.queued = false;
1196 }
1197
1198 kfree(uap->dmatx.buf);
1199 uap->using_tx_dma = false;
1200 }
1201
1202 if (uap->using_rx_dma) {
1203 dmaengine_terminate_all(uap->dmarx.chan);
1204 /* Clean up the RX DMA */
1205 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE);
1206 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE);
1207 if (uap->dmarx.poll_rate)
1208 del_timer_sync(&uap->dmarx.timer);
1209 uap->using_rx_dma = false;
1210 }
1211}
1212
1213static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1214{
1215 return uap->using_rx_dma;
1216}
1217
1218static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1219{
1220 return uap->using_rx_dma && uap->dmarx.running;
1221}
1222
1223#else
1224/* Blank functions if the DMA engine is not available */
1225static inline void pl011_dma_remove(struct uart_amba_port *uap)
1226{
1227}
1228
1229static inline void pl011_dma_startup(struct uart_amba_port *uap)
1230{
1231}
1232
1233static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1234{
1235}
1236
1237static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1238{
1239 return false;
1240}
1241
1242static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1243{
1244}
1245
1246static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1247{
1248 return false;
1249}
1250
1251static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1252{
1253}
1254
1255static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1256{
1257}
1258
1259static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1260{
1261 return -EIO;
1262}
1263
1264static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1265{
1266 return false;
1267}
1268
1269static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1270{
1271 return false;
1272}
1273
1274#define pl011_dma_flush_buffer NULL
1275#endif
1276
1277static void pl011_rs485_tx_stop(struct uart_amba_port *uap)
1278{
1279 /*
1280 * To be on the safe side only time out after twice as many iterations
1281 * as fifo size.
1282 */
1283 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2;
1284 struct uart_port *port = &uap->port;
1285 int i = 0;
1286 u32 cr;
1287
1288 /* Wait until hardware tx queue is empty */
1289 while (!pl011_tx_empty(port)) {
1290 if (i > MAX_TX_DRAIN_ITERS) {
1291 dev_warn(port->dev,
1292 "timeout while draining hardware tx queue\n");
1293 break;
1294 }
1295
1296 udelay(uap->rs485_tx_drain_interval);
1297 i++;
1298 }
1299
1300 if (port->rs485.delay_rts_after_send)
1301 mdelay(port->rs485.delay_rts_after_send);
1302
1303 cr = pl011_read(uap, REG_CR);
1304
1305 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1306 cr &= ~UART011_CR_RTS;
1307 else
1308 cr |= UART011_CR_RTS;
1309
1310 /* Disable the transmitter and reenable the transceiver */
1311 cr &= ~UART011_CR_TXE;
1312 cr |= UART011_CR_RXE;
1313 pl011_write(cr, uap, REG_CR);
1314
1315 uap->rs485_tx_started = false;
1316}
1317
1318static void pl011_stop_tx(struct uart_port *port)
1319{
1320 struct uart_amba_port *uap =
1321 container_of(port, struct uart_amba_port, port);
1322
1323 uap->im &= ~UART011_TXIM;
1324 pl011_write(uap->im, uap, REG_IMSC);
1325 pl011_dma_tx_stop(uap);
1326
1327 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1328 pl011_rs485_tx_stop(uap);
1329}
1330
1331static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1332
1333/* Start TX with programmed I/O only (no DMA) */
1334static void pl011_start_tx_pio(struct uart_amba_port *uap)
1335{
1336 if (pl011_tx_chars(uap, false)) {
1337 uap->im |= UART011_TXIM;
1338 pl011_write(uap->im, uap, REG_IMSC);
1339 }
1340}
1341
1342static void pl011_rs485_tx_start(struct uart_amba_port *uap)
1343{
1344 struct uart_port *port = &uap->port;
1345 u32 cr;
1346
1347 /* Enable transmitter */
1348 cr = pl011_read(uap, REG_CR);
1349 cr |= UART011_CR_TXE;
1350
1351 /* Disable receiver if half-duplex */
1352 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1353 cr &= ~UART011_CR_RXE;
1354
1355 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
1356 cr &= ~UART011_CR_RTS;
1357 else
1358 cr |= UART011_CR_RTS;
1359
1360 pl011_write(cr, uap, REG_CR);
1361
1362 if (port->rs485.delay_rts_before_send)
1363 mdelay(port->rs485.delay_rts_before_send);
1364
1365 uap->rs485_tx_started = true;
1366}
1367
1368static void pl011_start_tx(struct uart_port *port)
1369{
1370 struct uart_amba_port *uap =
1371 container_of(port, struct uart_amba_port, port);
1372
1373 if ((uap->port.rs485.flags & SER_RS485_ENABLED) &&
1374 !uap->rs485_tx_started)
1375 pl011_rs485_tx_start(uap);
1376
1377 if (!pl011_dma_tx_start(uap))
1378 pl011_start_tx_pio(uap);
1379}
1380
1381static void pl011_stop_rx(struct uart_port *port)
1382{
1383 struct uart_amba_port *uap =
1384 container_of(port, struct uart_amba_port, port);
1385
1386 uap->im &= ~(UART011_RXIM | UART011_RTIM | UART011_FEIM |
1387 UART011_PEIM | UART011_BEIM | UART011_OEIM);
1388 pl011_write(uap->im, uap, REG_IMSC);
1389
1390 pl011_dma_rx_stop(uap);
1391}
1392
1393static void pl011_throttle_rx(struct uart_port *port)
1394{
1395 unsigned long flags;
1396
1397 uart_port_lock_irqsave(port, &flags);
1398 pl011_stop_rx(port);
1399 uart_port_unlock_irqrestore(port, flags);
1400}
1401
1402static void pl011_enable_ms(struct uart_port *port)
1403{
1404 struct uart_amba_port *uap =
1405 container_of(port, struct uart_amba_port, port);
1406
1407 uap->im |= UART011_RIMIM | UART011_CTSMIM | UART011_DCDMIM | UART011_DSRMIM;
1408 pl011_write(uap->im, uap, REG_IMSC);
1409}
1410
1411static void pl011_rx_chars(struct uart_amba_port *uap)
1412__releases(&uap->port.lock)
1413__acquires(&uap->port.lock)
1414{
1415 pl011_fifo_to_tty(uap);
1416
1417 uart_port_unlock(&uap->port);
1418 tty_flip_buffer_push(&uap->port.state->port);
1419 /*
1420 * If we were temporarily out of DMA mode for a while,
1421 * attempt to switch back to DMA mode again.
1422 */
1423 if (pl011_dma_rx_available(uap)) {
1424 if (pl011_dma_rx_trigger_dma(uap)) {
1425 dev_dbg(uap->port.dev,
1426 "could not trigger RX DMA job fall back to interrupt mode again\n");
1427 uap->im |= UART011_RXIM;
1428 pl011_write(uap->im, uap, REG_IMSC);
1429 } else {
1430#ifdef CONFIG_DMA_ENGINE
1431 /* Start Rx DMA poll */
1432 if (uap->dmarx.poll_rate) {
1433 uap->dmarx.last_jiffies = jiffies;
1434 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1435 mod_timer(&uap->dmarx.timer,
1436 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1437 }
1438#endif
1439 }
1440 }
1441 uart_port_lock(&uap->port);
1442}
1443
1444static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1445 bool from_irq)
1446{
1447 if (unlikely(!from_irq) &&
1448 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1449 return false; /* unable to transmit character */
1450
1451 pl011_write(c, uap, REG_DR);
1452 uap->port.icount.tx++;
1453
1454 return true;
1455}
1456
1457/* Returns true if tx interrupts have to be (kept) enabled */
1458static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1459{
1460 struct circ_buf *xmit = &uap->port.state->xmit;
1461 int count = uap->fifosize >> 1;
1462
1463 if (uap->port.x_char) {
1464 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1465 return true;
1466 uap->port.x_char = 0;
1467 --count;
1468 }
1469 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1470 pl011_stop_tx(&uap->port);
1471 return false;
1472 }
1473
1474 /* If we are using DMA mode, try to send some characters. */
1475 if (pl011_dma_tx_irq(uap))
1476 return true;
1477
1478 do {
1479 if (likely(from_irq) && count-- == 0)
1480 break;
1481
1482 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1483 break;
1484
1485 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1486 } while (!uart_circ_empty(xmit));
1487
1488 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1489 uart_write_wakeup(&uap->port);
1490
1491 if (uart_circ_empty(xmit)) {
1492 pl011_stop_tx(&uap->port);
1493 return false;
1494 }
1495 return true;
1496}
1497
1498static void pl011_modem_status(struct uart_amba_port *uap)
1499{
1500 unsigned int status, delta;
1501
1502 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1503
1504 delta = status ^ uap->old_status;
1505 uap->old_status = status;
1506
1507 if (!delta)
1508 return;
1509
1510 if (delta & UART01x_FR_DCD)
1511 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1512
1513 if (delta & uap->vendor->fr_dsr)
1514 uap->port.icount.dsr++;
1515
1516 if (delta & uap->vendor->fr_cts)
1517 uart_handle_cts_change(&uap->port,
1518 status & uap->vendor->fr_cts);
1519
1520 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1521}
1522
1523static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1524{
1525 if (!uap->vendor->cts_event_workaround)
1526 return;
1527
1528 /* workaround to make sure that all bits are unlocked.. */
1529 pl011_write(0x00, uap, REG_ICR);
1530
1531 /*
1532 * WA: introduce 26ns(1 uart clk) delay before W1C;
1533 * single apb access will incur 2 pclk(133.12Mhz) delay,
1534 * so add 2 dummy reads
1535 */
1536 pl011_read(uap, REG_ICR);
1537 pl011_read(uap, REG_ICR);
1538}
1539
1540static irqreturn_t pl011_int(int irq, void *dev_id)
1541{
1542 struct uart_amba_port *uap = dev_id;
1543 unsigned long flags;
1544 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1545 int handled = 0;
1546
1547 uart_port_lock_irqsave(&uap->port, &flags);
1548 status = pl011_read(uap, REG_RIS) & uap->im;
1549 if (status) {
1550 do {
1551 check_apply_cts_event_workaround(uap);
1552
1553 pl011_write(status & ~(UART011_TXIS | UART011_RTIS | UART011_RXIS),
1554 uap, REG_ICR);
1555
1556 if (status & (UART011_RTIS | UART011_RXIS)) {
1557 if (pl011_dma_rx_running(uap))
1558 pl011_dma_rx_irq(uap);
1559 else
1560 pl011_rx_chars(uap);
1561 }
1562 if (status & (UART011_DSRMIS | UART011_DCDMIS |
1563 UART011_CTSMIS | UART011_RIMIS))
1564 pl011_modem_status(uap);
1565 if (status & UART011_TXIS)
1566 pl011_tx_chars(uap, true);
1567
1568 if (pass_counter-- == 0)
1569 break;
1570
1571 status = pl011_read(uap, REG_RIS) & uap->im;
1572 } while (status != 0);
1573 handled = 1;
1574 }
1575
1576 uart_port_unlock_irqrestore(&uap->port, flags);
1577
1578 return IRQ_RETVAL(handled);
1579}
1580
1581static unsigned int pl011_tx_empty(struct uart_port *port)
1582{
1583 struct uart_amba_port *uap =
1584 container_of(port, struct uart_amba_port, port);
1585
1586 /* Allow feature register bits to be inverted to work around errata */
1587 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1588
1589 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1590 0 : TIOCSER_TEMT;
1591}
1592
1593static void pl011_maybe_set_bit(bool cond, unsigned int *ptr, unsigned int mask)
1594{
1595 if (cond)
1596 *ptr |= mask;
1597}
1598
1599static unsigned int pl011_get_mctrl(struct uart_port *port)
1600{
1601 struct uart_amba_port *uap =
1602 container_of(port, struct uart_amba_port, port);
1603 unsigned int result = 0;
1604 unsigned int status = pl011_read(uap, REG_FR);
1605
1606 pl011_maybe_set_bit(status & UART01x_FR_DCD, &result, TIOCM_CAR);
1607 pl011_maybe_set_bit(status & uap->vendor->fr_dsr, &result, TIOCM_DSR);
1608 pl011_maybe_set_bit(status & uap->vendor->fr_cts, &result, TIOCM_CTS);
1609 pl011_maybe_set_bit(status & uap->vendor->fr_ri, &result, TIOCM_RNG);
1610
1611 return result;
1612}
1613
1614static void pl011_assign_bit(bool cond, unsigned int *ptr, unsigned int mask)
1615{
1616 if (cond)
1617 *ptr |= mask;
1618 else
1619 *ptr &= ~mask;
1620}
1621
1622static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1623{
1624 struct uart_amba_port *uap =
1625 container_of(port, struct uart_amba_port, port);
1626 unsigned int cr;
1627
1628 cr = pl011_read(uap, REG_CR);
1629
1630 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTS);
1631 pl011_assign_bit(mctrl & TIOCM_DTR, &cr, UART011_CR_DTR);
1632 pl011_assign_bit(mctrl & TIOCM_OUT1, &cr, UART011_CR_OUT1);
1633 pl011_assign_bit(mctrl & TIOCM_OUT2, &cr, UART011_CR_OUT2);
1634 pl011_assign_bit(mctrl & TIOCM_LOOP, &cr, UART011_CR_LBE);
1635
1636 if (port->status & UPSTAT_AUTORTS) {
1637 /* We need to disable auto-RTS if we want to turn RTS off */
1638 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTSEN);
1639 }
1640
1641 pl011_write(cr, uap, REG_CR);
1642}
1643
1644static void pl011_break_ctl(struct uart_port *port, int break_state)
1645{
1646 struct uart_amba_port *uap =
1647 container_of(port, struct uart_amba_port, port);
1648 unsigned long flags;
1649 unsigned int lcr_h;
1650
1651 uart_port_lock_irqsave(&uap->port, &flags);
1652 lcr_h = pl011_read(uap, REG_LCRH_TX);
1653 if (break_state == -1)
1654 lcr_h |= UART01x_LCRH_BRK;
1655 else
1656 lcr_h &= ~UART01x_LCRH_BRK;
1657 pl011_write(lcr_h, uap, REG_LCRH_TX);
1658 uart_port_unlock_irqrestore(&uap->port, flags);
1659}
1660
1661#ifdef CONFIG_CONSOLE_POLL
1662
1663static void pl011_quiesce_irqs(struct uart_port *port)
1664{
1665 struct uart_amba_port *uap =
1666 container_of(port, struct uart_amba_port, port);
1667
1668 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1669 /*
1670 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1671 * we simply mask it. start_tx() will unmask it.
1672 *
1673 * Note we can race with start_tx(), and if the race happens, the
1674 * polling user might get another interrupt just after we clear it.
1675 * But it should be OK and can happen even w/o the race, e.g.
1676 * controller immediately got some new data and raised the IRQ.
1677 *
1678 * And whoever uses polling routines assumes that it manages the device
1679 * (including tx queue), so we're also fine with start_tx()'s caller
1680 * side.
1681 */
1682 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1683 REG_IMSC);
1684}
1685
1686static int pl011_get_poll_char(struct uart_port *port)
1687{
1688 struct uart_amba_port *uap =
1689 container_of(port, struct uart_amba_port, port);
1690 unsigned int status;
1691
1692 /*
1693 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1694 * debugger.
1695 */
1696 pl011_quiesce_irqs(port);
1697
1698 status = pl011_read(uap, REG_FR);
1699 if (status & UART01x_FR_RXFE)
1700 return NO_POLL_CHAR;
1701
1702 return pl011_read(uap, REG_DR);
1703}
1704
1705static void pl011_put_poll_char(struct uart_port *port, unsigned char ch)
1706{
1707 struct uart_amba_port *uap =
1708 container_of(port, struct uart_amba_port, port);
1709
1710 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1711 cpu_relax();
1712
1713 pl011_write(ch, uap, REG_DR);
1714}
1715
1716#endif /* CONFIG_CONSOLE_POLL */
1717
1718static int pl011_hwinit(struct uart_port *port)
1719{
1720 struct uart_amba_port *uap =
1721 container_of(port, struct uart_amba_port, port);
1722 int retval;
1723
1724 /* Optionaly enable pins to be muxed in and configured */
1725 pinctrl_pm_select_default_state(port->dev);
1726
1727 /*
1728 * Try to enable the clock producer.
1729 */
1730 retval = clk_prepare_enable(uap->clk);
1731 if (retval)
1732 return retval;
1733
1734 uap->port.uartclk = clk_get_rate(uap->clk);
1735
1736 /* Clear pending error and receive interrupts */
1737 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1738 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1739 uap, REG_ICR);
1740
1741 /*
1742 * Save interrupts enable mask, and enable RX interrupts in case if
1743 * the interrupt is used for NMI entry.
1744 */
1745 uap->im = pl011_read(uap, REG_IMSC);
1746 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1747
1748 if (dev_get_platdata(uap->port.dev)) {
1749 struct amba_pl011_data *plat;
1750
1751 plat = dev_get_platdata(uap->port.dev);
1752 if (plat->init)
1753 plat->init();
1754 }
1755 return 0;
1756}
1757
1758static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1759{
1760 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1761 pl011_reg_to_offset(uap, REG_LCRH_TX);
1762}
1763
1764static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1765{
1766 pl011_write(lcr_h, uap, REG_LCRH_RX);
1767 if (pl011_split_lcrh(uap)) {
1768 int i;
1769 /*
1770 * Wait 10 PCLKs before writing LCRH_TX register,
1771 * to get this delay write read only register 10 times
1772 */
1773 for (i = 0; i < 10; ++i)
1774 pl011_write(0xff, uap, REG_MIS);
1775 pl011_write(lcr_h, uap, REG_LCRH_TX);
1776 }
1777}
1778
1779static int pl011_allocate_irq(struct uart_amba_port *uap)
1780{
1781 pl011_write(uap->im, uap, REG_IMSC);
1782
1783 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1784}
1785
1786/*
1787 * Enable interrupts, only timeouts when using DMA
1788 * if initial RX DMA job failed, start in interrupt mode
1789 * as well.
1790 */
1791static void pl011_enable_interrupts(struct uart_amba_port *uap)
1792{
1793 unsigned long flags;
1794 unsigned int i;
1795
1796 uart_port_lock_irqsave(&uap->port, &flags);
1797
1798 /* Clear out any spuriously appearing RX interrupts */
1799 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1800
1801 /*
1802 * RXIS is asserted only when the RX FIFO transitions from below
1803 * to above the trigger threshold. If the RX FIFO is already
1804 * full to the threshold this can't happen and RXIS will now be
1805 * stuck off. Drain the RX FIFO explicitly to fix this:
1806 */
1807 for (i = 0; i < uap->fifosize * 2; ++i) {
1808 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1809 break;
1810
1811 pl011_read(uap, REG_DR);
1812 }
1813
1814 uap->im = UART011_RTIM;
1815 if (!pl011_dma_rx_running(uap))
1816 uap->im |= UART011_RXIM;
1817 pl011_write(uap->im, uap, REG_IMSC);
1818 uart_port_unlock_irqrestore(&uap->port, flags);
1819}
1820
1821static void pl011_unthrottle_rx(struct uart_port *port)
1822{
1823 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
1824 unsigned long flags;
1825
1826 uart_port_lock_irqsave(&uap->port, &flags);
1827
1828 uap->im = UART011_RTIM;
1829 if (!pl011_dma_rx_running(uap))
1830 uap->im |= UART011_RXIM;
1831
1832 pl011_write(uap->im, uap, REG_IMSC);
1833
1834 uart_port_unlock_irqrestore(&uap->port, flags);
1835}
1836
1837static int pl011_startup(struct uart_port *port)
1838{
1839 struct uart_amba_port *uap =
1840 container_of(port, struct uart_amba_port, port);
1841 unsigned int cr;
1842 int retval;
1843
1844 retval = pl011_hwinit(port);
1845 if (retval)
1846 goto clk_dis;
1847
1848 retval = pl011_allocate_irq(uap);
1849 if (retval)
1850 goto clk_dis;
1851
1852 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1853
1854 uart_port_lock_irq(&uap->port);
1855
1856 cr = pl011_read(uap, REG_CR);
1857 cr &= UART011_CR_RTS | UART011_CR_DTR;
1858 cr |= UART01x_CR_UARTEN | UART011_CR_RXE;
1859
1860 if (!(port->rs485.flags & SER_RS485_ENABLED))
1861 cr |= UART011_CR_TXE;
1862
1863 pl011_write(cr, uap, REG_CR);
1864
1865 uart_port_unlock_irq(&uap->port);
1866
1867 /*
1868 * initialise the old status of the modem signals
1869 */
1870 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1871
1872 /* Startup DMA */
1873 pl011_dma_startup(uap);
1874
1875 pl011_enable_interrupts(uap);
1876
1877 return 0;
1878
1879 clk_dis:
1880 clk_disable_unprepare(uap->clk);
1881 return retval;
1882}
1883
1884static int sbsa_uart_startup(struct uart_port *port)
1885{
1886 struct uart_amba_port *uap =
1887 container_of(port, struct uart_amba_port, port);
1888 int retval;
1889
1890 retval = pl011_hwinit(port);
1891 if (retval)
1892 return retval;
1893
1894 retval = pl011_allocate_irq(uap);
1895 if (retval)
1896 return retval;
1897
1898 /* The SBSA UART does not support any modem status lines. */
1899 uap->old_status = 0;
1900
1901 pl011_enable_interrupts(uap);
1902
1903 return 0;
1904}
1905
1906static void pl011_shutdown_channel(struct uart_amba_port *uap, unsigned int lcrh)
1907{
1908 unsigned long val;
1909
1910 val = pl011_read(uap, lcrh);
1911 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1912 pl011_write(val, uap, lcrh);
1913}
1914
1915/*
1916 * disable the port. It should not disable RTS and DTR.
1917 * Also RTS and DTR state should be preserved to restore
1918 * it during startup().
1919 */
1920static void pl011_disable_uart(struct uart_amba_port *uap)
1921{
1922 unsigned int cr;
1923
1924 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1925 uart_port_lock_irq(&uap->port);
1926 cr = pl011_read(uap, REG_CR);
1927 cr &= UART011_CR_RTS | UART011_CR_DTR;
1928 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1929 pl011_write(cr, uap, REG_CR);
1930 uart_port_unlock_irq(&uap->port);
1931
1932 /*
1933 * disable break condition and fifos
1934 */
1935 pl011_shutdown_channel(uap, REG_LCRH_RX);
1936 if (pl011_split_lcrh(uap))
1937 pl011_shutdown_channel(uap, REG_LCRH_TX);
1938}
1939
1940static void pl011_disable_interrupts(struct uart_amba_port *uap)
1941{
1942 uart_port_lock_irq(&uap->port);
1943
1944 /* mask all interrupts and clear all pending ones */
1945 uap->im = 0;
1946 pl011_write(uap->im, uap, REG_IMSC);
1947 pl011_write(0xffff, uap, REG_ICR);
1948
1949 uart_port_unlock_irq(&uap->port);
1950}
1951
1952static void pl011_shutdown(struct uart_port *port)
1953{
1954 struct uart_amba_port *uap =
1955 container_of(port, struct uart_amba_port, port);
1956
1957 pl011_disable_interrupts(uap);
1958
1959 pl011_dma_shutdown(uap);
1960
1961 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1962 pl011_rs485_tx_stop(uap);
1963
1964 free_irq(uap->port.irq, uap);
1965
1966 pl011_disable_uart(uap);
1967
1968 /*
1969 * Shut down the clock producer
1970 */
1971 clk_disable_unprepare(uap->clk);
1972 /* Optionally let pins go into sleep states */
1973 pinctrl_pm_select_sleep_state(port->dev);
1974
1975 if (dev_get_platdata(uap->port.dev)) {
1976 struct amba_pl011_data *plat;
1977
1978 plat = dev_get_platdata(uap->port.dev);
1979 if (plat->exit)
1980 plat->exit();
1981 }
1982
1983 if (uap->port.ops->flush_buffer)
1984 uap->port.ops->flush_buffer(port);
1985}
1986
1987static void sbsa_uart_shutdown(struct uart_port *port)
1988{
1989 struct uart_amba_port *uap =
1990 container_of(port, struct uart_amba_port, port);
1991
1992 pl011_disable_interrupts(uap);
1993
1994 free_irq(uap->port.irq, uap);
1995
1996 if (uap->port.ops->flush_buffer)
1997 uap->port.ops->flush_buffer(port);
1998}
1999
2000static void
2001pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
2002{
2003 port->read_status_mask = UART011_DR_OE | 255;
2004 if (termios->c_iflag & INPCK)
2005 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
2006 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2007 port->read_status_mask |= UART011_DR_BE;
2008
2009 /*
2010 * Characters to ignore
2011 */
2012 port->ignore_status_mask = 0;
2013 if (termios->c_iflag & IGNPAR)
2014 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
2015 if (termios->c_iflag & IGNBRK) {
2016 port->ignore_status_mask |= UART011_DR_BE;
2017 /*
2018 * If we're ignoring parity and break indicators,
2019 * ignore overruns too (for real raw support).
2020 */
2021 if (termios->c_iflag & IGNPAR)
2022 port->ignore_status_mask |= UART011_DR_OE;
2023 }
2024
2025 /*
2026 * Ignore all characters if CREAD is not set.
2027 */
2028 if ((termios->c_cflag & CREAD) == 0)
2029 port->ignore_status_mask |= UART_DUMMY_DR_RX;
2030}
2031
2032static void
2033pl011_set_termios(struct uart_port *port, struct ktermios *termios,
2034 const struct ktermios *old)
2035{
2036 struct uart_amba_port *uap =
2037 container_of(port, struct uart_amba_port, port);
2038 unsigned int lcr_h, old_cr;
2039 unsigned long flags;
2040 unsigned int baud, quot, clkdiv;
2041 unsigned int bits;
2042
2043 if (uap->vendor->oversampling)
2044 clkdiv = 8;
2045 else
2046 clkdiv = 16;
2047
2048 /*
2049 * Ask the core to calculate the divisor for us.
2050 */
2051 baud = uart_get_baud_rate(port, termios, old, 0,
2052 port->uartclk / clkdiv);
2053#ifdef CONFIG_DMA_ENGINE
2054 /*
2055 * Adjust RX DMA polling rate with baud rate if not specified.
2056 */
2057 if (uap->dmarx.auto_poll_rate)
2058 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
2059#endif
2060
2061 if (baud > port->uartclk / 16)
2062 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
2063 else
2064 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
2065
2066 switch (termios->c_cflag & CSIZE) {
2067 case CS5:
2068 lcr_h = UART01x_LCRH_WLEN_5;
2069 break;
2070 case CS6:
2071 lcr_h = UART01x_LCRH_WLEN_6;
2072 break;
2073 case CS7:
2074 lcr_h = UART01x_LCRH_WLEN_7;
2075 break;
2076 default: // CS8
2077 lcr_h = UART01x_LCRH_WLEN_8;
2078 break;
2079 }
2080 if (termios->c_cflag & CSTOPB)
2081 lcr_h |= UART01x_LCRH_STP2;
2082 if (termios->c_cflag & PARENB) {
2083 lcr_h |= UART01x_LCRH_PEN;
2084 if (!(termios->c_cflag & PARODD))
2085 lcr_h |= UART01x_LCRH_EPS;
2086 if (termios->c_cflag & CMSPAR)
2087 lcr_h |= UART011_LCRH_SPS;
2088 }
2089 if (uap->fifosize > 1)
2090 lcr_h |= UART01x_LCRH_FEN;
2091
2092 bits = tty_get_frame_size(termios->c_cflag);
2093
2094 uart_port_lock_irqsave(port, &flags);
2095
2096 /*
2097 * Update the per-port timeout.
2098 */
2099 uart_update_timeout(port, termios->c_cflag, baud);
2100
2101 /*
2102 * Calculate the approximated time it takes to transmit one character
2103 * with the given baud rate. We use this as the poll interval when we
2104 * wait for the tx queue to empty.
2105 */
2106 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud);
2107
2108 pl011_setup_status_masks(port, termios);
2109
2110 if (UART_ENABLE_MS(port, termios->c_cflag))
2111 pl011_enable_ms(port);
2112
2113 if (port->rs485.flags & SER_RS485_ENABLED)
2114 termios->c_cflag &= ~CRTSCTS;
2115
2116 old_cr = pl011_read(uap, REG_CR);
2117
2118 if (termios->c_cflag & CRTSCTS) {
2119 if (old_cr & UART011_CR_RTS)
2120 old_cr |= UART011_CR_RTSEN;
2121
2122 old_cr |= UART011_CR_CTSEN;
2123 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2124 } else {
2125 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2126 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2127 }
2128
2129 if (uap->vendor->oversampling) {
2130 if (baud > port->uartclk / 16)
2131 old_cr |= ST_UART011_CR_OVSFACT;
2132 else
2133 old_cr &= ~ST_UART011_CR_OVSFACT;
2134 }
2135
2136 /*
2137 * Workaround for the ST Micro oversampling variants to
2138 * increase the bitrate slightly, by lowering the divisor,
2139 * to avoid delayed sampling of start bit at high speeds,
2140 * else we see data corruption.
2141 */
2142 if (uap->vendor->oversampling) {
2143 if (baud >= 3000000 && baud < 3250000 && quot > 1)
2144 quot -= 1;
2145 else if (baud > 3250000 && quot > 2)
2146 quot -= 2;
2147 }
2148 /* Set baud rate */
2149 pl011_write(quot & 0x3f, uap, REG_FBRD);
2150 pl011_write(quot >> 6, uap, REG_IBRD);
2151
2152 /*
2153 * ----------v----------v----------v----------v-----
2154 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2155 * REG_FBRD & REG_IBRD.
2156 * ----------^----------^----------^----------^-----
2157 */
2158 pl011_write_lcr_h(uap, lcr_h);
2159
2160 /*
2161 * Receive was disabled by pl011_disable_uart during shutdown.
2162 * Need to reenable receive if you need to use a tty_driver
2163 * returns from tty_find_polling_driver() after a port shutdown.
2164 */
2165 old_cr |= UART011_CR_RXE;
2166 pl011_write(old_cr, uap, REG_CR);
2167
2168 uart_port_unlock_irqrestore(port, flags);
2169}
2170
2171static void
2172sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2173 const struct ktermios *old)
2174{
2175 struct uart_amba_port *uap =
2176 container_of(port, struct uart_amba_port, port);
2177 unsigned long flags;
2178
2179 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2180
2181 /* The SBSA UART only supports 8n1 without hardware flow control. */
2182 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2183 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2184 termios->c_cflag |= CS8 | CLOCAL;
2185
2186 uart_port_lock_irqsave(port, &flags);
2187 uart_update_timeout(port, CS8, uap->fixed_baud);
2188 pl011_setup_status_masks(port, termios);
2189 uart_port_unlock_irqrestore(port, flags);
2190}
2191
2192static const char *pl011_type(struct uart_port *port)
2193{
2194 struct uart_amba_port *uap =
2195 container_of(port, struct uart_amba_port, port);
2196 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2197}
2198
2199/*
2200 * Configure/autoconfigure the port.
2201 */
2202static void pl011_config_port(struct uart_port *port, int flags)
2203{
2204 if (flags & UART_CONFIG_TYPE)
2205 port->type = PORT_AMBA;
2206}
2207
2208/*
2209 * verify the new serial_struct (for TIOCSSERIAL).
2210 */
2211static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2212{
2213 int ret = 0;
2214
2215 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2216 ret = -EINVAL;
2217 if (ser->irq < 0 || ser->irq >= nr_irqs)
2218 ret = -EINVAL;
2219 if (ser->baud_base < 9600)
2220 ret = -EINVAL;
2221 if (port->mapbase != (unsigned long)ser->iomem_base)
2222 ret = -EINVAL;
2223 return ret;
2224}
2225
2226static int pl011_rs485_config(struct uart_port *port, struct ktermios *termios,
2227 struct serial_rs485 *rs485)
2228{
2229 struct uart_amba_port *uap =
2230 container_of(port, struct uart_amba_port, port);
2231
2232 if (port->rs485.flags & SER_RS485_ENABLED)
2233 pl011_rs485_tx_stop(uap);
2234
2235 /* Make sure auto RTS is disabled */
2236 if (rs485->flags & SER_RS485_ENABLED) {
2237 u32 cr = pl011_read(uap, REG_CR);
2238
2239 cr &= ~UART011_CR_RTSEN;
2240 pl011_write(cr, uap, REG_CR);
2241 port->status &= ~UPSTAT_AUTORTS;
2242 }
2243
2244 return 0;
2245}
2246
2247static const struct uart_ops amba_pl011_pops = {
2248 .tx_empty = pl011_tx_empty,
2249 .set_mctrl = pl011_set_mctrl,
2250 .get_mctrl = pl011_get_mctrl,
2251 .stop_tx = pl011_stop_tx,
2252 .start_tx = pl011_start_tx,
2253 .stop_rx = pl011_stop_rx,
2254 .throttle = pl011_throttle_rx,
2255 .unthrottle = pl011_unthrottle_rx,
2256 .enable_ms = pl011_enable_ms,
2257 .break_ctl = pl011_break_ctl,
2258 .startup = pl011_startup,
2259 .shutdown = pl011_shutdown,
2260 .flush_buffer = pl011_dma_flush_buffer,
2261 .set_termios = pl011_set_termios,
2262 .type = pl011_type,
2263 .config_port = pl011_config_port,
2264 .verify_port = pl011_verify_port,
2265#ifdef CONFIG_CONSOLE_POLL
2266 .poll_init = pl011_hwinit,
2267 .poll_get_char = pl011_get_poll_char,
2268 .poll_put_char = pl011_put_poll_char,
2269#endif
2270};
2271
2272static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2273{
2274}
2275
2276static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2277{
2278 return 0;
2279}
2280
2281static const struct uart_ops sbsa_uart_pops = {
2282 .tx_empty = pl011_tx_empty,
2283 .set_mctrl = sbsa_uart_set_mctrl,
2284 .get_mctrl = sbsa_uart_get_mctrl,
2285 .stop_tx = pl011_stop_tx,
2286 .start_tx = pl011_start_tx,
2287 .stop_rx = pl011_stop_rx,
2288 .startup = sbsa_uart_startup,
2289 .shutdown = sbsa_uart_shutdown,
2290 .set_termios = sbsa_uart_set_termios,
2291 .type = pl011_type,
2292 .config_port = pl011_config_port,
2293 .verify_port = pl011_verify_port,
2294#ifdef CONFIG_CONSOLE_POLL
2295 .poll_init = pl011_hwinit,
2296 .poll_get_char = pl011_get_poll_char,
2297 .poll_put_char = pl011_put_poll_char,
2298#endif
2299};
2300
2301static struct uart_amba_port *amba_ports[UART_NR];
2302
2303#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2304
2305static void pl011_console_putchar(struct uart_port *port, unsigned char ch)
2306{
2307 struct uart_amba_port *uap =
2308 container_of(port, struct uart_amba_port, port);
2309
2310 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2311 cpu_relax();
2312 pl011_write(ch, uap, REG_DR);
2313}
2314
2315static void
2316pl011_console_write(struct console *co, const char *s, unsigned int count)
2317{
2318 struct uart_amba_port *uap = amba_ports[co->index];
2319 unsigned int old_cr = 0, new_cr;
2320 unsigned long flags;
2321 int locked = 1;
2322
2323 clk_enable(uap->clk);
2324
2325 local_irq_save(flags);
2326 if (uap->port.sysrq)
2327 locked = 0;
2328 else if (oops_in_progress)
2329 locked = uart_port_trylock(&uap->port);
2330 else
2331 uart_port_lock(&uap->port);
2332
2333 /*
2334 * First save the CR then disable the interrupts
2335 */
2336 if (!uap->vendor->always_enabled) {
2337 old_cr = pl011_read(uap, REG_CR);
2338 new_cr = old_cr & ~UART011_CR_CTSEN;
2339 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2340 pl011_write(new_cr, uap, REG_CR);
2341 }
2342
2343 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2344
2345 /*
2346 * Finally, wait for transmitter to become empty and restore the
2347 * TCR. Allow feature register bits to be inverted to work around
2348 * errata.
2349 */
2350 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2351 & uap->vendor->fr_busy)
2352 cpu_relax();
2353 if (!uap->vendor->always_enabled)
2354 pl011_write(old_cr, uap, REG_CR);
2355
2356 if (locked)
2357 uart_port_unlock(&uap->port);
2358 local_irq_restore(flags);
2359
2360 clk_disable(uap->clk);
2361}
2362
2363static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2364 int *parity, int *bits)
2365{
2366 unsigned int lcr_h, ibrd, fbrd;
2367
2368 if (!(pl011_read(uap, REG_CR) & UART01x_CR_UARTEN))
2369 return;
2370
2371 lcr_h = pl011_read(uap, REG_LCRH_TX);
2372
2373 *parity = 'n';
2374 if (lcr_h & UART01x_LCRH_PEN) {
2375 if (lcr_h & UART01x_LCRH_EPS)
2376 *parity = 'e';
2377 else
2378 *parity = 'o';
2379 }
2380
2381 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2382 *bits = 7;
2383 else
2384 *bits = 8;
2385
2386 ibrd = pl011_read(uap, REG_IBRD);
2387 fbrd = pl011_read(uap, REG_FBRD);
2388
2389 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2390
2391 if (uap->vendor->oversampling &&
2392 (pl011_read(uap, REG_CR) & ST_UART011_CR_OVSFACT))
2393 *baud *= 2;
2394}
2395
2396static int pl011_console_setup(struct console *co, char *options)
2397{
2398 struct uart_amba_port *uap;
2399 int baud = 38400;
2400 int bits = 8;
2401 int parity = 'n';
2402 int flow = 'n';
2403 int ret;
2404
2405 /*
2406 * Check whether an invalid uart number has been specified, and
2407 * if so, search for the first available port that does have
2408 * console support.
2409 */
2410 if (co->index >= UART_NR)
2411 co->index = 0;
2412 uap = amba_ports[co->index];
2413 if (!uap)
2414 return -ENODEV;
2415
2416 /* Allow pins to be muxed in and configured */
2417 pinctrl_pm_select_default_state(uap->port.dev);
2418
2419 ret = clk_prepare(uap->clk);
2420 if (ret)
2421 return ret;
2422
2423 if (dev_get_platdata(uap->port.dev)) {
2424 struct amba_pl011_data *plat;
2425
2426 plat = dev_get_platdata(uap->port.dev);
2427 if (plat->init)
2428 plat->init();
2429 }
2430
2431 uap->port.uartclk = clk_get_rate(uap->clk);
2432
2433 if (uap->vendor->fixed_options) {
2434 baud = uap->fixed_baud;
2435 } else {
2436 if (options)
2437 uart_parse_options(options,
2438 &baud, &parity, &bits, &flow);
2439 else
2440 pl011_console_get_options(uap, &baud, &parity, &bits);
2441 }
2442
2443 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2444}
2445
2446/**
2447 * pl011_console_match - non-standard console matching
2448 * @co: registering console
2449 * @name: name from console command line
2450 * @idx: index from console command line
2451 * @options: ptr to option string from console command line
2452 *
2453 * Only attempts to match console command lines of the form:
2454 * console=pl011,mmio|mmio32,<addr>[,<options>]
2455 * console=pl011,0x<addr>[,<options>]
2456 * This form is used to register an initial earlycon boot console and
2457 * replace it with the amba_console at pl011 driver init.
2458 *
2459 * Performs console setup for a match (as required by interface)
2460 * If no <options> are specified, then assume the h/w is already setup.
2461 *
2462 * Returns 0 if console matches; otherwise non-zero to use default matching
2463 */
2464static int pl011_console_match(struct console *co, char *name, int idx,
2465 char *options)
2466{
2467 unsigned char iotype;
2468 resource_size_t addr;
2469 int i;
2470
2471 /*
2472 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2473 * have a distinct console name, so make sure we check for that.
2474 * The actual implementation of the erratum occurs in the probe
2475 * function.
2476 */
2477 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2478 return -ENODEV;
2479
2480 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2481 return -ENODEV;
2482
2483 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2484 return -ENODEV;
2485
2486 /* try to match the port specified on the command line */
2487 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2488 struct uart_port *port;
2489
2490 if (!amba_ports[i])
2491 continue;
2492
2493 port = &amba_ports[i]->port;
2494
2495 if (port->mapbase != addr)
2496 continue;
2497
2498 co->index = i;
2499 port->cons = co;
2500 return pl011_console_setup(co, options);
2501 }
2502
2503 return -ENODEV;
2504}
2505
2506static struct uart_driver amba_reg;
2507static struct console amba_console = {
2508 .name = "ttyAMA",
2509 .write = pl011_console_write,
2510 .device = uart_console_device,
2511 .setup = pl011_console_setup,
2512 .match = pl011_console_match,
2513 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2514 .index = -1,
2515 .data = &amba_reg,
2516};
2517
2518#define AMBA_CONSOLE (&amba_console)
2519
2520static void qdf2400_e44_putc(struct uart_port *port, unsigned char c)
2521{
2522 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2523 cpu_relax();
2524 writel(c, port->membase + UART01x_DR);
2525 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2526 cpu_relax();
2527}
2528
2529static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned int n)
2530{
2531 struct earlycon_device *dev = con->data;
2532
2533 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2534}
2535
2536static void pl011_putc(struct uart_port *port, unsigned char c)
2537{
2538 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2539 cpu_relax();
2540 if (port->iotype == UPIO_MEM32)
2541 writel(c, port->membase + UART01x_DR);
2542 else
2543 writeb(c, port->membase + UART01x_DR);
2544 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2545 cpu_relax();
2546}
2547
2548static void pl011_early_write(struct console *con, const char *s, unsigned int n)
2549{
2550 struct earlycon_device *dev = con->data;
2551
2552 uart_console_write(&dev->port, s, n, pl011_putc);
2553}
2554
2555#ifdef CONFIG_CONSOLE_POLL
2556static int pl011_getc(struct uart_port *port)
2557{
2558 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)
2559 return NO_POLL_CHAR;
2560
2561 if (port->iotype == UPIO_MEM32)
2562 return readl(port->membase + UART01x_DR);
2563 else
2564 return readb(port->membase + UART01x_DR);
2565}
2566
2567static int pl011_early_read(struct console *con, char *s, unsigned int n)
2568{
2569 struct earlycon_device *dev = con->data;
2570 int ch, num_read = 0;
2571
2572 while (num_read < n) {
2573 ch = pl011_getc(&dev->port);
2574 if (ch == NO_POLL_CHAR)
2575 break;
2576
2577 s[num_read++] = ch;
2578 }
2579
2580 return num_read;
2581}
2582#else
2583#define pl011_early_read NULL
2584#endif
2585
2586/*
2587 * On non-ACPI systems, earlycon is enabled by specifying
2588 * "earlycon=pl011,<address>" on the kernel command line.
2589 *
2590 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2591 * by specifying only "earlycon" on the command line. Because it requires
2592 * SPCR, the console starts after ACPI is parsed, which is later than a
2593 * traditional early console.
2594 *
2595 * To get the traditional early console that starts before ACPI is parsed,
2596 * specify the full "earlycon=pl011,<address>" option.
2597 */
2598static int __init pl011_early_console_setup(struct earlycon_device *device,
2599 const char *opt)
2600{
2601 if (!device->port.membase)
2602 return -ENODEV;
2603
2604 device->con->write = pl011_early_write;
2605 device->con->read = pl011_early_read;
2606
2607 return 0;
2608}
2609
2610OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2611
2612OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2613
2614/*
2615 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2616 * Erratum 44, traditional earlycon can be enabled by specifying
2617 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2618 *
2619 * Alternatively, you can just specify "earlycon", and the early console
2620 * will be enabled with the information from the SPCR table. In this
2621 * case, the SPCR code will detect the need for the E44 work-around,
2622 * and set the console name to "qdf2400_e44".
2623 */
2624static int __init
2625qdf2400_e44_early_console_setup(struct earlycon_device *device,
2626 const char *opt)
2627{
2628 if (!device->port.membase)
2629 return -ENODEV;
2630
2631 device->con->write = qdf2400_e44_early_write;
2632 return 0;
2633}
2634
2635EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2636
2637#else
2638#define AMBA_CONSOLE NULL
2639#endif
2640
2641static struct uart_driver amba_reg = {
2642 .owner = THIS_MODULE,
2643 .driver_name = "ttyAMA",
2644 .dev_name = "ttyAMA",
2645 .major = SERIAL_AMBA_MAJOR,
2646 .minor = SERIAL_AMBA_MINOR,
2647 .nr = UART_NR,
2648 .cons = AMBA_CONSOLE,
2649};
2650
2651static int pl011_probe_dt_alias(int index, struct device *dev)
2652{
2653 struct device_node *np;
2654 static bool seen_dev_with_alias;
2655 static bool seen_dev_without_alias;
2656 int ret = index;
2657
2658 if (!IS_ENABLED(CONFIG_OF))
2659 return ret;
2660
2661 np = dev->of_node;
2662 if (!np)
2663 return ret;
2664
2665 ret = of_alias_get_id(np, "serial");
2666 if (ret < 0) {
2667 seen_dev_without_alias = true;
2668 ret = index;
2669 } else {
2670 seen_dev_with_alias = true;
2671 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret]) {
2672 dev_warn(dev, "requested serial port %d not available.\n", ret);
2673 ret = index;
2674 }
2675 }
2676
2677 if (seen_dev_with_alias && seen_dev_without_alias)
2678 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2679
2680 return ret;
2681}
2682
2683/* unregisters the driver also if no more ports are left */
2684static void pl011_unregister_port(struct uart_amba_port *uap)
2685{
2686 int i;
2687 bool busy = false;
2688
2689 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2690 if (amba_ports[i] == uap)
2691 amba_ports[i] = NULL;
2692 else if (amba_ports[i])
2693 busy = true;
2694 }
2695 pl011_dma_remove(uap);
2696 if (!busy)
2697 uart_unregister_driver(&amba_reg);
2698}
2699
2700static int pl011_find_free_port(void)
2701{
2702 int i;
2703
2704 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2705 if (!amba_ports[i])
2706 return i;
2707
2708 return -EBUSY;
2709}
2710
2711static int pl011_get_rs485_mode(struct uart_amba_port *uap)
2712{
2713 struct uart_port *port = &uap->port;
2714 int ret;
2715
2716 ret = uart_get_rs485_mode(port);
2717 if (ret)
2718 return ret;
2719
2720 return 0;
2721}
2722
2723static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2724 struct resource *mmiobase, int index)
2725{
2726 void __iomem *base;
2727 int ret;
2728
2729 base = devm_ioremap_resource(dev, mmiobase);
2730 if (IS_ERR(base))
2731 return PTR_ERR(base);
2732
2733 index = pl011_probe_dt_alias(index, dev);
2734
2735 uap->port.dev = dev;
2736 uap->port.mapbase = mmiobase->start;
2737 uap->port.membase = base;
2738 uap->port.fifosize = uap->fifosize;
2739 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2740 uap->port.flags = UPF_BOOT_AUTOCONF;
2741 uap->port.line = index;
2742
2743 ret = pl011_get_rs485_mode(uap);
2744 if (ret)
2745 return ret;
2746
2747 amba_ports[index] = uap;
2748
2749 return 0;
2750}
2751
2752static int pl011_register_port(struct uart_amba_port *uap)
2753{
2754 int ret, i;
2755
2756 /* Ensure interrupts from this UART are masked and cleared */
2757 pl011_write(0, uap, REG_IMSC);
2758 pl011_write(0xffff, uap, REG_ICR);
2759
2760 if (!amba_reg.state) {
2761 ret = uart_register_driver(&amba_reg);
2762 if (ret < 0) {
2763 dev_err(uap->port.dev,
2764 "Failed to register AMBA-PL011 driver\n");
2765 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2766 if (amba_ports[i] == uap)
2767 amba_ports[i] = NULL;
2768 return ret;
2769 }
2770 }
2771
2772 ret = uart_add_one_port(&amba_reg, &uap->port);
2773 if (ret)
2774 pl011_unregister_port(uap);
2775
2776 return ret;
2777}
2778
2779static const struct serial_rs485 pl011_rs485_supported = {
2780 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2781 SER_RS485_RX_DURING_TX,
2782 .delay_rts_before_send = 1,
2783 .delay_rts_after_send = 1,
2784};
2785
2786static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2787{
2788 struct uart_amba_port *uap;
2789 struct vendor_data *vendor = id->data;
2790 int portnr, ret;
2791 u32 val;
2792
2793 portnr = pl011_find_free_port();
2794 if (portnr < 0)
2795 return portnr;
2796
2797 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2798 GFP_KERNEL);
2799 if (!uap)
2800 return -ENOMEM;
2801
2802 uap->clk = devm_clk_get(&dev->dev, NULL);
2803 if (IS_ERR(uap->clk))
2804 return PTR_ERR(uap->clk);
2805
2806 uap->reg_offset = vendor->reg_offset;
2807 uap->vendor = vendor;
2808 uap->fifosize = vendor->get_fifosize(dev);
2809 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2810 uap->port.irq = dev->irq[0];
2811 uap->port.ops = &amba_pl011_pops;
2812 uap->port.rs485_config = pl011_rs485_config;
2813 uap->port.rs485_supported = pl011_rs485_supported;
2814 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2815
2816 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) {
2817 switch (val) {
2818 case 1:
2819 uap->port.iotype = UPIO_MEM;
2820 break;
2821 case 4:
2822 uap->port.iotype = UPIO_MEM32;
2823 break;
2824 default:
2825 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n",
2826 val);
2827 return -EINVAL;
2828 }
2829 }
2830
2831 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2832 if (ret)
2833 return ret;
2834
2835 amba_set_drvdata(dev, uap);
2836
2837 return pl011_register_port(uap);
2838}
2839
2840static void pl011_remove(struct amba_device *dev)
2841{
2842 struct uart_amba_port *uap = amba_get_drvdata(dev);
2843
2844 uart_remove_one_port(&amba_reg, &uap->port);
2845 pl011_unregister_port(uap);
2846}
2847
2848#ifdef CONFIG_PM_SLEEP
2849static int pl011_suspend(struct device *dev)
2850{
2851 struct uart_amba_port *uap = dev_get_drvdata(dev);
2852
2853 if (!uap)
2854 return -EINVAL;
2855
2856 return uart_suspend_port(&amba_reg, &uap->port);
2857}
2858
2859static int pl011_resume(struct device *dev)
2860{
2861 struct uart_amba_port *uap = dev_get_drvdata(dev);
2862
2863 if (!uap)
2864 return -EINVAL;
2865
2866 return uart_resume_port(&amba_reg, &uap->port);
2867}
2868#endif
2869
2870static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2871
2872#ifdef CONFIG_ACPI_SPCR_TABLE
2873static void qpdf2400_erratum44_workaround(struct device *dev,
2874 struct uart_amba_port *uap)
2875{
2876 if (!qdf2400_e44_present)
2877 return;
2878
2879 dev_info(dev, "working around QDF2400 SoC erratum 44\n");
2880 uap->vendor = &vendor_qdt_qdf2400_e44;
2881}
2882#else
2883static void qpdf2400_erratum44_workaround(struct device *dev,
2884 struct uart_amba_port *uap)
2885{ /* empty */ }
2886#endif
2887
2888static int sbsa_uart_probe(struct platform_device *pdev)
2889{
2890 struct uart_amba_port *uap;
2891 struct resource *r;
2892 int portnr, ret;
2893 int baudrate;
2894
2895 /*
2896 * Check the mandatory baud rate parameter in the DT node early
2897 * so that we can easily exit with the error.
2898 */
2899 if (pdev->dev.of_node) {
2900 struct device_node *np = pdev->dev.of_node;
2901
2902 ret = of_property_read_u32(np, "current-speed", &baudrate);
2903 if (ret)
2904 return ret;
2905 } else {
2906 baudrate = 115200;
2907 }
2908
2909 portnr = pl011_find_free_port();
2910 if (portnr < 0)
2911 return portnr;
2912
2913 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2914 GFP_KERNEL);
2915 if (!uap)
2916 return -ENOMEM;
2917
2918 ret = platform_get_irq(pdev, 0);
2919 if (ret < 0)
2920 return ret;
2921 uap->port.irq = ret;
2922
2923 uap->vendor = &vendor_sbsa;
2924 qpdf2400_erratum44_workaround(&pdev->dev, uap);
2925
2926 uap->reg_offset = uap->vendor->reg_offset;
2927 uap->fifosize = 32;
2928 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2929 uap->port.ops = &sbsa_uart_pops;
2930 uap->fixed_baud = baudrate;
2931
2932 snprintf(uap->type, sizeof(uap->type), "SBSA");
2933
2934 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2935
2936 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2937 if (ret)
2938 return ret;
2939
2940 platform_set_drvdata(pdev, uap);
2941
2942 return pl011_register_port(uap);
2943}
2944
2945static void sbsa_uart_remove(struct platform_device *pdev)
2946{
2947 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2948
2949 uart_remove_one_port(&amba_reg, &uap->port);
2950 pl011_unregister_port(uap);
2951}
2952
2953static const struct of_device_id sbsa_uart_of_match[] = {
2954 { .compatible = "arm,sbsa-uart", },
2955 {},
2956};
2957MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2958
2959static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = {
2960 { "ARMH0011", 0 },
2961 { "ARMHB000", 0 },
2962 {},
2963};
2964MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2965
2966static struct platform_driver arm_sbsa_uart_platform_driver = {
2967 .probe = sbsa_uart_probe,
2968 .remove_new = sbsa_uart_remove,
2969 .driver = {
2970 .name = "sbsa-uart",
2971 .pm = &pl011_dev_pm_ops,
2972 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2973 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2974 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2975 },
2976};
2977
2978static const struct amba_id pl011_ids[] = {
2979 {
2980 .id = 0x00041011,
2981 .mask = 0x000fffff,
2982 .data = &vendor_arm,
2983 },
2984 {
2985 .id = 0x00380802,
2986 .mask = 0x00ffffff,
2987 .data = &vendor_st,
2988 },
2989 { 0, 0 },
2990};
2991
2992MODULE_DEVICE_TABLE(amba, pl011_ids);
2993
2994static struct amba_driver pl011_driver = {
2995 .drv = {
2996 .name = "uart-pl011",
2997 .pm = &pl011_dev_pm_ops,
2998 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2999 },
3000 .id_table = pl011_ids,
3001 .probe = pl011_probe,
3002 .remove = pl011_remove,
3003};
3004
3005static int __init pl011_init(void)
3006{
3007 pr_info("Serial: AMBA PL011 UART driver\n");
3008
3009 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
3010 pr_warn("could not register SBSA UART platform driver\n");
3011 return amba_driver_register(&pl011_driver);
3012}
3013
3014static void __exit pl011_exit(void)
3015{
3016 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
3017 amba_driver_unregister(&pl011_driver);
3018}
3019
3020/*
3021 * While this can be a module, if builtin it's most likely the console
3022 * So let's leave module_exit but move module_init to an earlier place
3023 */
3024arch_initcall(pl011_init);
3025module_exit(pl011_exit);
3026
3027MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
3028MODULE_DESCRIPTION("ARM AMBA serial port driver");
3029MODULE_LICENSE("GPL");
1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32
33#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34#define SUPPORT_SYSRQ
35#endif
36
37#include <linux/module.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/sysrq.h>
42#include <linux/device.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
47#include <linux/amba/bus.h>
48#include <linux/amba/serial.h>
49#include <linux/clk.h>
50#include <linux/slab.h>
51#include <linux/dmaengine.h>
52#include <linux/dma-mapping.h>
53#include <linux/scatterlist.h>
54#include <linux/delay.h>
55#include <linux/types.h>
56#include <linux/of.h>
57#include <linux/of_device.h>
58#include <linux/pinctrl/consumer.h>
59#include <linux/sizes.h>
60#include <linux/io.h>
61#include <linux/acpi.h>
62
63#include "amba-pl011.h"
64
65#define UART_NR 14
66
67#define SERIAL_AMBA_MAJOR 204
68#define SERIAL_AMBA_MINOR 64
69#define SERIAL_AMBA_NR UART_NR
70
71#define AMBA_ISR_PASS_LIMIT 256
72
73#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
74#define UART_DUMMY_DR_RX (1 << 16)
75
76static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
77 [REG_DR] = UART01x_DR,
78 [REG_FR] = UART01x_FR,
79 [REG_LCRH_RX] = UART011_LCRH,
80 [REG_LCRH_TX] = UART011_LCRH,
81 [REG_IBRD] = UART011_IBRD,
82 [REG_FBRD] = UART011_FBRD,
83 [REG_CR] = UART011_CR,
84 [REG_IFLS] = UART011_IFLS,
85 [REG_IMSC] = UART011_IMSC,
86 [REG_RIS] = UART011_RIS,
87 [REG_MIS] = UART011_MIS,
88 [REG_ICR] = UART011_ICR,
89 [REG_DMACR] = UART011_DMACR,
90};
91
92/* There is by now at least one vendor with differing details, so handle it */
93struct vendor_data {
94 const u16 *reg_offset;
95 unsigned int ifls;
96 unsigned int fr_busy;
97 unsigned int fr_dsr;
98 unsigned int fr_cts;
99 unsigned int fr_ri;
100 bool access_32b;
101 bool oversampling;
102 bool dma_threshold;
103 bool cts_event_workaround;
104 bool always_enabled;
105 bool fixed_options;
106
107 unsigned int (*get_fifosize)(struct amba_device *dev);
108};
109
110static unsigned int get_fifosize_arm(struct amba_device *dev)
111{
112 return amba_rev(dev) < 3 ? 16 : 32;
113}
114
115static struct vendor_data vendor_arm = {
116 .reg_offset = pl011_std_offsets,
117 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
118 .fr_busy = UART01x_FR_BUSY,
119 .fr_dsr = UART01x_FR_DSR,
120 .fr_cts = UART01x_FR_CTS,
121 .fr_ri = UART011_FR_RI,
122 .oversampling = false,
123 .dma_threshold = false,
124 .cts_event_workaround = false,
125 .always_enabled = false,
126 .fixed_options = false,
127 .get_fifosize = get_fifosize_arm,
128};
129
130static struct vendor_data vendor_sbsa = {
131 .reg_offset = pl011_std_offsets,
132 .fr_busy = UART01x_FR_BUSY,
133 .fr_dsr = UART01x_FR_DSR,
134 .fr_cts = UART01x_FR_CTS,
135 .fr_ri = UART011_FR_RI,
136 .access_32b = true,
137 .oversampling = false,
138 .dma_threshold = false,
139 .cts_event_workaround = false,
140 .always_enabled = true,
141 .fixed_options = true,
142};
143
144static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
145 [REG_DR] = UART01x_DR,
146 [REG_ST_DMAWM] = ST_UART011_DMAWM,
147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
148 [REG_FR] = UART01x_FR,
149 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
150 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
151 [REG_IBRD] = UART011_IBRD,
152 [REG_FBRD] = UART011_FBRD,
153 [REG_CR] = UART011_CR,
154 [REG_IFLS] = UART011_IFLS,
155 [REG_IMSC] = UART011_IMSC,
156 [REG_RIS] = UART011_RIS,
157 [REG_MIS] = UART011_MIS,
158 [REG_ICR] = UART011_ICR,
159 [REG_DMACR] = UART011_DMACR,
160 [REG_ST_XFCR] = ST_UART011_XFCR,
161 [REG_ST_XON1] = ST_UART011_XON1,
162 [REG_ST_XON2] = ST_UART011_XON2,
163 [REG_ST_XOFF1] = ST_UART011_XOFF1,
164 [REG_ST_XOFF2] = ST_UART011_XOFF2,
165 [REG_ST_ITCR] = ST_UART011_ITCR,
166 [REG_ST_ITIP] = ST_UART011_ITIP,
167 [REG_ST_ABCR] = ST_UART011_ABCR,
168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
169};
170
171static unsigned int get_fifosize_st(struct amba_device *dev)
172{
173 return 64;
174}
175
176static struct vendor_data vendor_st = {
177 .reg_offset = pl011_st_offsets,
178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
179 .fr_busy = UART01x_FR_BUSY,
180 .fr_dsr = UART01x_FR_DSR,
181 .fr_cts = UART01x_FR_CTS,
182 .fr_ri = UART011_FR_RI,
183 .oversampling = true,
184 .dma_threshold = true,
185 .cts_event_workaround = true,
186 .always_enabled = false,
187 .fixed_options = false,
188 .get_fifosize = get_fifosize_st,
189};
190
191static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
192 [REG_DR] = ZX_UART011_DR,
193 [REG_FR] = ZX_UART011_FR,
194 [REG_LCRH_RX] = ZX_UART011_LCRH,
195 [REG_LCRH_TX] = ZX_UART011_LCRH,
196 [REG_IBRD] = ZX_UART011_IBRD,
197 [REG_FBRD] = ZX_UART011_FBRD,
198 [REG_CR] = ZX_UART011_CR,
199 [REG_IFLS] = ZX_UART011_IFLS,
200 [REG_IMSC] = ZX_UART011_IMSC,
201 [REG_RIS] = ZX_UART011_RIS,
202 [REG_MIS] = ZX_UART011_MIS,
203 [REG_ICR] = ZX_UART011_ICR,
204 [REG_DMACR] = ZX_UART011_DMACR,
205};
206
207static unsigned int get_fifosize_zte(struct amba_device *dev)
208{
209 return 16;
210}
211
212static struct vendor_data vendor_zte = {
213 .reg_offset = pl011_zte_offsets,
214 .access_32b = true,
215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
216 .fr_busy = ZX_UART01x_FR_BUSY,
217 .fr_dsr = ZX_UART01x_FR_DSR,
218 .fr_cts = ZX_UART01x_FR_CTS,
219 .fr_ri = ZX_UART011_FR_RI,
220 .get_fifosize = get_fifosize_zte,
221};
222
223/* Deals with DMA transactions */
224
225struct pl011_sgbuf {
226 struct scatterlist sg;
227 char *buf;
228};
229
230struct pl011_dmarx_data {
231 struct dma_chan *chan;
232 struct completion complete;
233 bool use_buf_b;
234 struct pl011_sgbuf sgbuf_a;
235 struct pl011_sgbuf sgbuf_b;
236 dma_cookie_t cookie;
237 bool running;
238 struct timer_list timer;
239 unsigned int last_residue;
240 unsigned long last_jiffies;
241 bool auto_poll_rate;
242 unsigned int poll_rate;
243 unsigned int poll_timeout;
244};
245
246struct pl011_dmatx_data {
247 struct dma_chan *chan;
248 struct scatterlist sg;
249 char *buf;
250 bool queued;
251};
252
253/*
254 * We wrap our port structure around the generic uart_port.
255 */
256struct uart_amba_port {
257 struct uart_port port;
258 const u16 *reg_offset;
259 struct clk *clk;
260 const struct vendor_data *vendor;
261 unsigned int dmacr; /* dma control reg */
262 unsigned int im; /* interrupt mask */
263 unsigned int old_status;
264 unsigned int fifosize; /* vendor-specific */
265 unsigned int old_cr; /* state during shutdown */
266 bool autorts;
267 unsigned int fixed_baud; /* vendor-set fixed baud rate */
268 char type[12];
269#ifdef CONFIG_DMA_ENGINE
270 /* DMA stuff */
271 bool using_tx_dma;
272 bool using_rx_dma;
273 struct pl011_dmarx_data dmarx;
274 struct pl011_dmatx_data dmatx;
275 bool dma_probed;
276#endif
277};
278
279static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
280 unsigned int reg)
281{
282 return uap->reg_offset[reg];
283}
284
285static unsigned int pl011_read(const struct uart_amba_port *uap,
286 unsigned int reg)
287{
288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
289
290 return (uap->port.iotype == UPIO_MEM32) ?
291 readl_relaxed(addr) : readw_relaxed(addr);
292}
293
294static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
295 unsigned int reg)
296{
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
298
299 if (uap->port.iotype == UPIO_MEM32)
300 writel_relaxed(val, addr);
301 else
302 writew_relaxed(val, addr);
303}
304
305/*
306 * Reads up to 256 characters from the FIFO or until it's empty and
307 * inserts them into the TTY layer. Returns the number of characters
308 * read from the FIFO.
309 */
310static int pl011_fifo_to_tty(struct uart_amba_port *uap)
311{
312 u16 status;
313 unsigned int ch, flag, max_count = 256;
314 int fifotaken = 0;
315
316 while (max_count--) {
317 status = pl011_read(uap, REG_FR);
318 if (status & UART01x_FR_RXFE)
319 break;
320
321 /* Take chars from the FIFO and update status */
322 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
323 flag = TTY_NORMAL;
324 uap->port.icount.rx++;
325 fifotaken++;
326
327 if (unlikely(ch & UART_DR_ERROR)) {
328 if (ch & UART011_DR_BE) {
329 ch &= ~(UART011_DR_FE | UART011_DR_PE);
330 uap->port.icount.brk++;
331 if (uart_handle_break(&uap->port))
332 continue;
333 } else if (ch & UART011_DR_PE)
334 uap->port.icount.parity++;
335 else if (ch & UART011_DR_FE)
336 uap->port.icount.frame++;
337 if (ch & UART011_DR_OE)
338 uap->port.icount.overrun++;
339
340 ch &= uap->port.read_status_mask;
341
342 if (ch & UART011_DR_BE)
343 flag = TTY_BREAK;
344 else if (ch & UART011_DR_PE)
345 flag = TTY_PARITY;
346 else if (ch & UART011_DR_FE)
347 flag = TTY_FRAME;
348 }
349
350 if (uart_handle_sysrq_char(&uap->port, ch & 255))
351 continue;
352
353 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
354 }
355
356 return fifotaken;
357}
358
359
360/*
361 * All the DMA operation mode stuff goes inside this ifdef.
362 * This assumes that you have a generic DMA device interface,
363 * no custom DMA interfaces are supported.
364 */
365#ifdef CONFIG_DMA_ENGINE
366
367#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
368
369static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
370 enum dma_data_direction dir)
371{
372 dma_addr_t dma_addr;
373
374 sg->buf = dma_alloc_coherent(chan->device->dev,
375 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
376 if (!sg->buf)
377 return -ENOMEM;
378
379 sg_init_table(&sg->sg, 1);
380 sg_set_page(&sg->sg, phys_to_page(dma_addr),
381 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
382 sg_dma_address(&sg->sg) = dma_addr;
383 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
384
385 return 0;
386}
387
388static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
389 enum dma_data_direction dir)
390{
391 if (sg->buf) {
392 dma_free_coherent(chan->device->dev,
393 PL011_DMA_BUFFER_SIZE, sg->buf,
394 sg_dma_address(&sg->sg));
395 }
396}
397
398static void pl011_dma_probe(struct uart_amba_port *uap)
399{
400 /* DMA is the sole user of the platform data right now */
401 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
402 struct device *dev = uap->port.dev;
403 struct dma_slave_config tx_conf = {
404 .dst_addr = uap->port.mapbase +
405 pl011_reg_to_offset(uap, REG_DR),
406 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
407 .direction = DMA_MEM_TO_DEV,
408 .dst_maxburst = uap->fifosize >> 1,
409 .device_fc = false,
410 };
411 struct dma_chan *chan;
412 dma_cap_mask_t mask;
413
414 uap->dma_probed = true;
415 chan = dma_request_slave_channel_reason(dev, "tx");
416 if (IS_ERR(chan)) {
417 if (PTR_ERR(chan) == -EPROBE_DEFER) {
418 uap->dma_probed = false;
419 return;
420 }
421
422 /* We need platform data */
423 if (!plat || !plat->dma_filter) {
424 dev_info(uap->port.dev, "no DMA platform data\n");
425 return;
426 }
427
428 /* Try to acquire a generic DMA engine slave TX channel */
429 dma_cap_zero(mask);
430 dma_cap_set(DMA_SLAVE, mask);
431
432 chan = dma_request_channel(mask, plat->dma_filter,
433 plat->dma_tx_param);
434 if (!chan) {
435 dev_err(uap->port.dev, "no TX DMA channel!\n");
436 return;
437 }
438 }
439
440 dmaengine_slave_config(chan, &tx_conf);
441 uap->dmatx.chan = chan;
442
443 dev_info(uap->port.dev, "DMA channel TX %s\n",
444 dma_chan_name(uap->dmatx.chan));
445
446 /* Optionally make use of an RX channel as well */
447 chan = dma_request_slave_channel(dev, "rx");
448
449 if (!chan && plat && plat->dma_rx_param) {
450 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
451
452 if (!chan) {
453 dev_err(uap->port.dev, "no RX DMA channel!\n");
454 return;
455 }
456 }
457
458 if (chan) {
459 struct dma_slave_config rx_conf = {
460 .src_addr = uap->port.mapbase +
461 pl011_reg_to_offset(uap, REG_DR),
462 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
463 .direction = DMA_DEV_TO_MEM,
464 .src_maxburst = uap->fifosize >> 2,
465 .device_fc = false,
466 };
467 struct dma_slave_caps caps;
468
469 /*
470 * Some DMA controllers provide information on their capabilities.
471 * If the controller does, check for suitable residue processing
472 * otherwise assime all is well.
473 */
474 if (0 == dma_get_slave_caps(chan, &caps)) {
475 if (caps.residue_granularity ==
476 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
477 dma_release_channel(chan);
478 dev_info(uap->port.dev,
479 "RX DMA disabled - no residue processing\n");
480 return;
481 }
482 }
483 dmaengine_slave_config(chan, &rx_conf);
484 uap->dmarx.chan = chan;
485
486 uap->dmarx.auto_poll_rate = false;
487 if (plat && plat->dma_rx_poll_enable) {
488 /* Set poll rate if specified. */
489 if (plat->dma_rx_poll_rate) {
490 uap->dmarx.auto_poll_rate = false;
491 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
492 } else {
493 /*
494 * 100 ms defaults to poll rate if not
495 * specified. This will be adjusted with
496 * the baud rate at set_termios.
497 */
498 uap->dmarx.auto_poll_rate = true;
499 uap->dmarx.poll_rate = 100;
500 }
501 /* 3 secs defaults poll_timeout if not specified. */
502 if (plat->dma_rx_poll_timeout)
503 uap->dmarx.poll_timeout =
504 plat->dma_rx_poll_timeout;
505 else
506 uap->dmarx.poll_timeout = 3000;
507 } else if (!plat && dev->of_node) {
508 uap->dmarx.auto_poll_rate = of_property_read_bool(
509 dev->of_node, "auto-poll");
510 if (uap->dmarx.auto_poll_rate) {
511 u32 x;
512
513 if (0 == of_property_read_u32(dev->of_node,
514 "poll-rate-ms", &x))
515 uap->dmarx.poll_rate = x;
516 else
517 uap->dmarx.poll_rate = 100;
518 if (0 == of_property_read_u32(dev->of_node,
519 "poll-timeout-ms", &x))
520 uap->dmarx.poll_timeout = x;
521 else
522 uap->dmarx.poll_timeout = 3000;
523 }
524 }
525 dev_info(uap->port.dev, "DMA channel RX %s\n",
526 dma_chan_name(uap->dmarx.chan));
527 }
528}
529
530static void pl011_dma_remove(struct uart_amba_port *uap)
531{
532 if (uap->dmatx.chan)
533 dma_release_channel(uap->dmatx.chan);
534 if (uap->dmarx.chan)
535 dma_release_channel(uap->dmarx.chan);
536}
537
538/* Forward declare these for the refill routine */
539static int pl011_dma_tx_refill(struct uart_amba_port *uap);
540static void pl011_start_tx_pio(struct uart_amba_port *uap);
541
542/*
543 * The current DMA TX buffer has been sent.
544 * Try to queue up another DMA buffer.
545 */
546static void pl011_dma_tx_callback(void *data)
547{
548 struct uart_amba_port *uap = data;
549 struct pl011_dmatx_data *dmatx = &uap->dmatx;
550 unsigned long flags;
551 u16 dmacr;
552
553 spin_lock_irqsave(&uap->port.lock, flags);
554 if (uap->dmatx.queued)
555 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
556 DMA_TO_DEVICE);
557
558 dmacr = uap->dmacr;
559 uap->dmacr = dmacr & ~UART011_TXDMAE;
560 pl011_write(uap->dmacr, uap, REG_DMACR);
561
562 /*
563 * If TX DMA was disabled, it means that we've stopped the DMA for
564 * some reason (eg, XOFF received, or we want to send an X-char.)
565 *
566 * Note: we need to be careful here of a potential race between DMA
567 * and the rest of the driver - if the driver disables TX DMA while
568 * a TX buffer completing, we must update the tx queued status to
569 * get further refills (hence we check dmacr).
570 */
571 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
572 uart_circ_empty(&uap->port.state->xmit)) {
573 uap->dmatx.queued = false;
574 spin_unlock_irqrestore(&uap->port.lock, flags);
575 return;
576 }
577
578 if (pl011_dma_tx_refill(uap) <= 0)
579 /*
580 * We didn't queue a DMA buffer for some reason, but we
581 * have data pending to be sent. Re-enable the TX IRQ.
582 */
583 pl011_start_tx_pio(uap);
584
585 spin_unlock_irqrestore(&uap->port.lock, flags);
586}
587
588/*
589 * Try to refill the TX DMA buffer.
590 * Locking: called with port lock held and IRQs disabled.
591 * Returns:
592 * 1 if we queued up a TX DMA buffer.
593 * 0 if we didn't want to handle this by DMA
594 * <0 on error
595 */
596static int pl011_dma_tx_refill(struct uart_amba_port *uap)
597{
598 struct pl011_dmatx_data *dmatx = &uap->dmatx;
599 struct dma_chan *chan = dmatx->chan;
600 struct dma_device *dma_dev = chan->device;
601 struct dma_async_tx_descriptor *desc;
602 struct circ_buf *xmit = &uap->port.state->xmit;
603 unsigned int count;
604
605 /*
606 * Try to avoid the overhead involved in using DMA if the
607 * transaction fits in the first half of the FIFO, by using
608 * the standard interrupt handling. This ensures that we
609 * issue a uart_write_wakeup() at the appropriate time.
610 */
611 count = uart_circ_chars_pending(xmit);
612 if (count < (uap->fifosize >> 1)) {
613 uap->dmatx.queued = false;
614 return 0;
615 }
616
617 /*
618 * Bodge: don't send the last character by DMA, as this
619 * will prevent XON from notifying us to restart DMA.
620 */
621 count -= 1;
622
623 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
624 if (count > PL011_DMA_BUFFER_SIZE)
625 count = PL011_DMA_BUFFER_SIZE;
626
627 if (xmit->tail < xmit->head)
628 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
629 else {
630 size_t first = UART_XMIT_SIZE - xmit->tail;
631 size_t second;
632
633 if (first > count)
634 first = count;
635 second = count - first;
636
637 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
638 if (second)
639 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
640 }
641
642 dmatx->sg.length = count;
643
644 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
645 uap->dmatx.queued = false;
646 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
647 return -EBUSY;
648 }
649
650 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
651 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
652 if (!desc) {
653 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
654 uap->dmatx.queued = false;
655 /*
656 * If DMA cannot be used right now, we complete this
657 * transaction via IRQ and let the TTY layer retry.
658 */
659 dev_dbg(uap->port.dev, "TX DMA busy\n");
660 return -EBUSY;
661 }
662
663 /* Some data to go along to the callback */
664 desc->callback = pl011_dma_tx_callback;
665 desc->callback_param = uap;
666
667 /* All errors should happen at prepare time */
668 dmaengine_submit(desc);
669
670 /* Fire the DMA transaction */
671 dma_dev->device_issue_pending(chan);
672
673 uap->dmacr |= UART011_TXDMAE;
674 pl011_write(uap->dmacr, uap, REG_DMACR);
675 uap->dmatx.queued = true;
676
677 /*
678 * Now we know that DMA will fire, so advance the ring buffer
679 * with the stuff we just dispatched.
680 */
681 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
682 uap->port.icount.tx += count;
683
684 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
685 uart_write_wakeup(&uap->port);
686
687 return 1;
688}
689
690/*
691 * We received a transmit interrupt without a pending X-char but with
692 * pending characters.
693 * Locking: called with port lock held and IRQs disabled.
694 * Returns:
695 * false if we want to use PIO to transmit
696 * true if we queued a DMA buffer
697 */
698static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
699{
700 if (!uap->using_tx_dma)
701 return false;
702
703 /*
704 * If we already have a TX buffer queued, but received a
705 * TX interrupt, it will be because we've just sent an X-char.
706 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
707 */
708 if (uap->dmatx.queued) {
709 uap->dmacr |= UART011_TXDMAE;
710 pl011_write(uap->dmacr, uap, REG_DMACR);
711 uap->im &= ~UART011_TXIM;
712 pl011_write(uap->im, uap, REG_IMSC);
713 return true;
714 }
715
716 /*
717 * We don't have a TX buffer queued, so try to queue one.
718 * If we successfully queued a buffer, mask the TX IRQ.
719 */
720 if (pl011_dma_tx_refill(uap) > 0) {
721 uap->im &= ~UART011_TXIM;
722 pl011_write(uap->im, uap, REG_IMSC);
723 return true;
724 }
725 return false;
726}
727
728/*
729 * Stop the DMA transmit (eg, due to received XOFF).
730 * Locking: called with port lock held and IRQs disabled.
731 */
732static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
733{
734 if (uap->dmatx.queued) {
735 uap->dmacr &= ~UART011_TXDMAE;
736 pl011_write(uap->dmacr, uap, REG_DMACR);
737 }
738}
739
740/*
741 * Try to start a DMA transmit, or in the case of an XON/OFF
742 * character queued for send, try to get that character out ASAP.
743 * Locking: called with port lock held and IRQs disabled.
744 * Returns:
745 * false if we want the TX IRQ to be enabled
746 * true if we have a buffer queued
747 */
748static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
749{
750 u16 dmacr;
751
752 if (!uap->using_tx_dma)
753 return false;
754
755 if (!uap->port.x_char) {
756 /* no X-char, try to push chars out in DMA mode */
757 bool ret = true;
758
759 if (!uap->dmatx.queued) {
760 if (pl011_dma_tx_refill(uap) > 0) {
761 uap->im &= ~UART011_TXIM;
762 pl011_write(uap->im, uap, REG_IMSC);
763 } else
764 ret = false;
765 } else if (!(uap->dmacr & UART011_TXDMAE)) {
766 uap->dmacr |= UART011_TXDMAE;
767 pl011_write(uap->dmacr, uap, REG_DMACR);
768 }
769 return ret;
770 }
771
772 /*
773 * We have an X-char to send. Disable DMA to prevent it loading
774 * the TX fifo, and then see if we can stuff it into the FIFO.
775 */
776 dmacr = uap->dmacr;
777 uap->dmacr &= ~UART011_TXDMAE;
778 pl011_write(uap->dmacr, uap, REG_DMACR);
779
780 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
781 /*
782 * No space in the FIFO, so enable the transmit interrupt
783 * so we know when there is space. Note that once we've
784 * loaded the character, we should just re-enable DMA.
785 */
786 return false;
787 }
788
789 pl011_write(uap->port.x_char, uap, REG_DR);
790 uap->port.icount.tx++;
791 uap->port.x_char = 0;
792
793 /* Success - restore the DMA state */
794 uap->dmacr = dmacr;
795 pl011_write(dmacr, uap, REG_DMACR);
796
797 return true;
798}
799
800/*
801 * Flush the transmit buffer.
802 * Locking: called with port lock held and IRQs disabled.
803 */
804static void pl011_dma_flush_buffer(struct uart_port *port)
805__releases(&uap->port.lock)
806__acquires(&uap->port.lock)
807{
808 struct uart_amba_port *uap =
809 container_of(port, struct uart_amba_port, port);
810
811 if (!uap->using_tx_dma)
812 return;
813
814 /* Avoid deadlock with the DMA engine callback */
815 spin_unlock(&uap->port.lock);
816 dmaengine_terminate_all(uap->dmatx.chan);
817 spin_lock(&uap->port.lock);
818 if (uap->dmatx.queued) {
819 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
820 DMA_TO_DEVICE);
821 uap->dmatx.queued = false;
822 uap->dmacr &= ~UART011_TXDMAE;
823 pl011_write(uap->dmacr, uap, REG_DMACR);
824 }
825}
826
827static void pl011_dma_rx_callback(void *data);
828
829static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
830{
831 struct dma_chan *rxchan = uap->dmarx.chan;
832 struct pl011_dmarx_data *dmarx = &uap->dmarx;
833 struct dma_async_tx_descriptor *desc;
834 struct pl011_sgbuf *sgbuf;
835
836 if (!rxchan)
837 return -EIO;
838
839 /* Start the RX DMA job */
840 sgbuf = uap->dmarx.use_buf_b ?
841 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
842 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
843 DMA_DEV_TO_MEM,
844 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
845 /*
846 * If the DMA engine is busy and cannot prepare a
847 * channel, no big deal, the driver will fall back
848 * to interrupt mode as a result of this error code.
849 */
850 if (!desc) {
851 uap->dmarx.running = false;
852 dmaengine_terminate_all(rxchan);
853 return -EBUSY;
854 }
855
856 /* Some data to go along to the callback */
857 desc->callback = pl011_dma_rx_callback;
858 desc->callback_param = uap;
859 dmarx->cookie = dmaengine_submit(desc);
860 dma_async_issue_pending(rxchan);
861
862 uap->dmacr |= UART011_RXDMAE;
863 pl011_write(uap->dmacr, uap, REG_DMACR);
864 uap->dmarx.running = true;
865
866 uap->im &= ~UART011_RXIM;
867 pl011_write(uap->im, uap, REG_IMSC);
868
869 return 0;
870}
871
872/*
873 * This is called when either the DMA job is complete, or
874 * the FIFO timeout interrupt occurred. This must be called
875 * with the port spinlock uap->port.lock held.
876 */
877static void pl011_dma_rx_chars(struct uart_amba_port *uap,
878 u32 pending, bool use_buf_b,
879 bool readfifo)
880{
881 struct tty_port *port = &uap->port.state->port;
882 struct pl011_sgbuf *sgbuf = use_buf_b ?
883 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
884 int dma_count = 0;
885 u32 fifotaken = 0; /* only used for vdbg() */
886
887 struct pl011_dmarx_data *dmarx = &uap->dmarx;
888 int dmataken = 0;
889
890 if (uap->dmarx.poll_rate) {
891 /* The data can be taken by polling */
892 dmataken = sgbuf->sg.length - dmarx->last_residue;
893 /* Recalculate the pending size */
894 if (pending >= dmataken)
895 pending -= dmataken;
896 }
897
898 /* Pick the remain data from the DMA */
899 if (pending) {
900
901 /*
902 * First take all chars in the DMA pipe, then look in the FIFO.
903 * Note that tty_insert_flip_buf() tries to take as many chars
904 * as it can.
905 */
906 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
907 pending);
908
909 uap->port.icount.rx += dma_count;
910 if (dma_count < pending)
911 dev_warn(uap->port.dev,
912 "couldn't insert all characters (TTY is full?)\n");
913 }
914
915 /* Reset the last_residue for Rx DMA poll */
916 if (uap->dmarx.poll_rate)
917 dmarx->last_residue = sgbuf->sg.length;
918
919 /*
920 * Only continue with trying to read the FIFO if all DMA chars have
921 * been taken first.
922 */
923 if (dma_count == pending && readfifo) {
924 /* Clear any error flags */
925 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
926 UART011_FEIS, uap, REG_ICR);
927
928 /*
929 * If we read all the DMA'd characters, and we had an
930 * incomplete buffer, that could be due to an rx error, or
931 * maybe we just timed out. Read any pending chars and check
932 * the error status.
933 *
934 * Error conditions will only occur in the FIFO, these will
935 * trigger an immediate interrupt and stop the DMA job, so we
936 * will always find the error in the FIFO, never in the DMA
937 * buffer.
938 */
939 fifotaken = pl011_fifo_to_tty(uap);
940 }
941
942 spin_unlock(&uap->port.lock);
943 dev_vdbg(uap->port.dev,
944 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
945 dma_count, fifotaken);
946 tty_flip_buffer_push(port);
947 spin_lock(&uap->port.lock);
948}
949
950static void pl011_dma_rx_irq(struct uart_amba_port *uap)
951{
952 struct pl011_dmarx_data *dmarx = &uap->dmarx;
953 struct dma_chan *rxchan = dmarx->chan;
954 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
955 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
956 size_t pending;
957 struct dma_tx_state state;
958 enum dma_status dmastat;
959
960 /*
961 * Pause the transfer so we can trust the current counter,
962 * do this before we pause the PL011 block, else we may
963 * overflow the FIFO.
964 */
965 if (dmaengine_pause(rxchan))
966 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
967 dmastat = rxchan->device->device_tx_status(rxchan,
968 dmarx->cookie, &state);
969 if (dmastat != DMA_PAUSED)
970 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
971
972 /* Disable RX DMA - incoming data will wait in the FIFO */
973 uap->dmacr &= ~UART011_RXDMAE;
974 pl011_write(uap->dmacr, uap, REG_DMACR);
975 uap->dmarx.running = false;
976
977 pending = sgbuf->sg.length - state.residue;
978 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
979 /* Then we terminate the transfer - we now know our residue */
980 dmaengine_terminate_all(rxchan);
981
982 /*
983 * This will take the chars we have so far and insert
984 * into the framework.
985 */
986 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
987
988 /* Switch buffer & re-trigger DMA job */
989 dmarx->use_buf_b = !dmarx->use_buf_b;
990 if (pl011_dma_rx_trigger_dma(uap)) {
991 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
992 "fall back to interrupt mode\n");
993 uap->im |= UART011_RXIM;
994 pl011_write(uap->im, uap, REG_IMSC);
995 }
996}
997
998static void pl011_dma_rx_callback(void *data)
999{
1000 struct uart_amba_port *uap = data;
1001 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1002 struct dma_chan *rxchan = dmarx->chan;
1003 bool lastbuf = dmarx->use_buf_b;
1004 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1005 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1006 size_t pending;
1007 struct dma_tx_state state;
1008 int ret;
1009
1010 /*
1011 * This completion interrupt occurs typically when the
1012 * RX buffer is totally stuffed but no timeout has yet
1013 * occurred. When that happens, we just want the RX
1014 * routine to flush out the secondary DMA buffer while
1015 * we immediately trigger the next DMA job.
1016 */
1017 spin_lock_irq(&uap->port.lock);
1018 /*
1019 * Rx data can be taken by the UART interrupts during
1020 * the DMA irq handler. So we check the residue here.
1021 */
1022 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1023 pending = sgbuf->sg.length - state.residue;
1024 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1025 /* Then we terminate the transfer - we now know our residue */
1026 dmaengine_terminate_all(rxchan);
1027
1028 uap->dmarx.running = false;
1029 dmarx->use_buf_b = !lastbuf;
1030 ret = pl011_dma_rx_trigger_dma(uap);
1031
1032 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1033 spin_unlock_irq(&uap->port.lock);
1034 /*
1035 * Do this check after we picked the DMA chars so we don't
1036 * get some IRQ immediately from RX.
1037 */
1038 if (ret) {
1039 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1040 "fall back to interrupt mode\n");
1041 uap->im |= UART011_RXIM;
1042 pl011_write(uap->im, uap, REG_IMSC);
1043 }
1044}
1045
1046/*
1047 * Stop accepting received characters, when we're shutting down or
1048 * suspending this port.
1049 * Locking: called with port lock held and IRQs disabled.
1050 */
1051static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1052{
1053 /* FIXME. Just disable the DMA enable */
1054 uap->dmacr &= ~UART011_RXDMAE;
1055 pl011_write(uap->dmacr, uap, REG_DMACR);
1056}
1057
1058/*
1059 * Timer handler for Rx DMA polling.
1060 * Every polling, It checks the residue in the dma buffer and transfer
1061 * data to the tty. Also, last_residue is updated for the next polling.
1062 */
1063static void pl011_dma_rx_poll(unsigned long args)
1064{
1065 struct uart_amba_port *uap = (struct uart_amba_port *)args;
1066 struct tty_port *port = &uap->port.state->port;
1067 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1068 struct dma_chan *rxchan = uap->dmarx.chan;
1069 unsigned long flags = 0;
1070 unsigned int dmataken = 0;
1071 unsigned int size = 0;
1072 struct pl011_sgbuf *sgbuf;
1073 int dma_count;
1074 struct dma_tx_state state;
1075
1076 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1077 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1078 if (likely(state.residue < dmarx->last_residue)) {
1079 dmataken = sgbuf->sg.length - dmarx->last_residue;
1080 size = dmarx->last_residue - state.residue;
1081 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1082 size);
1083 if (dma_count == size)
1084 dmarx->last_residue = state.residue;
1085 dmarx->last_jiffies = jiffies;
1086 }
1087 tty_flip_buffer_push(port);
1088
1089 /*
1090 * If no data is received in poll_timeout, the driver will fall back
1091 * to interrupt mode. We will retrigger DMA at the first interrupt.
1092 */
1093 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1094 > uap->dmarx.poll_timeout) {
1095
1096 spin_lock_irqsave(&uap->port.lock, flags);
1097 pl011_dma_rx_stop(uap);
1098 uap->im |= UART011_RXIM;
1099 pl011_write(uap->im, uap, REG_IMSC);
1100 spin_unlock_irqrestore(&uap->port.lock, flags);
1101
1102 uap->dmarx.running = false;
1103 dmaengine_terminate_all(rxchan);
1104 del_timer(&uap->dmarx.timer);
1105 } else {
1106 mod_timer(&uap->dmarx.timer,
1107 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1108 }
1109}
1110
1111static void pl011_dma_startup(struct uart_amba_port *uap)
1112{
1113 int ret;
1114
1115 if (!uap->dma_probed)
1116 pl011_dma_probe(uap);
1117
1118 if (!uap->dmatx.chan)
1119 return;
1120
1121 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1122 if (!uap->dmatx.buf) {
1123 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1124 uap->port.fifosize = uap->fifosize;
1125 return;
1126 }
1127
1128 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1129
1130 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1131 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1132 uap->using_tx_dma = true;
1133
1134 if (!uap->dmarx.chan)
1135 goto skip_rx;
1136
1137 /* Allocate and map DMA RX buffers */
1138 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1139 DMA_FROM_DEVICE);
1140 if (ret) {
1141 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1142 "RX buffer A", ret);
1143 goto skip_rx;
1144 }
1145
1146 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1147 DMA_FROM_DEVICE);
1148 if (ret) {
1149 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1150 "RX buffer B", ret);
1151 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1152 DMA_FROM_DEVICE);
1153 goto skip_rx;
1154 }
1155
1156 uap->using_rx_dma = true;
1157
1158skip_rx:
1159 /* Turn on DMA error (RX/TX will be enabled on demand) */
1160 uap->dmacr |= UART011_DMAONERR;
1161 pl011_write(uap->dmacr, uap, REG_DMACR);
1162
1163 /*
1164 * ST Micro variants has some specific dma burst threshold
1165 * compensation. Set this to 16 bytes, so burst will only
1166 * be issued above/below 16 bytes.
1167 */
1168 if (uap->vendor->dma_threshold)
1169 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1170 uap, REG_ST_DMAWM);
1171
1172 if (uap->using_rx_dma) {
1173 if (pl011_dma_rx_trigger_dma(uap))
1174 dev_dbg(uap->port.dev, "could not trigger initial "
1175 "RX DMA job, fall back to interrupt mode\n");
1176 if (uap->dmarx.poll_rate) {
1177 init_timer(&(uap->dmarx.timer));
1178 uap->dmarx.timer.function = pl011_dma_rx_poll;
1179 uap->dmarx.timer.data = (unsigned long)uap;
1180 mod_timer(&uap->dmarx.timer,
1181 jiffies +
1182 msecs_to_jiffies(uap->dmarx.poll_rate));
1183 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1184 uap->dmarx.last_jiffies = jiffies;
1185 }
1186 }
1187}
1188
1189static void pl011_dma_shutdown(struct uart_amba_port *uap)
1190{
1191 if (!(uap->using_tx_dma || uap->using_rx_dma))
1192 return;
1193
1194 /* Disable RX and TX DMA */
1195 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1196 cpu_relax();
1197
1198 spin_lock_irq(&uap->port.lock);
1199 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1200 pl011_write(uap->dmacr, uap, REG_DMACR);
1201 spin_unlock_irq(&uap->port.lock);
1202
1203 if (uap->using_tx_dma) {
1204 /* In theory, this should already be done by pl011_dma_flush_buffer */
1205 dmaengine_terminate_all(uap->dmatx.chan);
1206 if (uap->dmatx.queued) {
1207 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1208 DMA_TO_DEVICE);
1209 uap->dmatx.queued = false;
1210 }
1211
1212 kfree(uap->dmatx.buf);
1213 uap->using_tx_dma = false;
1214 }
1215
1216 if (uap->using_rx_dma) {
1217 dmaengine_terminate_all(uap->dmarx.chan);
1218 /* Clean up the RX DMA */
1219 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1220 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1221 if (uap->dmarx.poll_rate)
1222 del_timer_sync(&uap->dmarx.timer);
1223 uap->using_rx_dma = false;
1224 }
1225}
1226
1227static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1228{
1229 return uap->using_rx_dma;
1230}
1231
1232static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1233{
1234 return uap->using_rx_dma && uap->dmarx.running;
1235}
1236
1237#else
1238/* Blank functions if the DMA engine is not available */
1239static inline void pl011_dma_probe(struct uart_amba_port *uap)
1240{
1241}
1242
1243static inline void pl011_dma_remove(struct uart_amba_port *uap)
1244{
1245}
1246
1247static inline void pl011_dma_startup(struct uart_amba_port *uap)
1248{
1249}
1250
1251static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1252{
1253}
1254
1255static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1256{
1257 return false;
1258}
1259
1260static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1261{
1262}
1263
1264static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1265{
1266 return false;
1267}
1268
1269static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1270{
1271}
1272
1273static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1274{
1275}
1276
1277static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1278{
1279 return -EIO;
1280}
1281
1282static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1283{
1284 return false;
1285}
1286
1287static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1288{
1289 return false;
1290}
1291
1292#define pl011_dma_flush_buffer NULL
1293#endif
1294
1295static void pl011_stop_tx(struct uart_port *port)
1296{
1297 struct uart_amba_port *uap =
1298 container_of(port, struct uart_amba_port, port);
1299
1300 uap->im &= ~UART011_TXIM;
1301 pl011_write(uap->im, uap, REG_IMSC);
1302 pl011_dma_tx_stop(uap);
1303}
1304
1305static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1306
1307/* Start TX with programmed I/O only (no DMA) */
1308static void pl011_start_tx_pio(struct uart_amba_port *uap)
1309{
1310 uap->im |= UART011_TXIM;
1311 pl011_write(uap->im, uap, REG_IMSC);
1312 pl011_tx_chars(uap, false);
1313}
1314
1315static void pl011_start_tx(struct uart_port *port)
1316{
1317 struct uart_amba_port *uap =
1318 container_of(port, struct uart_amba_port, port);
1319
1320 if (!pl011_dma_tx_start(uap))
1321 pl011_start_tx_pio(uap);
1322}
1323
1324static void pl011_stop_rx(struct uart_port *port)
1325{
1326 struct uart_amba_port *uap =
1327 container_of(port, struct uart_amba_port, port);
1328
1329 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1330 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1331 pl011_write(uap->im, uap, REG_IMSC);
1332
1333 pl011_dma_rx_stop(uap);
1334}
1335
1336static void pl011_enable_ms(struct uart_port *port)
1337{
1338 struct uart_amba_port *uap =
1339 container_of(port, struct uart_amba_port, port);
1340
1341 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1342 pl011_write(uap->im, uap, REG_IMSC);
1343}
1344
1345static void pl011_rx_chars(struct uart_amba_port *uap)
1346__releases(&uap->port.lock)
1347__acquires(&uap->port.lock)
1348{
1349 pl011_fifo_to_tty(uap);
1350
1351 spin_unlock(&uap->port.lock);
1352 tty_flip_buffer_push(&uap->port.state->port);
1353 /*
1354 * If we were temporarily out of DMA mode for a while,
1355 * attempt to switch back to DMA mode again.
1356 */
1357 if (pl011_dma_rx_available(uap)) {
1358 if (pl011_dma_rx_trigger_dma(uap)) {
1359 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1360 "fall back to interrupt mode again\n");
1361 uap->im |= UART011_RXIM;
1362 pl011_write(uap->im, uap, REG_IMSC);
1363 } else {
1364#ifdef CONFIG_DMA_ENGINE
1365 /* Start Rx DMA poll */
1366 if (uap->dmarx.poll_rate) {
1367 uap->dmarx.last_jiffies = jiffies;
1368 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1369 mod_timer(&uap->dmarx.timer,
1370 jiffies +
1371 msecs_to_jiffies(uap->dmarx.poll_rate));
1372 }
1373#endif
1374 }
1375 }
1376 spin_lock(&uap->port.lock);
1377}
1378
1379static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1380 bool from_irq)
1381{
1382 if (unlikely(!from_irq) &&
1383 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1384 return false; /* unable to transmit character */
1385
1386 pl011_write(c, uap, REG_DR);
1387 uap->port.icount.tx++;
1388
1389 return true;
1390}
1391
1392static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1393{
1394 struct circ_buf *xmit = &uap->port.state->xmit;
1395 int count = uap->fifosize >> 1;
1396
1397 if (uap->port.x_char) {
1398 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1399 return;
1400 uap->port.x_char = 0;
1401 --count;
1402 }
1403 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1404 pl011_stop_tx(&uap->port);
1405 return;
1406 }
1407
1408 /* If we are using DMA mode, try to send some characters. */
1409 if (pl011_dma_tx_irq(uap))
1410 return;
1411
1412 do {
1413 if (likely(from_irq) && count-- == 0)
1414 break;
1415
1416 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1417 break;
1418
1419 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1420 } while (!uart_circ_empty(xmit));
1421
1422 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1423 uart_write_wakeup(&uap->port);
1424
1425 if (uart_circ_empty(xmit))
1426 pl011_stop_tx(&uap->port);
1427}
1428
1429static void pl011_modem_status(struct uart_amba_port *uap)
1430{
1431 unsigned int status, delta;
1432
1433 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1434
1435 delta = status ^ uap->old_status;
1436 uap->old_status = status;
1437
1438 if (!delta)
1439 return;
1440
1441 if (delta & UART01x_FR_DCD)
1442 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1443
1444 if (delta & uap->vendor->fr_dsr)
1445 uap->port.icount.dsr++;
1446
1447 if (delta & uap->vendor->fr_cts)
1448 uart_handle_cts_change(&uap->port,
1449 status & uap->vendor->fr_cts);
1450
1451 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1452}
1453
1454static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1455{
1456 unsigned int dummy_read;
1457
1458 if (!uap->vendor->cts_event_workaround)
1459 return;
1460
1461 /* workaround to make sure that all bits are unlocked.. */
1462 pl011_write(0x00, uap, REG_ICR);
1463
1464 /*
1465 * WA: introduce 26ns(1 uart clk) delay before W1C;
1466 * single apb access will incur 2 pclk(133.12Mhz) delay,
1467 * so add 2 dummy reads
1468 */
1469 dummy_read = pl011_read(uap, REG_ICR);
1470 dummy_read = pl011_read(uap, REG_ICR);
1471}
1472
1473static irqreturn_t pl011_int(int irq, void *dev_id)
1474{
1475 struct uart_amba_port *uap = dev_id;
1476 unsigned long flags;
1477 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1478 u16 imsc;
1479 int handled = 0;
1480
1481 spin_lock_irqsave(&uap->port.lock, flags);
1482 imsc = pl011_read(uap, REG_IMSC);
1483 status = pl011_read(uap, REG_RIS) & imsc;
1484 if (status) {
1485 do {
1486 check_apply_cts_event_workaround(uap);
1487
1488 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1489 UART011_RXIS),
1490 uap, REG_ICR);
1491
1492 if (status & (UART011_RTIS|UART011_RXIS)) {
1493 if (pl011_dma_rx_running(uap))
1494 pl011_dma_rx_irq(uap);
1495 else
1496 pl011_rx_chars(uap);
1497 }
1498 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1499 UART011_CTSMIS|UART011_RIMIS))
1500 pl011_modem_status(uap);
1501 if (status & UART011_TXIS)
1502 pl011_tx_chars(uap, true);
1503
1504 if (pass_counter-- == 0)
1505 break;
1506
1507 status = pl011_read(uap, REG_RIS) & imsc;
1508 } while (status != 0);
1509 handled = 1;
1510 }
1511
1512 spin_unlock_irqrestore(&uap->port.lock, flags);
1513
1514 return IRQ_RETVAL(handled);
1515}
1516
1517static unsigned int pl011_tx_empty(struct uart_port *port)
1518{
1519 struct uart_amba_port *uap =
1520 container_of(port, struct uart_amba_port, port);
1521 unsigned int status = pl011_read(uap, REG_FR);
1522 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1523 0 : TIOCSER_TEMT;
1524}
1525
1526static unsigned int pl011_get_mctrl(struct uart_port *port)
1527{
1528 struct uart_amba_port *uap =
1529 container_of(port, struct uart_amba_port, port);
1530 unsigned int result = 0;
1531 unsigned int status = pl011_read(uap, REG_FR);
1532
1533#define TIOCMBIT(uartbit, tiocmbit) \
1534 if (status & uartbit) \
1535 result |= tiocmbit
1536
1537 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1538 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1539 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1540 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1541#undef TIOCMBIT
1542 return result;
1543}
1544
1545static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1546{
1547 struct uart_amba_port *uap =
1548 container_of(port, struct uart_amba_port, port);
1549 unsigned int cr;
1550
1551 cr = pl011_read(uap, REG_CR);
1552
1553#define TIOCMBIT(tiocmbit, uartbit) \
1554 if (mctrl & tiocmbit) \
1555 cr |= uartbit; \
1556 else \
1557 cr &= ~uartbit
1558
1559 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1560 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1561 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1562 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1563 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1564
1565 if (uap->autorts) {
1566 /* We need to disable auto-RTS if we want to turn RTS off */
1567 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1568 }
1569#undef TIOCMBIT
1570
1571 pl011_write(cr, uap, REG_CR);
1572}
1573
1574static void pl011_break_ctl(struct uart_port *port, int break_state)
1575{
1576 struct uart_amba_port *uap =
1577 container_of(port, struct uart_amba_port, port);
1578 unsigned long flags;
1579 unsigned int lcr_h;
1580
1581 spin_lock_irqsave(&uap->port.lock, flags);
1582 lcr_h = pl011_read(uap, REG_LCRH_TX);
1583 if (break_state == -1)
1584 lcr_h |= UART01x_LCRH_BRK;
1585 else
1586 lcr_h &= ~UART01x_LCRH_BRK;
1587 pl011_write(lcr_h, uap, REG_LCRH_TX);
1588 spin_unlock_irqrestore(&uap->port.lock, flags);
1589}
1590
1591#ifdef CONFIG_CONSOLE_POLL
1592
1593static void pl011_quiesce_irqs(struct uart_port *port)
1594{
1595 struct uart_amba_port *uap =
1596 container_of(port, struct uart_amba_port, port);
1597
1598 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1599 /*
1600 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1601 * we simply mask it. start_tx() will unmask it.
1602 *
1603 * Note we can race with start_tx(), and if the race happens, the
1604 * polling user might get another interrupt just after we clear it.
1605 * But it should be OK and can happen even w/o the race, e.g.
1606 * controller immediately got some new data and raised the IRQ.
1607 *
1608 * And whoever uses polling routines assumes that it manages the device
1609 * (including tx queue), so we're also fine with start_tx()'s caller
1610 * side.
1611 */
1612 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1613 REG_IMSC);
1614}
1615
1616static int pl011_get_poll_char(struct uart_port *port)
1617{
1618 struct uart_amba_port *uap =
1619 container_of(port, struct uart_amba_port, port);
1620 unsigned int status;
1621
1622 /*
1623 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1624 * debugger.
1625 */
1626 pl011_quiesce_irqs(port);
1627
1628 status = pl011_read(uap, REG_FR);
1629 if (status & UART01x_FR_RXFE)
1630 return NO_POLL_CHAR;
1631
1632 return pl011_read(uap, REG_DR);
1633}
1634
1635static void pl011_put_poll_char(struct uart_port *port,
1636 unsigned char ch)
1637{
1638 struct uart_amba_port *uap =
1639 container_of(port, struct uart_amba_port, port);
1640
1641 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1642 cpu_relax();
1643
1644 pl011_write(ch, uap, REG_DR);
1645}
1646
1647#endif /* CONFIG_CONSOLE_POLL */
1648
1649static int pl011_hwinit(struct uart_port *port)
1650{
1651 struct uart_amba_port *uap =
1652 container_of(port, struct uart_amba_port, port);
1653 int retval;
1654
1655 /* Optionaly enable pins to be muxed in and configured */
1656 pinctrl_pm_select_default_state(port->dev);
1657
1658 /*
1659 * Try to enable the clock producer.
1660 */
1661 retval = clk_prepare_enable(uap->clk);
1662 if (retval)
1663 return retval;
1664
1665 uap->port.uartclk = clk_get_rate(uap->clk);
1666
1667 /* Clear pending error and receive interrupts */
1668 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1669 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1670 uap, REG_ICR);
1671
1672 /*
1673 * Save interrupts enable mask, and enable RX interrupts in case if
1674 * the interrupt is used for NMI entry.
1675 */
1676 uap->im = pl011_read(uap, REG_IMSC);
1677 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1678
1679 if (dev_get_platdata(uap->port.dev)) {
1680 struct amba_pl011_data *plat;
1681
1682 plat = dev_get_platdata(uap->port.dev);
1683 if (plat->init)
1684 plat->init();
1685 }
1686 return 0;
1687}
1688
1689static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1690{
1691 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1692 pl011_reg_to_offset(uap, REG_LCRH_TX);
1693}
1694
1695static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1696{
1697 pl011_write(lcr_h, uap, REG_LCRH_RX);
1698 if (pl011_split_lcrh(uap)) {
1699 int i;
1700 /*
1701 * Wait 10 PCLKs before writing LCRH_TX register,
1702 * to get this delay write read only register 10 times
1703 */
1704 for (i = 0; i < 10; ++i)
1705 pl011_write(0xff, uap, REG_MIS);
1706 pl011_write(lcr_h, uap, REG_LCRH_TX);
1707 }
1708}
1709
1710static int pl011_allocate_irq(struct uart_amba_port *uap)
1711{
1712 pl011_write(uap->im, uap, REG_IMSC);
1713
1714 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1715}
1716
1717/*
1718 * Enable interrupts, only timeouts when using DMA
1719 * if initial RX DMA job failed, start in interrupt mode
1720 * as well.
1721 */
1722static void pl011_enable_interrupts(struct uart_amba_port *uap)
1723{
1724 spin_lock_irq(&uap->port.lock);
1725
1726 /* Clear out any spuriously appearing RX interrupts */
1727 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1728 uap->im = UART011_RTIM;
1729 if (!pl011_dma_rx_running(uap))
1730 uap->im |= UART011_RXIM;
1731 pl011_write(uap->im, uap, REG_IMSC);
1732 spin_unlock_irq(&uap->port.lock);
1733}
1734
1735static int pl011_startup(struct uart_port *port)
1736{
1737 struct uart_amba_port *uap =
1738 container_of(port, struct uart_amba_port, port);
1739 unsigned int cr;
1740 int retval;
1741
1742 retval = pl011_hwinit(port);
1743 if (retval)
1744 goto clk_dis;
1745
1746 retval = pl011_allocate_irq(uap);
1747 if (retval)
1748 goto clk_dis;
1749
1750 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1751
1752 spin_lock_irq(&uap->port.lock);
1753
1754 /* restore RTS and DTR */
1755 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1756 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1757 pl011_write(cr, uap, REG_CR);
1758
1759 spin_unlock_irq(&uap->port.lock);
1760
1761 /*
1762 * initialise the old status of the modem signals
1763 */
1764 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1765
1766 /* Startup DMA */
1767 pl011_dma_startup(uap);
1768
1769 pl011_enable_interrupts(uap);
1770
1771 return 0;
1772
1773 clk_dis:
1774 clk_disable_unprepare(uap->clk);
1775 return retval;
1776}
1777
1778static int sbsa_uart_startup(struct uart_port *port)
1779{
1780 struct uart_amba_port *uap =
1781 container_of(port, struct uart_amba_port, port);
1782 int retval;
1783
1784 retval = pl011_hwinit(port);
1785 if (retval)
1786 return retval;
1787
1788 retval = pl011_allocate_irq(uap);
1789 if (retval)
1790 return retval;
1791
1792 /* The SBSA UART does not support any modem status lines. */
1793 uap->old_status = 0;
1794
1795 pl011_enable_interrupts(uap);
1796
1797 return 0;
1798}
1799
1800static void pl011_shutdown_channel(struct uart_amba_port *uap,
1801 unsigned int lcrh)
1802{
1803 unsigned long val;
1804
1805 val = pl011_read(uap, lcrh);
1806 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1807 pl011_write(val, uap, lcrh);
1808}
1809
1810/*
1811 * disable the port. It should not disable RTS and DTR.
1812 * Also RTS and DTR state should be preserved to restore
1813 * it during startup().
1814 */
1815static void pl011_disable_uart(struct uart_amba_port *uap)
1816{
1817 unsigned int cr;
1818
1819 uap->autorts = false;
1820 spin_lock_irq(&uap->port.lock);
1821 cr = pl011_read(uap, REG_CR);
1822 uap->old_cr = cr;
1823 cr &= UART011_CR_RTS | UART011_CR_DTR;
1824 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1825 pl011_write(cr, uap, REG_CR);
1826 spin_unlock_irq(&uap->port.lock);
1827
1828 /*
1829 * disable break condition and fifos
1830 */
1831 pl011_shutdown_channel(uap, REG_LCRH_RX);
1832 if (pl011_split_lcrh(uap))
1833 pl011_shutdown_channel(uap, REG_LCRH_TX);
1834}
1835
1836static void pl011_disable_interrupts(struct uart_amba_port *uap)
1837{
1838 spin_lock_irq(&uap->port.lock);
1839
1840 /* mask all interrupts and clear all pending ones */
1841 uap->im = 0;
1842 pl011_write(uap->im, uap, REG_IMSC);
1843 pl011_write(0xffff, uap, REG_ICR);
1844
1845 spin_unlock_irq(&uap->port.lock);
1846}
1847
1848static void pl011_shutdown(struct uart_port *port)
1849{
1850 struct uart_amba_port *uap =
1851 container_of(port, struct uart_amba_port, port);
1852
1853 pl011_disable_interrupts(uap);
1854
1855 pl011_dma_shutdown(uap);
1856
1857 free_irq(uap->port.irq, uap);
1858
1859 pl011_disable_uart(uap);
1860
1861 /*
1862 * Shut down the clock producer
1863 */
1864 clk_disable_unprepare(uap->clk);
1865 /* Optionally let pins go into sleep states */
1866 pinctrl_pm_select_sleep_state(port->dev);
1867
1868 if (dev_get_platdata(uap->port.dev)) {
1869 struct amba_pl011_data *plat;
1870
1871 plat = dev_get_platdata(uap->port.dev);
1872 if (plat->exit)
1873 plat->exit();
1874 }
1875
1876 if (uap->port.ops->flush_buffer)
1877 uap->port.ops->flush_buffer(port);
1878}
1879
1880static void sbsa_uart_shutdown(struct uart_port *port)
1881{
1882 struct uart_amba_port *uap =
1883 container_of(port, struct uart_amba_port, port);
1884
1885 pl011_disable_interrupts(uap);
1886
1887 free_irq(uap->port.irq, uap);
1888
1889 if (uap->port.ops->flush_buffer)
1890 uap->port.ops->flush_buffer(port);
1891}
1892
1893static void
1894pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1895{
1896 port->read_status_mask = UART011_DR_OE | 255;
1897 if (termios->c_iflag & INPCK)
1898 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1899 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1900 port->read_status_mask |= UART011_DR_BE;
1901
1902 /*
1903 * Characters to ignore
1904 */
1905 port->ignore_status_mask = 0;
1906 if (termios->c_iflag & IGNPAR)
1907 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1908 if (termios->c_iflag & IGNBRK) {
1909 port->ignore_status_mask |= UART011_DR_BE;
1910 /*
1911 * If we're ignoring parity and break indicators,
1912 * ignore overruns too (for real raw support).
1913 */
1914 if (termios->c_iflag & IGNPAR)
1915 port->ignore_status_mask |= UART011_DR_OE;
1916 }
1917
1918 /*
1919 * Ignore all characters if CREAD is not set.
1920 */
1921 if ((termios->c_cflag & CREAD) == 0)
1922 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1923}
1924
1925static void
1926pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1927 struct ktermios *old)
1928{
1929 struct uart_amba_port *uap =
1930 container_of(port, struct uart_amba_port, port);
1931 unsigned int lcr_h, old_cr;
1932 unsigned long flags;
1933 unsigned int baud, quot, clkdiv;
1934
1935 if (uap->vendor->oversampling)
1936 clkdiv = 8;
1937 else
1938 clkdiv = 16;
1939
1940 /*
1941 * Ask the core to calculate the divisor for us.
1942 */
1943 baud = uart_get_baud_rate(port, termios, old, 0,
1944 port->uartclk / clkdiv);
1945#ifdef CONFIG_DMA_ENGINE
1946 /*
1947 * Adjust RX DMA polling rate with baud rate if not specified.
1948 */
1949 if (uap->dmarx.auto_poll_rate)
1950 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1951#endif
1952
1953 if (baud > port->uartclk/16)
1954 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1955 else
1956 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1957
1958 switch (termios->c_cflag & CSIZE) {
1959 case CS5:
1960 lcr_h = UART01x_LCRH_WLEN_5;
1961 break;
1962 case CS6:
1963 lcr_h = UART01x_LCRH_WLEN_6;
1964 break;
1965 case CS7:
1966 lcr_h = UART01x_LCRH_WLEN_7;
1967 break;
1968 default: // CS8
1969 lcr_h = UART01x_LCRH_WLEN_8;
1970 break;
1971 }
1972 if (termios->c_cflag & CSTOPB)
1973 lcr_h |= UART01x_LCRH_STP2;
1974 if (termios->c_cflag & PARENB) {
1975 lcr_h |= UART01x_LCRH_PEN;
1976 if (!(termios->c_cflag & PARODD))
1977 lcr_h |= UART01x_LCRH_EPS;
1978 if (termios->c_cflag & CMSPAR)
1979 lcr_h |= UART011_LCRH_SPS;
1980 }
1981 if (uap->fifosize > 1)
1982 lcr_h |= UART01x_LCRH_FEN;
1983
1984 spin_lock_irqsave(&port->lock, flags);
1985
1986 /*
1987 * Update the per-port timeout.
1988 */
1989 uart_update_timeout(port, termios->c_cflag, baud);
1990
1991 pl011_setup_status_masks(port, termios);
1992
1993 if (UART_ENABLE_MS(port, termios->c_cflag))
1994 pl011_enable_ms(port);
1995
1996 /* first, disable everything */
1997 old_cr = pl011_read(uap, REG_CR);
1998 pl011_write(0, uap, REG_CR);
1999
2000 if (termios->c_cflag & CRTSCTS) {
2001 if (old_cr & UART011_CR_RTS)
2002 old_cr |= UART011_CR_RTSEN;
2003
2004 old_cr |= UART011_CR_CTSEN;
2005 uap->autorts = true;
2006 } else {
2007 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2008 uap->autorts = false;
2009 }
2010
2011 if (uap->vendor->oversampling) {
2012 if (baud > port->uartclk / 16)
2013 old_cr |= ST_UART011_CR_OVSFACT;
2014 else
2015 old_cr &= ~ST_UART011_CR_OVSFACT;
2016 }
2017
2018 /*
2019 * Workaround for the ST Micro oversampling variants to
2020 * increase the bitrate slightly, by lowering the divisor,
2021 * to avoid delayed sampling of start bit at high speeds,
2022 * else we see data corruption.
2023 */
2024 if (uap->vendor->oversampling) {
2025 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2026 quot -= 1;
2027 else if ((baud > 3250000) && (quot > 2))
2028 quot -= 2;
2029 }
2030 /* Set baud rate */
2031 pl011_write(quot & 0x3f, uap, REG_FBRD);
2032 pl011_write(quot >> 6, uap, REG_IBRD);
2033
2034 /*
2035 * ----------v----------v----------v----------v-----
2036 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2037 * REG_FBRD & REG_IBRD.
2038 * ----------^----------^----------^----------^-----
2039 */
2040 pl011_write_lcr_h(uap, lcr_h);
2041 pl011_write(old_cr, uap, REG_CR);
2042
2043 spin_unlock_irqrestore(&port->lock, flags);
2044}
2045
2046static void
2047sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2048 struct ktermios *old)
2049{
2050 struct uart_amba_port *uap =
2051 container_of(port, struct uart_amba_port, port);
2052 unsigned long flags;
2053
2054 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2055
2056 /* The SBSA UART only supports 8n1 without hardware flow control. */
2057 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2058 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2059 termios->c_cflag |= CS8 | CLOCAL;
2060
2061 spin_lock_irqsave(&port->lock, flags);
2062 uart_update_timeout(port, CS8, uap->fixed_baud);
2063 pl011_setup_status_masks(port, termios);
2064 spin_unlock_irqrestore(&port->lock, flags);
2065}
2066
2067static const char *pl011_type(struct uart_port *port)
2068{
2069 struct uart_amba_port *uap =
2070 container_of(port, struct uart_amba_port, port);
2071 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2072}
2073
2074/*
2075 * Release the memory region(s) being used by 'port'
2076 */
2077static void pl011_release_port(struct uart_port *port)
2078{
2079 release_mem_region(port->mapbase, SZ_4K);
2080}
2081
2082/*
2083 * Request the memory region(s) being used by 'port'
2084 */
2085static int pl011_request_port(struct uart_port *port)
2086{
2087 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2088 != NULL ? 0 : -EBUSY;
2089}
2090
2091/*
2092 * Configure/autoconfigure the port.
2093 */
2094static void pl011_config_port(struct uart_port *port, int flags)
2095{
2096 if (flags & UART_CONFIG_TYPE) {
2097 port->type = PORT_AMBA;
2098 pl011_request_port(port);
2099 }
2100}
2101
2102/*
2103 * verify the new serial_struct (for TIOCSSERIAL).
2104 */
2105static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2106{
2107 int ret = 0;
2108 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2109 ret = -EINVAL;
2110 if (ser->irq < 0 || ser->irq >= nr_irqs)
2111 ret = -EINVAL;
2112 if (ser->baud_base < 9600)
2113 ret = -EINVAL;
2114 return ret;
2115}
2116
2117static struct uart_ops amba_pl011_pops = {
2118 .tx_empty = pl011_tx_empty,
2119 .set_mctrl = pl011_set_mctrl,
2120 .get_mctrl = pl011_get_mctrl,
2121 .stop_tx = pl011_stop_tx,
2122 .start_tx = pl011_start_tx,
2123 .stop_rx = pl011_stop_rx,
2124 .enable_ms = pl011_enable_ms,
2125 .break_ctl = pl011_break_ctl,
2126 .startup = pl011_startup,
2127 .shutdown = pl011_shutdown,
2128 .flush_buffer = pl011_dma_flush_buffer,
2129 .set_termios = pl011_set_termios,
2130 .type = pl011_type,
2131 .release_port = pl011_release_port,
2132 .request_port = pl011_request_port,
2133 .config_port = pl011_config_port,
2134 .verify_port = pl011_verify_port,
2135#ifdef CONFIG_CONSOLE_POLL
2136 .poll_init = pl011_hwinit,
2137 .poll_get_char = pl011_get_poll_char,
2138 .poll_put_char = pl011_put_poll_char,
2139#endif
2140};
2141
2142static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2143{
2144}
2145
2146static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2147{
2148 return 0;
2149}
2150
2151static const struct uart_ops sbsa_uart_pops = {
2152 .tx_empty = pl011_tx_empty,
2153 .set_mctrl = sbsa_uart_set_mctrl,
2154 .get_mctrl = sbsa_uart_get_mctrl,
2155 .stop_tx = pl011_stop_tx,
2156 .start_tx = pl011_start_tx,
2157 .stop_rx = pl011_stop_rx,
2158 .startup = sbsa_uart_startup,
2159 .shutdown = sbsa_uart_shutdown,
2160 .set_termios = sbsa_uart_set_termios,
2161 .type = pl011_type,
2162 .release_port = pl011_release_port,
2163 .request_port = pl011_request_port,
2164 .config_port = pl011_config_port,
2165 .verify_port = pl011_verify_port,
2166#ifdef CONFIG_CONSOLE_POLL
2167 .poll_init = pl011_hwinit,
2168 .poll_get_char = pl011_get_poll_char,
2169 .poll_put_char = pl011_put_poll_char,
2170#endif
2171};
2172
2173static struct uart_amba_port *amba_ports[UART_NR];
2174
2175#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2176
2177static void pl011_console_putchar(struct uart_port *port, int ch)
2178{
2179 struct uart_amba_port *uap =
2180 container_of(port, struct uart_amba_port, port);
2181
2182 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2183 cpu_relax();
2184 pl011_write(ch, uap, REG_DR);
2185}
2186
2187static void
2188pl011_console_write(struct console *co, const char *s, unsigned int count)
2189{
2190 struct uart_amba_port *uap = amba_ports[co->index];
2191 unsigned int old_cr = 0, new_cr;
2192 unsigned long flags;
2193 int locked = 1;
2194
2195 clk_enable(uap->clk);
2196
2197 local_irq_save(flags);
2198 if (uap->port.sysrq)
2199 locked = 0;
2200 else if (oops_in_progress)
2201 locked = spin_trylock(&uap->port.lock);
2202 else
2203 spin_lock(&uap->port.lock);
2204
2205 /*
2206 * First save the CR then disable the interrupts
2207 */
2208 if (!uap->vendor->always_enabled) {
2209 old_cr = pl011_read(uap, REG_CR);
2210 new_cr = old_cr & ~UART011_CR_CTSEN;
2211 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2212 pl011_write(new_cr, uap, REG_CR);
2213 }
2214
2215 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2216
2217 /*
2218 * Finally, wait for transmitter to become empty
2219 * and restore the TCR
2220 */
2221 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
2222 cpu_relax();
2223 if (!uap->vendor->always_enabled)
2224 pl011_write(old_cr, uap, REG_CR);
2225
2226 if (locked)
2227 spin_unlock(&uap->port.lock);
2228 local_irq_restore(flags);
2229
2230 clk_disable(uap->clk);
2231}
2232
2233static void __init
2234pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2235 int *parity, int *bits)
2236{
2237 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2238 unsigned int lcr_h, ibrd, fbrd;
2239
2240 lcr_h = pl011_read(uap, REG_LCRH_TX);
2241
2242 *parity = 'n';
2243 if (lcr_h & UART01x_LCRH_PEN) {
2244 if (lcr_h & UART01x_LCRH_EPS)
2245 *parity = 'e';
2246 else
2247 *parity = 'o';
2248 }
2249
2250 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2251 *bits = 7;
2252 else
2253 *bits = 8;
2254
2255 ibrd = pl011_read(uap, REG_IBRD);
2256 fbrd = pl011_read(uap, REG_FBRD);
2257
2258 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2259
2260 if (uap->vendor->oversampling) {
2261 if (pl011_read(uap, REG_CR)
2262 & ST_UART011_CR_OVSFACT)
2263 *baud *= 2;
2264 }
2265 }
2266}
2267
2268static int __init pl011_console_setup(struct console *co, char *options)
2269{
2270 struct uart_amba_port *uap;
2271 int baud = 38400;
2272 int bits = 8;
2273 int parity = 'n';
2274 int flow = 'n';
2275 int ret;
2276
2277 /*
2278 * Check whether an invalid uart number has been specified, and
2279 * if so, search for the first available port that does have
2280 * console support.
2281 */
2282 if (co->index >= UART_NR)
2283 co->index = 0;
2284 uap = amba_ports[co->index];
2285 if (!uap)
2286 return -ENODEV;
2287
2288 /* Allow pins to be muxed in and configured */
2289 pinctrl_pm_select_default_state(uap->port.dev);
2290
2291 ret = clk_prepare(uap->clk);
2292 if (ret)
2293 return ret;
2294
2295 if (dev_get_platdata(uap->port.dev)) {
2296 struct amba_pl011_data *plat;
2297
2298 plat = dev_get_platdata(uap->port.dev);
2299 if (plat->init)
2300 plat->init();
2301 }
2302
2303 uap->port.uartclk = clk_get_rate(uap->clk);
2304
2305 if (uap->vendor->fixed_options) {
2306 baud = uap->fixed_baud;
2307 } else {
2308 if (options)
2309 uart_parse_options(options,
2310 &baud, &parity, &bits, &flow);
2311 else
2312 pl011_console_get_options(uap, &baud, &parity, &bits);
2313 }
2314
2315 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2316}
2317
2318/**
2319 * pl011_console_match - non-standard console matching
2320 * @co: registering console
2321 * @name: name from console command line
2322 * @idx: index from console command line
2323 * @options: ptr to option string from console command line
2324 *
2325 * Only attempts to match console command lines of the form:
2326 * console=pl011,mmio|mmio32,<addr>[,<options>]
2327 * console=pl011,0x<addr>[,<options>]
2328 * This form is used to register an initial earlycon boot console and
2329 * replace it with the amba_console at pl011 driver init.
2330 *
2331 * Performs console setup for a match (as required by interface)
2332 * If no <options> are specified, then assume the h/w is already setup.
2333 *
2334 * Returns 0 if console matches; otherwise non-zero to use default matching
2335 */
2336static int __init pl011_console_match(struct console *co, char *name, int idx,
2337 char *options)
2338{
2339 unsigned char iotype;
2340 resource_size_t addr;
2341 int i;
2342
2343 if (strcmp(name, "pl011") != 0)
2344 return -ENODEV;
2345
2346 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2347 return -ENODEV;
2348
2349 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2350 return -ENODEV;
2351
2352 /* try to match the port specified on the command line */
2353 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2354 struct uart_port *port;
2355
2356 if (!amba_ports[i])
2357 continue;
2358
2359 port = &amba_ports[i]->port;
2360
2361 if (port->mapbase != addr)
2362 continue;
2363
2364 co->index = i;
2365 port->cons = co;
2366 return pl011_console_setup(co, options);
2367 }
2368
2369 return -ENODEV;
2370}
2371
2372static struct uart_driver amba_reg;
2373static struct console amba_console = {
2374 .name = "ttyAMA",
2375 .write = pl011_console_write,
2376 .device = uart_console_device,
2377 .setup = pl011_console_setup,
2378 .match = pl011_console_match,
2379 .flags = CON_PRINTBUFFER,
2380 .index = -1,
2381 .data = &amba_reg,
2382};
2383
2384#define AMBA_CONSOLE (&amba_console)
2385
2386static void pl011_putc(struct uart_port *port, int c)
2387{
2388 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2389 cpu_relax();
2390 if (port->iotype == UPIO_MEM32)
2391 writel(c, port->membase + UART01x_DR);
2392 else
2393 writeb(c, port->membase + UART01x_DR);
2394 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2395 cpu_relax();
2396}
2397
2398static void pl011_early_write(struct console *con, const char *s, unsigned n)
2399{
2400 struct earlycon_device *dev = con->data;
2401
2402 uart_console_write(&dev->port, s, n, pl011_putc);
2403}
2404
2405static int __init pl011_early_console_setup(struct earlycon_device *device,
2406 const char *opt)
2407{
2408 if (!device->port.membase)
2409 return -ENODEV;
2410
2411 device->con->write = pl011_early_write;
2412 return 0;
2413}
2414OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2415OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2416
2417#else
2418#define AMBA_CONSOLE NULL
2419#endif
2420
2421static struct uart_driver amba_reg = {
2422 .owner = THIS_MODULE,
2423 .driver_name = "ttyAMA",
2424 .dev_name = "ttyAMA",
2425 .major = SERIAL_AMBA_MAJOR,
2426 .minor = SERIAL_AMBA_MINOR,
2427 .nr = UART_NR,
2428 .cons = AMBA_CONSOLE,
2429};
2430
2431static int pl011_probe_dt_alias(int index, struct device *dev)
2432{
2433 struct device_node *np;
2434 static bool seen_dev_with_alias = false;
2435 static bool seen_dev_without_alias = false;
2436 int ret = index;
2437
2438 if (!IS_ENABLED(CONFIG_OF))
2439 return ret;
2440
2441 np = dev->of_node;
2442 if (!np)
2443 return ret;
2444
2445 ret = of_alias_get_id(np, "serial");
2446 if (ret < 0) {
2447 seen_dev_without_alias = true;
2448 ret = index;
2449 } else {
2450 seen_dev_with_alias = true;
2451 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2452 dev_warn(dev, "requested serial port %d not available.\n", ret);
2453 ret = index;
2454 }
2455 }
2456
2457 if (seen_dev_with_alias && seen_dev_without_alias)
2458 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2459
2460 return ret;
2461}
2462
2463/* unregisters the driver also if no more ports are left */
2464static void pl011_unregister_port(struct uart_amba_port *uap)
2465{
2466 int i;
2467 bool busy = false;
2468
2469 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2470 if (amba_ports[i] == uap)
2471 amba_ports[i] = NULL;
2472 else if (amba_ports[i])
2473 busy = true;
2474 }
2475 pl011_dma_remove(uap);
2476 if (!busy)
2477 uart_unregister_driver(&amba_reg);
2478}
2479
2480static int pl011_find_free_port(void)
2481{
2482 int i;
2483
2484 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2485 if (amba_ports[i] == NULL)
2486 return i;
2487
2488 return -EBUSY;
2489}
2490
2491static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2492 struct resource *mmiobase, int index)
2493{
2494 void __iomem *base;
2495
2496 base = devm_ioremap_resource(dev, mmiobase);
2497 if (IS_ERR(base))
2498 return PTR_ERR(base);
2499
2500 index = pl011_probe_dt_alias(index, dev);
2501
2502 uap->old_cr = 0;
2503 uap->port.dev = dev;
2504 uap->port.mapbase = mmiobase->start;
2505 uap->port.membase = base;
2506 uap->port.fifosize = uap->fifosize;
2507 uap->port.flags = UPF_BOOT_AUTOCONF;
2508 uap->port.line = index;
2509
2510 amba_ports[index] = uap;
2511
2512 return 0;
2513}
2514
2515static int pl011_register_port(struct uart_amba_port *uap)
2516{
2517 int ret;
2518
2519 /* Ensure interrupts from this UART are masked and cleared */
2520 pl011_write(0, uap, REG_IMSC);
2521 pl011_write(0xffff, uap, REG_ICR);
2522
2523 if (!amba_reg.state) {
2524 ret = uart_register_driver(&amba_reg);
2525 if (ret < 0) {
2526 dev_err(uap->port.dev,
2527 "Failed to register AMBA-PL011 driver\n");
2528 return ret;
2529 }
2530 }
2531
2532 ret = uart_add_one_port(&amba_reg, &uap->port);
2533 if (ret)
2534 pl011_unregister_port(uap);
2535
2536 return ret;
2537}
2538
2539static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2540{
2541 struct uart_amba_port *uap;
2542 struct vendor_data *vendor = id->data;
2543 int portnr, ret;
2544
2545 portnr = pl011_find_free_port();
2546 if (portnr < 0)
2547 return portnr;
2548
2549 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2550 GFP_KERNEL);
2551 if (!uap)
2552 return -ENOMEM;
2553
2554 uap->clk = devm_clk_get(&dev->dev, NULL);
2555 if (IS_ERR(uap->clk))
2556 return PTR_ERR(uap->clk);
2557
2558 uap->reg_offset = vendor->reg_offset;
2559 uap->vendor = vendor;
2560 uap->fifosize = vendor->get_fifosize(dev);
2561 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2562 uap->port.irq = dev->irq[0];
2563 uap->port.ops = &amba_pl011_pops;
2564
2565 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2566
2567 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2568 if (ret)
2569 return ret;
2570
2571 amba_set_drvdata(dev, uap);
2572
2573 return pl011_register_port(uap);
2574}
2575
2576static int pl011_remove(struct amba_device *dev)
2577{
2578 struct uart_amba_port *uap = amba_get_drvdata(dev);
2579
2580 uart_remove_one_port(&amba_reg, &uap->port);
2581 pl011_unregister_port(uap);
2582 return 0;
2583}
2584
2585#ifdef CONFIG_PM_SLEEP
2586static int pl011_suspend(struct device *dev)
2587{
2588 struct uart_amba_port *uap = dev_get_drvdata(dev);
2589
2590 if (!uap)
2591 return -EINVAL;
2592
2593 return uart_suspend_port(&amba_reg, &uap->port);
2594}
2595
2596static int pl011_resume(struct device *dev)
2597{
2598 struct uart_amba_port *uap = dev_get_drvdata(dev);
2599
2600 if (!uap)
2601 return -EINVAL;
2602
2603 return uart_resume_port(&amba_reg, &uap->port);
2604}
2605#endif
2606
2607static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2608
2609static int sbsa_uart_probe(struct platform_device *pdev)
2610{
2611 struct uart_amba_port *uap;
2612 struct resource *r;
2613 int portnr, ret;
2614 int baudrate;
2615
2616 /*
2617 * Check the mandatory baud rate parameter in the DT node early
2618 * so that we can easily exit with the error.
2619 */
2620 if (pdev->dev.of_node) {
2621 struct device_node *np = pdev->dev.of_node;
2622
2623 ret = of_property_read_u32(np, "current-speed", &baudrate);
2624 if (ret)
2625 return ret;
2626 } else {
2627 baudrate = 115200;
2628 }
2629
2630 portnr = pl011_find_free_port();
2631 if (portnr < 0)
2632 return portnr;
2633
2634 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2635 GFP_KERNEL);
2636 if (!uap)
2637 return -ENOMEM;
2638
2639 ret = platform_get_irq(pdev, 0);
2640 if (ret < 0) {
2641 if (ret != -EPROBE_DEFER)
2642 dev_err(&pdev->dev, "cannot obtain irq\n");
2643 return ret;
2644 }
2645 uap->port.irq = ret;
2646
2647 uap->reg_offset = vendor_sbsa.reg_offset;
2648 uap->vendor = &vendor_sbsa;
2649 uap->fifosize = 32;
2650 uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM;
2651 uap->port.ops = &sbsa_uart_pops;
2652 uap->fixed_baud = baudrate;
2653
2654 snprintf(uap->type, sizeof(uap->type), "SBSA");
2655
2656 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2657
2658 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2659 if (ret)
2660 return ret;
2661
2662 platform_set_drvdata(pdev, uap);
2663
2664 return pl011_register_port(uap);
2665}
2666
2667static int sbsa_uart_remove(struct platform_device *pdev)
2668{
2669 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2670
2671 uart_remove_one_port(&amba_reg, &uap->port);
2672 pl011_unregister_port(uap);
2673 return 0;
2674}
2675
2676static const struct of_device_id sbsa_uart_of_match[] = {
2677 { .compatible = "arm,sbsa-uart", },
2678 {},
2679};
2680MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2681
2682static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2683 { "ARMH0011", 0 },
2684 {},
2685};
2686MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2687
2688static struct platform_driver arm_sbsa_uart_platform_driver = {
2689 .probe = sbsa_uart_probe,
2690 .remove = sbsa_uart_remove,
2691 .driver = {
2692 .name = "sbsa-uart",
2693 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2694 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2695 },
2696};
2697
2698static struct amba_id pl011_ids[] = {
2699 {
2700 .id = 0x00041011,
2701 .mask = 0x000fffff,
2702 .data = &vendor_arm,
2703 },
2704 {
2705 .id = 0x00380802,
2706 .mask = 0x00ffffff,
2707 .data = &vendor_st,
2708 },
2709 {
2710 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2711 .mask = 0x00ffffff,
2712 .data = &vendor_zte,
2713 },
2714 { 0, 0 },
2715};
2716
2717MODULE_DEVICE_TABLE(amba, pl011_ids);
2718
2719static struct amba_driver pl011_driver = {
2720 .drv = {
2721 .name = "uart-pl011",
2722 .pm = &pl011_dev_pm_ops,
2723 },
2724 .id_table = pl011_ids,
2725 .probe = pl011_probe,
2726 .remove = pl011_remove,
2727};
2728
2729static int __init pl011_init(void)
2730{
2731 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2732
2733 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2734 pr_warn("could not register SBSA UART platform driver\n");
2735 return amba_driver_register(&pl011_driver);
2736}
2737
2738static void __exit pl011_exit(void)
2739{
2740 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2741 amba_driver_unregister(&pl011_driver);
2742}
2743
2744/*
2745 * While this can be a module, if builtin it's most likely the console
2746 * So let's leave module_exit but move module_init to an earlier place
2747 */
2748arch_initcall(pl011_init);
2749module_exit(pl011_exit);
2750
2751MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2752MODULE_DESCRIPTION("ARM AMBA serial port driver");
2753MODULE_LICENSE("GPL");