Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * rtc-ds1305.c -- driver for DS1305 and DS1306 SPI RTC chips
4 *
5 * Copyright (C) 2008 David Brownell
6 */
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/bcd.h>
10#include <linux/slab.h>
11#include <linux/rtc.h>
12#include <linux/workqueue.h>
13
14#include <linux/spi/spi.h>
15#include <linux/spi/ds1305.h>
16#include <linux/module.h>
17
18
19/*
20 * Registers ... mask DS1305_WRITE into register address to write,
21 * otherwise you're reading it. All non-bitmask values are BCD.
22 */
23#define DS1305_WRITE 0x80
24
25
26/* RTC date/time ... the main special cases are that we:
27 * - Need fancy "hours" encoding in 12hour mode
28 * - Don't rely on the "day-of-week" field (or tm_wday)
29 * - Are a 21st-century clock (2000 <= year < 2100)
30 */
31#define DS1305_RTC_LEN 7 /* bytes for RTC regs */
32
33#define DS1305_SEC 0x00 /* register addresses */
34#define DS1305_MIN 0x01
35#define DS1305_HOUR 0x02
36# define DS1305_HR_12 0x40 /* set == 12 hr mode */
37# define DS1305_HR_PM 0x20 /* set == PM (12hr mode) */
38#define DS1305_WDAY 0x03
39#define DS1305_MDAY 0x04
40#define DS1305_MON 0x05
41#define DS1305_YEAR 0x06
42
43
44/* The two alarms have only sec/min/hour/wday fields (ALM_LEN).
45 * DS1305_ALM_DISABLE disables a match field (some combos are bad).
46 *
47 * NOTE that since we don't use WDAY, we limit ourselves to alarms
48 * only one day into the future (vs potentially up to a week).
49 *
50 * NOTE ALSO that while we could generate once-a-second IRQs (UIE), we
51 * don't currently support them. We'd either need to do it only when
52 * no alarm is pending (not the standard model), or to use the second
53 * alarm (implying that this is a DS1305 not DS1306, *and* that either
54 * it's wired up a second IRQ we know, or that INTCN is set)
55 */
56#define DS1305_ALM_LEN 4 /* bytes for ALM regs */
57#define DS1305_ALM_DISABLE 0x80
58
59#define DS1305_ALM0(r) (0x07 + (r)) /* register addresses */
60#define DS1305_ALM1(r) (0x0b + (r))
61
62
63/* three control registers */
64#define DS1305_CONTROL_LEN 3 /* bytes of control regs */
65
66#define DS1305_CONTROL 0x0f /* register addresses */
67# define DS1305_nEOSC 0x80 /* low enables oscillator */
68# define DS1305_WP 0x40 /* write protect */
69# define DS1305_INTCN 0x04 /* clear == only int0 used */
70# define DS1306_1HZ 0x04 /* enable 1Hz output */
71# define DS1305_AEI1 0x02 /* enable ALM1 IRQ */
72# define DS1305_AEI0 0x01 /* enable ALM0 IRQ */
73#define DS1305_STATUS 0x10
74/* status has just AEIx bits, mirrored as IRQFx */
75#define DS1305_TRICKLE 0x11
76/* trickle bits are defined in <linux/spi/ds1305.h> */
77
78/* a bunch of NVRAM */
79#define DS1305_NVRAM_LEN 96 /* bytes of NVRAM */
80
81#define DS1305_NVRAM 0x20 /* register addresses */
82
83
84struct ds1305 {
85 struct spi_device *spi;
86 struct rtc_device *rtc;
87
88 struct work_struct work;
89
90 unsigned long flags;
91#define FLAG_EXITING 0
92
93 bool hr12;
94 u8 ctrl[DS1305_CONTROL_LEN];
95};
96
97
98/*----------------------------------------------------------------------*/
99
100/*
101 * Utilities ... tolerate 12-hour AM/PM notation in case of non-Linux
102 * software (like a bootloader) which may require it.
103 */
104
105static unsigned bcd2hour(u8 bcd)
106{
107 if (bcd & DS1305_HR_12) {
108 unsigned hour = 0;
109
110 bcd &= ~DS1305_HR_12;
111 if (bcd & DS1305_HR_PM) {
112 hour = 12;
113 bcd &= ~DS1305_HR_PM;
114 }
115 hour += bcd2bin(bcd);
116 return hour - 1;
117 }
118 return bcd2bin(bcd);
119}
120
121static u8 hour2bcd(bool hr12, int hour)
122{
123 if (hr12) {
124 hour++;
125 if (hour <= 12)
126 return DS1305_HR_12 | bin2bcd(hour);
127 hour -= 12;
128 return DS1305_HR_12 | DS1305_HR_PM | bin2bcd(hour);
129 }
130 return bin2bcd(hour);
131}
132
133/*----------------------------------------------------------------------*/
134
135/*
136 * Interface to RTC framework
137 */
138
139static int ds1305_alarm_irq_enable(struct device *dev, unsigned int enabled)
140{
141 struct ds1305 *ds1305 = dev_get_drvdata(dev);
142 u8 buf[2];
143 long err = -EINVAL;
144
145 buf[0] = DS1305_WRITE | DS1305_CONTROL;
146 buf[1] = ds1305->ctrl[0];
147
148 if (enabled) {
149 if (ds1305->ctrl[0] & DS1305_AEI0)
150 goto done;
151 buf[1] |= DS1305_AEI0;
152 } else {
153 if (!(buf[1] & DS1305_AEI0))
154 goto done;
155 buf[1] &= ~DS1305_AEI0;
156 }
157 err = spi_write_then_read(ds1305->spi, buf, sizeof(buf), NULL, 0);
158 if (err >= 0)
159 ds1305->ctrl[0] = buf[1];
160done:
161 return err;
162
163}
164
165
166/*
167 * Get/set of date and time is pretty normal.
168 */
169
170static int ds1305_get_time(struct device *dev, struct rtc_time *time)
171{
172 struct ds1305 *ds1305 = dev_get_drvdata(dev);
173 u8 addr = DS1305_SEC;
174 u8 buf[DS1305_RTC_LEN];
175 int status;
176
177 /* Use write-then-read to get all the date/time registers
178 * since dma from stack is nonportable
179 */
180 status = spi_write_then_read(ds1305->spi, &addr, sizeof(addr),
181 buf, sizeof(buf));
182 if (status < 0)
183 return status;
184
185 dev_vdbg(dev, "%s: %3ph, %4ph\n", "read", &buf[0], &buf[3]);
186
187 /* Decode the registers */
188 time->tm_sec = bcd2bin(buf[DS1305_SEC]);
189 time->tm_min = bcd2bin(buf[DS1305_MIN]);
190 time->tm_hour = bcd2hour(buf[DS1305_HOUR]);
191 time->tm_wday = buf[DS1305_WDAY] - 1;
192 time->tm_mday = bcd2bin(buf[DS1305_MDAY]);
193 time->tm_mon = bcd2bin(buf[DS1305_MON]) - 1;
194 time->tm_year = bcd2bin(buf[DS1305_YEAR]) + 100;
195
196 dev_vdbg(dev, "%s secs=%d, mins=%d, "
197 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
198 "read", time->tm_sec, time->tm_min,
199 time->tm_hour, time->tm_mday,
200 time->tm_mon, time->tm_year, time->tm_wday);
201
202 return 0;
203}
204
205static int ds1305_set_time(struct device *dev, struct rtc_time *time)
206{
207 struct ds1305 *ds1305 = dev_get_drvdata(dev);
208 u8 buf[1 + DS1305_RTC_LEN];
209 u8 *bp = buf;
210
211 dev_vdbg(dev, "%s secs=%d, mins=%d, "
212 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
213 "write", time->tm_sec, time->tm_min,
214 time->tm_hour, time->tm_mday,
215 time->tm_mon, time->tm_year, time->tm_wday);
216
217 /* Write registers starting at the first time/date address. */
218 *bp++ = DS1305_WRITE | DS1305_SEC;
219
220 *bp++ = bin2bcd(time->tm_sec);
221 *bp++ = bin2bcd(time->tm_min);
222 *bp++ = hour2bcd(ds1305->hr12, time->tm_hour);
223 *bp++ = (time->tm_wday < 7) ? (time->tm_wday + 1) : 1;
224 *bp++ = bin2bcd(time->tm_mday);
225 *bp++ = bin2bcd(time->tm_mon + 1);
226 *bp++ = bin2bcd(time->tm_year - 100);
227
228 dev_dbg(dev, "%s: %3ph, %4ph\n", "write", &buf[1], &buf[4]);
229
230 /* use write-then-read since dma from stack is nonportable */
231 return spi_write_then_read(ds1305->spi, buf, sizeof(buf),
232 NULL, 0);
233}
234
235/*
236 * Get/set of alarm is a bit funky:
237 *
238 * - First there's the inherent raciness of getting the (partitioned)
239 * status of an alarm that could trigger while we're reading parts
240 * of that status.
241 *
242 * - Second there's its limited range (we could increase it a bit by
243 * relying on WDAY), which means it will easily roll over.
244 *
245 * - Third there's the choice of two alarms and alarm signals.
246 * Here we use ALM0 and expect that nINT0 (open drain) is used;
247 * that's the only real option for DS1306 runtime alarms, and is
248 * natural on DS1305.
249 *
250 * - Fourth, there's also ALM1, and a second interrupt signal:
251 * + On DS1305 ALM1 uses nINT1 (when INTCN=1) else nINT0;
252 * + On DS1306 ALM1 only uses INT1 (an active high pulse)
253 * and it won't work when VCC1 is active.
254 *
255 * So to be most general, we should probably set both alarms to the
256 * same value, letting ALM1 be the wakeup event source on DS1306
257 * and handling several wiring options on DS1305.
258 *
259 * - Fifth, we support the polled mode (as well as possible; why not?)
260 * even when no interrupt line is wired to an IRQ.
261 */
262
263/*
264 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
265 */
266static int ds1305_get_alarm(struct device *dev, struct rtc_wkalrm *alm)
267{
268 struct ds1305 *ds1305 = dev_get_drvdata(dev);
269 struct spi_device *spi = ds1305->spi;
270 u8 addr;
271 int status;
272 u8 buf[DS1305_ALM_LEN];
273
274 /* Refresh control register cache BEFORE reading ALM0 registers,
275 * since reading alarm registers acks any pending IRQ. That
276 * makes returning "pending" status a bit of a lie, but that bit
277 * of EFI status is at best fragile anyway (given IRQ handlers).
278 */
279 addr = DS1305_CONTROL;
280 status = spi_write_then_read(spi, &addr, sizeof(addr),
281 ds1305->ctrl, sizeof(ds1305->ctrl));
282 if (status < 0)
283 return status;
284
285 alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0);
286 alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0);
287
288 /* get and check ALM0 registers */
289 addr = DS1305_ALM0(DS1305_SEC);
290 status = spi_write_then_read(spi, &addr, sizeof(addr),
291 buf, sizeof(buf));
292 if (status < 0)
293 return status;
294
295 dev_vdbg(dev, "%s: %02x %02x %02x %02x\n",
296 "alm0 read", buf[DS1305_SEC], buf[DS1305_MIN],
297 buf[DS1305_HOUR], buf[DS1305_WDAY]);
298
299 if ((DS1305_ALM_DISABLE & buf[DS1305_SEC])
300 || (DS1305_ALM_DISABLE & buf[DS1305_MIN])
301 || (DS1305_ALM_DISABLE & buf[DS1305_HOUR]))
302 return -EIO;
303
304 /* Stuff these values into alm->time and let RTC framework code
305 * fill in the rest ... and also handle rollover to tomorrow when
306 * that's needed.
307 */
308 alm->time.tm_sec = bcd2bin(buf[DS1305_SEC]);
309 alm->time.tm_min = bcd2bin(buf[DS1305_MIN]);
310 alm->time.tm_hour = bcd2hour(buf[DS1305_HOUR]);
311
312 return 0;
313}
314
315/*
316 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
317 */
318static int ds1305_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
319{
320 struct ds1305 *ds1305 = dev_get_drvdata(dev);
321 struct spi_device *spi = ds1305->spi;
322 unsigned long now, later;
323 struct rtc_time tm;
324 int status;
325 u8 buf[1 + DS1305_ALM_LEN];
326
327 /* convert desired alarm to time_t */
328 later = rtc_tm_to_time64(&alm->time);
329
330 /* Read current time as time_t */
331 status = ds1305_get_time(dev, &tm);
332 if (status < 0)
333 return status;
334 now = rtc_tm_to_time64(&tm);
335
336 /* make sure alarm fires within the next 24 hours */
337 if (later <= now)
338 return -EINVAL;
339 if ((later - now) > ds1305->rtc->alarm_offset_max)
340 return -ERANGE;
341
342 /* disable alarm if needed */
343 if (ds1305->ctrl[0] & DS1305_AEI0) {
344 ds1305->ctrl[0] &= ~DS1305_AEI0;
345
346 buf[0] = DS1305_WRITE | DS1305_CONTROL;
347 buf[1] = ds1305->ctrl[0];
348 status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
349 if (status < 0)
350 return status;
351 }
352
353 /* write alarm */
354 buf[0] = DS1305_WRITE | DS1305_ALM0(DS1305_SEC);
355 buf[1 + DS1305_SEC] = bin2bcd(alm->time.tm_sec);
356 buf[1 + DS1305_MIN] = bin2bcd(alm->time.tm_min);
357 buf[1 + DS1305_HOUR] = hour2bcd(ds1305->hr12, alm->time.tm_hour);
358 buf[1 + DS1305_WDAY] = DS1305_ALM_DISABLE;
359
360 dev_dbg(dev, "%s: %02x %02x %02x %02x\n",
361 "alm0 write", buf[1 + DS1305_SEC], buf[1 + DS1305_MIN],
362 buf[1 + DS1305_HOUR], buf[1 + DS1305_WDAY]);
363
364 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
365 if (status < 0)
366 return status;
367
368 /* enable alarm if requested */
369 if (alm->enabled) {
370 ds1305->ctrl[0] |= DS1305_AEI0;
371
372 buf[0] = DS1305_WRITE | DS1305_CONTROL;
373 buf[1] = ds1305->ctrl[0];
374 status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
375 }
376
377 return status;
378}
379
380#ifdef CONFIG_PROC_FS
381
382static int ds1305_proc(struct device *dev, struct seq_file *seq)
383{
384 struct ds1305 *ds1305 = dev_get_drvdata(dev);
385 char *diodes = "no";
386 char *resistors = "";
387
388 /* ctrl[2] is treated as read-only; no locking needed */
389 if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) {
390 switch (ds1305->ctrl[2] & 0x0c) {
391 case DS1305_TRICKLE_DS2:
392 diodes = "2 diodes, ";
393 break;
394 case DS1305_TRICKLE_DS1:
395 diodes = "1 diode, ";
396 break;
397 default:
398 goto done;
399 }
400 switch (ds1305->ctrl[2] & 0x03) {
401 case DS1305_TRICKLE_2K:
402 resistors = "2k Ohm";
403 break;
404 case DS1305_TRICKLE_4K:
405 resistors = "4k Ohm";
406 break;
407 case DS1305_TRICKLE_8K:
408 resistors = "8k Ohm";
409 break;
410 default:
411 diodes = "no";
412 break;
413 }
414 }
415
416done:
417 seq_printf(seq, "trickle_charge\t: %s%s\n", diodes, resistors);
418
419 return 0;
420}
421
422#else
423#define ds1305_proc NULL
424#endif
425
426static const struct rtc_class_ops ds1305_ops = {
427 .read_time = ds1305_get_time,
428 .set_time = ds1305_set_time,
429 .read_alarm = ds1305_get_alarm,
430 .set_alarm = ds1305_set_alarm,
431 .proc = ds1305_proc,
432 .alarm_irq_enable = ds1305_alarm_irq_enable,
433};
434
435static void ds1305_work(struct work_struct *work)
436{
437 struct ds1305 *ds1305 = container_of(work, struct ds1305, work);
438 struct spi_device *spi = ds1305->spi;
439 u8 buf[3];
440 int status;
441
442 /* lock to protect ds1305->ctrl */
443 rtc_lock(ds1305->rtc);
444
445 /* Disable the IRQ, and clear its status ... for now, we "know"
446 * that if more than one alarm is active, they're in sync.
447 * Note that reading ALM data registers also clears IRQ status.
448 */
449 ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0);
450 ds1305->ctrl[1] = 0;
451
452 buf[0] = DS1305_WRITE | DS1305_CONTROL;
453 buf[1] = ds1305->ctrl[0];
454 buf[2] = 0;
455
456 status = spi_write_then_read(spi, buf, sizeof(buf),
457 NULL, 0);
458 if (status < 0)
459 dev_dbg(&spi->dev, "clear irq --> %d\n", status);
460
461 rtc_unlock(ds1305->rtc);
462
463 if (!test_bit(FLAG_EXITING, &ds1305->flags))
464 enable_irq(spi->irq);
465
466 rtc_update_irq(ds1305->rtc, 1, RTC_AF | RTC_IRQF);
467}
468
469/*
470 * This "real" IRQ handler hands off to a workqueue mostly to allow
471 * mutex locking for ds1305->ctrl ... unlike I2C, we could issue async
472 * I/O requests in IRQ context (to clear the IRQ status).
473 */
474static irqreturn_t ds1305_irq(int irq, void *p)
475{
476 struct ds1305 *ds1305 = p;
477
478 disable_irq(irq);
479 schedule_work(&ds1305->work);
480 return IRQ_HANDLED;
481}
482
483/*----------------------------------------------------------------------*/
484
485/*
486 * Interface for NVRAM
487 */
488
489static void msg_init(struct spi_message *m, struct spi_transfer *x,
490 u8 *addr, size_t count, char *tx, char *rx)
491{
492 spi_message_init(m);
493 memset(x, 0, 2 * sizeof(*x));
494
495 x->tx_buf = addr;
496 x->len = 1;
497 spi_message_add_tail(x, m);
498
499 x++;
500
501 x->tx_buf = tx;
502 x->rx_buf = rx;
503 x->len = count;
504 spi_message_add_tail(x, m);
505}
506
507static int ds1305_nvram_read(void *priv, unsigned int off, void *buf,
508 size_t count)
509{
510 struct ds1305 *ds1305 = priv;
511 struct spi_device *spi = ds1305->spi;
512 u8 addr;
513 struct spi_message m;
514 struct spi_transfer x[2];
515
516 addr = DS1305_NVRAM + off;
517 msg_init(&m, x, &addr, count, NULL, buf);
518
519 return spi_sync(spi, &m);
520}
521
522static int ds1305_nvram_write(void *priv, unsigned int off, void *buf,
523 size_t count)
524{
525 struct ds1305 *ds1305 = priv;
526 struct spi_device *spi = ds1305->spi;
527 u8 addr;
528 struct spi_message m;
529 struct spi_transfer x[2];
530
531 addr = (DS1305_WRITE | DS1305_NVRAM) + off;
532 msg_init(&m, x, &addr, count, buf, NULL);
533
534 return spi_sync(spi, &m);
535}
536
537/*----------------------------------------------------------------------*/
538
539/*
540 * Interface to SPI stack
541 */
542
543static int ds1305_probe(struct spi_device *spi)
544{
545 struct ds1305 *ds1305;
546 int status;
547 u8 addr, value;
548 struct ds1305_platform_data *pdata = dev_get_platdata(&spi->dev);
549 bool write_ctrl = false;
550 struct nvmem_config ds1305_nvmem_cfg = {
551 .name = "ds1305_nvram",
552 .word_size = 1,
553 .stride = 1,
554 .size = DS1305_NVRAM_LEN,
555 .reg_read = ds1305_nvram_read,
556 .reg_write = ds1305_nvram_write,
557 };
558
559 /* Sanity check board setup data. This may be hooked up
560 * in 3wire mode, but we don't care. Note that unless
561 * there's an inverter in place, this needs SPI_CS_HIGH!
562 */
563 if ((spi->bits_per_word && spi->bits_per_word != 8)
564 || (spi->max_speed_hz > 2000000)
565 || !(spi->mode & SPI_CPHA))
566 return -EINVAL;
567
568 /* set up driver data */
569 ds1305 = devm_kzalloc(&spi->dev, sizeof(*ds1305), GFP_KERNEL);
570 if (!ds1305)
571 return -ENOMEM;
572 ds1305->spi = spi;
573 spi_set_drvdata(spi, ds1305);
574
575 /* read and cache control registers */
576 addr = DS1305_CONTROL;
577 status = spi_write_then_read(spi, &addr, sizeof(addr),
578 ds1305->ctrl, sizeof(ds1305->ctrl));
579 if (status < 0) {
580 dev_dbg(&spi->dev, "can't %s, %d\n",
581 "read", status);
582 return status;
583 }
584
585 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl);
586
587 /* Sanity check register values ... partially compensating for the
588 * fact that SPI has no device handshake. A pullup on MISO would
589 * make these tests fail; but not all systems will have one. If
590 * some register is neither 0x00 nor 0xff, a chip is likely there.
591 */
592 if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) {
593 dev_dbg(&spi->dev, "RTC chip is not present\n");
594 return -ENODEV;
595 }
596 if (ds1305->ctrl[2] == 0)
597 dev_dbg(&spi->dev, "chip may not be present\n");
598
599 /* enable writes if needed ... if we were paranoid it would
600 * make sense to enable them only when absolutely necessary.
601 */
602 if (ds1305->ctrl[0] & DS1305_WP) {
603 u8 buf[2];
604
605 ds1305->ctrl[0] &= ~DS1305_WP;
606
607 buf[0] = DS1305_WRITE | DS1305_CONTROL;
608 buf[1] = ds1305->ctrl[0];
609 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
610
611 dev_dbg(&spi->dev, "clear WP --> %d\n", status);
612 if (status < 0)
613 return status;
614 }
615
616 /* on DS1305, maybe start oscillator; like most low power
617 * oscillators, it may take a second to stabilize
618 */
619 if (ds1305->ctrl[0] & DS1305_nEOSC) {
620 ds1305->ctrl[0] &= ~DS1305_nEOSC;
621 write_ctrl = true;
622 dev_warn(&spi->dev, "SET TIME!\n");
623 }
624
625 /* ack any pending IRQs */
626 if (ds1305->ctrl[1]) {
627 ds1305->ctrl[1] = 0;
628 write_ctrl = true;
629 }
630
631 /* this may need one-time (re)init */
632 if (pdata) {
633 /* maybe enable trickle charge */
634 if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) {
635 ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC
636 | pdata->trickle;
637 write_ctrl = true;
638 }
639
640 /* on DS1306, configure 1 Hz signal */
641 if (pdata->is_ds1306) {
642 if (pdata->en_1hz) {
643 if (!(ds1305->ctrl[0] & DS1306_1HZ)) {
644 ds1305->ctrl[0] |= DS1306_1HZ;
645 write_ctrl = true;
646 }
647 } else {
648 if (ds1305->ctrl[0] & DS1306_1HZ) {
649 ds1305->ctrl[0] &= ~DS1306_1HZ;
650 write_ctrl = true;
651 }
652 }
653 }
654 }
655
656 if (write_ctrl) {
657 u8 buf[4];
658
659 buf[0] = DS1305_WRITE | DS1305_CONTROL;
660 buf[1] = ds1305->ctrl[0];
661 buf[2] = ds1305->ctrl[1];
662 buf[3] = ds1305->ctrl[2];
663 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
664 if (status < 0) {
665 dev_dbg(&spi->dev, "can't %s, %d\n",
666 "write", status);
667 return status;
668 }
669
670 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl);
671 }
672
673 /* see if non-Linux software set up AM/PM mode */
674 addr = DS1305_HOUR;
675 status = spi_write_then_read(spi, &addr, sizeof(addr),
676 &value, sizeof(value));
677 if (status < 0) {
678 dev_dbg(&spi->dev, "read HOUR --> %d\n", status);
679 return status;
680 }
681
682 ds1305->hr12 = (DS1305_HR_12 & value) != 0;
683 if (ds1305->hr12)
684 dev_dbg(&spi->dev, "AM/PM\n");
685
686 /* register RTC ... from here on, ds1305->ctrl needs locking */
687 ds1305->rtc = devm_rtc_allocate_device(&spi->dev);
688 if (IS_ERR(ds1305->rtc))
689 return PTR_ERR(ds1305->rtc);
690
691 ds1305->rtc->ops = &ds1305_ops;
692 ds1305->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
693 ds1305->rtc->range_max = RTC_TIMESTAMP_END_2099;
694 ds1305->rtc->alarm_offset_max = 24 * 60 * 60;
695
696 ds1305_nvmem_cfg.priv = ds1305;
697 status = devm_rtc_register_device(ds1305->rtc);
698 if (status)
699 return status;
700
701 devm_rtc_nvmem_register(ds1305->rtc, &ds1305_nvmem_cfg);
702
703 /* Maybe set up alarm IRQ; be ready to handle it triggering right
704 * away. NOTE that we don't share this. The signal is active low,
705 * and we can't ack it before a SPI message delay. We temporarily
706 * disable the IRQ until it's acked, which lets us work with more
707 * IRQ trigger modes (not all IRQ controllers can do falling edge).
708 */
709 if (spi->irq) {
710 INIT_WORK(&ds1305->work, ds1305_work);
711 status = devm_request_irq(&spi->dev, spi->irq, ds1305_irq,
712 0, dev_name(&ds1305->rtc->dev), ds1305);
713 if (status < 0) {
714 dev_err(&spi->dev, "request_irq %d --> %d\n",
715 spi->irq, status);
716 } else {
717 device_set_wakeup_capable(&spi->dev, 1);
718 }
719 }
720
721 return 0;
722}
723
724static void ds1305_remove(struct spi_device *spi)
725{
726 struct ds1305 *ds1305 = spi_get_drvdata(spi);
727
728 /* carefully shut down irq and workqueue, if present */
729 if (spi->irq) {
730 set_bit(FLAG_EXITING, &ds1305->flags);
731 devm_free_irq(&spi->dev, spi->irq, ds1305);
732 cancel_work_sync(&ds1305->work);
733 }
734}
735
736static struct spi_driver ds1305_driver = {
737 .driver.name = "rtc-ds1305",
738 .probe = ds1305_probe,
739 .remove = ds1305_remove,
740 /* REVISIT add suspend/resume */
741};
742
743module_spi_driver(ds1305_driver);
744
745MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips");
746MODULE_LICENSE("GPL");
747MODULE_ALIAS("spi:rtc-ds1305");
1/*
2 * rtc-ds1305.c -- driver for DS1305 and DS1306 SPI RTC chips
3 *
4 * Copyright (C) 2008 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/bcd.h>
14#include <linux/slab.h>
15#include <linux/rtc.h>
16#include <linux/workqueue.h>
17
18#include <linux/spi/spi.h>
19#include <linux/spi/ds1305.h>
20#include <linux/module.h>
21
22
23/*
24 * Registers ... mask DS1305_WRITE into register address to write,
25 * otherwise you're reading it. All non-bitmask values are BCD.
26 */
27#define DS1305_WRITE 0x80
28
29
30/* RTC date/time ... the main special cases are that we:
31 * - Need fancy "hours" encoding in 12hour mode
32 * - Don't rely on the "day-of-week" field (or tm_wday)
33 * - Are a 21st-century clock (2000 <= year < 2100)
34 */
35#define DS1305_RTC_LEN 7 /* bytes for RTC regs */
36
37#define DS1305_SEC 0x00 /* register addresses */
38#define DS1305_MIN 0x01
39#define DS1305_HOUR 0x02
40# define DS1305_HR_12 0x40 /* set == 12 hr mode */
41# define DS1305_HR_PM 0x20 /* set == PM (12hr mode) */
42#define DS1305_WDAY 0x03
43#define DS1305_MDAY 0x04
44#define DS1305_MON 0x05
45#define DS1305_YEAR 0x06
46
47
48/* The two alarms have only sec/min/hour/wday fields (ALM_LEN).
49 * DS1305_ALM_DISABLE disables a match field (some combos are bad).
50 *
51 * NOTE that since we don't use WDAY, we limit ourselves to alarms
52 * only one day into the future (vs potentially up to a week).
53 *
54 * NOTE ALSO that while we could generate once-a-second IRQs (UIE), we
55 * don't currently support them. We'd either need to do it only when
56 * no alarm is pending (not the standard model), or to use the second
57 * alarm (implying that this is a DS1305 not DS1306, *and* that either
58 * it's wired up a second IRQ we know, or that INTCN is set)
59 */
60#define DS1305_ALM_LEN 4 /* bytes for ALM regs */
61#define DS1305_ALM_DISABLE 0x80
62
63#define DS1305_ALM0(r) (0x07 + (r)) /* register addresses */
64#define DS1305_ALM1(r) (0x0b + (r))
65
66
67/* three control registers */
68#define DS1305_CONTROL_LEN 3 /* bytes of control regs */
69
70#define DS1305_CONTROL 0x0f /* register addresses */
71# define DS1305_nEOSC 0x80 /* low enables oscillator */
72# define DS1305_WP 0x40 /* write protect */
73# define DS1305_INTCN 0x04 /* clear == only int0 used */
74# define DS1306_1HZ 0x04 /* enable 1Hz output */
75# define DS1305_AEI1 0x02 /* enable ALM1 IRQ */
76# define DS1305_AEI0 0x01 /* enable ALM0 IRQ */
77#define DS1305_STATUS 0x10
78/* status has just AEIx bits, mirrored as IRQFx */
79#define DS1305_TRICKLE 0x11
80/* trickle bits are defined in <linux/spi/ds1305.h> */
81
82/* a bunch of NVRAM */
83#define DS1305_NVRAM_LEN 96 /* bytes of NVRAM */
84
85#define DS1305_NVRAM 0x20 /* register addresses */
86
87
88struct ds1305 {
89 struct spi_device *spi;
90 struct rtc_device *rtc;
91
92 struct work_struct work;
93
94 unsigned long flags;
95#define FLAG_EXITING 0
96
97 bool hr12;
98 u8 ctrl[DS1305_CONTROL_LEN];
99};
100
101
102/*----------------------------------------------------------------------*/
103
104/*
105 * Utilities ... tolerate 12-hour AM/PM notation in case of non-Linux
106 * software (like a bootloader) which may require it.
107 */
108
109static unsigned bcd2hour(u8 bcd)
110{
111 if (bcd & DS1305_HR_12) {
112 unsigned hour = 0;
113
114 bcd &= ~DS1305_HR_12;
115 if (bcd & DS1305_HR_PM) {
116 hour = 12;
117 bcd &= ~DS1305_HR_PM;
118 }
119 hour += bcd2bin(bcd);
120 return hour - 1;
121 }
122 return bcd2bin(bcd);
123}
124
125static u8 hour2bcd(bool hr12, int hour)
126{
127 if (hr12) {
128 hour++;
129 if (hour <= 12)
130 return DS1305_HR_12 | bin2bcd(hour);
131 hour -= 12;
132 return DS1305_HR_12 | DS1305_HR_PM | bin2bcd(hour);
133 }
134 return bin2bcd(hour);
135}
136
137/*----------------------------------------------------------------------*/
138
139/*
140 * Interface to RTC framework
141 */
142
143static int ds1305_alarm_irq_enable(struct device *dev, unsigned int enabled)
144{
145 struct ds1305 *ds1305 = dev_get_drvdata(dev);
146 u8 buf[2];
147 long err = -EINVAL;
148
149 buf[0] = DS1305_WRITE | DS1305_CONTROL;
150 buf[1] = ds1305->ctrl[0];
151
152 if (enabled) {
153 if (ds1305->ctrl[0] & DS1305_AEI0)
154 goto done;
155 buf[1] |= DS1305_AEI0;
156 } else {
157 if (!(buf[1] & DS1305_AEI0))
158 goto done;
159 buf[1] &= ~DS1305_AEI0;
160 }
161 err = spi_write_then_read(ds1305->spi, buf, sizeof(buf), NULL, 0);
162 if (err >= 0)
163 ds1305->ctrl[0] = buf[1];
164done:
165 return err;
166
167}
168
169
170/*
171 * Get/set of date and time is pretty normal.
172 */
173
174static int ds1305_get_time(struct device *dev, struct rtc_time *time)
175{
176 struct ds1305 *ds1305 = dev_get_drvdata(dev);
177 u8 addr = DS1305_SEC;
178 u8 buf[DS1305_RTC_LEN];
179 int status;
180
181 /* Use write-then-read to get all the date/time registers
182 * since dma from stack is nonportable
183 */
184 status = spi_write_then_read(ds1305->spi, &addr, sizeof(addr),
185 buf, sizeof(buf));
186 if (status < 0)
187 return status;
188
189 dev_vdbg(dev, "%s: %3ph, %4ph\n", "read", &buf[0], &buf[3]);
190
191 /* Decode the registers */
192 time->tm_sec = bcd2bin(buf[DS1305_SEC]);
193 time->tm_min = bcd2bin(buf[DS1305_MIN]);
194 time->tm_hour = bcd2hour(buf[DS1305_HOUR]);
195 time->tm_wday = buf[DS1305_WDAY] - 1;
196 time->tm_mday = bcd2bin(buf[DS1305_MDAY]);
197 time->tm_mon = bcd2bin(buf[DS1305_MON]) - 1;
198 time->tm_year = bcd2bin(buf[DS1305_YEAR]) + 100;
199
200 dev_vdbg(dev, "%s secs=%d, mins=%d, "
201 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
202 "read", time->tm_sec, time->tm_min,
203 time->tm_hour, time->tm_mday,
204 time->tm_mon, time->tm_year, time->tm_wday);
205
206 /* Time may not be set */
207 return rtc_valid_tm(time);
208}
209
210static int ds1305_set_time(struct device *dev, struct rtc_time *time)
211{
212 struct ds1305 *ds1305 = dev_get_drvdata(dev);
213 u8 buf[1 + DS1305_RTC_LEN];
214 u8 *bp = buf;
215
216 dev_vdbg(dev, "%s secs=%d, mins=%d, "
217 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
218 "write", time->tm_sec, time->tm_min,
219 time->tm_hour, time->tm_mday,
220 time->tm_mon, time->tm_year, time->tm_wday);
221
222 /* Write registers starting at the first time/date address. */
223 *bp++ = DS1305_WRITE | DS1305_SEC;
224
225 *bp++ = bin2bcd(time->tm_sec);
226 *bp++ = bin2bcd(time->tm_min);
227 *bp++ = hour2bcd(ds1305->hr12, time->tm_hour);
228 *bp++ = (time->tm_wday < 7) ? (time->tm_wday + 1) : 1;
229 *bp++ = bin2bcd(time->tm_mday);
230 *bp++ = bin2bcd(time->tm_mon + 1);
231 *bp++ = bin2bcd(time->tm_year - 100);
232
233 dev_dbg(dev, "%s: %3ph, %4ph\n", "write", &buf[1], &buf[4]);
234
235 /* use write-then-read since dma from stack is nonportable */
236 return spi_write_then_read(ds1305->spi, buf, sizeof(buf),
237 NULL, 0);
238}
239
240/*
241 * Get/set of alarm is a bit funky:
242 *
243 * - First there's the inherent raciness of getting the (partitioned)
244 * status of an alarm that could trigger while we're reading parts
245 * of that status.
246 *
247 * - Second there's its limited range (we could increase it a bit by
248 * relying on WDAY), which means it will easily roll over.
249 *
250 * - Third there's the choice of two alarms and alarm signals.
251 * Here we use ALM0 and expect that nINT0 (open drain) is used;
252 * that's the only real option for DS1306 runtime alarms, and is
253 * natural on DS1305.
254 *
255 * - Fourth, there's also ALM1, and a second interrupt signal:
256 * + On DS1305 ALM1 uses nINT1 (when INTCN=1) else nINT0;
257 * + On DS1306 ALM1 only uses INT1 (an active high pulse)
258 * and it won't work when VCC1 is active.
259 *
260 * So to be most general, we should probably set both alarms to the
261 * same value, letting ALM1 be the wakeup event source on DS1306
262 * and handling several wiring options on DS1305.
263 *
264 * - Fifth, we support the polled mode (as well as possible; why not?)
265 * even when no interrupt line is wired to an IRQ.
266 */
267
268/*
269 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
270 */
271static int ds1305_get_alarm(struct device *dev, struct rtc_wkalrm *alm)
272{
273 struct ds1305 *ds1305 = dev_get_drvdata(dev);
274 struct spi_device *spi = ds1305->spi;
275 u8 addr;
276 int status;
277 u8 buf[DS1305_ALM_LEN];
278
279 /* Refresh control register cache BEFORE reading ALM0 registers,
280 * since reading alarm registers acks any pending IRQ. That
281 * makes returning "pending" status a bit of a lie, but that bit
282 * of EFI status is at best fragile anyway (given IRQ handlers).
283 */
284 addr = DS1305_CONTROL;
285 status = spi_write_then_read(spi, &addr, sizeof(addr),
286 ds1305->ctrl, sizeof(ds1305->ctrl));
287 if (status < 0)
288 return status;
289
290 alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0);
291 alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0);
292
293 /* get and check ALM0 registers */
294 addr = DS1305_ALM0(DS1305_SEC);
295 status = spi_write_then_read(spi, &addr, sizeof(addr),
296 buf, sizeof(buf));
297 if (status < 0)
298 return status;
299
300 dev_vdbg(dev, "%s: %02x %02x %02x %02x\n",
301 "alm0 read", buf[DS1305_SEC], buf[DS1305_MIN],
302 buf[DS1305_HOUR], buf[DS1305_WDAY]);
303
304 if ((DS1305_ALM_DISABLE & buf[DS1305_SEC])
305 || (DS1305_ALM_DISABLE & buf[DS1305_MIN])
306 || (DS1305_ALM_DISABLE & buf[DS1305_HOUR]))
307 return -EIO;
308
309 /* Stuff these values into alm->time and let RTC framework code
310 * fill in the rest ... and also handle rollover to tomorrow when
311 * that's needed.
312 */
313 alm->time.tm_sec = bcd2bin(buf[DS1305_SEC]);
314 alm->time.tm_min = bcd2bin(buf[DS1305_MIN]);
315 alm->time.tm_hour = bcd2hour(buf[DS1305_HOUR]);
316
317 return 0;
318}
319
320/*
321 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
322 */
323static int ds1305_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
324{
325 struct ds1305 *ds1305 = dev_get_drvdata(dev);
326 struct spi_device *spi = ds1305->spi;
327 unsigned long now, later;
328 struct rtc_time tm;
329 int status;
330 u8 buf[1 + DS1305_ALM_LEN];
331
332 /* convert desired alarm to time_t */
333 status = rtc_tm_to_time(&alm->time, &later);
334 if (status < 0)
335 return status;
336
337 /* Read current time as time_t */
338 status = ds1305_get_time(dev, &tm);
339 if (status < 0)
340 return status;
341 status = rtc_tm_to_time(&tm, &now);
342 if (status < 0)
343 return status;
344
345 /* make sure alarm fires within the next 24 hours */
346 if (later <= now)
347 return -EINVAL;
348 if ((later - now) > 24 * 60 * 60)
349 return -EDOM;
350
351 /* disable alarm if needed */
352 if (ds1305->ctrl[0] & DS1305_AEI0) {
353 ds1305->ctrl[0] &= ~DS1305_AEI0;
354
355 buf[0] = DS1305_WRITE | DS1305_CONTROL;
356 buf[1] = ds1305->ctrl[0];
357 status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
358 if (status < 0)
359 return status;
360 }
361
362 /* write alarm */
363 buf[0] = DS1305_WRITE | DS1305_ALM0(DS1305_SEC);
364 buf[1 + DS1305_SEC] = bin2bcd(alm->time.tm_sec);
365 buf[1 + DS1305_MIN] = bin2bcd(alm->time.tm_min);
366 buf[1 + DS1305_HOUR] = hour2bcd(ds1305->hr12, alm->time.tm_hour);
367 buf[1 + DS1305_WDAY] = DS1305_ALM_DISABLE;
368
369 dev_dbg(dev, "%s: %02x %02x %02x %02x\n",
370 "alm0 write", buf[1 + DS1305_SEC], buf[1 + DS1305_MIN],
371 buf[1 + DS1305_HOUR], buf[1 + DS1305_WDAY]);
372
373 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
374 if (status < 0)
375 return status;
376
377 /* enable alarm if requested */
378 if (alm->enabled) {
379 ds1305->ctrl[0] |= DS1305_AEI0;
380
381 buf[0] = DS1305_WRITE | DS1305_CONTROL;
382 buf[1] = ds1305->ctrl[0];
383 status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
384 }
385
386 return status;
387}
388
389#ifdef CONFIG_PROC_FS
390
391static int ds1305_proc(struct device *dev, struct seq_file *seq)
392{
393 struct ds1305 *ds1305 = dev_get_drvdata(dev);
394 char *diodes = "no";
395 char *resistors = "";
396
397 /* ctrl[2] is treated as read-only; no locking needed */
398 if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) {
399 switch (ds1305->ctrl[2] & 0x0c) {
400 case DS1305_TRICKLE_DS2:
401 diodes = "2 diodes, ";
402 break;
403 case DS1305_TRICKLE_DS1:
404 diodes = "1 diode, ";
405 break;
406 default:
407 goto done;
408 }
409 switch (ds1305->ctrl[2] & 0x03) {
410 case DS1305_TRICKLE_2K:
411 resistors = "2k Ohm";
412 break;
413 case DS1305_TRICKLE_4K:
414 resistors = "4k Ohm";
415 break;
416 case DS1305_TRICKLE_8K:
417 resistors = "8k Ohm";
418 break;
419 default:
420 diodes = "no";
421 break;
422 }
423 }
424
425done:
426 seq_printf(seq, "trickle_charge\t: %s%s\n", diodes, resistors);
427
428 return 0;
429}
430
431#else
432#define ds1305_proc NULL
433#endif
434
435static const struct rtc_class_ops ds1305_ops = {
436 .read_time = ds1305_get_time,
437 .set_time = ds1305_set_time,
438 .read_alarm = ds1305_get_alarm,
439 .set_alarm = ds1305_set_alarm,
440 .proc = ds1305_proc,
441 .alarm_irq_enable = ds1305_alarm_irq_enable,
442};
443
444static void ds1305_work(struct work_struct *work)
445{
446 struct ds1305 *ds1305 = container_of(work, struct ds1305, work);
447 struct mutex *lock = &ds1305->rtc->ops_lock;
448 struct spi_device *spi = ds1305->spi;
449 u8 buf[3];
450 int status;
451
452 /* lock to protect ds1305->ctrl */
453 mutex_lock(lock);
454
455 /* Disable the IRQ, and clear its status ... for now, we "know"
456 * that if more than one alarm is active, they're in sync.
457 * Note that reading ALM data registers also clears IRQ status.
458 */
459 ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0);
460 ds1305->ctrl[1] = 0;
461
462 buf[0] = DS1305_WRITE | DS1305_CONTROL;
463 buf[1] = ds1305->ctrl[0];
464 buf[2] = 0;
465
466 status = spi_write_then_read(spi, buf, sizeof(buf),
467 NULL, 0);
468 if (status < 0)
469 dev_dbg(&spi->dev, "clear irq --> %d\n", status);
470
471 mutex_unlock(lock);
472
473 if (!test_bit(FLAG_EXITING, &ds1305->flags))
474 enable_irq(spi->irq);
475
476 rtc_update_irq(ds1305->rtc, 1, RTC_AF | RTC_IRQF);
477}
478
479/*
480 * This "real" IRQ handler hands off to a workqueue mostly to allow
481 * mutex locking for ds1305->ctrl ... unlike I2C, we could issue async
482 * I/O requests in IRQ context (to clear the IRQ status).
483 */
484static irqreturn_t ds1305_irq(int irq, void *p)
485{
486 struct ds1305 *ds1305 = p;
487
488 disable_irq(irq);
489 schedule_work(&ds1305->work);
490 return IRQ_HANDLED;
491}
492
493/*----------------------------------------------------------------------*/
494
495/*
496 * Interface for NVRAM
497 */
498
499static void msg_init(struct spi_message *m, struct spi_transfer *x,
500 u8 *addr, size_t count, char *tx, char *rx)
501{
502 spi_message_init(m);
503 memset(x, 0, 2 * sizeof(*x));
504
505 x->tx_buf = addr;
506 x->len = 1;
507 spi_message_add_tail(x, m);
508
509 x++;
510
511 x->tx_buf = tx;
512 x->rx_buf = rx;
513 x->len = count;
514 spi_message_add_tail(x, m);
515}
516
517static ssize_t
518ds1305_nvram_read(struct file *filp, struct kobject *kobj,
519 struct bin_attribute *attr,
520 char *buf, loff_t off, size_t count)
521{
522 struct spi_device *spi;
523 u8 addr;
524 struct spi_message m;
525 struct spi_transfer x[2];
526 int status;
527
528 spi = to_spi_device(kobj_to_dev(kobj));
529
530 addr = DS1305_NVRAM + off;
531 msg_init(&m, x, &addr, count, NULL, buf);
532
533 status = spi_sync(spi, &m);
534 if (status < 0)
535 dev_err(&spi->dev, "nvram %s error %d\n", "read", status);
536 return (status < 0) ? status : count;
537}
538
539static ssize_t
540ds1305_nvram_write(struct file *filp, struct kobject *kobj,
541 struct bin_attribute *attr,
542 char *buf, loff_t off, size_t count)
543{
544 struct spi_device *spi;
545 u8 addr;
546 struct spi_message m;
547 struct spi_transfer x[2];
548 int status;
549
550 spi = to_spi_device(kobj_to_dev(kobj));
551
552 addr = (DS1305_WRITE | DS1305_NVRAM) + off;
553 msg_init(&m, x, &addr, count, buf, NULL);
554
555 status = spi_sync(spi, &m);
556 if (status < 0)
557 dev_err(&spi->dev, "nvram %s error %d\n", "write", status);
558 return (status < 0) ? status : count;
559}
560
561static struct bin_attribute nvram = {
562 .attr.name = "nvram",
563 .attr.mode = S_IRUGO | S_IWUSR,
564 .read = ds1305_nvram_read,
565 .write = ds1305_nvram_write,
566 .size = DS1305_NVRAM_LEN,
567};
568
569/*----------------------------------------------------------------------*/
570
571/*
572 * Interface to SPI stack
573 */
574
575static int ds1305_probe(struct spi_device *spi)
576{
577 struct ds1305 *ds1305;
578 int status;
579 u8 addr, value;
580 struct ds1305_platform_data *pdata = dev_get_platdata(&spi->dev);
581 bool write_ctrl = false;
582
583 /* Sanity check board setup data. This may be hooked up
584 * in 3wire mode, but we don't care. Note that unless
585 * there's an inverter in place, this needs SPI_CS_HIGH!
586 */
587 if ((spi->bits_per_word && spi->bits_per_word != 8)
588 || (spi->max_speed_hz > 2000000)
589 || !(spi->mode & SPI_CPHA))
590 return -EINVAL;
591
592 /* set up driver data */
593 ds1305 = devm_kzalloc(&spi->dev, sizeof(*ds1305), GFP_KERNEL);
594 if (!ds1305)
595 return -ENOMEM;
596 ds1305->spi = spi;
597 spi_set_drvdata(spi, ds1305);
598
599 /* read and cache control registers */
600 addr = DS1305_CONTROL;
601 status = spi_write_then_read(spi, &addr, sizeof(addr),
602 ds1305->ctrl, sizeof(ds1305->ctrl));
603 if (status < 0) {
604 dev_dbg(&spi->dev, "can't %s, %d\n",
605 "read", status);
606 return status;
607 }
608
609 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl);
610
611 /* Sanity check register values ... partially compensating for the
612 * fact that SPI has no device handshake. A pullup on MISO would
613 * make these tests fail; but not all systems will have one. If
614 * some register is neither 0x00 nor 0xff, a chip is likely there.
615 */
616 if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) {
617 dev_dbg(&spi->dev, "RTC chip is not present\n");
618 return -ENODEV;
619 }
620 if (ds1305->ctrl[2] == 0)
621 dev_dbg(&spi->dev, "chip may not be present\n");
622
623 /* enable writes if needed ... if we were paranoid it would
624 * make sense to enable them only when absolutely necessary.
625 */
626 if (ds1305->ctrl[0] & DS1305_WP) {
627 u8 buf[2];
628
629 ds1305->ctrl[0] &= ~DS1305_WP;
630
631 buf[0] = DS1305_WRITE | DS1305_CONTROL;
632 buf[1] = ds1305->ctrl[0];
633 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
634
635 dev_dbg(&spi->dev, "clear WP --> %d\n", status);
636 if (status < 0)
637 return status;
638 }
639
640 /* on DS1305, maybe start oscillator; like most low power
641 * oscillators, it may take a second to stabilize
642 */
643 if (ds1305->ctrl[0] & DS1305_nEOSC) {
644 ds1305->ctrl[0] &= ~DS1305_nEOSC;
645 write_ctrl = true;
646 dev_warn(&spi->dev, "SET TIME!\n");
647 }
648
649 /* ack any pending IRQs */
650 if (ds1305->ctrl[1]) {
651 ds1305->ctrl[1] = 0;
652 write_ctrl = true;
653 }
654
655 /* this may need one-time (re)init */
656 if (pdata) {
657 /* maybe enable trickle charge */
658 if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) {
659 ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC
660 | pdata->trickle;
661 write_ctrl = true;
662 }
663
664 /* on DS1306, configure 1 Hz signal */
665 if (pdata->is_ds1306) {
666 if (pdata->en_1hz) {
667 if (!(ds1305->ctrl[0] & DS1306_1HZ)) {
668 ds1305->ctrl[0] |= DS1306_1HZ;
669 write_ctrl = true;
670 }
671 } else {
672 if (ds1305->ctrl[0] & DS1306_1HZ) {
673 ds1305->ctrl[0] &= ~DS1306_1HZ;
674 write_ctrl = true;
675 }
676 }
677 }
678 }
679
680 if (write_ctrl) {
681 u8 buf[4];
682
683 buf[0] = DS1305_WRITE | DS1305_CONTROL;
684 buf[1] = ds1305->ctrl[0];
685 buf[2] = ds1305->ctrl[1];
686 buf[3] = ds1305->ctrl[2];
687 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
688 if (status < 0) {
689 dev_dbg(&spi->dev, "can't %s, %d\n",
690 "write", status);
691 return status;
692 }
693
694 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl);
695 }
696
697 /* see if non-Linux software set up AM/PM mode */
698 addr = DS1305_HOUR;
699 status = spi_write_then_read(spi, &addr, sizeof(addr),
700 &value, sizeof(value));
701 if (status < 0) {
702 dev_dbg(&spi->dev, "read HOUR --> %d\n", status);
703 return status;
704 }
705
706 ds1305->hr12 = (DS1305_HR_12 & value) != 0;
707 if (ds1305->hr12)
708 dev_dbg(&spi->dev, "AM/PM\n");
709
710 /* register RTC ... from here on, ds1305->ctrl needs locking */
711 ds1305->rtc = devm_rtc_device_register(&spi->dev, "ds1305",
712 &ds1305_ops, THIS_MODULE);
713 if (IS_ERR(ds1305->rtc)) {
714 status = PTR_ERR(ds1305->rtc);
715 dev_dbg(&spi->dev, "register rtc --> %d\n", status);
716 return status;
717 }
718
719 /* Maybe set up alarm IRQ; be ready to handle it triggering right
720 * away. NOTE that we don't share this. The signal is active low,
721 * and we can't ack it before a SPI message delay. We temporarily
722 * disable the IRQ until it's acked, which lets us work with more
723 * IRQ trigger modes (not all IRQ controllers can do falling edge).
724 */
725 if (spi->irq) {
726 INIT_WORK(&ds1305->work, ds1305_work);
727 status = devm_request_irq(&spi->dev, spi->irq, ds1305_irq,
728 0, dev_name(&ds1305->rtc->dev), ds1305);
729 if (status < 0) {
730 dev_err(&spi->dev, "request_irq %d --> %d\n",
731 spi->irq, status);
732 } else {
733 device_set_wakeup_capable(&spi->dev, 1);
734 }
735 }
736
737 /* export NVRAM */
738 status = sysfs_create_bin_file(&spi->dev.kobj, &nvram);
739 if (status < 0) {
740 dev_err(&spi->dev, "register nvram --> %d\n", status);
741 }
742
743 return 0;
744}
745
746static int ds1305_remove(struct spi_device *spi)
747{
748 struct ds1305 *ds1305 = spi_get_drvdata(spi);
749
750 sysfs_remove_bin_file(&spi->dev.kobj, &nvram);
751
752 /* carefully shut down irq and workqueue, if present */
753 if (spi->irq) {
754 set_bit(FLAG_EXITING, &ds1305->flags);
755 devm_free_irq(&spi->dev, spi->irq, ds1305);
756 cancel_work_sync(&ds1305->work);
757 }
758
759 return 0;
760}
761
762static struct spi_driver ds1305_driver = {
763 .driver.name = "rtc-ds1305",
764 .probe = ds1305_probe,
765 .remove = ds1305_remove,
766 /* REVISIT add suspend/resume */
767};
768
769module_spi_driver(ds1305_driver);
770
771MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips");
772MODULE_LICENSE("GPL");
773MODULE_ALIAS("spi:rtc-ds1305");