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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * RTC Driver for X-Powers AC100
4 *
5 * Copyright (c) 2016 Chen-Yu Tsai
6 *
7 * Chen-Yu Tsai <wens@csie.org>
8 */
9
10#include <linux/bcd.h>
11#include <linux/clk-provider.h>
12#include <linux/device.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/mfd/ac100.h>
16#include <linux/module.h>
17#include <linux/mutex.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include <linux/rtc.h>
22#include <linux/types.h>
23
24/* Control register */
25#define AC100_RTC_CTRL_24HOUR BIT(0)
26
27/* Clock output register bits */
28#define AC100_CLKOUT_PRE_DIV_SHIFT 5
29#define AC100_CLKOUT_PRE_DIV_WIDTH 3
30#define AC100_CLKOUT_MUX_SHIFT 4
31#define AC100_CLKOUT_MUX_WIDTH 1
32#define AC100_CLKOUT_DIV_SHIFT 1
33#define AC100_CLKOUT_DIV_WIDTH 3
34#define AC100_CLKOUT_EN BIT(0)
35
36/* RTC */
37#define AC100_RTC_SEC_MASK GENMASK(6, 0)
38#define AC100_RTC_MIN_MASK GENMASK(6, 0)
39#define AC100_RTC_HOU_MASK GENMASK(5, 0)
40#define AC100_RTC_WEE_MASK GENMASK(2, 0)
41#define AC100_RTC_DAY_MASK GENMASK(5, 0)
42#define AC100_RTC_MON_MASK GENMASK(4, 0)
43#define AC100_RTC_YEA_MASK GENMASK(7, 0)
44#define AC100_RTC_YEA_LEAP BIT(15)
45#define AC100_RTC_UPD_TRIGGER BIT(15)
46
47/* Alarm (wall clock) */
48#define AC100_ALM_INT_ENABLE BIT(0)
49
50#define AC100_ALM_SEC_MASK GENMASK(6, 0)
51#define AC100_ALM_MIN_MASK GENMASK(6, 0)
52#define AC100_ALM_HOU_MASK GENMASK(5, 0)
53#define AC100_ALM_WEE_MASK GENMASK(2, 0)
54#define AC100_ALM_DAY_MASK GENMASK(5, 0)
55#define AC100_ALM_MON_MASK GENMASK(4, 0)
56#define AC100_ALM_YEA_MASK GENMASK(7, 0)
57#define AC100_ALM_ENABLE_FLAG BIT(15)
58#define AC100_ALM_UPD_TRIGGER BIT(15)
59
60/*
61 * The year parameter passed to the driver is usually an offset relative to
62 * the year 1900. This macro is used to convert this offset to another one
63 * relative to the minimum year allowed by the hardware.
64 *
65 * The year range is 1970 - 2069. This range is selected to match Allwinner's
66 * driver.
67 */
68#define AC100_YEAR_MIN 1970
69#define AC100_YEAR_MAX 2069
70#define AC100_YEAR_OFF (AC100_YEAR_MIN - 1900)
71
72struct ac100_clkout {
73 struct clk_hw hw;
74 struct regmap *regmap;
75 u8 offset;
76};
77
78#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw)
79
80#define AC100_RTC_32K_NAME "ac100-rtc-32k"
81#define AC100_RTC_32K_RATE 32768
82#define AC100_CLKOUT_NUM 3
83
84static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = {
85 "ac100-cko1-rtc",
86 "ac100-cko2-rtc",
87 "ac100-cko3-rtc",
88};
89
90struct ac100_rtc_dev {
91 struct rtc_device *rtc;
92 struct device *dev;
93 struct regmap *regmap;
94 int irq;
95 unsigned long alarm;
96
97 struct clk_hw *rtc_32k_clk;
98 struct ac100_clkout clks[AC100_CLKOUT_NUM];
99 struct clk_hw_onecell_data *clk_data;
100};
101
102/*
103 * Clock controls for 3 clock output pins
104 */
105
106static const struct clk_div_table ac100_clkout_prediv[] = {
107 { .val = 0, .div = 1 },
108 { .val = 1, .div = 2 },
109 { .val = 2, .div = 4 },
110 { .val = 3, .div = 8 },
111 { .val = 4, .div = 16 },
112 { .val = 5, .div = 32 },
113 { .val = 6, .div = 64 },
114 { .val = 7, .div = 122 },
115 { },
116};
117
118/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */
119static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,
120 unsigned long prate)
121{
122 struct ac100_clkout *clk = to_ac100_clkout(hw);
123 unsigned int reg, div;
124
125 regmap_read(clk->regmap, clk->offset, ®);
126
127 /* Handle pre-divider first */
128 if (prate != AC100_RTC_32K_RATE) {
129 div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &
130 ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);
131 prate = divider_recalc_rate(hw, prate, div,
132 ac100_clkout_prediv, 0,
133 AC100_CLKOUT_PRE_DIV_WIDTH);
134 }
135
136 div = (reg >> AC100_CLKOUT_DIV_SHIFT) &
137 (BIT(AC100_CLKOUT_DIV_WIDTH) - 1);
138 return divider_recalc_rate(hw, prate, div, NULL,
139 CLK_DIVIDER_POWER_OF_TWO,
140 AC100_CLKOUT_DIV_WIDTH);
141}
142
143static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
144 unsigned long prate)
145{
146 unsigned long best_rate = 0, tmp_rate, tmp_prate;
147 int i;
148
149 if (prate == AC100_RTC_32K_RATE)
150 return divider_round_rate(hw, rate, &prate, NULL,
151 AC100_CLKOUT_DIV_WIDTH,
152 CLK_DIVIDER_POWER_OF_TWO);
153
154 for (i = 0; ac100_clkout_prediv[i].div; i++) {
155 tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);
156 tmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL,
157 AC100_CLKOUT_DIV_WIDTH,
158 CLK_DIVIDER_POWER_OF_TWO);
159
160 if (tmp_rate > rate)
161 continue;
162 if (rate - tmp_rate < best_rate - tmp_rate)
163 best_rate = tmp_rate;
164 }
165
166 return best_rate;
167}
168
169static int ac100_clkout_determine_rate(struct clk_hw *hw,
170 struct clk_rate_request *req)
171{
172 struct clk_hw *best_parent;
173 unsigned long best = 0;
174 int i, num_parents = clk_hw_get_num_parents(hw);
175
176 for (i = 0; i < num_parents; i++) {
177 struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
178 unsigned long tmp, prate;
179
180 /*
181 * The clock has two parents, one is a fixed clock which is
182 * internally registered by the ac100 driver. The other parent
183 * is a clock from the codec side of the chip, which we
184 * properly declare and reference in the devicetree and is
185 * not implemented in any driver right now.
186 * If the clock core looks for the parent of that second
187 * missing clock, it can't find one that is registered and
188 * returns NULL.
189 * So we end up in a situation where clk_hw_get_num_parents
190 * returns the amount of clocks we can be parented to, but
191 * clk_hw_get_parent_by_index will not return the orphan
192 * clocks.
193 * Thus we need to check if the parent exists before
194 * we get the parent rate, so we could use the RTC
195 * without waiting for the codec to be supported.
196 */
197 if (!parent)
198 continue;
199
200 prate = clk_hw_get_rate(parent);
201
202 tmp = ac100_clkout_round_rate(hw, req->rate, prate);
203
204 if (tmp > req->rate)
205 continue;
206 if (req->rate - tmp < req->rate - best) {
207 best = tmp;
208 best_parent = parent;
209 }
210 }
211
212 if (!best)
213 return -EINVAL;
214
215 req->best_parent_hw = best_parent;
216 req->best_parent_rate = best;
217 req->rate = best;
218
219 return 0;
220}
221
222static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
223 unsigned long prate)
224{
225 struct ac100_clkout *clk = to_ac100_clkout(hw);
226 int div = 0, pre_div = 0;
227
228 do {
229 div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div,
230 prate, NULL, AC100_CLKOUT_DIV_WIDTH,
231 CLK_DIVIDER_POWER_OF_TWO);
232 if (div >= 0)
233 break;
234 } while (prate != AC100_RTC_32K_RATE &&
235 ac100_clkout_prediv[++pre_div].div);
236
237 if (div < 0)
238 return div;
239
240 pre_div = ac100_clkout_prediv[pre_div].val;
241
242 regmap_update_bits(clk->regmap, clk->offset,
243 ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT |
244 ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT,
245 (div - 1) << AC100_CLKOUT_DIV_SHIFT |
246 (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT);
247
248 return 0;
249}
250
251static int ac100_clkout_prepare(struct clk_hw *hw)
252{
253 struct ac100_clkout *clk = to_ac100_clkout(hw);
254
255 return regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN,
256 AC100_CLKOUT_EN);
257}
258
259static void ac100_clkout_unprepare(struct clk_hw *hw)
260{
261 struct ac100_clkout *clk = to_ac100_clkout(hw);
262
263 regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0);
264}
265
266static int ac100_clkout_is_prepared(struct clk_hw *hw)
267{
268 struct ac100_clkout *clk = to_ac100_clkout(hw);
269 unsigned int reg;
270
271 regmap_read(clk->regmap, clk->offset, ®);
272
273 return reg & AC100_CLKOUT_EN;
274}
275
276static u8 ac100_clkout_get_parent(struct clk_hw *hw)
277{
278 struct ac100_clkout *clk = to_ac100_clkout(hw);
279 unsigned int reg;
280
281 regmap_read(clk->regmap, clk->offset, ®);
282
283 return (reg >> AC100_CLKOUT_MUX_SHIFT) & 0x1;
284}
285
286static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index)
287{
288 struct ac100_clkout *clk = to_ac100_clkout(hw);
289
290 return regmap_update_bits(clk->regmap, clk->offset,
291 BIT(AC100_CLKOUT_MUX_SHIFT),
292 index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0);
293}
294
295static const struct clk_ops ac100_clkout_ops = {
296 .prepare = ac100_clkout_prepare,
297 .unprepare = ac100_clkout_unprepare,
298 .is_prepared = ac100_clkout_is_prepared,
299 .recalc_rate = ac100_clkout_recalc_rate,
300 .determine_rate = ac100_clkout_determine_rate,
301 .get_parent = ac100_clkout_get_parent,
302 .set_parent = ac100_clkout_set_parent,
303 .set_rate = ac100_clkout_set_rate,
304};
305
306static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip)
307{
308 struct device_node *np = chip->dev->of_node;
309 const char *parents[2] = {AC100_RTC_32K_NAME};
310 int i, ret;
311
312 chip->clk_data = devm_kzalloc(chip->dev,
313 struct_size(chip->clk_data, hws,
314 AC100_CLKOUT_NUM),
315 GFP_KERNEL);
316 if (!chip->clk_data)
317 return -ENOMEM;
318
319 chip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev,
320 AC100_RTC_32K_NAME,
321 NULL, 0,
322 AC100_RTC_32K_RATE);
323 if (IS_ERR(chip->rtc_32k_clk)) {
324 ret = PTR_ERR(chip->rtc_32k_clk);
325 dev_err(chip->dev, "Failed to register RTC-32k clock: %d\n",
326 ret);
327 return ret;
328 }
329
330 parents[1] = of_clk_get_parent_name(np, 0);
331 if (!parents[1]) {
332 dev_err(chip->dev, "Failed to get ADDA 4M clock\n");
333 return -EINVAL;
334 }
335
336 for (i = 0; i < AC100_CLKOUT_NUM; i++) {
337 struct ac100_clkout *clk = &chip->clks[i];
338 struct clk_init_data init = {
339 .name = ac100_clkout_names[i],
340 .ops = &ac100_clkout_ops,
341 .parent_names = parents,
342 .num_parents = ARRAY_SIZE(parents),
343 .flags = 0,
344 };
345
346 of_property_read_string_index(np, "clock-output-names",
347 i, &init.name);
348 clk->regmap = chip->regmap;
349 clk->offset = AC100_CLKOUT_CTRL1 + i;
350 clk->hw.init = &init;
351
352 ret = devm_clk_hw_register(chip->dev, &clk->hw);
353 if (ret) {
354 dev_err(chip->dev, "Failed to register clk '%s': %d\n",
355 init.name, ret);
356 goto err_unregister_rtc_32k;
357 }
358
359 chip->clk_data->hws[i] = &clk->hw;
360 }
361
362 chip->clk_data->num = i;
363 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data);
364 if (ret)
365 goto err_unregister_rtc_32k;
366
367 return 0;
368
369err_unregister_rtc_32k:
370 clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);
371
372 return ret;
373}
374
375static void ac100_rtc_unregister_clks(struct ac100_rtc_dev *chip)
376{
377 of_clk_del_provider(chip->dev->of_node);
378 clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);
379}
380
381/*
382 * RTC related bits
383 */
384static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm)
385{
386 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
387 struct regmap *regmap = chip->regmap;
388 u16 reg[7];
389 int ret;
390
391 ret = regmap_bulk_read(regmap, AC100_RTC_SEC, reg, 7);
392 if (ret)
393 return ret;
394
395 rtc_tm->tm_sec = bcd2bin(reg[0] & AC100_RTC_SEC_MASK);
396 rtc_tm->tm_min = bcd2bin(reg[1] & AC100_RTC_MIN_MASK);
397 rtc_tm->tm_hour = bcd2bin(reg[2] & AC100_RTC_HOU_MASK);
398 rtc_tm->tm_wday = bcd2bin(reg[3] & AC100_RTC_WEE_MASK);
399 rtc_tm->tm_mday = bcd2bin(reg[4] & AC100_RTC_DAY_MASK);
400 rtc_tm->tm_mon = bcd2bin(reg[5] & AC100_RTC_MON_MASK) - 1;
401 rtc_tm->tm_year = bcd2bin(reg[6] & AC100_RTC_YEA_MASK) +
402 AC100_YEAR_OFF;
403
404 return 0;
405}
406
407static int ac100_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
408{
409 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
410 struct regmap *regmap = chip->regmap;
411 int year;
412 u16 reg[8];
413
414 /* our RTC has a limited year range... */
415 year = rtc_tm->tm_year - AC100_YEAR_OFF;
416 if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
417 dev_err(dev, "rtc only supports year in range %d - %d\n",
418 AC100_YEAR_MIN, AC100_YEAR_MAX);
419 return -EINVAL;
420 }
421
422 /* convert to BCD */
423 reg[0] = bin2bcd(rtc_tm->tm_sec) & AC100_RTC_SEC_MASK;
424 reg[1] = bin2bcd(rtc_tm->tm_min) & AC100_RTC_MIN_MASK;
425 reg[2] = bin2bcd(rtc_tm->tm_hour) & AC100_RTC_HOU_MASK;
426 reg[3] = bin2bcd(rtc_tm->tm_wday) & AC100_RTC_WEE_MASK;
427 reg[4] = bin2bcd(rtc_tm->tm_mday) & AC100_RTC_DAY_MASK;
428 reg[5] = bin2bcd(rtc_tm->tm_mon + 1) & AC100_RTC_MON_MASK;
429 reg[6] = bin2bcd(year) & AC100_RTC_YEA_MASK;
430 /* trigger write */
431 reg[7] = AC100_RTC_UPD_TRIGGER;
432
433 /* Is it a leap year? */
434 if (is_leap_year(year + AC100_YEAR_OFF + 1900))
435 reg[6] |= AC100_RTC_YEA_LEAP;
436
437 return regmap_bulk_write(regmap, AC100_RTC_SEC, reg, 8);
438}
439
440static int ac100_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
441{
442 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
443 struct regmap *regmap = chip->regmap;
444 unsigned int val;
445
446 val = en ? AC100_ALM_INT_ENABLE : 0;
447
448 return regmap_write(regmap, AC100_ALM_INT_ENA, val);
449}
450
451static int ac100_rtc_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
452{
453 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
454 struct regmap *regmap = chip->regmap;
455 struct rtc_time *alrm_tm = &alrm->time;
456 u16 reg[7];
457 unsigned int val;
458 int ret;
459
460 ret = regmap_read(regmap, AC100_ALM_INT_ENA, &val);
461 if (ret)
462 return ret;
463
464 alrm->enabled = !!(val & AC100_ALM_INT_ENABLE);
465
466 ret = regmap_bulk_read(regmap, AC100_ALM_SEC, reg, 7);
467 if (ret)
468 return ret;
469
470 alrm_tm->tm_sec = bcd2bin(reg[0] & AC100_ALM_SEC_MASK);
471 alrm_tm->tm_min = bcd2bin(reg[1] & AC100_ALM_MIN_MASK);
472 alrm_tm->tm_hour = bcd2bin(reg[2] & AC100_ALM_HOU_MASK);
473 alrm_tm->tm_wday = bcd2bin(reg[3] & AC100_ALM_WEE_MASK);
474 alrm_tm->tm_mday = bcd2bin(reg[4] & AC100_ALM_DAY_MASK);
475 alrm_tm->tm_mon = bcd2bin(reg[5] & AC100_ALM_MON_MASK) - 1;
476 alrm_tm->tm_year = bcd2bin(reg[6] & AC100_ALM_YEA_MASK) +
477 AC100_YEAR_OFF;
478
479 return 0;
480}
481
482static int ac100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
483{
484 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
485 struct regmap *regmap = chip->regmap;
486 struct rtc_time *alrm_tm = &alrm->time;
487 u16 reg[8];
488 int year;
489 int ret;
490
491 /* our alarm has a limited year range... */
492 year = alrm_tm->tm_year - AC100_YEAR_OFF;
493 if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
494 dev_err(dev, "alarm only supports year in range %d - %d\n",
495 AC100_YEAR_MIN, AC100_YEAR_MAX);
496 return -EINVAL;
497 }
498
499 /* convert to BCD */
500 reg[0] = (bin2bcd(alrm_tm->tm_sec) & AC100_ALM_SEC_MASK) |
501 AC100_ALM_ENABLE_FLAG;
502 reg[1] = (bin2bcd(alrm_tm->tm_min) & AC100_ALM_MIN_MASK) |
503 AC100_ALM_ENABLE_FLAG;
504 reg[2] = (bin2bcd(alrm_tm->tm_hour) & AC100_ALM_HOU_MASK) |
505 AC100_ALM_ENABLE_FLAG;
506 /* Do not enable weekday alarm */
507 reg[3] = bin2bcd(alrm_tm->tm_wday) & AC100_ALM_WEE_MASK;
508 reg[4] = (bin2bcd(alrm_tm->tm_mday) & AC100_ALM_DAY_MASK) |
509 AC100_ALM_ENABLE_FLAG;
510 reg[5] = (bin2bcd(alrm_tm->tm_mon + 1) & AC100_ALM_MON_MASK) |
511 AC100_ALM_ENABLE_FLAG;
512 reg[6] = (bin2bcd(year) & AC100_ALM_YEA_MASK) |
513 AC100_ALM_ENABLE_FLAG;
514 /* trigger write */
515 reg[7] = AC100_ALM_UPD_TRIGGER;
516
517 ret = regmap_bulk_write(regmap, AC100_ALM_SEC, reg, 8);
518 if (ret)
519 return ret;
520
521 return ac100_rtc_alarm_irq_enable(dev, alrm->enabled);
522}
523
524static irqreturn_t ac100_rtc_irq(int irq, void *data)
525{
526 struct ac100_rtc_dev *chip = data;
527 struct regmap *regmap = chip->regmap;
528 unsigned int val = 0;
529 int ret;
530
531 rtc_lock(chip->rtc);
532
533 /* read status */
534 ret = regmap_read(regmap, AC100_ALM_INT_STA, &val);
535 if (ret)
536 goto out;
537
538 if (val & AC100_ALM_INT_ENABLE) {
539 /* signal rtc framework */
540 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
541
542 /* clear status */
543 ret = regmap_write(regmap, AC100_ALM_INT_STA, val);
544 if (ret)
545 goto out;
546
547 /* disable interrupt */
548 ret = ac100_rtc_alarm_irq_enable(chip->dev, 0);
549 if (ret)
550 goto out;
551 }
552
553out:
554 rtc_unlock(chip->rtc);
555 return IRQ_HANDLED;
556}
557
558static const struct rtc_class_ops ac100_rtc_ops = {
559 .read_time = ac100_rtc_get_time,
560 .set_time = ac100_rtc_set_time,
561 .read_alarm = ac100_rtc_get_alarm,
562 .set_alarm = ac100_rtc_set_alarm,
563 .alarm_irq_enable = ac100_rtc_alarm_irq_enable,
564};
565
566static int ac100_rtc_probe(struct platform_device *pdev)
567{
568 struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
569 struct ac100_rtc_dev *chip;
570 int ret;
571
572 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
573 if (!chip)
574 return -ENOMEM;
575
576 platform_set_drvdata(pdev, chip);
577 chip->dev = &pdev->dev;
578 chip->regmap = ac100->regmap;
579
580 chip->irq = platform_get_irq(pdev, 0);
581 if (chip->irq < 0)
582 return chip->irq;
583
584 chip->rtc = devm_rtc_allocate_device(&pdev->dev);
585 if (IS_ERR(chip->rtc))
586 return PTR_ERR(chip->rtc);
587
588 chip->rtc->ops = &ac100_rtc_ops;
589
590 ret = devm_request_threaded_irq(&pdev->dev, chip->irq, NULL,
591 ac100_rtc_irq,
592 IRQF_SHARED | IRQF_ONESHOT,
593 dev_name(&pdev->dev), chip);
594 if (ret) {
595 dev_err(&pdev->dev, "Could not request IRQ\n");
596 return ret;
597 }
598
599 /* always use 24 hour mode */
600 regmap_write_bits(chip->regmap, AC100_RTC_CTRL, AC100_RTC_CTRL_24HOUR,
601 AC100_RTC_CTRL_24HOUR);
602
603 /* disable counter alarm interrupt */
604 regmap_write(chip->regmap, AC100_ALM_INT_ENA, 0);
605
606 /* clear counter alarm pending interrupts */
607 regmap_write(chip->regmap, AC100_ALM_INT_STA, AC100_ALM_INT_ENABLE);
608
609 ret = ac100_rtc_register_clks(chip);
610 if (ret)
611 return ret;
612
613 return devm_rtc_register_device(chip->rtc);
614}
615
616static void ac100_rtc_remove(struct platform_device *pdev)
617{
618 struct ac100_rtc_dev *chip = platform_get_drvdata(pdev);
619
620 ac100_rtc_unregister_clks(chip);
621}
622
623static const struct of_device_id ac100_rtc_match[] = {
624 { .compatible = "x-powers,ac100-rtc" },
625 { },
626};
627MODULE_DEVICE_TABLE(of, ac100_rtc_match);
628
629static struct platform_driver ac100_rtc_driver = {
630 .probe = ac100_rtc_probe,
631 .remove_new = ac100_rtc_remove,
632 .driver = {
633 .name = "ac100-rtc",
634 .of_match_table = of_match_ptr(ac100_rtc_match),
635 },
636};
637module_platform_driver(ac100_rtc_driver);
638
639MODULE_DESCRIPTION("X-Powers AC100 RTC driver");
640MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
641MODULE_LICENSE("GPL v2");
1/*
2 * RTC Driver for X-Powers AC100
3 *
4 * Copyright (c) 2016 Chen-Yu Tsai
5 *
6 * Chen-Yu Tsai <wens@csie.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 */
17
18#include <linux/bcd.h>
19#include <linux/clk-provider.h>
20#include <linux/device.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/mfd/ac100.h>
24#include <linux/module.h>
25#include <linux/mutex.h>
26#include <linux/of.h>
27#include <linux/platform_device.h>
28#include <linux/regmap.h>
29#include <linux/rtc.h>
30#include <linux/types.h>
31
32/* Control register */
33#define AC100_RTC_CTRL_24HOUR BIT(0)
34
35/* Clock output register bits */
36#define AC100_CLKOUT_PRE_DIV_SHIFT 5
37#define AC100_CLKOUT_PRE_DIV_WIDTH 3
38#define AC100_CLKOUT_MUX_SHIFT 4
39#define AC100_CLKOUT_MUX_WIDTH 1
40#define AC100_CLKOUT_DIV_SHIFT 1
41#define AC100_CLKOUT_DIV_WIDTH 3
42#define AC100_CLKOUT_EN BIT(0)
43
44/* RTC */
45#define AC100_RTC_SEC_MASK GENMASK(6, 0)
46#define AC100_RTC_MIN_MASK GENMASK(6, 0)
47#define AC100_RTC_HOU_MASK GENMASK(5, 0)
48#define AC100_RTC_WEE_MASK GENMASK(2, 0)
49#define AC100_RTC_DAY_MASK GENMASK(5, 0)
50#define AC100_RTC_MON_MASK GENMASK(4, 0)
51#define AC100_RTC_YEA_MASK GENMASK(7, 0)
52#define AC100_RTC_YEA_LEAP BIT(15)
53#define AC100_RTC_UPD_TRIGGER BIT(15)
54
55/* Alarm (wall clock) */
56#define AC100_ALM_INT_ENABLE BIT(0)
57
58#define AC100_ALM_SEC_MASK GENMASK(6, 0)
59#define AC100_ALM_MIN_MASK GENMASK(6, 0)
60#define AC100_ALM_HOU_MASK GENMASK(5, 0)
61#define AC100_ALM_WEE_MASK GENMASK(2, 0)
62#define AC100_ALM_DAY_MASK GENMASK(5, 0)
63#define AC100_ALM_MON_MASK GENMASK(4, 0)
64#define AC100_ALM_YEA_MASK GENMASK(7, 0)
65#define AC100_ALM_ENABLE_FLAG BIT(15)
66#define AC100_ALM_UPD_TRIGGER BIT(15)
67
68/*
69 * The year parameter passed to the driver is usually an offset relative to
70 * the year 1900. This macro is used to convert this offset to another one
71 * relative to the minimum year allowed by the hardware.
72 *
73 * The year range is 1970 - 2069. This range is selected to match Allwinner's
74 * driver.
75 */
76#define AC100_YEAR_MIN 1970
77#define AC100_YEAR_MAX 2069
78#define AC100_YEAR_OFF (AC100_YEAR_MIN - 1900)
79
80struct ac100_clkout {
81 struct clk_hw hw;
82 struct regmap *regmap;
83 u8 offset;
84};
85
86#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw)
87
88#define AC100_RTC_32K_NAME "ac100-rtc-32k"
89#define AC100_RTC_32K_RATE 32768
90#define AC100_CLKOUT_NUM 3
91
92static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = {
93 "ac100-cko1-rtc",
94 "ac100-cko2-rtc",
95 "ac100-cko3-rtc",
96};
97
98struct ac100_rtc_dev {
99 struct rtc_device *rtc;
100 struct device *dev;
101 struct regmap *regmap;
102 int irq;
103 unsigned long alarm;
104
105 struct clk_hw *rtc_32k_clk;
106 struct ac100_clkout clks[AC100_CLKOUT_NUM];
107 struct clk_hw_onecell_data *clk_data;
108};
109
110/**
111 * Clock controls for 3 clock output pins
112 */
113
114static const struct clk_div_table ac100_clkout_prediv[] = {
115 { .val = 0, .div = 1 },
116 { .val = 1, .div = 2 },
117 { .val = 2, .div = 4 },
118 { .val = 3, .div = 8 },
119 { .val = 4, .div = 16 },
120 { .val = 5, .div = 32 },
121 { .val = 6, .div = 64 },
122 { .val = 7, .div = 122 },
123 { },
124};
125
126/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */
127static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,
128 unsigned long prate)
129{
130 struct ac100_clkout *clk = to_ac100_clkout(hw);
131 unsigned int reg, div;
132
133 regmap_read(clk->regmap, clk->offset, ®);
134
135 /* Handle pre-divider first */
136 if (prate != AC100_RTC_32K_RATE) {
137 div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &
138 ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);
139 prate = divider_recalc_rate(hw, prate, div,
140 ac100_clkout_prediv, 0);
141 }
142
143 div = (reg >> AC100_CLKOUT_DIV_SHIFT) &
144 (BIT(AC100_CLKOUT_DIV_WIDTH) - 1);
145 return divider_recalc_rate(hw, prate, div, NULL,
146 CLK_DIVIDER_POWER_OF_TWO);
147}
148
149static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
150 unsigned long prate)
151{
152 unsigned long best_rate = 0, tmp_rate, tmp_prate;
153 int i;
154
155 if (prate == AC100_RTC_32K_RATE)
156 return divider_round_rate(hw, rate, &prate, NULL,
157 AC100_CLKOUT_DIV_WIDTH,
158 CLK_DIVIDER_POWER_OF_TWO);
159
160 for (i = 0; ac100_clkout_prediv[i].div; i++) {
161 tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);
162 tmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL,
163 AC100_CLKOUT_DIV_WIDTH,
164 CLK_DIVIDER_POWER_OF_TWO);
165
166 if (tmp_rate > rate)
167 continue;
168 if (rate - tmp_rate < best_rate - tmp_rate)
169 best_rate = tmp_rate;
170 }
171
172 return best_rate;
173}
174
175static int ac100_clkout_determine_rate(struct clk_hw *hw,
176 struct clk_rate_request *req)
177{
178 struct clk_hw *best_parent;
179 unsigned long best = 0;
180 int i, num_parents = clk_hw_get_num_parents(hw);
181
182 for (i = 0; i < num_parents; i++) {
183 struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
184 unsigned long tmp, prate = clk_hw_get_rate(parent);
185
186 tmp = ac100_clkout_round_rate(hw, req->rate, prate);
187
188 if (tmp > req->rate)
189 continue;
190 if (req->rate - tmp < req->rate - best) {
191 best = tmp;
192 best_parent = parent;
193 }
194 }
195
196 if (!best)
197 return -EINVAL;
198
199 req->best_parent_hw = best_parent;
200 req->best_parent_rate = best;
201 req->rate = best;
202
203 return 0;
204}
205
206static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
207 unsigned long prate)
208{
209 struct ac100_clkout *clk = to_ac100_clkout(hw);
210 int div = 0, pre_div = 0;
211
212 do {
213 div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div,
214 prate, NULL, AC100_CLKOUT_DIV_WIDTH,
215 CLK_DIVIDER_POWER_OF_TWO);
216 if (div >= 0)
217 break;
218 } while (prate != AC100_RTC_32K_RATE &&
219 ac100_clkout_prediv[++pre_div].div);
220
221 if (div < 0)
222 return div;
223
224 pre_div = ac100_clkout_prediv[pre_div].val;
225
226 regmap_update_bits(clk->regmap, clk->offset,
227 ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT |
228 ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT,
229 (div - 1) << AC100_CLKOUT_DIV_SHIFT |
230 (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT);
231
232 return 0;
233}
234
235static int ac100_clkout_prepare(struct clk_hw *hw)
236{
237 struct ac100_clkout *clk = to_ac100_clkout(hw);
238
239 return regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN,
240 AC100_CLKOUT_EN);
241}
242
243static void ac100_clkout_unprepare(struct clk_hw *hw)
244{
245 struct ac100_clkout *clk = to_ac100_clkout(hw);
246
247 regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0);
248}
249
250static int ac100_clkout_is_prepared(struct clk_hw *hw)
251{
252 struct ac100_clkout *clk = to_ac100_clkout(hw);
253 unsigned int reg;
254
255 regmap_read(clk->regmap, clk->offset, ®);
256
257 return reg & AC100_CLKOUT_EN;
258}
259
260static u8 ac100_clkout_get_parent(struct clk_hw *hw)
261{
262 struct ac100_clkout *clk = to_ac100_clkout(hw);
263 unsigned int reg;
264
265 regmap_read(clk->regmap, clk->offset, ®);
266
267 return (reg >> AC100_CLKOUT_MUX_SHIFT) & 0x1;
268}
269
270static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index)
271{
272 struct ac100_clkout *clk = to_ac100_clkout(hw);
273
274 return regmap_update_bits(clk->regmap, clk->offset,
275 BIT(AC100_CLKOUT_MUX_SHIFT),
276 index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0);
277}
278
279static const struct clk_ops ac100_clkout_ops = {
280 .prepare = ac100_clkout_prepare,
281 .unprepare = ac100_clkout_unprepare,
282 .is_prepared = ac100_clkout_is_prepared,
283 .recalc_rate = ac100_clkout_recalc_rate,
284 .determine_rate = ac100_clkout_determine_rate,
285 .get_parent = ac100_clkout_get_parent,
286 .set_parent = ac100_clkout_set_parent,
287 .set_rate = ac100_clkout_set_rate,
288};
289
290static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip)
291{
292 struct device_node *np = chip->dev->of_node;
293 const char *parents[2] = {AC100_RTC_32K_NAME};
294 int i, ret;
295
296 chip->clk_data = devm_kzalloc(chip->dev, sizeof(*chip->clk_data) +
297 sizeof(*chip->clk_data->hws) *
298 AC100_CLKOUT_NUM,
299 GFP_KERNEL);
300 if (!chip->clk_data)
301 return -ENOMEM;
302
303 chip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev,
304 AC100_RTC_32K_NAME,
305 NULL, 0,
306 AC100_RTC_32K_RATE);
307 if (IS_ERR(chip->rtc_32k_clk)) {
308 ret = PTR_ERR(chip->rtc_32k_clk);
309 dev_err(chip->dev, "Failed to register RTC-32k clock: %d\n",
310 ret);
311 return ret;
312 }
313
314 parents[1] = of_clk_get_parent_name(np, 0);
315 if (!parents[1]) {
316 dev_err(chip->dev, "Failed to get ADDA 4M clock\n");
317 return -EINVAL;
318 }
319
320 for (i = 0; i < AC100_CLKOUT_NUM; i++) {
321 struct ac100_clkout *clk = &chip->clks[i];
322 struct clk_init_data init = {
323 .name = ac100_clkout_names[i],
324 .ops = &ac100_clkout_ops,
325 .parent_names = parents,
326 .num_parents = ARRAY_SIZE(parents),
327 .flags = 0,
328 };
329
330 of_property_read_string_index(np, "clock-output-names",
331 i, &init.name);
332 clk->regmap = chip->regmap;
333 clk->offset = AC100_CLKOUT_CTRL1 + i;
334 clk->hw.init = &init;
335
336 ret = devm_clk_hw_register(chip->dev, &clk->hw);
337 if (ret) {
338 dev_err(chip->dev, "Failed to register clk '%s': %d\n",
339 init.name, ret);
340 goto err_unregister_rtc_32k;
341 }
342
343 chip->clk_data->hws[i] = &clk->hw;
344 }
345
346 chip->clk_data->num = i;
347 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data);
348 if (ret)
349 goto err_unregister_rtc_32k;
350
351 return 0;
352
353err_unregister_rtc_32k:
354 clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);
355
356 return ret;
357}
358
359static void ac100_rtc_unregister_clks(struct ac100_rtc_dev *chip)
360{
361 of_clk_del_provider(chip->dev->of_node);
362 clk_unregister_fixed_rate(chip->rtc_32k_clk->clk);
363}
364
365/**
366 * RTC related bits
367 */
368static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm)
369{
370 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
371 struct regmap *regmap = chip->regmap;
372 u16 reg[7];
373 int ret;
374
375 ret = regmap_bulk_read(regmap, AC100_RTC_SEC, reg, 7);
376 if (ret)
377 return ret;
378
379 rtc_tm->tm_sec = bcd2bin(reg[0] & AC100_RTC_SEC_MASK);
380 rtc_tm->tm_min = bcd2bin(reg[1] & AC100_RTC_MIN_MASK);
381 rtc_tm->tm_hour = bcd2bin(reg[2] & AC100_RTC_HOU_MASK);
382 rtc_tm->tm_wday = bcd2bin(reg[3] & AC100_RTC_WEE_MASK);
383 rtc_tm->tm_mday = bcd2bin(reg[4] & AC100_RTC_DAY_MASK);
384 rtc_tm->tm_mon = bcd2bin(reg[5] & AC100_RTC_MON_MASK) - 1;
385 rtc_tm->tm_year = bcd2bin(reg[6] & AC100_RTC_YEA_MASK) +
386 AC100_YEAR_OFF;
387
388 return rtc_valid_tm(rtc_tm);
389}
390
391static int ac100_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
392{
393 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
394 struct regmap *regmap = chip->regmap;
395 int year;
396 u16 reg[8];
397
398 /* our RTC has a limited year range... */
399 year = rtc_tm->tm_year - AC100_YEAR_OFF;
400 if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
401 dev_err(dev, "rtc only supports year in range %d - %d\n",
402 AC100_YEAR_MIN, AC100_YEAR_MAX);
403 return -EINVAL;
404 }
405
406 /* convert to BCD */
407 reg[0] = bin2bcd(rtc_tm->tm_sec) & AC100_RTC_SEC_MASK;
408 reg[1] = bin2bcd(rtc_tm->tm_min) & AC100_RTC_MIN_MASK;
409 reg[2] = bin2bcd(rtc_tm->tm_hour) & AC100_RTC_HOU_MASK;
410 reg[3] = bin2bcd(rtc_tm->tm_wday) & AC100_RTC_WEE_MASK;
411 reg[4] = bin2bcd(rtc_tm->tm_mday) & AC100_RTC_DAY_MASK;
412 reg[5] = bin2bcd(rtc_tm->tm_mon + 1) & AC100_RTC_MON_MASK;
413 reg[6] = bin2bcd(year) & AC100_RTC_YEA_MASK;
414 /* trigger write */
415 reg[7] = AC100_RTC_UPD_TRIGGER;
416
417 /* Is it a leap year? */
418 if (is_leap_year(year + AC100_YEAR_OFF + 1900))
419 reg[6] |= AC100_RTC_YEA_LEAP;
420
421 return regmap_bulk_write(regmap, AC100_RTC_SEC, reg, 8);
422}
423
424static int ac100_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
425{
426 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
427 struct regmap *regmap = chip->regmap;
428 unsigned int val;
429
430 val = en ? AC100_ALM_INT_ENABLE : 0;
431
432 return regmap_write(regmap, AC100_ALM_INT_ENA, val);
433}
434
435static int ac100_rtc_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
436{
437 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
438 struct regmap *regmap = chip->regmap;
439 struct rtc_time *alrm_tm = &alrm->time;
440 u16 reg[7];
441 unsigned int val;
442 int ret;
443
444 ret = regmap_read(regmap, AC100_ALM_INT_ENA, &val);
445 if (ret)
446 return ret;
447
448 alrm->enabled = !!(val & AC100_ALM_INT_ENABLE);
449
450 ret = regmap_bulk_read(regmap, AC100_ALM_SEC, reg, 7);
451 if (ret)
452 return ret;
453
454 alrm_tm->tm_sec = bcd2bin(reg[0] & AC100_ALM_SEC_MASK);
455 alrm_tm->tm_min = bcd2bin(reg[1] & AC100_ALM_MIN_MASK);
456 alrm_tm->tm_hour = bcd2bin(reg[2] & AC100_ALM_HOU_MASK);
457 alrm_tm->tm_wday = bcd2bin(reg[3] & AC100_ALM_WEE_MASK);
458 alrm_tm->tm_mday = bcd2bin(reg[4] & AC100_ALM_DAY_MASK);
459 alrm_tm->tm_mon = bcd2bin(reg[5] & AC100_ALM_MON_MASK) - 1;
460 alrm_tm->tm_year = bcd2bin(reg[6] & AC100_ALM_YEA_MASK) +
461 AC100_YEAR_OFF;
462
463 return 0;
464}
465
466static int ac100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
467{
468 struct ac100_rtc_dev *chip = dev_get_drvdata(dev);
469 struct regmap *regmap = chip->regmap;
470 struct rtc_time *alrm_tm = &alrm->time;
471 u16 reg[8];
472 int year;
473 int ret;
474
475 /* our alarm has a limited year range... */
476 year = alrm_tm->tm_year - AC100_YEAR_OFF;
477 if (year < 0 || year > (AC100_YEAR_MAX - 1900)) {
478 dev_err(dev, "alarm only supports year in range %d - %d\n",
479 AC100_YEAR_MIN, AC100_YEAR_MAX);
480 return -EINVAL;
481 }
482
483 /* convert to BCD */
484 reg[0] = (bin2bcd(alrm_tm->tm_sec) & AC100_ALM_SEC_MASK) |
485 AC100_ALM_ENABLE_FLAG;
486 reg[1] = (bin2bcd(alrm_tm->tm_min) & AC100_ALM_MIN_MASK) |
487 AC100_ALM_ENABLE_FLAG;
488 reg[2] = (bin2bcd(alrm_tm->tm_hour) & AC100_ALM_HOU_MASK) |
489 AC100_ALM_ENABLE_FLAG;
490 /* Do not enable weekday alarm */
491 reg[3] = bin2bcd(alrm_tm->tm_wday) & AC100_ALM_WEE_MASK;
492 reg[4] = (bin2bcd(alrm_tm->tm_mday) & AC100_ALM_DAY_MASK) |
493 AC100_ALM_ENABLE_FLAG;
494 reg[5] = (bin2bcd(alrm_tm->tm_mon + 1) & AC100_ALM_MON_MASK) |
495 AC100_ALM_ENABLE_FLAG;
496 reg[6] = (bin2bcd(year) & AC100_ALM_YEA_MASK) |
497 AC100_ALM_ENABLE_FLAG;
498 /* trigger write */
499 reg[7] = AC100_ALM_UPD_TRIGGER;
500
501 ret = regmap_bulk_write(regmap, AC100_ALM_SEC, reg, 8);
502 if (ret)
503 return ret;
504
505 return ac100_rtc_alarm_irq_enable(dev, alrm->enabled);
506}
507
508static irqreturn_t ac100_rtc_irq(int irq, void *data)
509{
510 struct ac100_rtc_dev *chip = data;
511 struct regmap *regmap = chip->regmap;
512 unsigned int val = 0;
513 int ret;
514
515 mutex_lock(&chip->rtc->ops_lock);
516
517 /* read status */
518 ret = regmap_read(regmap, AC100_ALM_INT_STA, &val);
519 if (ret)
520 goto out;
521
522 if (val & AC100_ALM_INT_ENABLE) {
523 /* signal rtc framework */
524 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
525
526 /* clear status */
527 ret = regmap_write(regmap, AC100_ALM_INT_STA, val);
528 if (ret)
529 goto out;
530
531 /* disable interrupt */
532 ret = ac100_rtc_alarm_irq_enable(chip->dev, 0);
533 if (ret)
534 goto out;
535 }
536
537out:
538 mutex_unlock(&chip->rtc->ops_lock);
539 return IRQ_HANDLED;
540}
541
542static const struct rtc_class_ops ac100_rtc_ops = {
543 .read_time = ac100_rtc_get_time,
544 .set_time = ac100_rtc_set_time,
545 .read_alarm = ac100_rtc_get_alarm,
546 .set_alarm = ac100_rtc_set_alarm,
547 .alarm_irq_enable = ac100_rtc_alarm_irq_enable,
548};
549
550static int ac100_rtc_probe(struct platform_device *pdev)
551{
552 struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
553 struct ac100_rtc_dev *chip;
554 int ret;
555
556 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
557 if (!chip)
558 return -ENOMEM;
559
560 platform_set_drvdata(pdev, chip);
561 chip->dev = &pdev->dev;
562 chip->regmap = ac100->regmap;
563
564 chip->irq = platform_get_irq(pdev, 0);
565 if (chip->irq < 0) {
566 dev_err(&pdev->dev, "No IRQ resource\n");
567 return chip->irq;
568 }
569
570 ret = devm_request_threaded_irq(&pdev->dev, chip->irq, NULL,
571 ac100_rtc_irq,
572 IRQF_SHARED | IRQF_ONESHOT,
573 dev_name(&pdev->dev), chip);
574 if (ret) {
575 dev_err(&pdev->dev, "Could not request IRQ\n");
576 return ret;
577 }
578
579 /* always use 24 hour mode */
580 regmap_write_bits(chip->regmap, AC100_RTC_CTRL, AC100_RTC_CTRL_24HOUR,
581 AC100_RTC_CTRL_24HOUR);
582
583 /* disable counter alarm interrupt */
584 regmap_write(chip->regmap, AC100_ALM_INT_ENA, 0);
585
586 /* clear counter alarm pending interrupts */
587 regmap_write(chip->regmap, AC100_ALM_INT_STA, AC100_ALM_INT_ENABLE);
588
589 chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-ac100",
590 &ac100_rtc_ops, THIS_MODULE);
591 if (IS_ERR(chip->rtc)) {
592 dev_err(&pdev->dev, "unable to register device\n");
593 return PTR_ERR(chip->rtc);
594 }
595
596 ret = ac100_rtc_register_clks(chip);
597 if (ret)
598 return ret;
599
600 dev_info(&pdev->dev, "RTC enabled\n");
601
602 return 0;
603}
604
605static int ac100_rtc_remove(struct platform_device *pdev)
606{
607 struct ac100_rtc_dev *chip = platform_get_drvdata(pdev);
608
609 ac100_rtc_unregister_clks(chip);
610
611 return 0;
612}
613
614static const struct of_device_id ac100_rtc_match[] = {
615 { .compatible = "x-powers,ac100-rtc" },
616 { },
617};
618MODULE_DEVICE_TABLE(of, ac100_rtc_match);
619
620static struct platform_driver ac100_rtc_driver = {
621 .probe = ac100_rtc_probe,
622 .remove = ac100_rtc_remove,
623 .driver = {
624 .name = "ac100-rtc",
625 .of_match_table = of_match_ptr(ac100_rtc_match),
626 },
627};
628module_platform_driver(ac100_rtc_driver);
629
630MODULE_DESCRIPTION("X-Powers AC100 RTC driver");
631MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
632MODULE_LICENSE("GPL v2");