1// SPDX-License-Identifier: ISC
  2/*
  3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
  4 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
  5 */
  6
  7#include <linux/kernel.h>
  8
  9#include "mt76x02.h"
 10#include "mt76x02_phy.h"
 11
 12void mt76x02_phy_set_rxpath(struct mt76x02_dev *dev)
 13{
 14	u32 val;
 15
 16	val = mt76_rr(dev, MT_BBP(AGC, 0));
 17	val &= ~BIT(4);
 18
 19	switch (dev->mphy.chainmask & 0xf) {
 20	case 2:
 21		val |= BIT(3);
 22		break;
 23	default:
 24		val &= ~BIT(3);
 25		break;
 26	}
 27
 28	mt76_wr(dev, MT_BBP(AGC, 0), val);
 29	mb();
 30	val = mt76_rr(dev, MT_BBP(AGC, 0));
 31}
 32EXPORT_SYMBOL_GPL(mt76x02_phy_set_rxpath);
 33
 34void mt76x02_phy_set_txdac(struct mt76x02_dev *dev)
 35{
 36	int txpath;
 37
 38	txpath = (dev->mphy.chainmask >> 8) & 0xf;
 39	switch (txpath) {
 40	case 2:
 41		mt76_set(dev, MT_BBP(TXBE, 5), 0x3);
 42		break;
 43	default:
 44		mt76_clear(dev, MT_BBP(TXBE, 5), 0x3);
 45		break;
 46	}
 47}
 48EXPORT_SYMBOL_GPL(mt76x02_phy_set_txdac);
 49
 50static u32
 51mt76x02_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4)
 52{
 53	u32 val = 0;
 54
 55	val |= (v1 & (BIT(6) - 1)) << 0;
 56	val |= (v2 & (BIT(6) - 1)) << 8;
 57	val |= (v3 & (BIT(6) - 1)) << 16;
 58	val |= (v4 & (BIT(6) - 1)) << 24;
 59	return val;
 60}
 61
 62int mt76x02_get_max_rate_power(struct mt76x02_rate_power *r)
 63{
 64	s8 ret = 0;
 65	int i;
 66
 67	for (i = 0; i < sizeof(r->all); i++)
 68		ret = max(ret, r->all[i]);
 69
 70	return ret;
 71}
 72EXPORT_SYMBOL_GPL(mt76x02_get_max_rate_power);
 73
 74void mt76x02_limit_rate_power(struct mt76x02_rate_power *r, int limit)
 75{
 76	int i;
 77
 78	for (i = 0; i < sizeof(r->all); i++)
 79		if (r->all[i] > limit)
 80			r->all[i] = limit;
 81}
 82EXPORT_SYMBOL_GPL(mt76x02_limit_rate_power);
 83
 84void mt76x02_add_rate_power_offset(struct mt76x02_rate_power *r, int offset)
 85{
 86	int i;
 87
 88	for (i = 0; i < sizeof(r->all); i++)
 89		r->all[i] += offset;
 90}
 91EXPORT_SYMBOL_GPL(mt76x02_add_rate_power_offset);
 92
 93void mt76x02_phy_set_txpower(struct mt76x02_dev *dev, int txp_0, int txp_1)
 94{
 95	struct mt76x02_rate_power *t = &dev->rate_power;
 96
 97	mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
 98	mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
 99
100	mt76_wr(dev, MT_TX_PWR_CFG_0,
101		mt76x02_tx_power_mask(t->cck[0], t->cck[2], t->ofdm[0],
102				      t->ofdm[2]));
103	mt76_wr(dev, MT_TX_PWR_CFG_1,
104		mt76x02_tx_power_mask(t->ofdm[4], t->ofdm[6], t->ht[0],
105				      t->ht[2]));
106	mt76_wr(dev, MT_TX_PWR_CFG_2,
107		mt76x02_tx_power_mask(t->ht[4], t->ht[6], t->ht[8],
108				      t->ht[10]));
109	mt76_wr(dev, MT_TX_PWR_CFG_3,
110		mt76x02_tx_power_mask(t->ht[12], t->ht[14], t->ht[0],
111				      t->ht[2]));
112	mt76_wr(dev, MT_TX_PWR_CFG_4,
113		mt76x02_tx_power_mask(t->ht[4], t->ht[6], 0, 0));
114	mt76_wr(dev, MT_TX_PWR_CFG_7,
115		mt76x02_tx_power_mask(t->ofdm[7], t->vht[0], t->ht[7],
116				      t->vht[1]));
117	mt76_wr(dev, MT_TX_PWR_CFG_8,
118		mt76x02_tx_power_mask(t->ht[14], 0, t->vht[0], t->vht[1]));
119	mt76_wr(dev, MT_TX_PWR_CFG_9,
120		mt76x02_tx_power_mask(t->ht[7], 0, t->vht[0], t->vht[1]));
121}
122EXPORT_SYMBOL_GPL(mt76x02_phy_set_txpower);
123
124void mt76x02_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl)
125{
126	int core_val, agc_val;
127
128	switch (width) {
129	case NL80211_CHAN_WIDTH_80:
130		core_val = 3;
131		agc_val = 7;
132		break;
133	case NL80211_CHAN_WIDTH_40:
134		core_val = 2;
135		agc_val = 3;
136		break;
137	default:
138		core_val = 0;
139		agc_val = 1;
140		break;
141	}
142
143	mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
144	mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
145	mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
146	mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
147}
148EXPORT_SYMBOL_GPL(mt76x02_phy_set_bw);
149
150void mt76x02_phy_set_band(struct mt76x02_dev *dev, int band,
151			  bool primary_upper)
152{
153	switch (band) {
154	case NL80211_BAND_2GHZ:
155		mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
156		mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
157		break;
158	case NL80211_BAND_5GHZ:
159		mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
160		mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
161		break;
162	}
163
164	mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
165		       primary_upper);
166}
167EXPORT_SYMBOL_GPL(mt76x02_phy_set_band);
168
169bool mt76x02_phy_adjust_vga_gain(struct mt76x02_dev *dev)
170{
171	u8 limit = dev->cal.low_gain > 0 ? 16 : 4;
172	bool ret = false;
173	u32 false_cca;
174
175	false_cca = FIELD_GET(MT_RX_STAT_1_CCA_ERRORS,
176			      mt76_rr(dev, MT_RX_STAT_1));
177	dev->cal.false_cca = false_cca;
178	if (false_cca > 800 && dev->cal.agc_gain_adjust < limit) {
179		dev->cal.agc_gain_adjust += 2;
180		ret = true;
181	} else if ((false_cca < 10 && dev->cal.agc_gain_adjust > 0) ||
182		   (dev->cal.agc_gain_adjust >= limit && false_cca < 500)) {
183		dev->cal.agc_gain_adjust -= 2;
184		ret = true;
185	}
186
187	dev->cal.agc_lowest_gain = dev->cal.agc_gain_adjust >= limit;
188
189	return ret;
190}
191EXPORT_SYMBOL_GPL(mt76x02_phy_adjust_vga_gain);
192
193void mt76x02_init_agc_gain(struct mt76x02_dev *dev)
194{
195	dev->cal.agc_gain_init[0] = mt76_get_field(dev, MT_BBP(AGC, 8),
196						   MT_BBP_AGC_GAIN);
197	dev->cal.agc_gain_init[1] = mt76_get_field(dev, MT_BBP(AGC, 9),
198						   MT_BBP_AGC_GAIN);
199	memcpy(dev->cal.agc_gain_cur, dev->cal.agc_gain_init,
200	       sizeof(dev->cal.agc_gain_cur));
201	dev->cal.low_gain = -1;
202	dev->cal.gain_init_done = true;
203}
204EXPORT_SYMBOL_GPL(mt76x02_init_agc_gain);