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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 *
5 * Copyright 2008 JMicron Technology Corporation
6 * https://www.jmicron.com/
7 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/netdevice.h>
18#include <linux/etherdevice.h>
19#include <linux/ethtool.h>
20#include <linux/mii.h>
21#include <linux/crc32.h>
22#include <linux/delay.h>
23#include <linux/spinlock.h>
24#include <linux/in.h>
25#include <linux/ip.h>
26#include <linux/ipv6.h>
27#include <linux/tcp.h>
28#include <linux/udp.h>
29#include <linux/if_vlan.h>
30#include <linux/slab.h>
31#include <linux/jiffies.h>
32#include <net/ip6_checksum.h>
33#include "jme.h"
34
35static int force_pseudohp = -1;
36static int no_pseudohp = -1;
37static int no_extplug = -1;
38module_param(force_pseudohp, int, 0);
39MODULE_PARM_DESC(force_pseudohp,
40 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
41module_param(no_pseudohp, int, 0);
42MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
43module_param(no_extplug, int, 0);
44MODULE_PARM_DESC(no_extplug,
45 "Do not use external plug signal for pseudo hot-plug.");
46
47static int
48jme_mdio_read(struct net_device *netdev, int phy, int reg)
49{
50 struct jme_adapter *jme = netdev_priv(netdev);
51 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
52
53read_again:
54 jwrite32(jme, JME_SMI, SMI_OP_REQ |
55 smi_phy_addr(phy) |
56 smi_reg_addr(reg));
57
58 wmb();
59 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
60 udelay(20);
61 val = jread32(jme, JME_SMI);
62 if ((val & SMI_OP_REQ) == 0)
63 break;
64 }
65
66 if (i == 0) {
67 pr_err("phy(%d) read timeout : %d\n", phy, reg);
68 return 0;
69 }
70
71 if (again--)
72 goto read_again;
73
74 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
75}
76
77static void
78jme_mdio_write(struct net_device *netdev,
79 int phy, int reg, int val)
80{
81 struct jme_adapter *jme = netdev_priv(netdev);
82 int i;
83
84 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
85 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
86 smi_phy_addr(phy) | smi_reg_addr(reg));
87
88 wmb();
89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
90 udelay(20);
91 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
92 break;
93 }
94
95 if (i == 0)
96 pr_err("phy(%d) write timeout : %d\n", phy, reg);
97}
98
99static inline void
100jme_reset_phy_processor(struct jme_adapter *jme)
101{
102 u32 val;
103
104 jme_mdio_write(jme->dev,
105 jme->mii_if.phy_id,
106 MII_ADVERTISE, ADVERTISE_ALL |
107 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
108
109 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
110 jme_mdio_write(jme->dev,
111 jme->mii_if.phy_id,
112 MII_CTRL1000,
113 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
114
115 val = jme_mdio_read(jme->dev,
116 jme->mii_if.phy_id,
117 MII_BMCR);
118
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
121 MII_BMCR, val | BMCR_RESET);
122}
123
124static void
125jme_setup_wakeup_frame(struct jme_adapter *jme,
126 const u32 *mask, u32 crc, int fnr)
127{
128 int i;
129
130 /*
131 * Setup CRC pattern
132 */
133 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
134 wmb();
135 jwrite32(jme, JME_WFODP, crc);
136 wmb();
137
138 /*
139 * Setup Mask
140 */
141 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
142 jwrite32(jme, JME_WFOI,
143 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
144 (fnr & WFOI_FRAME_SEL));
145 wmb();
146 jwrite32(jme, JME_WFODP, mask[i]);
147 wmb();
148 }
149}
150
151static inline void
152jme_mac_rxclk_off(struct jme_adapter *jme)
153{
154 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
155 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
156}
157
158static inline void
159jme_mac_rxclk_on(struct jme_adapter *jme)
160{
161 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
162 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
163}
164
165static inline void
166jme_mac_txclk_off(struct jme_adapter *jme)
167{
168 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
169 jwrite32f(jme, JME_GHC, jme->reg_ghc);
170}
171
172static inline void
173jme_mac_txclk_on(struct jme_adapter *jme)
174{
175 u32 speed = jme->reg_ghc & GHC_SPEED;
176 if (speed == GHC_SPEED_1000M)
177 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
178 else
179 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
180 jwrite32f(jme, JME_GHC, jme->reg_ghc);
181}
182
183static inline void
184jme_reset_ghc_speed(struct jme_adapter *jme)
185{
186 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
187 jwrite32f(jme, JME_GHC, jme->reg_ghc);
188}
189
190static inline void
191jme_reset_250A2_workaround(struct jme_adapter *jme)
192{
193 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
194 GPREG1_RSSPATCH);
195 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
196}
197
198static inline void
199jme_assert_ghc_reset(struct jme_adapter *jme)
200{
201 jme->reg_ghc |= GHC_SWRST;
202 jwrite32f(jme, JME_GHC, jme->reg_ghc);
203}
204
205static inline void
206jme_clear_ghc_reset(struct jme_adapter *jme)
207{
208 jme->reg_ghc &= ~GHC_SWRST;
209 jwrite32f(jme, JME_GHC, jme->reg_ghc);
210}
211
212static void
213jme_reset_mac_processor(struct jme_adapter *jme)
214{
215 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
216 u32 crc = 0xCDCDCDCD;
217 u32 gpreg0;
218 int i;
219
220 jme_reset_ghc_speed(jme);
221 jme_reset_250A2_workaround(jme);
222
223 jme_mac_rxclk_on(jme);
224 jme_mac_txclk_on(jme);
225 udelay(1);
226 jme_assert_ghc_reset(jme);
227 udelay(1);
228 jme_mac_rxclk_off(jme);
229 jme_mac_txclk_off(jme);
230 udelay(1);
231 jme_clear_ghc_reset(jme);
232 udelay(1);
233 jme_mac_rxclk_on(jme);
234 jme_mac_txclk_on(jme);
235 udelay(1);
236 jme_mac_rxclk_off(jme);
237 jme_mac_txclk_off(jme);
238
239 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
240 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
241 jwrite32(jme, JME_RXQDC, 0x00000000);
242 jwrite32(jme, JME_RXNDA, 0x00000000);
243 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
244 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
245 jwrite32(jme, JME_TXQDC, 0x00000000);
246 jwrite32(jme, JME_TXNDA, 0x00000000);
247
248 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
249 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
250 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
251 jme_setup_wakeup_frame(jme, mask, crc, i);
252 if (jme->fpgaver)
253 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
254 else
255 gpreg0 = GPREG0_DEFAULT;
256 jwrite32(jme, JME_GPREG0, gpreg0);
257}
258
259static inline void
260jme_clear_pm_enable_wol(struct jme_adapter *jme)
261{
262 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
263}
264
265static inline void
266jme_clear_pm_disable_wol(struct jme_adapter *jme)
267{
268 jwrite32(jme, JME_PMCS, PMCS_STMASK);
269}
270
271static int
272jme_reload_eeprom(struct jme_adapter *jme)
273{
274 u32 val;
275 int i;
276
277 val = jread32(jme, JME_SMBCSR);
278
279 if (val & SMBCSR_EEPROMD) {
280 val |= SMBCSR_CNACK;
281 jwrite32(jme, JME_SMBCSR, val);
282 val |= SMBCSR_RELOAD;
283 jwrite32(jme, JME_SMBCSR, val);
284 mdelay(12);
285
286 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
287 mdelay(1);
288 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
289 break;
290 }
291
292 if (i == 0) {
293 pr_err("eeprom reload timeout\n");
294 return -EIO;
295 }
296 }
297
298 return 0;
299}
300
301static void
302jme_load_macaddr(struct net_device *netdev)
303{
304 struct jme_adapter *jme = netdev_priv(netdev);
305 unsigned char macaddr[ETH_ALEN];
306 u32 val;
307
308 spin_lock_bh(&jme->macaddr_lock);
309 val = jread32(jme, JME_RXUMA_LO);
310 macaddr[0] = (val >> 0) & 0xFF;
311 macaddr[1] = (val >> 8) & 0xFF;
312 macaddr[2] = (val >> 16) & 0xFF;
313 macaddr[3] = (val >> 24) & 0xFF;
314 val = jread32(jme, JME_RXUMA_HI);
315 macaddr[4] = (val >> 0) & 0xFF;
316 macaddr[5] = (val >> 8) & 0xFF;
317 eth_hw_addr_set(netdev, macaddr);
318 spin_unlock_bh(&jme->macaddr_lock);
319}
320
321static inline void
322jme_set_rx_pcc(struct jme_adapter *jme, int p)
323{
324 switch (p) {
325 case PCC_OFF:
326 jwrite32(jme, JME_PCCRX0,
327 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
328 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
329 break;
330 case PCC_P1:
331 jwrite32(jme, JME_PCCRX0,
332 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
333 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
334 break;
335 case PCC_P2:
336 jwrite32(jme, JME_PCCRX0,
337 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
338 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
339 break;
340 case PCC_P3:
341 jwrite32(jme, JME_PCCRX0,
342 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
343 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
344 break;
345 default:
346 break;
347 }
348 wmb();
349
350 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
351 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
352}
353
354static void
355jme_start_irq(struct jme_adapter *jme)
356{
357 register struct dynpcc_info *dpi = &(jme->dpi);
358
359 jme_set_rx_pcc(jme, PCC_P1);
360 dpi->cur = PCC_P1;
361 dpi->attempt = PCC_P1;
362 dpi->cnt = 0;
363
364 jwrite32(jme, JME_PCCTX,
365 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
366 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
367 PCCTXQ0_EN
368 );
369
370 /*
371 * Enable Interrupts
372 */
373 jwrite32(jme, JME_IENS, INTR_ENABLE);
374}
375
376static inline void
377jme_stop_irq(struct jme_adapter *jme)
378{
379 /*
380 * Disable Interrupts
381 */
382 jwrite32f(jme, JME_IENC, INTR_ENABLE);
383}
384
385static u32
386jme_linkstat_from_phy(struct jme_adapter *jme)
387{
388 u32 phylink, bmsr;
389
390 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
391 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
392 if (bmsr & BMSR_ANCOMP)
393 phylink |= PHY_LINK_AUTONEG_COMPLETE;
394
395 return phylink;
396}
397
398static inline void
399jme_set_phyfifo_5level(struct jme_adapter *jme)
400{
401 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
402}
403
404static inline void
405jme_set_phyfifo_8level(struct jme_adapter *jme)
406{
407 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
408}
409
410static int
411jme_check_link(struct net_device *netdev, int testonly)
412{
413 struct jme_adapter *jme = netdev_priv(netdev);
414 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
415 char linkmsg[64];
416 int rc = 0;
417
418 linkmsg[0] = '\0';
419
420 if (jme->fpgaver)
421 phylink = jme_linkstat_from_phy(jme);
422 else
423 phylink = jread32(jme, JME_PHY_LINK);
424
425 if (phylink & PHY_LINK_UP) {
426 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
427 /*
428 * If we did not enable AN
429 * Speed/Duplex Info should be obtained from SMI
430 */
431 phylink = PHY_LINK_UP;
432
433 bmcr = jme_mdio_read(jme->dev,
434 jme->mii_if.phy_id,
435 MII_BMCR);
436
437 phylink |= ((bmcr & BMCR_SPEED1000) &&
438 (bmcr & BMCR_SPEED100) == 0) ?
439 PHY_LINK_SPEED_1000M :
440 (bmcr & BMCR_SPEED100) ?
441 PHY_LINK_SPEED_100M :
442 PHY_LINK_SPEED_10M;
443
444 phylink |= (bmcr & BMCR_FULLDPLX) ?
445 PHY_LINK_DUPLEX : 0;
446
447 strcat(linkmsg, "Forced: ");
448 } else {
449 /*
450 * Keep polling for speed/duplex resolve complete
451 */
452 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
453 --cnt) {
454
455 udelay(1);
456
457 if (jme->fpgaver)
458 phylink = jme_linkstat_from_phy(jme);
459 else
460 phylink = jread32(jme, JME_PHY_LINK);
461 }
462 if (!cnt)
463 pr_err("Waiting speed resolve timeout\n");
464
465 strcat(linkmsg, "ANed: ");
466 }
467
468 if (jme->phylink == phylink) {
469 rc = 1;
470 goto out;
471 }
472 if (testonly)
473 goto out;
474
475 jme->phylink = phylink;
476
477 /*
478 * The speed/duplex setting of jme->reg_ghc already cleared
479 * by jme_reset_mac_processor()
480 */
481 switch (phylink & PHY_LINK_SPEED_MASK) {
482 case PHY_LINK_SPEED_10M:
483 jme->reg_ghc |= GHC_SPEED_10M;
484 strcat(linkmsg, "10 Mbps, ");
485 break;
486 case PHY_LINK_SPEED_100M:
487 jme->reg_ghc |= GHC_SPEED_100M;
488 strcat(linkmsg, "100 Mbps, ");
489 break;
490 case PHY_LINK_SPEED_1000M:
491 jme->reg_ghc |= GHC_SPEED_1000M;
492 strcat(linkmsg, "1000 Mbps, ");
493 break;
494 default:
495 break;
496 }
497
498 if (phylink & PHY_LINK_DUPLEX) {
499 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
500 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
501 jme->reg_ghc |= GHC_DPX;
502 } else {
503 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
504 TXMCS_BACKOFF |
505 TXMCS_CARRIERSENSE |
506 TXMCS_COLLISION);
507 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
508 }
509
510 jwrite32(jme, JME_GHC, jme->reg_ghc);
511
512 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
513 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
514 GPREG1_RSSPATCH);
515 if (!(phylink & PHY_LINK_DUPLEX))
516 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
517 switch (phylink & PHY_LINK_SPEED_MASK) {
518 case PHY_LINK_SPEED_10M:
519 jme_set_phyfifo_8level(jme);
520 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
521 break;
522 case PHY_LINK_SPEED_100M:
523 jme_set_phyfifo_5level(jme);
524 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
525 break;
526 case PHY_LINK_SPEED_1000M:
527 jme_set_phyfifo_8level(jme);
528 break;
529 default:
530 break;
531 }
532 }
533 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
534
535 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
536 "Full-Duplex, " :
537 "Half-Duplex, ");
538 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
539 "MDI-X" :
540 "MDI");
541 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
542 netif_carrier_on(netdev);
543 } else {
544 if (testonly)
545 goto out;
546
547 netif_info(jme, link, jme->dev, "Link is down\n");
548 jme->phylink = 0;
549 netif_carrier_off(netdev);
550 }
551
552out:
553 return rc;
554}
555
556static int
557jme_setup_tx_resources(struct jme_adapter *jme)
558{
559 struct jme_ring *txring = &(jme->txring[0]);
560
561 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
562 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
563 &(txring->dmaalloc),
564 GFP_ATOMIC);
565
566 if (!txring->alloc)
567 goto err_set_null;
568
569 /*
570 * 16 Bytes align
571 */
572 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
573 RING_DESC_ALIGN);
574 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
575 txring->next_to_use = 0;
576 atomic_set(&txring->next_to_clean, 0);
577 atomic_set(&txring->nr_free, jme->tx_ring_size);
578
579 txring->bufinf = kcalloc(jme->tx_ring_size,
580 sizeof(struct jme_buffer_info),
581 GFP_ATOMIC);
582 if (unlikely(!(txring->bufinf)))
583 goto err_free_txring;
584
585 return 0;
586
587err_free_txring:
588 dma_free_coherent(&(jme->pdev->dev),
589 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
590 txring->alloc,
591 txring->dmaalloc);
592
593err_set_null:
594 txring->desc = NULL;
595 txring->dmaalloc = 0;
596 txring->dma = 0;
597 txring->bufinf = NULL;
598
599 return -ENOMEM;
600}
601
602static void
603jme_free_tx_resources(struct jme_adapter *jme)
604{
605 int i;
606 struct jme_ring *txring = &(jme->txring[0]);
607 struct jme_buffer_info *txbi;
608
609 if (txring->alloc) {
610 if (txring->bufinf) {
611 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
612 txbi = txring->bufinf + i;
613 if (txbi->skb) {
614 dev_kfree_skb(txbi->skb);
615 txbi->skb = NULL;
616 }
617 txbi->mapping = 0;
618 txbi->len = 0;
619 txbi->nr_desc = 0;
620 txbi->start_xmit = 0;
621 }
622 kfree(txring->bufinf);
623 }
624
625 dma_free_coherent(&(jme->pdev->dev),
626 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
627 txring->alloc,
628 txring->dmaalloc);
629
630 txring->alloc = NULL;
631 txring->desc = NULL;
632 txring->dmaalloc = 0;
633 txring->dma = 0;
634 txring->bufinf = NULL;
635 }
636 txring->next_to_use = 0;
637 atomic_set(&txring->next_to_clean, 0);
638 atomic_set(&txring->nr_free, 0);
639}
640
641static inline void
642jme_enable_tx_engine(struct jme_adapter *jme)
643{
644 /*
645 * Select Queue 0
646 */
647 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
648 wmb();
649
650 /*
651 * Setup TX Queue 0 DMA Bass Address
652 */
653 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
654 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
655 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
656
657 /*
658 * Setup TX Descptor Count
659 */
660 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
661
662 /*
663 * Enable TX Engine
664 */
665 wmb();
666 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
667 TXCS_SELECT_QUEUE0 |
668 TXCS_ENABLE);
669
670 /*
671 * Start clock for TX MAC Processor
672 */
673 jme_mac_txclk_on(jme);
674}
675
676static inline void
677jme_disable_tx_engine(struct jme_adapter *jme)
678{
679 int i;
680 u32 val;
681
682 /*
683 * Disable TX Engine
684 */
685 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
686 wmb();
687
688 val = jread32(jme, JME_TXCS);
689 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
690 mdelay(1);
691 val = jread32(jme, JME_TXCS);
692 rmb();
693 }
694
695 if (!i)
696 pr_err("Disable TX engine timeout\n");
697
698 /*
699 * Stop clock for TX MAC Processor
700 */
701 jme_mac_txclk_off(jme);
702}
703
704static void
705jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
706{
707 struct jme_ring *rxring = &(jme->rxring[0]);
708 register struct rxdesc *rxdesc = rxring->desc;
709 struct jme_buffer_info *rxbi = rxring->bufinf;
710 rxdesc += i;
711 rxbi += i;
712
713 rxdesc->dw[0] = 0;
714 rxdesc->dw[1] = 0;
715 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
716 rxdesc->desc1.bufaddrl = cpu_to_le32(
717 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
718 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
719 if (jme->dev->features & NETIF_F_HIGHDMA)
720 rxdesc->desc1.flags = RXFLAG_64BIT;
721 wmb();
722 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
723}
724
725static int
726jme_make_new_rx_buf(struct jme_adapter *jme, int i)
727{
728 struct jme_ring *rxring = &(jme->rxring[0]);
729 struct jme_buffer_info *rxbi = rxring->bufinf + i;
730 struct sk_buff *skb;
731 dma_addr_t mapping;
732
733 skb = netdev_alloc_skb(jme->dev,
734 jme->dev->mtu + RX_EXTRA_LEN);
735 if (unlikely(!skb))
736 return -ENOMEM;
737
738 mapping = dma_map_page(&jme->pdev->dev, virt_to_page(skb->data),
739 offset_in_page(skb->data), skb_tailroom(skb),
740 DMA_FROM_DEVICE);
741 if (unlikely(dma_mapping_error(&jme->pdev->dev, mapping))) {
742 dev_kfree_skb(skb);
743 return -ENOMEM;
744 }
745
746 if (likely(rxbi->mapping))
747 dma_unmap_page(&jme->pdev->dev, rxbi->mapping, rxbi->len,
748 DMA_FROM_DEVICE);
749
750 rxbi->skb = skb;
751 rxbi->len = skb_tailroom(skb);
752 rxbi->mapping = mapping;
753 return 0;
754}
755
756static void
757jme_free_rx_buf(struct jme_adapter *jme, int i)
758{
759 struct jme_ring *rxring = &(jme->rxring[0]);
760 struct jme_buffer_info *rxbi = rxring->bufinf;
761 rxbi += i;
762
763 if (rxbi->skb) {
764 dma_unmap_page(&jme->pdev->dev, rxbi->mapping, rxbi->len,
765 DMA_FROM_DEVICE);
766 dev_kfree_skb(rxbi->skb);
767 rxbi->skb = NULL;
768 rxbi->mapping = 0;
769 rxbi->len = 0;
770 }
771}
772
773static void
774jme_free_rx_resources(struct jme_adapter *jme)
775{
776 int i;
777 struct jme_ring *rxring = &(jme->rxring[0]);
778
779 if (rxring->alloc) {
780 if (rxring->bufinf) {
781 for (i = 0 ; i < jme->rx_ring_size ; ++i)
782 jme_free_rx_buf(jme, i);
783 kfree(rxring->bufinf);
784 }
785
786 dma_free_coherent(&(jme->pdev->dev),
787 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
788 rxring->alloc,
789 rxring->dmaalloc);
790 rxring->alloc = NULL;
791 rxring->desc = NULL;
792 rxring->dmaalloc = 0;
793 rxring->dma = 0;
794 rxring->bufinf = NULL;
795 }
796 rxring->next_to_use = 0;
797 atomic_set(&rxring->next_to_clean, 0);
798}
799
800static int
801jme_setup_rx_resources(struct jme_adapter *jme)
802{
803 int i;
804 struct jme_ring *rxring = &(jme->rxring[0]);
805
806 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
807 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
808 &(rxring->dmaalloc),
809 GFP_ATOMIC);
810 if (!rxring->alloc)
811 goto err_set_null;
812
813 /*
814 * 16 Bytes align
815 */
816 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
817 RING_DESC_ALIGN);
818 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
819 rxring->next_to_use = 0;
820 atomic_set(&rxring->next_to_clean, 0);
821
822 rxring->bufinf = kcalloc(jme->rx_ring_size,
823 sizeof(struct jme_buffer_info),
824 GFP_ATOMIC);
825 if (unlikely(!(rxring->bufinf)))
826 goto err_free_rxring;
827
828 /*
829 * Initiallize Receive Descriptors
830 */
831 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
832 if (unlikely(jme_make_new_rx_buf(jme, i))) {
833 jme_free_rx_resources(jme);
834 return -ENOMEM;
835 }
836
837 jme_set_clean_rxdesc(jme, i);
838 }
839
840 return 0;
841
842err_free_rxring:
843 dma_free_coherent(&(jme->pdev->dev),
844 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
845 rxring->alloc,
846 rxring->dmaalloc);
847err_set_null:
848 rxring->desc = NULL;
849 rxring->dmaalloc = 0;
850 rxring->dma = 0;
851 rxring->bufinf = NULL;
852
853 return -ENOMEM;
854}
855
856static inline void
857jme_enable_rx_engine(struct jme_adapter *jme)
858{
859 /*
860 * Select Queue 0
861 */
862 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
863 RXCS_QUEUESEL_Q0);
864 wmb();
865
866 /*
867 * Setup RX DMA Bass Address
868 */
869 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
870 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
871 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
872
873 /*
874 * Setup RX Descriptor Count
875 */
876 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
877
878 /*
879 * Setup Unicast Filter
880 */
881 jme_set_unicastaddr(jme->dev);
882 jme_set_multi(jme->dev);
883
884 /*
885 * Enable RX Engine
886 */
887 wmb();
888 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
889 RXCS_QUEUESEL_Q0 |
890 RXCS_ENABLE |
891 RXCS_QST);
892
893 /*
894 * Start clock for RX MAC Processor
895 */
896 jme_mac_rxclk_on(jme);
897}
898
899static inline void
900jme_restart_rx_engine(struct jme_adapter *jme)
901{
902 /*
903 * Start RX Engine
904 */
905 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
906 RXCS_QUEUESEL_Q0 |
907 RXCS_ENABLE |
908 RXCS_QST);
909}
910
911static inline void
912jme_disable_rx_engine(struct jme_adapter *jme)
913{
914 int i;
915 u32 val;
916
917 /*
918 * Disable RX Engine
919 */
920 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
921 wmb();
922
923 val = jread32(jme, JME_RXCS);
924 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
925 mdelay(1);
926 val = jread32(jme, JME_RXCS);
927 rmb();
928 }
929
930 if (!i)
931 pr_err("Disable RX engine timeout\n");
932
933 /*
934 * Stop clock for RX MAC Processor
935 */
936 jme_mac_rxclk_off(jme);
937}
938
939static u16
940jme_udpsum(struct sk_buff *skb)
941{
942 u16 csum = 0xFFFFu;
943
944 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
945 return csum;
946 if (skb->protocol != htons(ETH_P_IP))
947 return csum;
948 skb_set_network_header(skb, ETH_HLEN);
949 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
950 (skb->len < (ETH_HLEN +
951 (ip_hdr(skb)->ihl << 2) +
952 sizeof(struct udphdr)))) {
953 skb_reset_network_header(skb);
954 return csum;
955 }
956 skb_set_transport_header(skb,
957 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
958 csum = udp_hdr(skb)->check;
959 skb_reset_transport_header(skb);
960 skb_reset_network_header(skb);
961
962 return csum;
963}
964
965static int
966jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
967{
968 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
969 return false;
970
971 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
972 == RXWBFLAG_TCPON)) {
973 if (flags & RXWBFLAG_IPV4)
974 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
975 return false;
976 }
977
978 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
979 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
980 if (flags & RXWBFLAG_IPV4)
981 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
982 return false;
983 }
984
985 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
986 == RXWBFLAG_IPV4)) {
987 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
988 return false;
989 }
990
991 return true;
992}
993
994static void
995jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
996{
997 struct jme_ring *rxring = &(jme->rxring[0]);
998 struct rxdesc *rxdesc = rxring->desc;
999 struct jme_buffer_info *rxbi = rxring->bufinf;
1000 struct sk_buff *skb;
1001 int framesize;
1002
1003 rxdesc += idx;
1004 rxbi += idx;
1005
1006 skb = rxbi->skb;
1007 dma_sync_single_for_cpu(&jme->pdev->dev, rxbi->mapping, rxbi->len,
1008 DMA_FROM_DEVICE);
1009
1010 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1011 dma_sync_single_for_device(&jme->pdev->dev, rxbi->mapping,
1012 rxbi->len, DMA_FROM_DEVICE);
1013
1014 ++(NET_STAT(jme).rx_dropped);
1015 } else {
1016 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1017 - RX_PREPAD_SIZE;
1018
1019 skb_reserve(skb, RX_PREPAD_SIZE);
1020 skb_put(skb, framesize);
1021 skb->protocol = eth_type_trans(skb, jme->dev);
1022
1023 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1024 skb->ip_summed = CHECKSUM_UNNECESSARY;
1025 else
1026 skb_checksum_none_assert(skb);
1027
1028 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1029 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1030
1031 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1032 NET_STAT(jme).rx_bytes += 4;
1033 }
1034 jme->jme_rx(skb);
1035
1036 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1037 cpu_to_le16(RXWBFLAG_DEST_MUL))
1038 ++(NET_STAT(jme).multicast);
1039
1040 NET_STAT(jme).rx_bytes += framesize;
1041 ++(NET_STAT(jme).rx_packets);
1042 }
1043
1044 jme_set_clean_rxdesc(jme, idx);
1045
1046}
1047
1048static int
1049jme_process_receive(struct jme_adapter *jme, int limit)
1050{
1051 struct jme_ring *rxring = &(jme->rxring[0]);
1052 struct rxdesc *rxdesc;
1053 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1054
1055 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1056 goto out_inc;
1057
1058 if (unlikely(atomic_read(&jme->link_changing) != 1))
1059 goto out_inc;
1060
1061 if (unlikely(!netif_carrier_ok(jme->dev)))
1062 goto out_inc;
1063
1064 i = atomic_read(&rxring->next_to_clean);
1065 while (limit > 0) {
1066 rxdesc = rxring->desc;
1067 rxdesc += i;
1068
1069 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1070 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1071 goto out;
1072 --limit;
1073
1074 rmb();
1075 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1076
1077 if (unlikely(desccnt > 1 ||
1078 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1079
1080 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1081 ++(NET_STAT(jme).rx_crc_errors);
1082 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1083 ++(NET_STAT(jme).rx_fifo_errors);
1084 else
1085 ++(NET_STAT(jme).rx_errors);
1086
1087 if (desccnt > 1)
1088 limit -= desccnt - 1;
1089
1090 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1091 jme_set_clean_rxdesc(jme, j);
1092 j = (j + 1) & (mask);
1093 }
1094
1095 } else {
1096 jme_alloc_and_feed_skb(jme, i);
1097 }
1098
1099 i = (i + desccnt) & (mask);
1100 }
1101
1102out:
1103 atomic_set(&rxring->next_to_clean, i);
1104
1105out_inc:
1106 atomic_inc(&jme->rx_cleaning);
1107
1108 return limit > 0 ? limit : 0;
1109
1110}
1111
1112static void
1113jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1114{
1115 if (likely(atmp == dpi->cur)) {
1116 dpi->cnt = 0;
1117 return;
1118 }
1119
1120 if (dpi->attempt == atmp) {
1121 ++(dpi->cnt);
1122 } else {
1123 dpi->attempt = atmp;
1124 dpi->cnt = 0;
1125 }
1126
1127}
1128
1129static void
1130jme_dynamic_pcc(struct jme_adapter *jme)
1131{
1132 register struct dynpcc_info *dpi = &(jme->dpi);
1133
1134 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1135 jme_attempt_pcc(dpi, PCC_P3);
1136 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1137 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1138 jme_attempt_pcc(dpi, PCC_P2);
1139 else
1140 jme_attempt_pcc(dpi, PCC_P1);
1141
1142 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1143 if (dpi->attempt < dpi->cur)
1144 tasklet_schedule(&jme->rxclean_task);
1145 jme_set_rx_pcc(jme, dpi->attempt);
1146 dpi->cur = dpi->attempt;
1147 dpi->cnt = 0;
1148 }
1149}
1150
1151static void
1152jme_start_pcc_timer(struct jme_adapter *jme)
1153{
1154 struct dynpcc_info *dpi = &(jme->dpi);
1155 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1156 dpi->last_pkts = NET_STAT(jme).rx_packets;
1157 dpi->intr_cnt = 0;
1158 jwrite32(jme, JME_TMCSR,
1159 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1160}
1161
1162static inline void
1163jme_stop_pcc_timer(struct jme_adapter *jme)
1164{
1165 jwrite32(jme, JME_TMCSR, 0);
1166}
1167
1168static void
1169jme_shutdown_nic(struct jme_adapter *jme)
1170{
1171 u32 phylink;
1172
1173 phylink = jme_linkstat_from_phy(jme);
1174
1175 if (!(phylink & PHY_LINK_UP)) {
1176 /*
1177 * Disable all interrupt before issue timer
1178 */
1179 jme_stop_irq(jme);
1180 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1181 }
1182}
1183
1184static void
1185jme_pcc_tasklet(struct tasklet_struct *t)
1186{
1187 struct jme_adapter *jme = from_tasklet(jme, t, pcc_task);
1188 struct net_device *netdev = jme->dev;
1189
1190 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1191 jme_shutdown_nic(jme);
1192 return;
1193 }
1194
1195 if (unlikely(!netif_carrier_ok(netdev) ||
1196 (atomic_read(&jme->link_changing) != 1)
1197 )) {
1198 jme_stop_pcc_timer(jme);
1199 return;
1200 }
1201
1202 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1203 jme_dynamic_pcc(jme);
1204
1205 jme_start_pcc_timer(jme);
1206}
1207
1208static inline void
1209jme_polling_mode(struct jme_adapter *jme)
1210{
1211 jme_set_rx_pcc(jme, PCC_OFF);
1212}
1213
1214static inline void
1215jme_interrupt_mode(struct jme_adapter *jme)
1216{
1217 jme_set_rx_pcc(jme, PCC_P1);
1218}
1219
1220static inline int
1221jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1222{
1223 u32 apmc;
1224 apmc = jread32(jme, JME_APMC);
1225 return apmc & JME_APMC_PSEUDO_HP_EN;
1226}
1227
1228static void
1229jme_start_shutdown_timer(struct jme_adapter *jme)
1230{
1231 u32 apmc;
1232
1233 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1234 apmc &= ~JME_APMC_EPIEN_CTRL;
1235 if (!no_extplug) {
1236 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1237 wmb();
1238 }
1239 jwrite32f(jme, JME_APMC, apmc);
1240
1241 jwrite32f(jme, JME_TIMER2, 0);
1242 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1243 jwrite32(jme, JME_TMCSR,
1244 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1245}
1246
1247static void
1248jme_stop_shutdown_timer(struct jme_adapter *jme)
1249{
1250 u32 apmc;
1251
1252 jwrite32f(jme, JME_TMCSR, 0);
1253 jwrite32f(jme, JME_TIMER2, 0);
1254 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1255
1256 apmc = jread32(jme, JME_APMC);
1257 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1258 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1259 wmb();
1260 jwrite32f(jme, JME_APMC, apmc);
1261}
1262
1263static void jme_link_change_work(struct work_struct *work)
1264{
1265 struct jme_adapter *jme = container_of(work, struct jme_adapter, linkch_task);
1266 struct net_device *netdev = jme->dev;
1267 int rc;
1268
1269 while (!atomic_dec_and_test(&jme->link_changing)) {
1270 atomic_inc(&jme->link_changing);
1271 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1272 while (atomic_read(&jme->link_changing) != 1)
1273 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1274 }
1275
1276 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1277 goto out;
1278
1279 jme->old_mtu = netdev->mtu;
1280 netif_stop_queue(netdev);
1281 if (jme_pseudo_hotplug_enabled(jme))
1282 jme_stop_shutdown_timer(jme);
1283
1284 jme_stop_pcc_timer(jme);
1285 tasklet_disable(&jme->txclean_task);
1286 tasklet_disable(&jme->rxclean_task);
1287 tasklet_disable(&jme->rxempty_task);
1288
1289 if (netif_carrier_ok(netdev)) {
1290 jme_disable_rx_engine(jme);
1291 jme_disable_tx_engine(jme);
1292 jme_reset_mac_processor(jme);
1293 jme_free_rx_resources(jme);
1294 jme_free_tx_resources(jme);
1295
1296 if (test_bit(JME_FLAG_POLL, &jme->flags))
1297 jme_polling_mode(jme);
1298
1299 netif_carrier_off(netdev);
1300 }
1301
1302 jme_check_link(netdev, 0);
1303 if (netif_carrier_ok(netdev)) {
1304 rc = jme_setup_rx_resources(jme);
1305 if (rc) {
1306 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1307 goto out_enable_tasklet;
1308 }
1309
1310 rc = jme_setup_tx_resources(jme);
1311 if (rc) {
1312 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1313 goto err_out_free_rx_resources;
1314 }
1315
1316 jme_enable_rx_engine(jme);
1317 jme_enable_tx_engine(jme);
1318
1319 netif_start_queue(netdev);
1320
1321 if (test_bit(JME_FLAG_POLL, &jme->flags))
1322 jme_interrupt_mode(jme);
1323
1324 jme_start_pcc_timer(jme);
1325 } else if (jme_pseudo_hotplug_enabled(jme)) {
1326 jme_start_shutdown_timer(jme);
1327 }
1328
1329 goto out_enable_tasklet;
1330
1331err_out_free_rx_resources:
1332 jme_free_rx_resources(jme);
1333out_enable_tasklet:
1334 tasklet_enable(&jme->txclean_task);
1335 tasklet_enable(&jme->rxclean_task);
1336 tasklet_enable(&jme->rxempty_task);
1337out:
1338 atomic_inc(&jme->link_changing);
1339}
1340
1341static void
1342jme_rx_clean_tasklet(struct tasklet_struct *t)
1343{
1344 struct jme_adapter *jme = from_tasklet(jme, t, rxclean_task);
1345 struct dynpcc_info *dpi = &(jme->dpi);
1346
1347 jme_process_receive(jme, jme->rx_ring_size);
1348 ++(dpi->intr_cnt);
1349
1350}
1351
1352static int
1353jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1354{
1355 struct jme_adapter *jme = jme_napi_priv(holder);
1356 int rest;
1357
1358 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1359
1360 while (atomic_read(&jme->rx_empty) > 0) {
1361 atomic_dec(&jme->rx_empty);
1362 ++(NET_STAT(jme).rx_dropped);
1363 jme_restart_rx_engine(jme);
1364 }
1365 atomic_inc(&jme->rx_empty);
1366
1367 if (rest) {
1368 JME_RX_COMPLETE(netdev, holder);
1369 jme_interrupt_mode(jme);
1370 }
1371
1372 JME_NAPI_WEIGHT_SET(budget, rest);
1373 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1374}
1375
1376static void
1377jme_rx_empty_tasklet(struct tasklet_struct *t)
1378{
1379 struct jme_adapter *jme = from_tasklet(jme, t, rxempty_task);
1380
1381 if (unlikely(atomic_read(&jme->link_changing) != 1))
1382 return;
1383
1384 if (unlikely(!netif_carrier_ok(jme->dev)))
1385 return;
1386
1387 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1388
1389 jme_rx_clean_tasklet(&jme->rxclean_task);
1390
1391 while (atomic_read(&jme->rx_empty) > 0) {
1392 atomic_dec(&jme->rx_empty);
1393 ++(NET_STAT(jme).rx_dropped);
1394 jme_restart_rx_engine(jme);
1395 }
1396 atomic_inc(&jme->rx_empty);
1397}
1398
1399static void
1400jme_wake_queue_if_stopped(struct jme_adapter *jme)
1401{
1402 struct jme_ring *txring = &(jme->txring[0]);
1403
1404 smp_wmb();
1405 if (unlikely(netif_queue_stopped(jme->dev) &&
1406 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1407 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1408 netif_wake_queue(jme->dev);
1409 }
1410
1411}
1412
1413static void jme_tx_clean_tasklet(struct tasklet_struct *t)
1414{
1415 struct jme_adapter *jme = from_tasklet(jme, t, txclean_task);
1416 struct jme_ring *txring = &(jme->txring[0]);
1417 struct txdesc *txdesc = txring->desc;
1418 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1419 int i, j, cnt = 0, max, err, mask;
1420
1421 tx_dbg(jme, "Into txclean\n");
1422
1423 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1424 goto out;
1425
1426 if (unlikely(atomic_read(&jme->link_changing) != 1))
1427 goto out;
1428
1429 if (unlikely(!netif_carrier_ok(jme->dev)))
1430 goto out;
1431
1432 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1433 mask = jme->tx_ring_mask;
1434
1435 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1436
1437 ctxbi = txbi + i;
1438
1439 if (likely(ctxbi->skb &&
1440 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1441
1442 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1443 i, ctxbi->nr_desc, jiffies);
1444
1445 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1446
1447 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1448 ttxbi = txbi + ((i + j) & (mask));
1449 txdesc[(i + j) & (mask)].dw[0] = 0;
1450
1451 dma_unmap_page(&jme->pdev->dev,
1452 ttxbi->mapping, ttxbi->len,
1453 DMA_TO_DEVICE);
1454
1455 ttxbi->mapping = 0;
1456 ttxbi->len = 0;
1457 }
1458
1459 dev_kfree_skb(ctxbi->skb);
1460
1461 cnt += ctxbi->nr_desc;
1462
1463 if (unlikely(err)) {
1464 ++(NET_STAT(jme).tx_carrier_errors);
1465 } else {
1466 ++(NET_STAT(jme).tx_packets);
1467 NET_STAT(jme).tx_bytes += ctxbi->len;
1468 }
1469
1470 ctxbi->skb = NULL;
1471 ctxbi->len = 0;
1472 ctxbi->start_xmit = 0;
1473
1474 } else {
1475 break;
1476 }
1477
1478 i = (i + ctxbi->nr_desc) & mask;
1479
1480 ctxbi->nr_desc = 0;
1481 }
1482
1483 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1484 atomic_set(&txring->next_to_clean, i);
1485 atomic_add(cnt, &txring->nr_free);
1486
1487 jme_wake_queue_if_stopped(jme);
1488
1489out:
1490 atomic_inc(&jme->tx_cleaning);
1491}
1492
1493static void
1494jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1495{
1496 /*
1497 * Disable interrupt
1498 */
1499 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1500
1501 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1502 /*
1503 * Link change event is critical
1504 * all other events are ignored
1505 */
1506 jwrite32(jme, JME_IEVE, intrstat);
1507 schedule_work(&jme->linkch_task);
1508 goto out_reenable;
1509 }
1510
1511 if (intrstat & INTR_TMINTR) {
1512 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1513 tasklet_schedule(&jme->pcc_task);
1514 }
1515
1516 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1517 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1518 tasklet_schedule(&jme->txclean_task);
1519 }
1520
1521 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1522 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1523 INTR_PCCRX0 |
1524 INTR_RX0EMP)) |
1525 INTR_RX0);
1526 }
1527
1528 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1529 if (intrstat & INTR_RX0EMP)
1530 atomic_inc(&jme->rx_empty);
1531
1532 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1533 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1534 jme_polling_mode(jme);
1535 JME_RX_SCHEDULE(jme);
1536 }
1537 }
1538 } else {
1539 if (intrstat & INTR_RX0EMP) {
1540 atomic_inc(&jme->rx_empty);
1541 tasklet_hi_schedule(&jme->rxempty_task);
1542 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1543 tasklet_hi_schedule(&jme->rxclean_task);
1544 }
1545 }
1546
1547out_reenable:
1548 /*
1549 * Re-enable interrupt
1550 */
1551 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1552}
1553
1554static irqreturn_t
1555jme_intr(int irq, void *dev_id)
1556{
1557 struct net_device *netdev = dev_id;
1558 struct jme_adapter *jme = netdev_priv(netdev);
1559 u32 intrstat;
1560
1561 intrstat = jread32(jme, JME_IEVE);
1562
1563 /*
1564 * Check if it's really an interrupt for us
1565 */
1566 if (unlikely((intrstat & INTR_ENABLE) == 0))
1567 return IRQ_NONE;
1568
1569 /*
1570 * Check if the device still exist
1571 */
1572 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1573 return IRQ_NONE;
1574
1575 jme_intr_msi(jme, intrstat);
1576
1577 return IRQ_HANDLED;
1578}
1579
1580static irqreturn_t
1581jme_msi(int irq, void *dev_id)
1582{
1583 struct net_device *netdev = dev_id;
1584 struct jme_adapter *jme = netdev_priv(netdev);
1585 u32 intrstat;
1586
1587 intrstat = jread32(jme, JME_IEVE);
1588
1589 jme_intr_msi(jme, intrstat);
1590
1591 return IRQ_HANDLED;
1592}
1593
1594static void
1595jme_reset_link(struct jme_adapter *jme)
1596{
1597 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1598}
1599
1600static void
1601jme_restart_an(struct jme_adapter *jme)
1602{
1603 u32 bmcr;
1604
1605 spin_lock_bh(&jme->phy_lock);
1606 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1607 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1608 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1609 spin_unlock_bh(&jme->phy_lock);
1610}
1611
1612static int
1613jme_request_irq(struct jme_adapter *jme)
1614{
1615 int rc;
1616 struct net_device *netdev = jme->dev;
1617 irq_handler_t handler = jme_intr;
1618 int irq_flags = IRQF_SHARED;
1619
1620 if (!pci_enable_msi(jme->pdev)) {
1621 set_bit(JME_FLAG_MSI, &jme->flags);
1622 handler = jme_msi;
1623 irq_flags = 0;
1624 }
1625
1626 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1627 netdev);
1628 if (rc) {
1629 netdev_err(netdev,
1630 "Unable to request %s interrupt (return: %d)\n",
1631 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1632 rc);
1633
1634 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1635 pci_disable_msi(jme->pdev);
1636 clear_bit(JME_FLAG_MSI, &jme->flags);
1637 }
1638 } else {
1639 netdev->irq = jme->pdev->irq;
1640 }
1641
1642 return rc;
1643}
1644
1645static void
1646jme_free_irq(struct jme_adapter *jme)
1647{
1648 free_irq(jme->pdev->irq, jme->dev);
1649 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1650 pci_disable_msi(jme->pdev);
1651 clear_bit(JME_FLAG_MSI, &jme->flags);
1652 jme->dev->irq = jme->pdev->irq;
1653 }
1654}
1655
1656static inline void
1657jme_new_phy_on(struct jme_adapter *jme)
1658{
1659 u32 reg;
1660
1661 reg = jread32(jme, JME_PHY_PWR);
1662 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1663 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1664 jwrite32(jme, JME_PHY_PWR, reg);
1665
1666 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1667 reg &= ~PE1_GPREG0_PBG;
1668 reg |= PE1_GPREG0_ENBG;
1669 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1670}
1671
1672static inline void
1673jme_new_phy_off(struct jme_adapter *jme)
1674{
1675 u32 reg;
1676
1677 reg = jread32(jme, JME_PHY_PWR);
1678 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1679 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1680 jwrite32(jme, JME_PHY_PWR, reg);
1681
1682 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1683 reg &= ~PE1_GPREG0_PBG;
1684 reg |= PE1_GPREG0_PDD3COLD;
1685 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1686}
1687
1688static inline void
1689jme_phy_on(struct jme_adapter *jme)
1690{
1691 u32 bmcr;
1692
1693 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1694 bmcr &= ~BMCR_PDOWN;
1695 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1696
1697 if (new_phy_power_ctrl(jme->chip_main_rev))
1698 jme_new_phy_on(jme);
1699}
1700
1701static inline void
1702jme_phy_off(struct jme_adapter *jme)
1703{
1704 u32 bmcr;
1705
1706 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1707 bmcr |= BMCR_PDOWN;
1708 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1709
1710 if (new_phy_power_ctrl(jme->chip_main_rev))
1711 jme_new_phy_off(jme);
1712}
1713
1714static int
1715jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1716{
1717 u32 phy_addr;
1718
1719 phy_addr = JM_PHY_SPEC_REG_READ | specreg;
1720 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1721 phy_addr);
1722 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1723 JM_PHY_SPEC_DATA_REG);
1724}
1725
1726static void
1727jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1728{
1729 u32 phy_addr;
1730
1731 phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg;
1732 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1733 phy_data);
1734 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1735 phy_addr);
1736}
1737
1738static int
1739jme_phy_calibration(struct jme_adapter *jme)
1740{
1741 u32 ctrl1000, phy_data;
1742
1743 jme_phy_off(jme);
1744 jme_phy_on(jme);
1745 /* Enabel PHY test mode 1 */
1746 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1747 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1748 ctrl1000 |= PHY_GAD_TEST_MODE_1;
1749 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1750
1751 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1752 phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0;
1753 phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH |
1754 JM_PHY_EXT_COMM_2_CALI_ENABLE;
1755 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1756 msleep(20);
1757 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1758 phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE |
1759 JM_PHY_EXT_COMM_2_CALI_MODE_0 |
1760 JM_PHY_EXT_COMM_2_CALI_LATCH);
1761 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1762
1763 /* Disable PHY test mode */
1764 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1765 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1766 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1767 return 0;
1768}
1769
1770static int
1771jme_phy_setEA(struct jme_adapter *jme)
1772{
1773 u32 phy_comm0 = 0, phy_comm1 = 0;
1774 u8 nic_ctrl;
1775
1776 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1777 if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE)
1778 return 0;
1779
1780 switch (jme->pdev->device) {
1781 case PCI_DEVICE_ID_JMICRON_JMC250:
1782 if (((jme->chip_main_rev == 5) &&
1783 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1784 (jme->chip_sub_rev == 3))) ||
1785 (jme->chip_main_rev >= 6)) {
1786 phy_comm0 = 0x008A;
1787 phy_comm1 = 0x4109;
1788 }
1789 if ((jme->chip_main_rev == 3) &&
1790 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1791 phy_comm0 = 0xE088;
1792 break;
1793 case PCI_DEVICE_ID_JMICRON_JMC260:
1794 if (((jme->chip_main_rev == 5) &&
1795 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1796 (jme->chip_sub_rev == 3))) ||
1797 (jme->chip_main_rev >= 6)) {
1798 phy_comm0 = 0x008A;
1799 phy_comm1 = 0x4109;
1800 }
1801 if ((jme->chip_main_rev == 3) &&
1802 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1803 phy_comm0 = 0xE088;
1804 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1805 phy_comm0 = 0x608A;
1806 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1807 phy_comm0 = 0x408A;
1808 break;
1809 default:
1810 return -ENODEV;
1811 }
1812 if (phy_comm0)
1813 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1814 if (phy_comm1)
1815 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1816
1817 return 0;
1818}
1819
1820static int
1821jme_open(struct net_device *netdev)
1822{
1823 struct jme_adapter *jme = netdev_priv(netdev);
1824 int rc;
1825
1826 jme_clear_pm_disable_wol(jme);
1827 JME_NAPI_ENABLE(jme);
1828
1829 tasklet_setup(&jme->txclean_task, jme_tx_clean_tasklet);
1830 tasklet_setup(&jme->rxclean_task, jme_rx_clean_tasklet);
1831 tasklet_setup(&jme->rxempty_task, jme_rx_empty_tasklet);
1832
1833 rc = jme_request_irq(jme);
1834 if (rc)
1835 goto err_out;
1836
1837 jme_start_irq(jme);
1838
1839 jme_phy_on(jme);
1840 if (test_bit(JME_FLAG_SSET, &jme->flags))
1841 jme_set_link_ksettings(netdev, &jme->old_cmd);
1842 else
1843 jme_reset_phy_processor(jme);
1844 jme_phy_calibration(jme);
1845 jme_phy_setEA(jme);
1846 jme_reset_link(jme);
1847
1848 return 0;
1849
1850err_out:
1851 netif_stop_queue(netdev);
1852 netif_carrier_off(netdev);
1853 return rc;
1854}
1855
1856static void
1857jme_set_100m_half(struct jme_adapter *jme)
1858{
1859 u32 bmcr, tmp;
1860
1861 jme_phy_on(jme);
1862 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1863 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1864 BMCR_SPEED1000 | BMCR_FULLDPLX);
1865 tmp |= BMCR_SPEED100;
1866
1867 if (bmcr != tmp)
1868 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1869
1870 if (jme->fpgaver)
1871 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1872 else
1873 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1874}
1875
1876#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1877static void
1878jme_wait_link(struct jme_adapter *jme)
1879{
1880 u32 phylink, to = JME_WAIT_LINK_TIME;
1881
1882 msleep(1000);
1883 phylink = jme_linkstat_from_phy(jme);
1884 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1885 usleep_range(10000, 11000);
1886 phylink = jme_linkstat_from_phy(jme);
1887 }
1888}
1889
1890static void
1891jme_powersave_phy(struct jme_adapter *jme)
1892{
1893 if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) {
1894 jme_set_100m_half(jme);
1895 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1896 jme_wait_link(jme);
1897 jme_clear_pm_enable_wol(jme);
1898 } else {
1899 jme_phy_off(jme);
1900 }
1901}
1902
1903static int
1904jme_close(struct net_device *netdev)
1905{
1906 struct jme_adapter *jme = netdev_priv(netdev);
1907
1908 netif_stop_queue(netdev);
1909 netif_carrier_off(netdev);
1910
1911 jme_stop_irq(jme);
1912 jme_free_irq(jme);
1913
1914 JME_NAPI_DISABLE(jme);
1915
1916 cancel_work_sync(&jme->linkch_task);
1917 tasklet_kill(&jme->txclean_task);
1918 tasklet_kill(&jme->rxclean_task);
1919 tasklet_kill(&jme->rxempty_task);
1920
1921 jme_disable_rx_engine(jme);
1922 jme_disable_tx_engine(jme);
1923 jme_reset_mac_processor(jme);
1924 jme_free_rx_resources(jme);
1925 jme_free_tx_resources(jme);
1926 jme->phylink = 0;
1927 jme_phy_off(jme);
1928
1929 return 0;
1930}
1931
1932static int
1933jme_alloc_txdesc(struct jme_adapter *jme,
1934 struct sk_buff *skb)
1935{
1936 struct jme_ring *txring = &(jme->txring[0]);
1937 int idx, nr_alloc, mask = jme->tx_ring_mask;
1938
1939 idx = txring->next_to_use;
1940 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1941
1942 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1943 return -1;
1944
1945 atomic_sub(nr_alloc, &txring->nr_free);
1946
1947 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1948
1949 return idx;
1950}
1951
1952static int
1953jme_fill_tx_map(struct pci_dev *pdev,
1954 struct txdesc *txdesc,
1955 struct jme_buffer_info *txbi,
1956 struct page *page,
1957 u32 page_offset,
1958 u32 len,
1959 bool hidma)
1960{
1961 dma_addr_t dmaaddr;
1962
1963 dmaaddr = dma_map_page(&pdev->dev, page, page_offset, len,
1964 DMA_TO_DEVICE);
1965
1966 if (unlikely(dma_mapping_error(&pdev->dev, dmaaddr)))
1967 return -EINVAL;
1968
1969 dma_sync_single_for_device(&pdev->dev, dmaaddr, len, DMA_TO_DEVICE);
1970
1971 txdesc->dw[0] = 0;
1972 txdesc->dw[1] = 0;
1973 txdesc->desc2.flags = TXFLAG_OWN;
1974 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1975 txdesc->desc2.datalen = cpu_to_le16(len);
1976 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1977 txdesc->desc2.bufaddrl = cpu_to_le32(
1978 (__u64)dmaaddr & 0xFFFFFFFFUL);
1979
1980 txbi->mapping = dmaaddr;
1981 txbi->len = len;
1982 return 0;
1983}
1984
1985static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count)
1986{
1987 struct jme_ring *txring = &(jme->txring[0]);
1988 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1989 int mask = jme->tx_ring_mask;
1990 int j;
1991
1992 for (j = 0 ; j < count ; j++) {
1993 ctxbi = txbi + ((startidx + j + 2) & (mask));
1994 dma_unmap_page(&jme->pdev->dev, ctxbi->mapping, ctxbi->len,
1995 DMA_TO_DEVICE);
1996
1997 ctxbi->mapping = 0;
1998 ctxbi->len = 0;
1999 }
2000}
2001
2002static int
2003jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2004{
2005 struct jme_ring *txring = &(jme->txring[0]);
2006 struct txdesc *txdesc = txring->desc, *ctxdesc;
2007 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2008 bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
2009 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2010 int mask = jme->tx_ring_mask;
2011 u32 len;
2012 int ret = 0;
2013
2014 for (i = 0 ; i < nr_frags ; ++i) {
2015 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2016
2017 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2018 ctxbi = txbi + ((idx + i + 2) & (mask));
2019
2020 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2021 skb_frag_page(frag), skb_frag_off(frag),
2022 skb_frag_size(frag), hidma);
2023 if (ret) {
2024 jme_drop_tx_map(jme, idx, i);
2025 goto out;
2026 }
2027 }
2028
2029 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2030 ctxdesc = txdesc + ((idx + 1) & (mask));
2031 ctxbi = txbi + ((idx + 1) & (mask));
2032 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2033 offset_in_page(skb->data), len, hidma);
2034 if (ret)
2035 jme_drop_tx_map(jme, idx, i);
2036
2037out:
2038 return ret;
2039
2040}
2041
2042
2043static int
2044jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2045{
2046 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2047 if (*mss) {
2048 *flags |= TXFLAG_LSEN;
2049
2050 if (skb->protocol == htons(ETH_P_IP)) {
2051 struct iphdr *iph = ip_hdr(skb);
2052
2053 iph->check = 0;
2054 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2055 iph->daddr, 0,
2056 IPPROTO_TCP,
2057 0);
2058 } else {
2059 tcp_v6_gso_csum_prep(skb);
2060 }
2061
2062 return 0;
2063 }
2064
2065 return 1;
2066}
2067
2068static void
2069jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2070{
2071 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2072 u8 ip_proto;
2073
2074 switch (skb->protocol) {
2075 case htons(ETH_P_IP):
2076 ip_proto = ip_hdr(skb)->protocol;
2077 break;
2078 case htons(ETH_P_IPV6):
2079 ip_proto = ipv6_hdr(skb)->nexthdr;
2080 break;
2081 default:
2082 ip_proto = 0;
2083 break;
2084 }
2085
2086 switch (ip_proto) {
2087 case IPPROTO_TCP:
2088 *flags |= TXFLAG_TCPCS;
2089 break;
2090 case IPPROTO_UDP:
2091 *flags |= TXFLAG_UDPCS;
2092 break;
2093 default:
2094 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2095 break;
2096 }
2097 }
2098}
2099
2100static inline void
2101jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2102{
2103 if (skb_vlan_tag_present(skb)) {
2104 *flags |= TXFLAG_TAGON;
2105 *vlan = cpu_to_le16(skb_vlan_tag_get(skb));
2106 }
2107}
2108
2109static int
2110jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2111{
2112 struct jme_ring *txring = &(jme->txring[0]);
2113 struct txdesc *txdesc;
2114 struct jme_buffer_info *txbi;
2115 u8 flags;
2116 int ret = 0;
2117
2118 txdesc = (struct txdesc *)txring->desc + idx;
2119 txbi = txring->bufinf + idx;
2120
2121 txdesc->dw[0] = 0;
2122 txdesc->dw[1] = 0;
2123 txdesc->dw[2] = 0;
2124 txdesc->dw[3] = 0;
2125 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2126 /*
2127 * Set OWN bit at final.
2128 * When kernel transmit faster than NIC.
2129 * And NIC trying to send this descriptor before we tell
2130 * it to start sending this TX queue.
2131 * Other fields are already filled correctly.
2132 */
2133 wmb();
2134 flags = TXFLAG_OWN | TXFLAG_INT;
2135 /*
2136 * Set checksum flags while not tso
2137 */
2138 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2139 jme_tx_csum(jme, skb, &flags);
2140 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2141 ret = jme_map_tx_skb(jme, skb, idx);
2142 if (ret)
2143 return ret;
2144
2145 txdesc->desc1.flags = flags;
2146 /*
2147 * Set tx buffer info after telling NIC to send
2148 * For better tx_clean timing
2149 */
2150 wmb();
2151 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2152 txbi->skb = skb;
2153 txbi->len = skb->len;
2154 txbi->start_xmit = jiffies;
2155 if (!txbi->start_xmit)
2156 txbi->start_xmit = (0UL-1);
2157
2158 return 0;
2159}
2160
2161static void
2162jme_stop_queue_if_full(struct jme_adapter *jme)
2163{
2164 struct jme_ring *txring = &(jme->txring[0]);
2165 struct jme_buffer_info *txbi = txring->bufinf;
2166 int idx = atomic_read(&txring->next_to_clean);
2167
2168 txbi += idx;
2169
2170 smp_wmb();
2171 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2172 netif_stop_queue(jme->dev);
2173 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2174 smp_wmb();
2175 if (atomic_read(&txring->nr_free)
2176 >= (jme->tx_wake_threshold)) {
2177 netif_wake_queue(jme->dev);
2178 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2179 }
2180 }
2181
2182 if (unlikely(txbi->start_xmit &&
2183 time_is_before_eq_jiffies(txbi->start_xmit + TX_TIMEOUT) &&
2184 txbi->skb)) {
2185 netif_stop_queue(jme->dev);
2186 netif_info(jme, tx_queued, jme->dev,
2187 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2188 }
2189}
2190
2191/*
2192 * This function is already protected by netif_tx_lock()
2193 */
2194
2195static netdev_tx_t
2196jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2197{
2198 struct jme_adapter *jme = netdev_priv(netdev);
2199 int idx;
2200
2201 if (unlikely(skb_is_gso(skb) && skb_cow_head(skb, 0))) {
2202 dev_kfree_skb_any(skb);
2203 ++(NET_STAT(jme).tx_dropped);
2204 return NETDEV_TX_OK;
2205 }
2206
2207 idx = jme_alloc_txdesc(jme, skb);
2208
2209 if (unlikely(idx < 0)) {
2210 netif_stop_queue(netdev);
2211 netif_err(jme, tx_err, jme->dev,
2212 "BUG! Tx ring full when queue awake!\n");
2213
2214 return NETDEV_TX_BUSY;
2215 }
2216
2217 if (jme_fill_tx_desc(jme, skb, idx))
2218 return NETDEV_TX_OK;
2219
2220 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2221 TXCS_SELECT_QUEUE0 |
2222 TXCS_QUEUE0S |
2223 TXCS_ENABLE);
2224
2225 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2226 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2227 jme_stop_queue_if_full(jme);
2228
2229 return NETDEV_TX_OK;
2230}
2231
2232static void
2233jme_set_unicastaddr(struct net_device *netdev)
2234{
2235 struct jme_adapter *jme = netdev_priv(netdev);
2236 u32 val;
2237
2238 val = (netdev->dev_addr[3] & 0xff) << 24 |
2239 (netdev->dev_addr[2] & 0xff) << 16 |
2240 (netdev->dev_addr[1] & 0xff) << 8 |
2241 (netdev->dev_addr[0] & 0xff);
2242 jwrite32(jme, JME_RXUMA_LO, val);
2243 val = (netdev->dev_addr[5] & 0xff) << 8 |
2244 (netdev->dev_addr[4] & 0xff);
2245 jwrite32(jme, JME_RXUMA_HI, val);
2246}
2247
2248static int
2249jme_set_macaddr(struct net_device *netdev, void *p)
2250{
2251 struct jme_adapter *jme = netdev_priv(netdev);
2252 struct sockaddr *addr = p;
2253
2254 if (netif_running(netdev))
2255 return -EBUSY;
2256
2257 spin_lock_bh(&jme->macaddr_lock);
2258 eth_hw_addr_set(netdev, addr->sa_data);
2259 jme_set_unicastaddr(netdev);
2260 spin_unlock_bh(&jme->macaddr_lock);
2261
2262 return 0;
2263}
2264
2265static void
2266jme_set_multi(struct net_device *netdev)
2267{
2268 struct jme_adapter *jme = netdev_priv(netdev);
2269 u32 mc_hash[2] = {};
2270
2271 spin_lock_bh(&jme->rxmcs_lock);
2272
2273 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2274
2275 if (netdev->flags & IFF_PROMISC) {
2276 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2277 } else if (netdev->flags & IFF_ALLMULTI) {
2278 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2279 } else if (netdev->flags & IFF_MULTICAST) {
2280 struct netdev_hw_addr *ha;
2281 int bit_nr;
2282
2283 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2284 netdev_for_each_mc_addr(ha, netdev) {
2285 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2286 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2287 }
2288
2289 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2290 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2291 }
2292
2293 wmb();
2294 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2295
2296 spin_unlock_bh(&jme->rxmcs_lock);
2297}
2298
2299static int
2300jme_change_mtu(struct net_device *netdev, int new_mtu)
2301{
2302 struct jme_adapter *jme = netdev_priv(netdev);
2303
2304 netdev->mtu = new_mtu;
2305 netdev_update_features(netdev);
2306
2307 jme_restart_rx_engine(jme);
2308 jme_reset_link(jme);
2309
2310 return 0;
2311}
2312
2313static void
2314jme_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2315{
2316 struct jme_adapter *jme = netdev_priv(netdev);
2317
2318 jme->phylink = 0;
2319 jme_reset_phy_processor(jme);
2320 if (test_bit(JME_FLAG_SSET, &jme->flags))
2321 jme_set_link_ksettings(netdev, &jme->old_cmd);
2322
2323 /*
2324 * Force to Reset the link again
2325 */
2326 jme_reset_link(jme);
2327}
2328
2329static void
2330jme_get_drvinfo(struct net_device *netdev,
2331 struct ethtool_drvinfo *info)
2332{
2333 struct jme_adapter *jme = netdev_priv(netdev);
2334
2335 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
2336 strscpy(info->version, DRV_VERSION, sizeof(info->version));
2337 strscpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
2338}
2339
2340static int
2341jme_get_regs_len(struct net_device *netdev)
2342{
2343 return JME_REG_LEN;
2344}
2345
2346static void
2347mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2348{
2349 int i;
2350
2351 for (i = 0 ; i < len ; i += 4)
2352 p[i >> 2] = jread32(jme, reg + i);
2353}
2354
2355static void
2356mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2357{
2358 int i;
2359 u16 *p16 = (u16 *)p;
2360
2361 for (i = 0 ; i < reg_nr ; ++i)
2362 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2363}
2364
2365static void
2366jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2367{
2368 struct jme_adapter *jme = netdev_priv(netdev);
2369 u32 *p32 = (u32 *)p;
2370
2371 memset(p, 0xFF, JME_REG_LEN);
2372
2373 regs->version = 1;
2374 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2375
2376 p32 += 0x100 >> 2;
2377 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2378
2379 p32 += 0x100 >> 2;
2380 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2381
2382 p32 += 0x100 >> 2;
2383 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2384
2385 p32 += 0x100 >> 2;
2386 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2387}
2388
2389static int jme_get_coalesce(struct net_device *netdev,
2390 struct ethtool_coalesce *ecmd,
2391 struct kernel_ethtool_coalesce *kernel_coal,
2392 struct netlink_ext_ack *extack)
2393{
2394 struct jme_adapter *jme = netdev_priv(netdev);
2395
2396 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2397 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2398
2399 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2400 ecmd->use_adaptive_rx_coalesce = false;
2401 ecmd->rx_coalesce_usecs = 0;
2402 ecmd->rx_max_coalesced_frames = 0;
2403 return 0;
2404 }
2405
2406 ecmd->use_adaptive_rx_coalesce = true;
2407
2408 switch (jme->dpi.cur) {
2409 case PCC_P1:
2410 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2411 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2412 break;
2413 case PCC_P2:
2414 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2415 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2416 break;
2417 case PCC_P3:
2418 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2419 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2420 break;
2421 default:
2422 break;
2423 }
2424
2425 return 0;
2426}
2427
2428static int jme_set_coalesce(struct net_device *netdev,
2429 struct ethtool_coalesce *ecmd,
2430 struct kernel_ethtool_coalesce *kernel_coal,
2431 struct netlink_ext_ack *extack)
2432{
2433 struct jme_adapter *jme = netdev_priv(netdev);
2434 struct dynpcc_info *dpi = &(jme->dpi);
2435
2436 if (netif_running(netdev))
2437 return -EBUSY;
2438
2439 if (ecmd->use_adaptive_rx_coalesce &&
2440 test_bit(JME_FLAG_POLL, &jme->flags)) {
2441 clear_bit(JME_FLAG_POLL, &jme->flags);
2442 jme->jme_rx = netif_rx;
2443 dpi->cur = PCC_P1;
2444 dpi->attempt = PCC_P1;
2445 dpi->cnt = 0;
2446 jme_set_rx_pcc(jme, PCC_P1);
2447 jme_interrupt_mode(jme);
2448 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2449 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2450 set_bit(JME_FLAG_POLL, &jme->flags);
2451 jme->jme_rx = netif_receive_skb;
2452 jme_interrupt_mode(jme);
2453 }
2454
2455 return 0;
2456}
2457
2458static void
2459jme_get_pauseparam(struct net_device *netdev,
2460 struct ethtool_pauseparam *ecmd)
2461{
2462 struct jme_adapter *jme = netdev_priv(netdev);
2463 u32 val;
2464
2465 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2466 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2467
2468 spin_lock_bh(&jme->phy_lock);
2469 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2470 spin_unlock_bh(&jme->phy_lock);
2471
2472 ecmd->autoneg =
2473 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2474}
2475
2476static int
2477jme_set_pauseparam(struct net_device *netdev,
2478 struct ethtool_pauseparam *ecmd)
2479{
2480 struct jme_adapter *jme = netdev_priv(netdev);
2481 u32 val;
2482
2483 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2484 (ecmd->tx_pause != 0)) {
2485
2486 if (ecmd->tx_pause)
2487 jme->reg_txpfc |= TXPFC_PF_EN;
2488 else
2489 jme->reg_txpfc &= ~TXPFC_PF_EN;
2490
2491 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2492 }
2493
2494 spin_lock_bh(&jme->rxmcs_lock);
2495 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2496 (ecmd->rx_pause != 0)) {
2497
2498 if (ecmd->rx_pause)
2499 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2500 else
2501 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2502
2503 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2504 }
2505 spin_unlock_bh(&jme->rxmcs_lock);
2506
2507 spin_lock_bh(&jme->phy_lock);
2508 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2509 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2510 (ecmd->autoneg != 0)) {
2511
2512 if (ecmd->autoneg)
2513 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2514 else
2515 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2516
2517 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2518 MII_ADVERTISE, val);
2519 }
2520 spin_unlock_bh(&jme->phy_lock);
2521
2522 return 0;
2523}
2524
2525static void
2526jme_get_wol(struct net_device *netdev,
2527 struct ethtool_wolinfo *wol)
2528{
2529 struct jme_adapter *jme = netdev_priv(netdev);
2530
2531 wol->supported = WAKE_MAGIC | WAKE_PHY;
2532
2533 wol->wolopts = 0;
2534
2535 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2536 wol->wolopts |= WAKE_PHY;
2537
2538 if (jme->reg_pmcs & PMCS_MFEN)
2539 wol->wolopts |= WAKE_MAGIC;
2540
2541}
2542
2543static int
2544jme_set_wol(struct net_device *netdev,
2545 struct ethtool_wolinfo *wol)
2546{
2547 struct jme_adapter *jme = netdev_priv(netdev);
2548
2549 if (wol->wolopts & (WAKE_MAGICSECURE |
2550 WAKE_UCAST |
2551 WAKE_MCAST |
2552 WAKE_BCAST |
2553 WAKE_ARP))
2554 return -EOPNOTSUPP;
2555
2556 jme->reg_pmcs = 0;
2557
2558 if (wol->wolopts & WAKE_PHY)
2559 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2560
2561 if (wol->wolopts & WAKE_MAGIC)
2562 jme->reg_pmcs |= PMCS_MFEN;
2563
2564 return 0;
2565}
2566
2567static int
2568jme_get_link_ksettings(struct net_device *netdev,
2569 struct ethtool_link_ksettings *cmd)
2570{
2571 struct jme_adapter *jme = netdev_priv(netdev);
2572
2573 spin_lock_bh(&jme->phy_lock);
2574 mii_ethtool_get_link_ksettings(&jme->mii_if, cmd);
2575 spin_unlock_bh(&jme->phy_lock);
2576 return 0;
2577}
2578
2579static int
2580jme_set_link_ksettings(struct net_device *netdev,
2581 const struct ethtool_link_ksettings *cmd)
2582{
2583 struct jme_adapter *jme = netdev_priv(netdev);
2584 int rc, fdc = 0;
2585
2586 if (cmd->base.speed == SPEED_1000 &&
2587 cmd->base.autoneg != AUTONEG_ENABLE)
2588 return -EINVAL;
2589
2590 /*
2591 * Check If user changed duplex only while force_media.
2592 * Hardware would not generate link change interrupt.
2593 */
2594 if (jme->mii_if.force_media &&
2595 cmd->base.autoneg != AUTONEG_ENABLE &&
2596 (jme->mii_if.full_duplex != cmd->base.duplex))
2597 fdc = 1;
2598
2599 spin_lock_bh(&jme->phy_lock);
2600 rc = mii_ethtool_set_link_ksettings(&jme->mii_if, cmd);
2601 spin_unlock_bh(&jme->phy_lock);
2602
2603 if (!rc) {
2604 if (fdc)
2605 jme_reset_link(jme);
2606 jme->old_cmd = *cmd;
2607 set_bit(JME_FLAG_SSET, &jme->flags);
2608 }
2609
2610 return rc;
2611}
2612
2613static int
2614jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2615{
2616 int rc;
2617 struct jme_adapter *jme = netdev_priv(netdev);
2618 struct mii_ioctl_data *mii_data = if_mii(rq);
2619 unsigned int duplex_chg;
2620
2621 if (cmd == SIOCSMIIREG) {
2622 u16 val = mii_data->val_in;
2623 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2624 (val & BMCR_SPEED1000))
2625 return -EINVAL;
2626 }
2627
2628 spin_lock_bh(&jme->phy_lock);
2629 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2630 spin_unlock_bh(&jme->phy_lock);
2631
2632 if (!rc && (cmd == SIOCSMIIREG)) {
2633 if (duplex_chg)
2634 jme_reset_link(jme);
2635 jme_get_link_ksettings(netdev, &jme->old_cmd);
2636 set_bit(JME_FLAG_SSET, &jme->flags);
2637 }
2638
2639 return rc;
2640}
2641
2642static u32
2643jme_get_link(struct net_device *netdev)
2644{
2645 struct jme_adapter *jme = netdev_priv(netdev);
2646 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2647}
2648
2649static u32
2650jme_get_msglevel(struct net_device *netdev)
2651{
2652 struct jme_adapter *jme = netdev_priv(netdev);
2653 return jme->msg_enable;
2654}
2655
2656static void
2657jme_set_msglevel(struct net_device *netdev, u32 value)
2658{
2659 struct jme_adapter *jme = netdev_priv(netdev);
2660 jme->msg_enable = value;
2661}
2662
2663static netdev_features_t
2664jme_fix_features(struct net_device *netdev, netdev_features_t features)
2665{
2666 if (netdev->mtu > 1900)
2667 features &= ~(NETIF_F_ALL_TSO | NETIF_F_CSUM_MASK);
2668 return features;
2669}
2670
2671static int
2672jme_set_features(struct net_device *netdev, netdev_features_t features)
2673{
2674 struct jme_adapter *jme = netdev_priv(netdev);
2675
2676 spin_lock_bh(&jme->rxmcs_lock);
2677 if (features & NETIF_F_RXCSUM)
2678 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2679 else
2680 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2681 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2682 spin_unlock_bh(&jme->rxmcs_lock);
2683
2684 return 0;
2685}
2686
2687#ifdef CONFIG_NET_POLL_CONTROLLER
2688static void jme_netpoll(struct net_device *dev)
2689{
2690 unsigned long flags;
2691
2692 local_irq_save(flags);
2693 jme_intr(dev->irq, dev);
2694 local_irq_restore(flags);
2695}
2696#endif
2697
2698static int
2699jme_nway_reset(struct net_device *netdev)
2700{
2701 struct jme_adapter *jme = netdev_priv(netdev);
2702 jme_restart_an(jme);
2703 return 0;
2704}
2705
2706static u8
2707jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2708{
2709 u32 val;
2710 int to;
2711
2712 val = jread32(jme, JME_SMBCSR);
2713 to = JME_SMB_BUSY_TIMEOUT;
2714 while ((val & SMBCSR_BUSY) && --to) {
2715 msleep(1);
2716 val = jread32(jme, JME_SMBCSR);
2717 }
2718 if (!to) {
2719 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2720 return 0xFF;
2721 }
2722
2723 jwrite32(jme, JME_SMBINTF,
2724 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2725 SMBINTF_HWRWN_READ |
2726 SMBINTF_HWCMD);
2727
2728 val = jread32(jme, JME_SMBINTF);
2729 to = JME_SMB_BUSY_TIMEOUT;
2730 while ((val & SMBINTF_HWCMD) && --to) {
2731 msleep(1);
2732 val = jread32(jme, JME_SMBINTF);
2733 }
2734 if (!to) {
2735 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2736 return 0xFF;
2737 }
2738
2739 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2740}
2741
2742static void
2743jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2744{
2745 u32 val;
2746 int to;
2747
2748 val = jread32(jme, JME_SMBCSR);
2749 to = JME_SMB_BUSY_TIMEOUT;
2750 while ((val & SMBCSR_BUSY) && --to) {
2751 msleep(1);
2752 val = jread32(jme, JME_SMBCSR);
2753 }
2754 if (!to) {
2755 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2756 return;
2757 }
2758
2759 jwrite32(jme, JME_SMBINTF,
2760 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2761 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2762 SMBINTF_HWRWN_WRITE |
2763 SMBINTF_HWCMD);
2764
2765 val = jread32(jme, JME_SMBINTF);
2766 to = JME_SMB_BUSY_TIMEOUT;
2767 while ((val & SMBINTF_HWCMD) && --to) {
2768 msleep(1);
2769 val = jread32(jme, JME_SMBINTF);
2770 }
2771 if (!to) {
2772 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2773 return;
2774 }
2775
2776 mdelay(2);
2777}
2778
2779static int
2780jme_get_eeprom_len(struct net_device *netdev)
2781{
2782 struct jme_adapter *jme = netdev_priv(netdev);
2783 u32 val;
2784 val = jread32(jme, JME_SMBCSR);
2785 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2786}
2787
2788static int
2789jme_get_eeprom(struct net_device *netdev,
2790 struct ethtool_eeprom *eeprom, u8 *data)
2791{
2792 struct jme_adapter *jme = netdev_priv(netdev);
2793 int i, offset = eeprom->offset, len = eeprom->len;
2794
2795 /*
2796 * ethtool will check the boundary for us
2797 */
2798 eeprom->magic = JME_EEPROM_MAGIC;
2799 for (i = 0 ; i < len ; ++i)
2800 data[i] = jme_smb_read(jme, i + offset);
2801
2802 return 0;
2803}
2804
2805static int
2806jme_set_eeprom(struct net_device *netdev,
2807 struct ethtool_eeprom *eeprom, u8 *data)
2808{
2809 struct jme_adapter *jme = netdev_priv(netdev);
2810 int i, offset = eeprom->offset, len = eeprom->len;
2811
2812 if (eeprom->magic != JME_EEPROM_MAGIC)
2813 return -EINVAL;
2814
2815 /*
2816 * ethtool will check the boundary for us
2817 */
2818 for (i = 0 ; i < len ; ++i)
2819 jme_smb_write(jme, i + offset, data[i]);
2820
2821 return 0;
2822}
2823
2824static const struct ethtool_ops jme_ethtool_ops = {
2825 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2826 ETHTOOL_COALESCE_MAX_FRAMES |
2827 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
2828 .get_drvinfo = jme_get_drvinfo,
2829 .get_regs_len = jme_get_regs_len,
2830 .get_regs = jme_get_regs,
2831 .get_coalesce = jme_get_coalesce,
2832 .set_coalesce = jme_set_coalesce,
2833 .get_pauseparam = jme_get_pauseparam,
2834 .set_pauseparam = jme_set_pauseparam,
2835 .get_wol = jme_get_wol,
2836 .set_wol = jme_set_wol,
2837 .get_link = jme_get_link,
2838 .get_msglevel = jme_get_msglevel,
2839 .set_msglevel = jme_set_msglevel,
2840 .nway_reset = jme_nway_reset,
2841 .get_eeprom_len = jme_get_eeprom_len,
2842 .get_eeprom = jme_get_eeprom,
2843 .set_eeprom = jme_set_eeprom,
2844 .get_link_ksettings = jme_get_link_ksettings,
2845 .set_link_ksettings = jme_set_link_ksettings,
2846};
2847
2848static int
2849jme_pci_dma64(struct pci_dev *pdev)
2850{
2851 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2852 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
2853 return 1;
2854
2855 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2856 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)))
2857 return 1;
2858
2859 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2860 return 0;
2861
2862 return -1;
2863}
2864
2865static inline void
2866jme_phy_init(struct jme_adapter *jme)
2867{
2868 u16 reg26;
2869
2870 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2871 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2872}
2873
2874static inline void
2875jme_check_hw_ver(struct jme_adapter *jme)
2876{
2877 u32 chipmode;
2878
2879 chipmode = jread32(jme, JME_CHIPMODE);
2880
2881 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2882 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2883 jme->chip_main_rev = jme->chiprev & 0xF;
2884 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2885}
2886
2887static const struct net_device_ops jme_netdev_ops = {
2888 .ndo_open = jme_open,
2889 .ndo_stop = jme_close,
2890 .ndo_validate_addr = eth_validate_addr,
2891 .ndo_eth_ioctl = jme_ioctl,
2892 .ndo_start_xmit = jme_start_xmit,
2893 .ndo_set_mac_address = jme_set_macaddr,
2894 .ndo_set_rx_mode = jme_set_multi,
2895 .ndo_change_mtu = jme_change_mtu,
2896 .ndo_tx_timeout = jme_tx_timeout,
2897 .ndo_fix_features = jme_fix_features,
2898 .ndo_set_features = jme_set_features,
2899#ifdef CONFIG_NET_POLL_CONTROLLER
2900 .ndo_poll_controller = jme_netpoll,
2901#endif
2902};
2903
2904static int
2905jme_init_one(struct pci_dev *pdev,
2906 const struct pci_device_id *ent)
2907{
2908 int rc = 0, using_dac, i;
2909 struct net_device *netdev;
2910 struct jme_adapter *jme;
2911 u16 bmcr, bmsr;
2912 u32 apmc;
2913
2914 /*
2915 * set up PCI device basics
2916 */
2917 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2918 PCIE_LINK_STATE_CLKPM);
2919
2920 rc = pci_enable_device(pdev);
2921 if (rc) {
2922 pr_err("Cannot enable PCI device\n");
2923 goto err_out;
2924 }
2925
2926 using_dac = jme_pci_dma64(pdev);
2927 if (using_dac < 0) {
2928 pr_err("Cannot set PCI DMA Mask\n");
2929 rc = -EIO;
2930 goto err_out_disable_pdev;
2931 }
2932
2933 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2934 pr_err("No PCI resource region found\n");
2935 rc = -ENOMEM;
2936 goto err_out_disable_pdev;
2937 }
2938
2939 rc = pci_request_regions(pdev, DRV_NAME);
2940 if (rc) {
2941 pr_err("Cannot obtain PCI resource region\n");
2942 goto err_out_disable_pdev;
2943 }
2944
2945 pci_set_master(pdev);
2946
2947 /*
2948 * alloc and init net device
2949 */
2950 netdev = alloc_etherdev(sizeof(*jme));
2951 if (!netdev) {
2952 rc = -ENOMEM;
2953 goto err_out_release_regions;
2954 }
2955 netdev->netdev_ops = &jme_netdev_ops;
2956 netdev->ethtool_ops = &jme_ethtool_ops;
2957 netdev->watchdog_timeo = TX_TIMEOUT;
2958 netdev->hw_features = NETIF_F_IP_CSUM |
2959 NETIF_F_IPV6_CSUM |
2960 NETIF_F_SG |
2961 NETIF_F_TSO |
2962 NETIF_F_TSO6 |
2963 NETIF_F_RXCSUM;
2964 netdev->features = NETIF_F_IP_CSUM |
2965 NETIF_F_IPV6_CSUM |
2966 NETIF_F_SG |
2967 NETIF_F_TSO |
2968 NETIF_F_TSO6 |
2969 NETIF_F_HW_VLAN_CTAG_TX |
2970 NETIF_F_HW_VLAN_CTAG_RX;
2971 if (using_dac)
2972 netdev->features |= NETIF_F_HIGHDMA;
2973
2974 /* MTU range: 1280 - 9202*/
2975 netdev->min_mtu = IPV6_MIN_MTU;
2976 netdev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE - ETH_HLEN;
2977
2978 SET_NETDEV_DEV(netdev, &pdev->dev);
2979 pci_set_drvdata(pdev, netdev);
2980
2981 /*
2982 * init adapter info
2983 */
2984 jme = netdev_priv(netdev);
2985 jme->pdev = pdev;
2986 jme->dev = netdev;
2987 jme->jme_rx = netif_rx;
2988 jme->old_mtu = netdev->mtu = 1500;
2989 jme->phylink = 0;
2990 jme->tx_ring_size = 1 << 10;
2991 jme->tx_ring_mask = jme->tx_ring_size - 1;
2992 jme->tx_wake_threshold = 1 << 9;
2993 jme->rx_ring_size = 1 << 9;
2994 jme->rx_ring_mask = jme->rx_ring_size - 1;
2995 jme->msg_enable = JME_DEF_MSG_ENABLE;
2996 jme->regs = ioremap(pci_resource_start(pdev, 0),
2997 pci_resource_len(pdev, 0));
2998 if (!(jme->regs)) {
2999 pr_err("Mapping PCI resource region error\n");
3000 rc = -ENOMEM;
3001 goto err_out_free_netdev;
3002 }
3003
3004 if (no_pseudohp) {
3005 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3006 jwrite32(jme, JME_APMC, apmc);
3007 } else if (force_pseudohp) {
3008 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3009 jwrite32(jme, JME_APMC, apmc);
3010 }
3011
3012 netif_napi_add(netdev, &jme->napi, jme_poll);
3013
3014 spin_lock_init(&jme->phy_lock);
3015 spin_lock_init(&jme->macaddr_lock);
3016 spin_lock_init(&jme->rxmcs_lock);
3017
3018 atomic_set(&jme->link_changing, 1);
3019 atomic_set(&jme->rx_cleaning, 1);
3020 atomic_set(&jme->tx_cleaning, 1);
3021 atomic_set(&jme->rx_empty, 1);
3022
3023 tasklet_setup(&jme->pcc_task, jme_pcc_tasklet);
3024 INIT_WORK(&jme->linkch_task, jme_link_change_work);
3025 jme->dpi.cur = PCC_P1;
3026
3027 jme->reg_ghc = 0;
3028 jme->reg_rxcs = RXCS_DEFAULT;
3029 jme->reg_rxmcs = RXMCS_DEFAULT;
3030 jme->reg_txpfc = 0;
3031 jme->reg_pmcs = PMCS_MFEN;
3032 jme->reg_gpreg1 = GPREG1_DEFAULT;
3033
3034 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3035 netdev->features |= NETIF_F_RXCSUM;
3036
3037 /*
3038 * Get Max Read Req Size from PCI Config Space
3039 */
3040 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3041 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3042 switch (jme->mrrs) {
3043 case MRRS_128B:
3044 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3045 break;
3046 case MRRS_256B:
3047 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3048 break;
3049 default:
3050 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3051 break;
3052 }
3053
3054 /*
3055 * Must check before reset_mac_processor
3056 */
3057 jme_check_hw_ver(jme);
3058 jme->mii_if.dev = netdev;
3059 if (jme->fpgaver) {
3060 jme->mii_if.phy_id = 0;
3061 for (i = 1 ; i < 32 ; ++i) {
3062 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3063 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3064 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3065 jme->mii_if.phy_id = i;
3066 break;
3067 }
3068 }
3069
3070 if (!jme->mii_if.phy_id) {
3071 rc = -EIO;
3072 pr_err("Can not find phy_id\n");
3073 goto err_out_unmap;
3074 }
3075
3076 jme->reg_ghc |= GHC_LINK_POLL;
3077 } else {
3078 jme->mii_if.phy_id = 1;
3079 }
3080 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3081 jme->mii_if.supports_gmii = true;
3082 else
3083 jme->mii_if.supports_gmii = false;
3084 jme->mii_if.phy_id_mask = 0x1F;
3085 jme->mii_if.reg_num_mask = 0x1F;
3086 jme->mii_if.mdio_read = jme_mdio_read;
3087 jme->mii_if.mdio_write = jme_mdio_write;
3088
3089 jme_clear_pm_disable_wol(jme);
3090 device_init_wakeup(&pdev->dev, true);
3091
3092 jme_set_phyfifo_5level(jme);
3093 jme->pcirev = pdev->revision;
3094 if (!jme->fpgaver)
3095 jme_phy_init(jme);
3096 jme_phy_off(jme);
3097
3098 /*
3099 * Reset MAC processor and reload EEPROM for MAC Address
3100 */
3101 jme_reset_mac_processor(jme);
3102 rc = jme_reload_eeprom(jme);
3103 if (rc) {
3104 pr_err("Reload eeprom for reading MAC Address error\n");
3105 goto err_out_unmap;
3106 }
3107 jme_load_macaddr(netdev);
3108
3109 /*
3110 * Tell stack that we are not ready to work until open()
3111 */
3112 netif_carrier_off(netdev);
3113
3114 rc = register_netdev(netdev);
3115 if (rc) {
3116 pr_err("Cannot register net device\n");
3117 goto err_out_unmap;
3118 }
3119
3120 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3121 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3122 "JMC250 Gigabit Ethernet" :
3123 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3124 "JMC260 Fast Ethernet" : "Unknown",
3125 (jme->fpgaver != 0) ? " (FPGA)" : "",
3126 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3127 jme->pcirev, netdev->dev_addr);
3128
3129 return 0;
3130
3131err_out_unmap:
3132 iounmap(jme->regs);
3133err_out_free_netdev:
3134 free_netdev(netdev);
3135err_out_release_regions:
3136 pci_release_regions(pdev);
3137err_out_disable_pdev:
3138 pci_disable_device(pdev);
3139err_out:
3140 return rc;
3141}
3142
3143static void
3144jme_remove_one(struct pci_dev *pdev)
3145{
3146 struct net_device *netdev = pci_get_drvdata(pdev);
3147 struct jme_adapter *jme = netdev_priv(netdev);
3148
3149 unregister_netdev(netdev);
3150 iounmap(jme->regs);
3151 free_netdev(netdev);
3152 pci_release_regions(pdev);
3153 pci_disable_device(pdev);
3154
3155}
3156
3157static void
3158jme_shutdown(struct pci_dev *pdev)
3159{
3160 struct net_device *netdev = pci_get_drvdata(pdev);
3161 struct jme_adapter *jme = netdev_priv(netdev);
3162
3163 jme_powersave_phy(jme);
3164 pci_pme_active(pdev, true);
3165}
3166
3167#ifdef CONFIG_PM_SLEEP
3168static int
3169jme_suspend(struct device *dev)
3170{
3171 struct net_device *netdev = dev_get_drvdata(dev);
3172 struct jme_adapter *jme = netdev_priv(netdev);
3173
3174 if (!netif_running(netdev))
3175 return 0;
3176
3177 atomic_dec(&jme->link_changing);
3178
3179 netif_device_detach(netdev);
3180 netif_stop_queue(netdev);
3181 jme_stop_irq(jme);
3182
3183 tasklet_disable(&jme->txclean_task);
3184 tasklet_disable(&jme->rxclean_task);
3185 tasklet_disable(&jme->rxempty_task);
3186
3187 if (netif_carrier_ok(netdev)) {
3188 if (test_bit(JME_FLAG_POLL, &jme->flags))
3189 jme_polling_mode(jme);
3190
3191 jme_stop_pcc_timer(jme);
3192 jme_disable_rx_engine(jme);
3193 jme_disable_tx_engine(jme);
3194 jme_reset_mac_processor(jme);
3195 jme_free_rx_resources(jme);
3196 jme_free_tx_resources(jme);
3197 netif_carrier_off(netdev);
3198 jme->phylink = 0;
3199 }
3200
3201 tasklet_enable(&jme->txclean_task);
3202 tasklet_enable(&jme->rxclean_task);
3203 tasklet_enable(&jme->rxempty_task);
3204
3205 jme_powersave_phy(jme);
3206
3207 return 0;
3208}
3209
3210static int
3211jme_resume(struct device *dev)
3212{
3213 struct net_device *netdev = dev_get_drvdata(dev);
3214 struct jme_adapter *jme = netdev_priv(netdev);
3215
3216 if (!netif_running(netdev))
3217 return 0;
3218
3219 jme_clear_pm_disable_wol(jme);
3220 jme_phy_on(jme);
3221 if (test_bit(JME_FLAG_SSET, &jme->flags))
3222 jme_set_link_ksettings(netdev, &jme->old_cmd);
3223 else
3224 jme_reset_phy_processor(jme);
3225 jme_phy_calibration(jme);
3226 jme_phy_setEA(jme);
3227 netif_device_attach(netdev);
3228
3229 atomic_inc(&jme->link_changing);
3230
3231 jme_reset_link(jme);
3232
3233 jme_start_irq(jme);
3234
3235 return 0;
3236}
3237
3238static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3239#define JME_PM_OPS (&jme_pm_ops)
3240
3241#else
3242
3243#define JME_PM_OPS NULL
3244#endif
3245
3246static const struct pci_device_id jme_pci_tbl[] = {
3247 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3248 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3249 { }
3250};
3251
3252static struct pci_driver jme_driver = {
3253 .name = DRV_NAME,
3254 .id_table = jme_pci_tbl,
3255 .probe = jme_init_one,
3256 .remove = jme_remove_one,
3257 .shutdown = jme_shutdown,
3258 .driver.pm = JME_PM_OPS,
3259};
3260
3261static int __init
3262jme_init_module(void)
3263{
3264 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3265 return pci_register_driver(&jme_driver);
3266}
3267
3268static void __exit
3269jme_cleanup_module(void)
3270{
3271 pci_unregister_driver(&jme_driver);
3272}
3273
3274module_init(jme_init_module);
3275module_exit(jme_cleanup_module);
3276
3277MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3278MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3279MODULE_LICENSE("GPL");
3280MODULE_VERSION(DRV_VERSION);
3281MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/pci-aspm.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/crc32.h>
36#include <linux/delay.h>
37#include <linux/spinlock.h>
38#include <linux/in.h>
39#include <linux/ip.h>
40#include <linux/ipv6.h>
41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/if_vlan.h>
44#include <linux/slab.h>
45#include <net/ip6_checksum.h>
46#include "jme.h"
47
48static int force_pseudohp = -1;
49static int no_pseudohp = -1;
50static int no_extplug = -1;
51module_param(force_pseudohp, int, 0);
52MODULE_PARM_DESC(force_pseudohp,
53 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
54module_param(no_pseudohp, int, 0);
55MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
56module_param(no_extplug, int, 0);
57MODULE_PARM_DESC(no_extplug,
58 "Do not use external plug signal for pseudo hot-plug.");
59
60static int
61jme_mdio_read(struct net_device *netdev, int phy, int reg)
62{
63 struct jme_adapter *jme = netdev_priv(netdev);
64 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
65
66read_again:
67 jwrite32(jme, JME_SMI, SMI_OP_REQ |
68 smi_phy_addr(phy) |
69 smi_reg_addr(reg));
70
71 wmb();
72 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
73 udelay(20);
74 val = jread32(jme, JME_SMI);
75 if ((val & SMI_OP_REQ) == 0)
76 break;
77 }
78
79 if (i == 0) {
80 pr_err("phy(%d) read timeout : %d\n", phy, reg);
81 return 0;
82 }
83
84 if (again--)
85 goto read_again;
86
87 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
88}
89
90static void
91jme_mdio_write(struct net_device *netdev,
92 int phy, int reg, int val)
93{
94 struct jme_adapter *jme = netdev_priv(netdev);
95 int i;
96
97 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
98 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
99 smi_phy_addr(phy) | smi_reg_addr(reg));
100
101 wmb();
102 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
103 udelay(20);
104 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
105 break;
106 }
107
108 if (i == 0)
109 pr_err("phy(%d) write timeout : %d\n", phy, reg);
110}
111
112static inline void
113jme_reset_phy_processor(struct jme_adapter *jme)
114{
115 u32 val;
116
117 jme_mdio_write(jme->dev,
118 jme->mii_if.phy_id,
119 MII_ADVERTISE, ADVERTISE_ALL |
120 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
121
122 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
123 jme_mdio_write(jme->dev,
124 jme->mii_if.phy_id,
125 MII_CTRL1000,
126 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
127
128 val = jme_mdio_read(jme->dev,
129 jme->mii_if.phy_id,
130 MII_BMCR);
131
132 jme_mdio_write(jme->dev,
133 jme->mii_if.phy_id,
134 MII_BMCR, val | BMCR_RESET);
135}
136
137static void
138jme_setup_wakeup_frame(struct jme_adapter *jme,
139 const u32 *mask, u32 crc, int fnr)
140{
141 int i;
142
143 /*
144 * Setup CRC pattern
145 */
146 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
147 wmb();
148 jwrite32(jme, JME_WFODP, crc);
149 wmb();
150
151 /*
152 * Setup Mask
153 */
154 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
155 jwrite32(jme, JME_WFOI,
156 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
157 (fnr & WFOI_FRAME_SEL));
158 wmb();
159 jwrite32(jme, JME_WFODP, mask[i]);
160 wmb();
161 }
162}
163
164static inline void
165jme_mac_rxclk_off(struct jme_adapter *jme)
166{
167 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
168 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
169}
170
171static inline void
172jme_mac_rxclk_on(struct jme_adapter *jme)
173{
174 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
175 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
176}
177
178static inline void
179jme_mac_txclk_off(struct jme_adapter *jme)
180{
181 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
182 jwrite32f(jme, JME_GHC, jme->reg_ghc);
183}
184
185static inline void
186jme_mac_txclk_on(struct jme_adapter *jme)
187{
188 u32 speed = jme->reg_ghc & GHC_SPEED;
189 if (speed == GHC_SPEED_1000M)
190 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
191 else
192 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
193 jwrite32f(jme, JME_GHC, jme->reg_ghc);
194}
195
196static inline void
197jme_reset_ghc_speed(struct jme_adapter *jme)
198{
199 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
200 jwrite32f(jme, JME_GHC, jme->reg_ghc);
201}
202
203static inline void
204jme_reset_250A2_workaround(struct jme_adapter *jme)
205{
206 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
207 GPREG1_RSSPATCH);
208 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
209}
210
211static inline void
212jme_assert_ghc_reset(struct jme_adapter *jme)
213{
214 jme->reg_ghc |= GHC_SWRST;
215 jwrite32f(jme, JME_GHC, jme->reg_ghc);
216}
217
218static inline void
219jme_clear_ghc_reset(struct jme_adapter *jme)
220{
221 jme->reg_ghc &= ~GHC_SWRST;
222 jwrite32f(jme, JME_GHC, jme->reg_ghc);
223}
224
225static void
226jme_reset_mac_processor(struct jme_adapter *jme)
227{
228 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
229 u32 crc = 0xCDCDCDCD;
230 u32 gpreg0;
231 int i;
232
233 jme_reset_ghc_speed(jme);
234 jme_reset_250A2_workaround(jme);
235
236 jme_mac_rxclk_on(jme);
237 jme_mac_txclk_on(jme);
238 udelay(1);
239 jme_assert_ghc_reset(jme);
240 udelay(1);
241 jme_mac_rxclk_off(jme);
242 jme_mac_txclk_off(jme);
243 udelay(1);
244 jme_clear_ghc_reset(jme);
245 udelay(1);
246 jme_mac_rxclk_on(jme);
247 jme_mac_txclk_on(jme);
248 udelay(1);
249 jme_mac_rxclk_off(jme);
250 jme_mac_txclk_off(jme);
251
252 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
253 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
254 jwrite32(jme, JME_RXQDC, 0x00000000);
255 jwrite32(jme, JME_RXNDA, 0x00000000);
256 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
257 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
258 jwrite32(jme, JME_TXQDC, 0x00000000);
259 jwrite32(jme, JME_TXNDA, 0x00000000);
260
261 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
262 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
263 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
264 jme_setup_wakeup_frame(jme, mask, crc, i);
265 if (jme->fpgaver)
266 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
267 else
268 gpreg0 = GPREG0_DEFAULT;
269 jwrite32(jme, JME_GPREG0, gpreg0);
270}
271
272static inline void
273jme_clear_pm_enable_wol(struct jme_adapter *jme)
274{
275 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
276}
277
278static inline void
279jme_clear_pm_disable_wol(struct jme_adapter *jme)
280{
281 jwrite32(jme, JME_PMCS, PMCS_STMASK);
282}
283
284static int
285jme_reload_eeprom(struct jme_adapter *jme)
286{
287 u32 val;
288 int i;
289
290 val = jread32(jme, JME_SMBCSR);
291
292 if (val & SMBCSR_EEPROMD) {
293 val |= SMBCSR_CNACK;
294 jwrite32(jme, JME_SMBCSR, val);
295 val |= SMBCSR_RELOAD;
296 jwrite32(jme, JME_SMBCSR, val);
297 mdelay(12);
298
299 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
300 mdelay(1);
301 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
302 break;
303 }
304
305 if (i == 0) {
306 pr_err("eeprom reload timeout\n");
307 return -EIO;
308 }
309 }
310
311 return 0;
312}
313
314static void
315jme_load_macaddr(struct net_device *netdev)
316{
317 struct jme_adapter *jme = netdev_priv(netdev);
318 unsigned char macaddr[ETH_ALEN];
319 u32 val;
320
321 spin_lock_bh(&jme->macaddr_lock);
322 val = jread32(jme, JME_RXUMA_LO);
323 macaddr[0] = (val >> 0) & 0xFF;
324 macaddr[1] = (val >> 8) & 0xFF;
325 macaddr[2] = (val >> 16) & 0xFF;
326 macaddr[3] = (val >> 24) & 0xFF;
327 val = jread32(jme, JME_RXUMA_HI);
328 macaddr[4] = (val >> 0) & 0xFF;
329 macaddr[5] = (val >> 8) & 0xFF;
330 memcpy(netdev->dev_addr, macaddr, ETH_ALEN);
331 spin_unlock_bh(&jme->macaddr_lock);
332}
333
334static inline void
335jme_set_rx_pcc(struct jme_adapter *jme, int p)
336{
337 switch (p) {
338 case PCC_OFF:
339 jwrite32(jme, JME_PCCRX0,
340 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
341 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
342 break;
343 case PCC_P1:
344 jwrite32(jme, JME_PCCRX0,
345 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
346 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
347 break;
348 case PCC_P2:
349 jwrite32(jme, JME_PCCRX0,
350 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
351 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
352 break;
353 case PCC_P3:
354 jwrite32(jme, JME_PCCRX0,
355 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
356 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
357 break;
358 default:
359 break;
360 }
361 wmb();
362
363 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
364 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
365}
366
367static void
368jme_start_irq(struct jme_adapter *jme)
369{
370 register struct dynpcc_info *dpi = &(jme->dpi);
371
372 jme_set_rx_pcc(jme, PCC_P1);
373 dpi->cur = PCC_P1;
374 dpi->attempt = PCC_P1;
375 dpi->cnt = 0;
376
377 jwrite32(jme, JME_PCCTX,
378 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
379 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
380 PCCTXQ0_EN
381 );
382
383 /*
384 * Enable Interrupts
385 */
386 jwrite32(jme, JME_IENS, INTR_ENABLE);
387}
388
389static inline void
390jme_stop_irq(struct jme_adapter *jme)
391{
392 /*
393 * Disable Interrupts
394 */
395 jwrite32f(jme, JME_IENC, INTR_ENABLE);
396}
397
398static u32
399jme_linkstat_from_phy(struct jme_adapter *jme)
400{
401 u32 phylink, bmsr;
402
403 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
404 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
405 if (bmsr & BMSR_ANCOMP)
406 phylink |= PHY_LINK_AUTONEG_COMPLETE;
407
408 return phylink;
409}
410
411static inline void
412jme_set_phyfifo_5level(struct jme_adapter *jme)
413{
414 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
415}
416
417static inline void
418jme_set_phyfifo_8level(struct jme_adapter *jme)
419{
420 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
421}
422
423static int
424jme_check_link(struct net_device *netdev, int testonly)
425{
426 struct jme_adapter *jme = netdev_priv(netdev);
427 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
428 char linkmsg[64];
429 int rc = 0;
430
431 linkmsg[0] = '\0';
432
433 if (jme->fpgaver)
434 phylink = jme_linkstat_from_phy(jme);
435 else
436 phylink = jread32(jme, JME_PHY_LINK);
437
438 if (phylink & PHY_LINK_UP) {
439 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
440 /*
441 * If we did not enable AN
442 * Speed/Duplex Info should be obtained from SMI
443 */
444 phylink = PHY_LINK_UP;
445
446 bmcr = jme_mdio_read(jme->dev,
447 jme->mii_if.phy_id,
448 MII_BMCR);
449
450 phylink |= ((bmcr & BMCR_SPEED1000) &&
451 (bmcr & BMCR_SPEED100) == 0) ?
452 PHY_LINK_SPEED_1000M :
453 (bmcr & BMCR_SPEED100) ?
454 PHY_LINK_SPEED_100M :
455 PHY_LINK_SPEED_10M;
456
457 phylink |= (bmcr & BMCR_FULLDPLX) ?
458 PHY_LINK_DUPLEX : 0;
459
460 strcat(linkmsg, "Forced: ");
461 } else {
462 /*
463 * Keep polling for speed/duplex resolve complete
464 */
465 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
466 --cnt) {
467
468 udelay(1);
469
470 if (jme->fpgaver)
471 phylink = jme_linkstat_from_phy(jme);
472 else
473 phylink = jread32(jme, JME_PHY_LINK);
474 }
475 if (!cnt)
476 pr_err("Waiting speed resolve timeout\n");
477
478 strcat(linkmsg, "ANed: ");
479 }
480
481 if (jme->phylink == phylink) {
482 rc = 1;
483 goto out;
484 }
485 if (testonly)
486 goto out;
487
488 jme->phylink = phylink;
489
490 /*
491 * The speed/duplex setting of jme->reg_ghc already cleared
492 * by jme_reset_mac_processor()
493 */
494 switch (phylink & PHY_LINK_SPEED_MASK) {
495 case PHY_LINK_SPEED_10M:
496 jme->reg_ghc |= GHC_SPEED_10M;
497 strcat(linkmsg, "10 Mbps, ");
498 break;
499 case PHY_LINK_SPEED_100M:
500 jme->reg_ghc |= GHC_SPEED_100M;
501 strcat(linkmsg, "100 Mbps, ");
502 break;
503 case PHY_LINK_SPEED_1000M:
504 jme->reg_ghc |= GHC_SPEED_1000M;
505 strcat(linkmsg, "1000 Mbps, ");
506 break;
507 default:
508 break;
509 }
510
511 if (phylink & PHY_LINK_DUPLEX) {
512 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
513 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
514 jme->reg_ghc |= GHC_DPX;
515 } else {
516 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
517 TXMCS_BACKOFF |
518 TXMCS_CARRIERSENSE |
519 TXMCS_COLLISION);
520 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
521 }
522
523 jwrite32(jme, JME_GHC, jme->reg_ghc);
524
525 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
526 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
527 GPREG1_RSSPATCH);
528 if (!(phylink & PHY_LINK_DUPLEX))
529 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
530 switch (phylink & PHY_LINK_SPEED_MASK) {
531 case PHY_LINK_SPEED_10M:
532 jme_set_phyfifo_8level(jme);
533 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
534 break;
535 case PHY_LINK_SPEED_100M:
536 jme_set_phyfifo_5level(jme);
537 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
538 break;
539 case PHY_LINK_SPEED_1000M:
540 jme_set_phyfifo_8level(jme);
541 break;
542 default:
543 break;
544 }
545 }
546 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
547
548 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
549 "Full-Duplex, " :
550 "Half-Duplex, ");
551 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
552 "MDI-X" :
553 "MDI");
554 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
555 netif_carrier_on(netdev);
556 } else {
557 if (testonly)
558 goto out;
559
560 netif_info(jme, link, jme->dev, "Link is down\n");
561 jme->phylink = 0;
562 netif_carrier_off(netdev);
563 }
564
565out:
566 return rc;
567}
568
569static int
570jme_setup_tx_resources(struct jme_adapter *jme)
571{
572 struct jme_ring *txring = &(jme->txring[0]);
573
574 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
575 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
576 &(txring->dmaalloc),
577 GFP_ATOMIC);
578
579 if (!txring->alloc)
580 goto err_set_null;
581
582 /*
583 * 16 Bytes align
584 */
585 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
586 RING_DESC_ALIGN);
587 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
588 txring->next_to_use = 0;
589 atomic_set(&txring->next_to_clean, 0);
590 atomic_set(&txring->nr_free, jme->tx_ring_size);
591
592 txring->bufinf = kzalloc(sizeof(struct jme_buffer_info) *
593 jme->tx_ring_size, GFP_ATOMIC);
594 if (unlikely(!(txring->bufinf)))
595 goto err_free_txring;
596
597 /*
598 * Initialize Transmit Descriptors
599 */
600 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
601
602 return 0;
603
604err_free_txring:
605 dma_free_coherent(&(jme->pdev->dev),
606 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
607 txring->alloc,
608 txring->dmaalloc);
609
610err_set_null:
611 txring->desc = NULL;
612 txring->dmaalloc = 0;
613 txring->dma = 0;
614 txring->bufinf = NULL;
615
616 return -ENOMEM;
617}
618
619static void
620jme_free_tx_resources(struct jme_adapter *jme)
621{
622 int i;
623 struct jme_ring *txring = &(jme->txring[0]);
624 struct jme_buffer_info *txbi;
625
626 if (txring->alloc) {
627 if (txring->bufinf) {
628 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
629 txbi = txring->bufinf + i;
630 if (txbi->skb) {
631 dev_kfree_skb(txbi->skb);
632 txbi->skb = NULL;
633 }
634 txbi->mapping = 0;
635 txbi->len = 0;
636 txbi->nr_desc = 0;
637 txbi->start_xmit = 0;
638 }
639 kfree(txring->bufinf);
640 }
641
642 dma_free_coherent(&(jme->pdev->dev),
643 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
644 txring->alloc,
645 txring->dmaalloc);
646
647 txring->alloc = NULL;
648 txring->desc = NULL;
649 txring->dmaalloc = 0;
650 txring->dma = 0;
651 txring->bufinf = NULL;
652 }
653 txring->next_to_use = 0;
654 atomic_set(&txring->next_to_clean, 0);
655 atomic_set(&txring->nr_free, 0);
656}
657
658static inline void
659jme_enable_tx_engine(struct jme_adapter *jme)
660{
661 /*
662 * Select Queue 0
663 */
664 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
665 wmb();
666
667 /*
668 * Setup TX Queue 0 DMA Bass Address
669 */
670 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
671 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
672 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
673
674 /*
675 * Setup TX Descptor Count
676 */
677 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
678
679 /*
680 * Enable TX Engine
681 */
682 wmb();
683 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
684 TXCS_SELECT_QUEUE0 |
685 TXCS_ENABLE);
686
687 /*
688 * Start clock for TX MAC Processor
689 */
690 jme_mac_txclk_on(jme);
691}
692
693static inline void
694jme_restart_tx_engine(struct jme_adapter *jme)
695{
696 /*
697 * Restart TX Engine
698 */
699 jwrite32(jme, JME_TXCS, jme->reg_txcs |
700 TXCS_SELECT_QUEUE0 |
701 TXCS_ENABLE);
702}
703
704static inline void
705jme_disable_tx_engine(struct jme_adapter *jme)
706{
707 int i;
708 u32 val;
709
710 /*
711 * Disable TX Engine
712 */
713 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
714 wmb();
715
716 val = jread32(jme, JME_TXCS);
717 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
718 mdelay(1);
719 val = jread32(jme, JME_TXCS);
720 rmb();
721 }
722
723 if (!i)
724 pr_err("Disable TX engine timeout\n");
725
726 /*
727 * Stop clock for TX MAC Processor
728 */
729 jme_mac_txclk_off(jme);
730}
731
732static void
733jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
734{
735 struct jme_ring *rxring = &(jme->rxring[0]);
736 register struct rxdesc *rxdesc = rxring->desc;
737 struct jme_buffer_info *rxbi = rxring->bufinf;
738 rxdesc += i;
739 rxbi += i;
740
741 rxdesc->dw[0] = 0;
742 rxdesc->dw[1] = 0;
743 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
744 rxdesc->desc1.bufaddrl = cpu_to_le32(
745 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
746 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
747 if (jme->dev->features & NETIF_F_HIGHDMA)
748 rxdesc->desc1.flags = RXFLAG_64BIT;
749 wmb();
750 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
751}
752
753static int
754jme_make_new_rx_buf(struct jme_adapter *jme, int i)
755{
756 struct jme_ring *rxring = &(jme->rxring[0]);
757 struct jme_buffer_info *rxbi = rxring->bufinf + i;
758 struct sk_buff *skb;
759 dma_addr_t mapping;
760
761 skb = netdev_alloc_skb(jme->dev,
762 jme->dev->mtu + RX_EXTRA_LEN);
763 if (unlikely(!skb))
764 return -ENOMEM;
765
766 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
767 offset_in_page(skb->data), skb_tailroom(skb),
768 PCI_DMA_FROMDEVICE);
769 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
770 dev_kfree_skb(skb);
771 return -ENOMEM;
772 }
773
774 if (likely(rxbi->mapping))
775 pci_unmap_page(jme->pdev, rxbi->mapping,
776 rxbi->len, PCI_DMA_FROMDEVICE);
777
778 rxbi->skb = skb;
779 rxbi->len = skb_tailroom(skb);
780 rxbi->mapping = mapping;
781 return 0;
782}
783
784static void
785jme_free_rx_buf(struct jme_adapter *jme, int i)
786{
787 struct jme_ring *rxring = &(jme->rxring[0]);
788 struct jme_buffer_info *rxbi = rxring->bufinf;
789 rxbi += i;
790
791 if (rxbi->skb) {
792 pci_unmap_page(jme->pdev,
793 rxbi->mapping,
794 rxbi->len,
795 PCI_DMA_FROMDEVICE);
796 dev_kfree_skb(rxbi->skb);
797 rxbi->skb = NULL;
798 rxbi->mapping = 0;
799 rxbi->len = 0;
800 }
801}
802
803static void
804jme_free_rx_resources(struct jme_adapter *jme)
805{
806 int i;
807 struct jme_ring *rxring = &(jme->rxring[0]);
808
809 if (rxring->alloc) {
810 if (rxring->bufinf) {
811 for (i = 0 ; i < jme->rx_ring_size ; ++i)
812 jme_free_rx_buf(jme, i);
813 kfree(rxring->bufinf);
814 }
815
816 dma_free_coherent(&(jme->pdev->dev),
817 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
818 rxring->alloc,
819 rxring->dmaalloc);
820 rxring->alloc = NULL;
821 rxring->desc = NULL;
822 rxring->dmaalloc = 0;
823 rxring->dma = 0;
824 rxring->bufinf = NULL;
825 }
826 rxring->next_to_use = 0;
827 atomic_set(&rxring->next_to_clean, 0);
828}
829
830static int
831jme_setup_rx_resources(struct jme_adapter *jme)
832{
833 int i;
834 struct jme_ring *rxring = &(jme->rxring[0]);
835
836 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
837 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
838 &(rxring->dmaalloc),
839 GFP_ATOMIC);
840 if (!rxring->alloc)
841 goto err_set_null;
842
843 /*
844 * 16 Bytes align
845 */
846 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
847 RING_DESC_ALIGN);
848 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
849 rxring->next_to_use = 0;
850 atomic_set(&rxring->next_to_clean, 0);
851
852 rxring->bufinf = kzalloc(sizeof(struct jme_buffer_info) *
853 jme->rx_ring_size, GFP_ATOMIC);
854 if (unlikely(!(rxring->bufinf)))
855 goto err_free_rxring;
856
857 /*
858 * Initiallize Receive Descriptors
859 */
860 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
861 if (unlikely(jme_make_new_rx_buf(jme, i))) {
862 jme_free_rx_resources(jme);
863 return -ENOMEM;
864 }
865
866 jme_set_clean_rxdesc(jme, i);
867 }
868
869 return 0;
870
871err_free_rxring:
872 dma_free_coherent(&(jme->pdev->dev),
873 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
874 rxring->alloc,
875 rxring->dmaalloc);
876err_set_null:
877 rxring->desc = NULL;
878 rxring->dmaalloc = 0;
879 rxring->dma = 0;
880 rxring->bufinf = NULL;
881
882 return -ENOMEM;
883}
884
885static inline void
886jme_enable_rx_engine(struct jme_adapter *jme)
887{
888 /*
889 * Select Queue 0
890 */
891 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
892 RXCS_QUEUESEL_Q0);
893 wmb();
894
895 /*
896 * Setup RX DMA Bass Address
897 */
898 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
899 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
900 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
901
902 /*
903 * Setup RX Descriptor Count
904 */
905 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
906
907 /*
908 * Setup Unicast Filter
909 */
910 jme_set_unicastaddr(jme->dev);
911 jme_set_multi(jme->dev);
912
913 /*
914 * Enable RX Engine
915 */
916 wmb();
917 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
918 RXCS_QUEUESEL_Q0 |
919 RXCS_ENABLE |
920 RXCS_QST);
921
922 /*
923 * Start clock for RX MAC Processor
924 */
925 jme_mac_rxclk_on(jme);
926}
927
928static inline void
929jme_restart_rx_engine(struct jme_adapter *jme)
930{
931 /*
932 * Start RX Engine
933 */
934 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
935 RXCS_QUEUESEL_Q0 |
936 RXCS_ENABLE |
937 RXCS_QST);
938}
939
940static inline void
941jme_disable_rx_engine(struct jme_adapter *jme)
942{
943 int i;
944 u32 val;
945
946 /*
947 * Disable RX Engine
948 */
949 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
950 wmb();
951
952 val = jread32(jme, JME_RXCS);
953 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
954 mdelay(1);
955 val = jread32(jme, JME_RXCS);
956 rmb();
957 }
958
959 if (!i)
960 pr_err("Disable RX engine timeout\n");
961
962 /*
963 * Stop clock for RX MAC Processor
964 */
965 jme_mac_rxclk_off(jme);
966}
967
968static u16
969jme_udpsum(struct sk_buff *skb)
970{
971 u16 csum = 0xFFFFu;
972
973 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
974 return csum;
975 if (skb->protocol != htons(ETH_P_IP))
976 return csum;
977 skb_set_network_header(skb, ETH_HLEN);
978 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
979 (skb->len < (ETH_HLEN +
980 (ip_hdr(skb)->ihl << 2) +
981 sizeof(struct udphdr)))) {
982 skb_reset_network_header(skb);
983 return csum;
984 }
985 skb_set_transport_header(skb,
986 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
987 csum = udp_hdr(skb)->check;
988 skb_reset_transport_header(skb);
989 skb_reset_network_header(skb);
990
991 return csum;
992}
993
994static int
995jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
996{
997 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
998 return false;
999
1000 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1001 == RXWBFLAG_TCPON)) {
1002 if (flags & RXWBFLAG_IPV4)
1003 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1004 return false;
1005 }
1006
1007 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1008 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1009 if (flags & RXWBFLAG_IPV4)
1010 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1011 return false;
1012 }
1013
1014 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1015 == RXWBFLAG_IPV4)) {
1016 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1017 return false;
1018 }
1019
1020 return true;
1021}
1022
1023static void
1024jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1025{
1026 struct jme_ring *rxring = &(jme->rxring[0]);
1027 struct rxdesc *rxdesc = rxring->desc;
1028 struct jme_buffer_info *rxbi = rxring->bufinf;
1029 struct sk_buff *skb;
1030 int framesize;
1031
1032 rxdesc += idx;
1033 rxbi += idx;
1034
1035 skb = rxbi->skb;
1036 pci_dma_sync_single_for_cpu(jme->pdev,
1037 rxbi->mapping,
1038 rxbi->len,
1039 PCI_DMA_FROMDEVICE);
1040
1041 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1042 pci_dma_sync_single_for_device(jme->pdev,
1043 rxbi->mapping,
1044 rxbi->len,
1045 PCI_DMA_FROMDEVICE);
1046
1047 ++(NET_STAT(jme).rx_dropped);
1048 } else {
1049 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1050 - RX_PREPAD_SIZE;
1051
1052 skb_reserve(skb, RX_PREPAD_SIZE);
1053 skb_put(skb, framesize);
1054 skb->protocol = eth_type_trans(skb, jme->dev);
1055
1056 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1057 skb->ip_summed = CHECKSUM_UNNECESSARY;
1058 else
1059 skb_checksum_none_assert(skb);
1060
1061 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1062 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1063
1064 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1065 NET_STAT(jme).rx_bytes += 4;
1066 }
1067 jme->jme_rx(skb);
1068
1069 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1070 cpu_to_le16(RXWBFLAG_DEST_MUL))
1071 ++(NET_STAT(jme).multicast);
1072
1073 NET_STAT(jme).rx_bytes += framesize;
1074 ++(NET_STAT(jme).rx_packets);
1075 }
1076
1077 jme_set_clean_rxdesc(jme, idx);
1078
1079}
1080
1081static int
1082jme_process_receive(struct jme_adapter *jme, int limit)
1083{
1084 struct jme_ring *rxring = &(jme->rxring[0]);
1085 struct rxdesc *rxdesc = rxring->desc;
1086 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1087
1088 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1089 goto out_inc;
1090
1091 if (unlikely(atomic_read(&jme->link_changing) != 1))
1092 goto out_inc;
1093
1094 if (unlikely(!netif_carrier_ok(jme->dev)))
1095 goto out_inc;
1096
1097 i = atomic_read(&rxring->next_to_clean);
1098 while (limit > 0) {
1099 rxdesc = rxring->desc;
1100 rxdesc += i;
1101
1102 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1103 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1104 goto out;
1105 --limit;
1106
1107 rmb();
1108 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1109
1110 if (unlikely(desccnt > 1 ||
1111 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1112
1113 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1114 ++(NET_STAT(jme).rx_crc_errors);
1115 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1116 ++(NET_STAT(jme).rx_fifo_errors);
1117 else
1118 ++(NET_STAT(jme).rx_errors);
1119
1120 if (desccnt > 1)
1121 limit -= desccnt - 1;
1122
1123 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1124 jme_set_clean_rxdesc(jme, j);
1125 j = (j + 1) & (mask);
1126 }
1127
1128 } else {
1129 jme_alloc_and_feed_skb(jme, i);
1130 }
1131
1132 i = (i + desccnt) & (mask);
1133 }
1134
1135out:
1136 atomic_set(&rxring->next_to_clean, i);
1137
1138out_inc:
1139 atomic_inc(&jme->rx_cleaning);
1140
1141 return limit > 0 ? limit : 0;
1142
1143}
1144
1145static void
1146jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1147{
1148 if (likely(atmp == dpi->cur)) {
1149 dpi->cnt = 0;
1150 return;
1151 }
1152
1153 if (dpi->attempt == atmp) {
1154 ++(dpi->cnt);
1155 } else {
1156 dpi->attempt = atmp;
1157 dpi->cnt = 0;
1158 }
1159
1160}
1161
1162static void
1163jme_dynamic_pcc(struct jme_adapter *jme)
1164{
1165 register struct dynpcc_info *dpi = &(jme->dpi);
1166
1167 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1168 jme_attempt_pcc(dpi, PCC_P3);
1169 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1170 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1171 jme_attempt_pcc(dpi, PCC_P2);
1172 else
1173 jme_attempt_pcc(dpi, PCC_P1);
1174
1175 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1176 if (dpi->attempt < dpi->cur)
1177 tasklet_schedule(&jme->rxclean_task);
1178 jme_set_rx_pcc(jme, dpi->attempt);
1179 dpi->cur = dpi->attempt;
1180 dpi->cnt = 0;
1181 }
1182}
1183
1184static void
1185jme_start_pcc_timer(struct jme_adapter *jme)
1186{
1187 struct dynpcc_info *dpi = &(jme->dpi);
1188 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1189 dpi->last_pkts = NET_STAT(jme).rx_packets;
1190 dpi->intr_cnt = 0;
1191 jwrite32(jme, JME_TMCSR,
1192 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1193}
1194
1195static inline void
1196jme_stop_pcc_timer(struct jme_adapter *jme)
1197{
1198 jwrite32(jme, JME_TMCSR, 0);
1199}
1200
1201static void
1202jme_shutdown_nic(struct jme_adapter *jme)
1203{
1204 u32 phylink;
1205
1206 phylink = jme_linkstat_from_phy(jme);
1207
1208 if (!(phylink & PHY_LINK_UP)) {
1209 /*
1210 * Disable all interrupt before issue timer
1211 */
1212 jme_stop_irq(jme);
1213 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1214 }
1215}
1216
1217static void
1218jme_pcc_tasklet(unsigned long arg)
1219{
1220 struct jme_adapter *jme = (struct jme_adapter *)arg;
1221 struct net_device *netdev = jme->dev;
1222
1223 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1224 jme_shutdown_nic(jme);
1225 return;
1226 }
1227
1228 if (unlikely(!netif_carrier_ok(netdev) ||
1229 (atomic_read(&jme->link_changing) != 1)
1230 )) {
1231 jme_stop_pcc_timer(jme);
1232 return;
1233 }
1234
1235 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1236 jme_dynamic_pcc(jme);
1237
1238 jme_start_pcc_timer(jme);
1239}
1240
1241static inline void
1242jme_polling_mode(struct jme_adapter *jme)
1243{
1244 jme_set_rx_pcc(jme, PCC_OFF);
1245}
1246
1247static inline void
1248jme_interrupt_mode(struct jme_adapter *jme)
1249{
1250 jme_set_rx_pcc(jme, PCC_P1);
1251}
1252
1253static inline int
1254jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1255{
1256 u32 apmc;
1257 apmc = jread32(jme, JME_APMC);
1258 return apmc & JME_APMC_PSEUDO_HP_EN;
1259}
1260
1261static void
1262jme_start_shutdown_timer(struct jme_adapter *jme)
1263{
1264 u32 apmc;
1265
1266 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1267 apmc &= ~JME_APMC_EPIEN_CTRL;
1268 if (!no_extplug) {
1269 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1270 wmb();
1271 }
1272 jwrite32f(jme, JME_APMC, apmc);
1273
1274 jwrite32f(jme, JME_TIMER2, 0);
1275 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1276 jwrite32(jme, JME_TMCSR,
1277 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1278}
1279
1280static void
1281jme_stop_shutdown_timer(struct jme_adapter *jme)
1282{
1283 u32 apmc;
1284
1285 jwrite32f(jme, JME_TMCSR, 0);
1286 jwrite32f(jme, JME_TIMER2, 0);
1287 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1288
1289 apmc = jread32(jme, JME_APMC);
1290 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1291 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1292 wmb();
1293 jwrite32f(jme, JME_APMC, apmc);
1294}
1295
1296static void
1297jme_link_change_tasklet(unsigned long arg)
1298{
1299 struct jme_adapter *jme = (struct jme_adapter *)arg;
1300 struct net_device *netdev = jme->dev;
1301 int rc;
1302
1303 while (!atomic_dec_and_test(&jme->link_changing)) {
1304 atomic_inc(&jme->link_changing);
1305 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1306 while (atomic_read(&jme->link_changing) != 1)
1307 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1308 }
1309
1310 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1311 goto out;
1312
1313 jme->old_mtu = netdev->mtu;
1314 netif_stop_queue(netdev);
1315 if (jme_pseudo_hotplug_enabled(jme))
1316 jme_stop_shutdown_timer(jme);
1317
1318 jme_stop_pcc_timer(jme);
1319 tasklet_disable(&jme->txclean_task);
1320 tasklet_disable(&jme->rxclean_task);
1321 tasklet_disable(&jme->rxempty_task);
1322
1323 if (netif_carrier_ok(netdev)) {
1324 jme_disable_rx_engine(jme);
1325 jme_disable_tx_engine(jme);
1326 jme_reset_mac_processor(jme);
1327 jme_free_rx_resources(jme);
1328 jme_free_tx_resources(jme);
1329
1330 if (test_bit(JME_FLAG_POLL, &jme->flags))
1331 jme_polling_mode(jme);
1332
1333 netif_carrier_off(netdev);
1334 }
1335
1336 jme_check_link(netdev, 0);
1337 if (netif_carrier_ok(netdev)) {
1338 rc = jme_setup_rx_resources(jme);
1339 if (rc) {
1340 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1341 goto out_enable_tasklet;
1342 }
1343
1344 rc = jme_setup_tx_resources(jme);
1345 if (rc) {
1346 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1347 goto err_out_free_rx_resources;
1348 }
1349
1350 jme_enable_rx_engine(jme);
1351 jme_enable_tx_engine(jme);
1352
1353 netif_start_queue(netdev);
1354
1355 if (test_bit(JME_FLAG_POLL, &jme->flags))
1356 jme_interrupt_mode(jme);
1357
1358 jme_start_pcc_timer(jme);
1359 } else if (jme_pseudo_hotplug_enabled(jme)) {
1360 jme_start_shutdown_timer(jme);
1361 }
1362
1363 goto out_enable_tasklet;
1364
1365err_out_free_rx_resources:
1366 jme_free_rx_resources(jme);
1367out_enable_tasklet:
1368 tasklet_enable(&jme->txclean_task);
1369 tasklet_enable(&jme->rxclean_task);
1370 tasklet_enable(&jme->rxempty_task);
1371out:
1372 atomic_inc(&jme->link_changing);
1373}
1374
1375static void
1376jme_rx_clean_tasklet(unsigned long arg)
1377{
1378 struct jme_adapter *jme = (struct jme_adapter *)arg;
1379 struct dynpcc_info *dpi = &(jme->dpi);
1380
1381 jme_process_receive(jme, jme->rx_ring_size);
1382 ++(dpi->intr_cnt);
1383
1384}
1385
1386static int
1387jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1388{
1389 struct jme_adapter *jme = jme_napi_priv(holder);
1390 int rest;
1391
1392 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1393
1394 while (atomic_read(&jme->rx_empty) > 0) {
1395 atomic_dec(&jme->rx_empty);
1396 ++(NET_STAT(jme).rx_dropped);
1397 jme_restart_rx_engine(jme);
1398 }
1399 atomic_inc(&jme->rx_empty);
1400
1401 if (rest) {
1402 JME_RX_COMPLETE(netdev, holder);
1403 jme_interrupt_mode(jme);
1404 }
1405
1406 JME_NAPI_WEIGHT_SET(budget, rest);
1407 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1408}
1409
1410static void
1411jme_rx_empty_tasklet(unsigned long arg)
1412{
1413 struct jme_adapter *jme = (struct jme_adapter *)arg;
1414
1415 if (unlikely(atomic_read(&jme->link_changing) != 1))
1416 return;
1417
1418 if (unlikely(!netif_carrier_ok(jme->dev)))
1419 return;
1420
1421 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1422
1423 jme_rx_clean_tasklet(arg);
1424
1425 while (atomic_read(&jme->rx_empty) > 0) {
1426 atomic_dec(&jme->rx_empty);
1427 ++(NET_STAT(jme).rx_dropped);
1428 jme_restart_rx_engine(jme);
1429 }
1430 atomic_inc(&jme->rx_empty);
1431}
1432
1433static void
1434jme_wake_queue_if_stopped(struct jme_adapter *jme)
1435{
1436 struct jme_ring *txring = &(jme->txring[0]);
1437
1438 smp_wmb();
1439 if (unlikely(netif_queue_stopped(jme->dev) &&
1440 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1441 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1442 netif_wake_queue(jme->dev);
1443 }
1444
1445}
1446
1447static void
1448jme_tx_clean_tasklet(unsigned long arg)
1449{
1450 struct jme_adapter *jme = (struct jme_adapter *)arg;
1451 struct jme_ring *txring = &(jme->txring[0]);
1452 struct txdesc *txdesc = txring->desc;
1453 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1454 int i, j, cnt = 0, max, err, mask;
1455
1456 tx_dbg(jme, "Into txclean\n");
1457
1458 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1459 goto out;
1460
1461 if (unlikely(atomic_read(&jme->link_changing) != 1))
1462 goto out;
1463
1464 if (unlikely(!netif_carrier_ok(jme->dev)))
1465 goto out;
1466
1467 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1468 mask = jme->tx_ring_mask;
1469
1470 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1471
1472 ctxbi = txbi + i;
1473
1474 if (likely(ctxbi->skb &&
1475 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1476
1477 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1478 i, ctxbi->nr_desc, jiffies);
1479
1480 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1481
1482 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1483 ttxbi = txbi + ((i + j) & (mask));
1484 txdesc[(i + j) & (mask)].dw[0] = 0;
1485
1486 pci_unmap_page(jme->pdev,
1487 ttxbi->mapping,
1488 ttxbi->len,
1489 PCI_DMA_TODEVICE);
1490
1491 ttxbi->mapping = 0;
1492 ttxbi->len = 0;
1493 }
1494
1495 dev_kfree_skb(ctxbi->skb);
1496
1497 cnt += ctxbi->nr_desc;
1498
1499 if (unlikely(err)) {
1500 ++(NET_STAT(jme).tx_carrier_errors);
1501 } else {
1502 ++(NET_STAT(jme).tx_packets);
1503 NET_STAT(jme).tx_bytes += ctxbi->len;
1504 }
1505
1506 ctxbi->skb = NULL;
1507 ctxbi->len = 0;
1508 ctxbi->start_xmit = 0;
1509
1510 } else {
1511 break;
1512 }
1513
1514 i = (i + ctxbi->nr_desc) & mask;
1515
1516 ctxbi->nr_desc = 0;
1517 }
1518
1519 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1520 atomic_set(&txring->next_to_clean, i);
1521 atomic_add(cnt, &txring->nr_free);
1522
1523 jme_wake_queue_if_stopped(jme);
1524
1525out:
1526 atomic_inc(&jme->tx_cleaning);
1527}
1528
1529static void
1530jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1531{
1532 /*
1533 * Disable interrupt
1534 */
1535 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1536
1537 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1538 /*
1539 * Link change event is critical
1540 * all other events are ignored
1541 */
1542 jwrite32(jme, JME_IEVE, intrstat);
1543 tasklet_schedule(&jme->linkch_task);
1544 goto out_reenable;
1545 }
1546
1547 if (intrstat & INTR_TMINTR) {
1548 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1549 tasklet_schedule(&jme->pcc_task);
1550 }
1551
1552 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1553 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1554 tasklet_schedule(&jme->txclean_task);
1555 }
1556
1557 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1558 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1559 INTR_PCCRX0 |
1560 INTR_RX0EMP)) |
1561 INTR_RX0);
1562 }
1563
1564 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1565 if (intrstat & INTR_RX0EMP)
1566 atomic_inc(&jme->rx_empty);
1567
1568 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1569 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1570 jme_polling_mode(jme);
1571 JME_RX_SCHEDULE(jme);
1572 }
1573 }
1574 } else {
1575 if (intrstat & INTR_RX0EMP) {
1576 atomic_inc(&jme->rx_empty);
1577 tasklet_hi_schedule(&jme->rxempty_task);
1578 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1579 tasklet_hi_schedule(&jme->rxclean_task);
1580 }
1581 }
1582
1583out_reenable:
1584 /*
1585 * Re-enable interrupt
1586 */
1587 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1588}
1589
1590static irqreturn_t
1591jme_intr(int irq, void *dev_id)
1592{
1593 struct net_device *netdev = dev_id;
1594 struct jme_adapter *jme = netdev_priv(netdev);
1595 u32 intrstat;
1596
1597 intrstat = jread32(jme, JME_IEVE);
1598
1599 /*
1600 * Check if it's really an interrupt for us
1601 */
1602 if (unlikely((intrstat & INTR_ENABLE) == 0))
1603 return IRQ_NONE;
1604
1605 /*
1606 * Check if the device still exist
1607 */
1608 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1609 return IRQ_NONE;
1610
1611 jme_intr_msi(jme, intrstat);
1612
1613 return IRQ_HANDLED;
1614}
1615
1616static irqreturn_t
1617jme_msi(int irq, void *dev_id)
1618{
1619 struct net_device *netdev = dev_id;
1620 struct jme_adapter *jme = netdev_priv(netdev);
1621 u32 intrstat;
1622
1623 intrstat = jread32(jme, JME_IEVE);
1624
1625 jme_intr_msi(jme, intrstat);
1626
1627 return IRQ_HANDLED;
1628}
1629
1630static void
1631jme_reset_link(struct jme_adapter *jme)
1632{
1633 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1634}
1635
1636static void
1637jme_restart_an(struct jme_adapter *jme)
1638{
1639 u32 bmcr;
1640
1641 spin_lock_bh(&jme->phy_lock);
1642 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1643 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1644 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1645 spin_unlock_bh(&jme->phy_lock);
1646}
1647
1648static int
1649jme_request_irq(struct jme_adapter *jme)
1650{
1651 int rc;
1652 struct net_device *netdev = jme->dev;
1653 irq_handler_t handler = jme_intr;
1654 int irq_flags = IRQF_SHARED;
1655
1656 if (!pci_enable_msi(jme->pdev)) {
1657 set_bit(JME_FLAG_MSI, &jme->flags);
1658 handler = jme_msi;
1659 irq_flags = 0;
1660 }
1661
1662 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1663 netdev);
1664 if (rc) {
1665 netdev_err(netdev,
1666 "Unable to request %s interrupt (return: %d)\n",
1667 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1668 rc);
1669
1670 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1671 pci_disable_msi(jme->pdev);
1672 clear_bit(JME_FLAG_MSI, &jme->flags);
1673 }
1674 } else {
1675 netdev->irq = jme->pdev->irq;
1676 }
1677
1678 return rc;
1679}
1680
1681static void
1682jme_free_irq(struct jme_adapter *jme)
1683{
1684 free_irq(jme->pdev->irq, jme->dev);
1685 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1686 pci_disable_msi(jme->pdev);
1687 clear_bit(JME_FLAG_MSI, &jme->flags);
1688 jme->dev->irq = jme->pdev->irq;
1689 }
1690}
1691
1692static inline void
1693jme_new_phy_on(struct jme_adapter *jme)
1694{
1695 u32 reg;
1696
1697 reg = jread32(jme, JME_PHY_PWR);
1698 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1699 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1700 jwrite32(jme, JME_PHY_PWR, reg);
1701
1702 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1703 reg &= ~PE1_GPREG0_PBG;
1704 reg |= PE1_GPREG0_ENBG;
1705 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1706}
1707
1708static inline void
1709jme_new_phy_off(struct jme_adapter *jme)
1710{
1711 u32 reg;
1712
1713 reg = jread32(jme, JME_PHY_PWR);
1714 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1715 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1716 jwrite32(jme, JME_PHY_PWR, reg);
1717
1718 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1719 reg &= ~PE1_GPREG0_PBG;
1720 reg |= PE1_GPREG0_PDD3COLD;
1721 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1722}
1723
1724static inline void
1725jme_phy_on(struct jme_adapter *jme)
1726{
1727 u32 bmcr;
1728
1729 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1730 bmcr &= ~BMCR_PDOWN;
1731 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1732
1733 if (new_phy_power_ctrl(jme->chip_main_rev))
1734 jme_new_phy_on(jme);
1735}
1736
1737static inline void
1738jme_phy_off(struct jme_adapter *jme)
1739{
1740 u32 bmcr;
1741
1742 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1743 bmcr |= BMCR_PDOWN;
1744 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1745
1746 if (new_phy_power_ctrl(jme->chip_main_rev))
1747 jme_new_phy_off(jme);
1748}
1749
1750static int
1751jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1752{
1753 u32 phy_addr;
1754
1755 phy_addr = JM_PHY_SPEC_REG_READ | specreg;
1756 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1757 phy_addr);
1758 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1759 JM_PHY_SPEC_DATA_REG);
1760}
1761
1762static void
1763jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1764{
1765 u32 phy_addr;
1766
1767 phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg;
1768 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1769 phy_data);
1770 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1771 phy_addr);
1772}
1773
1774static int
1775jme_phy_calibration(struct jme_adapter *jme)
1776{
1777 u32 ctrl1000, phy_data;
1778
1779 jme_phy_off(jme);
1780 jme_phy_on(jme);
1781 /* Enabel PHY test mode 1 */
1782 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1783 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1784 ctrl1000 |= PHY_GAD_TEST_MODE_1;
1785 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1786
1787 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1788 phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0;
1789 phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH |
1790 JM_PHY_EXT_COMM_2_CALI_ENABLE;
1791 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1792 msleep(20);
1793 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1794 phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE |
1795 JM_PHY_EXT_COMM_2_CALI_MODE_0 |
1796 JM_PHY_EXT_COMM_2_CALI_LATCH);
1797 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1798
1799 /* Disable PHY test mode */
1800 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1801 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1802 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1803 return 0;
1804}
1805
1806static int
1807jme_phy_setEA(struct jme_adapter *jme)
1808{
1809 u32 phy_comm0 = 0, phy_comm1 = 0;
1810 u8 nic_ctrl;
1811
1812 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1813 if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE)
1814 return 0;
1815
1816 switch (jme->pdev->device) {
1817 case PCI_DEVICE_ID_JMICRON_JMC250:
1818 if (((jme->chip_main_rev == 5) &&
1819 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1820 (jme->chip_sub_rev == 3))) ||
1821 (jme->chip_main_rev >= 6)) {
1822 phy_comm0 = 0x008A;
1823 phy_comm1 = 0x4109;
1824 }
1825 if ((jme->chip_main_rev == 3) &&
1826 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1827 phy_comm0 = 0xE088;
1828 break;
1829 case PCI_DEVICE_ID_JMICRON_JMC260:
1830 if (((jme->chip_main_rev == 5) &&
1831 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1832 (jme->chip_sub_rev == 3))) ||
1833 (jme->chip_main_rev >= 6)) {
1834 phy_comm0 = 0x008A;
1835 phy_comm1 = 0x4109;
1836 }
1837 if ((jme->chip_main_rev == 3) &&
1838 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1839 phy_comm0 = 0xE088;
1840 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1841 phy_comm0 = 0x608A;
1842 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1843 phy_comm0 = 0x408A;
1844 break;
1845 default:
1846 return -ENODEV;
1847 }
1848 if (phy_comm0)
1849 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1850 if (phy_comm1)
1851 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1852
1853 return 0;
1854}
1855
1856static int
1857jme_open(struct net_device *netdev)
1858{
1859 struct jme_adapter *jme = netdev_priv(netdev);
1860 int rc;
1861
1862 jme_clear_pm_disable_wol(jme);
1863 JME_NAPI_ENABLE(jme);
1864
1865 tasklet_init(&jme->linkch_task, jme_link_change_tasklet,
1866 (unsigned long) jme);
1867 tasklet_init(&jme->txclean_task, jme_tx_clean_tasklet,
1868 (unsigned long) jme);
1869 tasklet_init(&jme->rxclean_task, jme_rx_clean_tasklet,
1870 (unsigned long) jme);
1871 tasklet_init(&jme->rxempty_task, jme_rx_empty_tasklet,
1872 (unsigned long) jme);
1873
1874 rc = jme_request_irq(jme);
1875 if (rc)
1876 goto err_out;
1877
1878 jme_start_irq(jme);
1879
1880 jme_phy_on(jme);
1881 if (test_bit(JME_FLAG_SSET, &jme->flags))
1882 jme_set_settings(netdev, &jme->old_ecmd);
1883 else
1884 jme_reset_phy_processor(jme);
1885 jme_phy_calibration(jme);
1886 jme_phy_setEA(jme);
1887 jme_reset_link(jme);
1888
1889 return 0;
1890
1891err_out:
1892 netif_stop_queue(netdev);
1893 netif_carrier_off(netdev);
1894 return rc;
1895}
1896
1897static void
1898jme_set_100m_half(struct jme_adapter *jme)
1899{
1900 u32 bmcr, tmp;
1901
1902 jme_phy_on(jme);
1903 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1904 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1905 BMCR_SPEED1000 | BMCR_FULLDPLX);
1906 tmp |= BMCR_SPEED100;
1907
1908 if (bmcr != tmp)
1909 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1910
1911 if (jme->fpgaver)
1912 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1913 else
1914 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1915}
1916
1917#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1918static void
1919jme_wait_link(struct jme_adapter *jme)
1920{
1921 u32 phylink, to = JME_WAIT_LINK_TIME;
1922
1923 mdelay(1000);
1924 phylink = jme_linkstat_from_phy(jme);
1925 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1926 mdelay(10);
1927 phylink = jme_linkstat_from_phy(jme);
1928 }
1929}
1930
1931static void
1932jme_powersave_phy(struct jme_adapter *jme)
1933{
1934 if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) {
1935 jme_set_100m_half(jme);
1936 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1937 jme_wait_link(jme);
1938 jme_clear_pm_enable_wol(jme);
1939 } else {
1940 jme_phy_off(jme);
1941 }
1942}
1943
1944static int
1945jme_close(struct net_device *netdev)
1946{
1947 struct jme_adapter *jme = netdev_priv(netdev);
1948
1949 netif_stop_queue(netdev);
1950 netif_carrier_off(netdev);
1951
1952 jme_stop_irq(jme);
1953 jme_free_irq(jme);
1954
1955 JME_NAPI_DISABLE(jme);
1956
1957 tasklet_kill(&jme->linkch_task);
1958 tasklet_kill(&jme->txclean_task);
1959 tasklet_kill(&jme->rxclean_task);
1960 tasklet_kill(&jme->rxempty_task);
1961
1962 jme_disable_rx_engine(jme);
1963 jme_disable_tx_engine(jme);
1964 jme_reset_mac_processor(jme);
1965 jme_free_rx_resources(jme);
1966 jme_free_tx_resources(jme);
1967 jme->phylink = 0;
1968 jme_phy_off(jme);
1969
1970 return 0;
1971}
1972
1973static int
1974jme_alloc_txdesc(struct jme_adapter *jme,
1975 struct sk_buff *skb)
1976{
1977 struct jme_ring *txring = &(jme->txring[0]);
1978 int idx, nr_alloc, mask = jme->tx_ring_mask;
1979
1980 idx = txring->next_to_use;
1981 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1982
1983 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1984 return -1;
1985
1986 atomic_sub(nr_alloc, &txring->nr_free);
1987
1988 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1989
1990 return idx;
1991}
1992
1993static int
1994jme_fill_tx_map(struct pci_dev *pdev,
1995 struct txdesc *txdesc,
1996 struct jme_buffer_info *txbi,
1997 struct page *page,
1998 u32 page_offset,
1999 u32 len,
2000 bool hidma)
2001{
2002 dma_addr_t dmaaddr;
2003
2004 dmaaddr = pci_map_page(pdev,
2005 page,
2006 page_offset,
2007 len,
2008 PCI_DMA_TODEVICE);
2009
2010 if (unlikely(pci_dma_mapping_error(pdev, dmaaddr)))
2011 return -EINVAL;
2012
2013 pci_dma_sync_single_for_device(pdev,
2014 dmaaddr,
2015 len,
2016 PCI_DMA_TODEVICE);
2017
2018 txdesc->dw[0] = 0;
2019 txdesc->dw[1] = 0;
2020 txdesc->desc2.flags = TXFLAG_OWN;
2021 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
2022 txdesc->desc2.datalen = cpu_to_le16(len);
2023 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
2024 txdesc->desc2.bufaddrl = cpu_to_le32(
2025 (__u64)dmaaddr & 0xFFFFFFFFUL);
2026
2027 txbi->mapping = dmaaddr;
2028 txbi->len = len;
2029 return 0;
2030}
2031
2032static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count)
2033{
2034 struct jme_ring *txring = &(jme->txring[0]);
2035 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2036 int mask = jme->tx_ring_mask;
2037 int j;
2038
2039 for (j = 0 ; j < count ; j++) {
2040 ctxbi = txbi + ((startidx + j + 2) & (mask));
2041 pci_unmap_page(jme->pdev,
2042 ctxbi->mapping,
2043 ctxbi->len,
2044 PCI_DMA_TODEVICE);
2045
2046 ctxbi->mapping = 0;
2047 ctxbi->len = 0;
2048 }
2049
2050}
2051
2052static int
2053jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2054{
2055 struct jme_ring *txring = &(jme->txring[0]);
2056 struct txdesc *txdesc = txring->desc, *ctxdesc;
2057 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2058 bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
2059 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2060 int mask = jme->tx_ring_mask;
2061 const struct skb_frag_struct *frag;
2062 u32 len;
2063 int ret = 0;
2064
2065 for (i = 0 ; i < nr_frags ; ++i) {
2066 frag = &skb_shinfo(skb)->frags[i];
2067 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2068 ctxbi = txbi + ((idx + i + 2) & (mask));
2069
2070 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2071 skb_frag_page(frag),
2072 frag->page_offset, skb_frag_size(frag), hidma);
2073 if (ret) {
2074 jme_drop_tx_map(jme, idx, i);
2075 goto out;
2076 }
2077
2078 }
2079
2080 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2081 ctxdesc = txdesc + ((idx + 1) & (mask));
2082 ctxbi = txbi + ((idx + 1) & (mask));
2083 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2084 offset_in_page(skb->data), len, hidma);
2085 if (ret)
2086 jme_drop_tx_map(jme, idx, i);
2087
2088out:
2089 return ret;
2090
2091}
2092
2093
2094static int
2095jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2096{
2097 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2098 if (*mss) {
2099 *flags |= TXFLAG_LSEN;
2100
2101 if (skb->protocol == htons(ETH_P_IP)) {
2102 struct iphdr *iph = ip_hdr(skb);
2103
2104 iph->check = 0;
2105 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2106 iph->daddr, 0,
2107 IPPROTO_TCP,
2108 0);
2109 } else {
2110 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2111
2112 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2113 &ip6h->daddr, 0,
2114 IPPROTO_TCP,
2115 0);
2116 }
2117
2118 return 0;
2119 }
2120
2121 return 1;
2122}
2123
2124static void
2125jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2126{
2127 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2128 u8 ip_proto;
2129
2130 switch (skb->protocol) {
2131 case htons(ETH_P_IP):
2132 ip_proto = ip_hdr(skb)->protocol;
2133 break;
2134 case htons(ETH_P_IPV6):
2135 ip_proto = ipv6_hdr(skb)->nexthdr;
2136 break;
2137 default:
2138 ip_proto = 0;
2139 break;
2140 }
2141
2142 switch (ip_proto) {
2143 case IPPROTO_TCP:
2144 *flags |= TXFLAG_TCPCS;
2145 break;
2146 case IPPROTO_UDP:
2147 *flags |= TXFLAG_UDPCS;
2148 break;
2149 default:
2150 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2151 break;
2152 }
2153 }
2154}
2155
2156static inline void
2157jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2158{
2159 if (skb_vlan_tag_present(skb)) {
2160 *flags |= TXFLAG_TAGON;
2161 *vlan = cpu_to_le16(skb_vlan_tag_get(skb));
2162 }
2163}
2164
2165static int
2166jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2167{
2168 struct jme_ring *txring = &(jme->txring[0]);
2169 struct txdesc *txdesc;
2170 struct jme_buffer_info *txbi;
2171 u8 flags;
2172 int ret = 0;
2173
2174 txdesc = (struct txdesc *)txring->desc + idx;
2175 txbi = txring->bufinf + idx;
2176
2177 txdesc->dw[0] = 0;
2178 txdesc->dw[1] = 0;
2179 txdesc->dw[2] = 0;
2180 txdesc->dw[3] = 0;
2181 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2182 /*
2183 * Set OWN bit at final.
2184 * When kernel transmit faster than NIC.
2185 * And NIC trying to send this descriptor before we tell
2186 * it to start sending this TX queue.
2187 * Other fields are already filled correctly.
2188 */
2189 wmb();
2190 flags = TXFLAG_OWN | TXFLAG_INT;
2191 /*
2192 * Set checksum flags while not tso
2193 */
2194 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2195 jme_tx_csum(jme, skb, &flags);
2196 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2197 ret = jme_map_tx_skb(jme, skb, idx);
2198 if (ret)
2199 return ret;
2200
2201 txdesc->desc1.flags = flags;
2202 /*
2203 * Set tx buffer info after telling NIC to send
2204 * For better tx_clean timing
2205 */
2206 wmb();
2207 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2208 txbi->skb = skb;
2209 txbi->len = skb->len;
2210 txbi->start_xmit = jiffies;
2211 if (!txbi->start_xmit)
2212 txbi->start_xmit = (0UL-1);
2213
2214 return 0;
2215}
2216
2217static void
2218jme_stop_queue_if_full(struct jme_adapter *jme)
2219{
2220 struct jme_ring *txring = &(jme->txring[0]);
2221 struct jme_buffer_info *txbi = txring->bufinf;
2222 int idx = atomic_read(&txring->next_to_clean);
2223
2224 txbi += idx;
2225
2226 smp_wmb();
2227 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2228 netif_stop_queue(jme->dev);
2229 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2230 smp_wmb();
2231 if (atomic_read(&txring->nr_free)
2232 >= (jme->tx_wake_threshold)) {
2233 netif_wake_queue(jme->dev);
2234 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2235 }
2236 }
2237
2238 if (unlikely(txbi->start_xmit &&
2239 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2240 txbi->skb)) {
2241 netif_stop_queue(jme->dev);
2242 netif_info(jme, tx_queued, jme->dev,
2243 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2244 }
2245}
2246
2247/*
2248 * This function is already protected by netif_tx_lock()
2249 */
2250
2251static netdev_tx_t
2252jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2253{
2254 struct jme_adapter *jme = netdev_priv(netdev);
2255 int idx;
2256
2257 if (unlikely(skb_is_gso(skb) && skb_cow_head(skb, 0))) {
2258 dev_kfree_skb_any(skb);
2259 ++(NET_STAT(jme).tx_dropped);
2260 return NETDEV_TX_OK;
2261 }
2262
2263 idx = jme_alloc_txdesc(jme, skb);
2264
2265 if (unlikely(idx < 0)) {
2266 netif_stop_queue(netdev);
2267 netif_err(jme, tx_err, jme->dev,
2268 "BUG! Tx ring full when queue awake!\n");
2269
2270 return NETDEV_TX_BUSY;
2271 }
2272
2273 if (jme_fill_tx_desc(jme, skb, idx))
2274 return NETDEV_TX_OK;
2275
2276 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2277 TXCS_SELECT_QUEUE0 |
2278 TXCS_QUEUE0S |
2279 TXCS_ENABLE);
2280
2281 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2282 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2283 jme_stop_queue_if_full(jme);
2284
2285 return NETDEV_TX_OK;
2286}
2287
2288static void
2289jme_set_unicastaddr(struct net_device *netdev)
2290{
2291 struct jme_adapter *jme = netdev_priv(netdev);
2292 u32 val;
2293
2294 val = (netdev->dev_addr[3] & 0xff) << 24 |
2295 (netdev->dev_addr[2] & 0xff) << 16 |
2296 (netdev->dev_addr[1] & 0xff) << 8 |
2297 (netdev->dev_addr[0] & 0xff);
2298 jwrite32(jme, JME_RXUMA_LO, val);
2299 val = (netdev->dev_addr[5] & 0xff) << 8 |
2300 (netdev->dev_addr[4] & 0xff);
2301 jwrite32(jme, JME_RXUMA_HI, val);
2302}
2303
2304static int
2305jme_set_macaddr(struct net_device *netdev, void *p)
2306{
2307 struct jme_adapter *jme = netdev_priv(netdev);
2308 struct sockaddr *addr = p;
2309
2310 if (netif_running(netdev))
2311 return -EBUSY;
2312
2313 spin_lock_bh(&jme->macaddr_lock);
2314 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2315 jme_set_unicastaddr(netdev);
2316 spin_unlock_bh(&jme->macaddr_lock);
2317
2318 return 0;
2319}
2320
2321static void
2322jme_set_multi(struct net_device *netdev)
2323{
2324 struct jme_adapter *jme = netdev_priv(netdev);
2325 u32 mc_hash[2] = {};
2326
2327 spin_lock_bh(&jme->rxmcs_lock);
2328
2329 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2330
2331 if (netdev->flags & IFF_PROMISC) {
2332 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2333 } else if (netdev->flags & IFF_ALLMULTI) {
2334 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2335 } else if (netdev->flags & IFF_MULTICAST) {
2336 struct netdev_hw_addr *ha;
2337 int bit_nr;
2338
2339 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2340 netdev_for_each_mc_addr(ha, netdev) {
2341 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2342 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2343 }
2344
2345 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2346 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2347 }
2348
2349 wmb();
2350 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2351
2352 spin_unlock_bh(&jme->rxmcs_lock);
2353}
2354
2355static int
2356jme_change_mtu(struct net_device *netdev, int new_mtu)
2357{
2358 struct jme_adapter *jme = netdev_priv(netdev);
2359
2360 netdev->mtu = new_mtu;
2361 netdev_update_features(netdev);
2362
2363 jme_restart_rx_engine(jme);
2364 jme_reset_link(jme);
2365
2366 return 0;
2367}
2368
2369static void
2370jme_tx_timeout(struct net_device *netdev)
2371{
2372 struct jme_adapter *jme = netdev_priv(netdev);
2373
2374 jme->phylink = 0;
2375 jme_reset_phy_processor(jme);
2376 if (test_bit(JME_FLAG_SSET, &jme->flags))
2377 jme_set_settings(netdev, &jme->old_ecmd);
2378
2379 /*
2380 * Force to Reset the link again
2381 */
2382 jme_reset_link(jme);
2383}
2384
2385static inline void jme_pause_rx(struct jme_adapter *jme)
2386{
2387 atomic_dec(&jme->link_changing);
2388
2389 jme_set_rx_pcc(jme, PCC_OFF);
2390 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2391 JME_NAPI_DISABLE(jme);
2392 } else {
2393 tasklet_disable(&jme->rxclean_task);
2394 tasklet_disable(&jme->rxempty_task);
2395 }
2396}
2397
2398static inline void jme_resume_rx(struct jme_adapter *jme)
2399{
2400 struct dynpcc_info *dpi = &(jme->dpi);
2401
2402 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2403 JME_NAPI_ENABLE(jme);
2404 } else {
2405 tasklet_enable(&jme->rxclean_task);
2406 tasklet_enable(&jme->rxempty_task);
2407 }
2408 dpi->cur = PCC_P1;
2409 dpi->attempt = PCC_P1;
2410 dpi->cnt = 0;
2411 jme_set_rx_pcc(jme, PCC_P1);
2412
2413 atomic_inc(&jme->link_changing);
2414}
2415
2416static void
2417jme_get_drvinfo(struct net_device *netdev,
2418 struct ethtool_drvinfo *info)
2419{
2420 struct jme_adapter *jme = netdev_priv(netdev);
2421
2422 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2423 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2424 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
2425}
2426
2427static int
2428jme_get_regs_len(struct net_device *netdev)
2429{
2430 return JME_REG_LEN;
2431}
2432
2433static void
2434mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2435{
2436 int i;
2437
2438 for (i = 0 ; i < len ; i += 4)
2439 p[i >> 2] = jread32(jme, reg + i);
2440}
2441
2442static void
2443mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2444{
2445 int i;
2446 u16 *p16 = (u16 *)p;
2447
2448 for (i = 0 ; i < reg_nr ; ++i)
2449 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2450}
2451
2452static void
2453jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2454{
2455 struct jme_adapter *jme = netdev_priv(netdev);
2456 u32 *p32 = (u32 *)p;
2457
2458 memset(p, 0xFF, JME_REG_LEN);
2459
2460 regs->version = 1;
2461 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2462
2463 p32 += 0x100 >> 2;
2464 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2465
2466 p32 += 0x100 >> 2;
2467 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2468
2469 p32 += 0x100 >> 2;
2470 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2471
2472 p32 += 0x100 >> 2;
2473 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2474}
2475
2476static int
2477jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2478{
2479 struct jme_adapter *jme = netdev_priv(netdev);
2480
2481 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2482 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2483
2484 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2485 ecmd->use_adaptive_rx_coalesce = false;
2486 ecmd->rx_coalesce_usecs = 0;
2487 ecmd->rx_max_coalesced_frames = 0;
2488 return 0;
2489 }
2490
2491 ecmd->use_adaptive_rx_coalesce = true;
2492
2493 switch (jme->dpi.cur) {
2494 case PCC_P1:
2495 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2496 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2497 break;
2498 case PCC_P2:
2499 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2500 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2501 break;
2502 case PCC_P3:
2503 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2504 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2505 break;
2506 default:
2507 break;
2508 }
2509
2510 return 0;
2511}
2512
2513static int
2514jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2515{
2516 struct jme_adapter *jme = netdev_priv(netdev);
2517 struct dynpcc_info *dpi = &(jme->dpi);
2518
2519 if (netif_running(netdev))
2520 return -EBUSY;
2521
2522 if (ecmd->use_adaptive_rx_coalesce &&
2523 test_bit(JME_FLAG_POLL, &jme->flags)) {
2524 clear_bit(JME_FLAG_POLL, &jme->flags);
2525 jme->jme_rx = netif_rx;
2526 dpi->cur = PCC_P1;
2527 dpi->attempt = PCC_P1;
2528 dpi->cnt = 0;
2529 jme_set_rx_pcc(jme, PCC_P1);
2530 jme_interrupt_mode(jme);
2531 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2532 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2533 set_bit(JME_FLAG_POLL, &jme->flags);
2534 jme->jme_rx = netif_receive_skb;
2535 jme_interrupt_mode(jme);
2536 }
2537
2538 return 0;
2539}
2540
2541static void
2542jme_get_pauseparam(struct net_device *netdev,
2543 struct ethtool_pauseparam *ecmd)
2544{
2545 struct jme_adapter *jme = netdev_priv(netdev);
2546 u32 val;
2547
2548 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2549 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2550
2551 spin_lock_bh(&jme->phy_lock);
2552 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2553 spin_unlock_bh(&jme->phy_lock);
2554
2555 ecmd->autoneg =
2556 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2557}
2558
2559static int
2560jme_set_pauseparam(struct net_device *netdev,
2561 struct ethtool_pauseparam *ecmd)
2562{
2563 struct jme_adapter *jme = netdev_priv(netdev);
2564 u32 val;
2565
2566 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2567 (ecmd->tx_pause != 0)) {
2568
2569 if (ecmd->tx_pause)
2570 jme->reg_txpfc |= TXPFC_PF_EN;
2571 else
2572 jme->reg_txpfc &= ~TXPFC_PF_EN;
2573
2574 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2575 }
2576
2577 spin_lock_bh(&jme->rxmcs_lock);
2578 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2579 (ecmd->rx_pause != 0)) {
2580
2581 if (ecmd->rx_pause)
2582 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2583 else
2584 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2585
2586 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2587 }
2588 spin_unlock_bh(&jme->rxmcs_lock);
2589
2590 spin_lock_bh(&jme->phy_lock);
2591 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2592 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2593 (ecmd->autoneg != 0)) {
2594
2595 if (ecmd->autoneg)
2596 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2597 else
2598 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2599
2600 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2601 MII_ADVERTISE, val);
2602 }
2603 spin_unlock_bh(&jme->phy_lock);
2604
2605 return 0;
2606}
2607
2608static void
2609jme_get_wol(struct net_device *netdev,
2610 struct ethtool_wolinfo *wol)
2611{
2612 struct jme_adapter *jme = netdev_priv(netdev);
2613
2614 wol->supported = WAKE_MAGIC | WAKE_PHY;
2615
2616 wol->wolopts = 0;
2617
2618 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2619 wol->wolopts |= WAKE_PHY;
2620
2621 if (jme->reg_pmcs & PMCS_MFEN)
2622 wol->wolopts |= WAKE_MAGIC;
2623
2624}
2625
2626static int
2627jme_set_wol(struct net_device *netdev,
2628 struct ethtool_wolinfo *wol)
2629{
2630 struct jme_adapter *jme = netdev_priv(netdev);
2631
2632 if (wol->wolopts & (WAKE_MAGICSECURE |
2633 WAKE_UCAST |
2634 WAKE_MCAST |
2635 WAKE_BCAST |
2636 WAKE_ARP))
2637 return -EOPNOTSUPP;
2638
2639 jme->reg_pmcs = 0;
2640
2641 if (wol->wolopts & WAKE_PHY)
2642 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2643
2644 if (wol->wolopts & WAKE_MAGIC)
2645 jme->reg_pmcs |= PMCS_MFEN;
2646
2647 return 0;
2648}
2649
2650static int
2651jme_get_settings(struct net_device *netdev,
2652 struct ethtool_cmd *ecmd)
2653{
2654 struct jme_adapter *jme = netdev_priv(netdev);
2655 int rc;
2656
2657 spin_lock_bh(&jme->phy_lock);
2658 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2659 spin_unlock_bh(&jme->phy_lock);
2660 return rc;
2661}
2662
2663static int
2664jme_set_settings(struct net_device *netdev,
2665 struct ethtool_cmd *ecmd)
2666{
2667 struct jme_adapter *jme = netdev_priv(netdev);
2668 int rc, fdc = 0;
2669
2670 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2671 && ecmd->autoneg != AUTONEG_ENABLE)
2672 return -EINVAL;
2673
2674 /*
2675 * Check If user changed duplex only while force_media.
2676 * Hardware would not generate link change interrupt.
2677 */
2678 if (jme->mii_if.force_media &&
2679 ecmd->autoneg != AUTONEG_ENABLE &&
2680 (jme->mii_if.full_duplex != ecmd->duplex))
2681 fdc = 1;
2682
2683 spin_lock_bh(&jme->phy_lock);
2684 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2685 spin_unlock_bh(&jme->phy_lock);
2686
2687 if (!rc) {
2688 if (fdc)
2689 jme_reset_link(jme);
2690 jme->old_ecmd = *ecmd;
2691 set_bit(JME_FLAG_SSET, &jme->flags);
2692 }
2693
2694 return rc;
2695}
2696
2697static int
2698jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2699{
2700 int rc;
2701 struct jme_adapter *jme = netdev_priv(netdev);
2702 struct mii_ioctl_data *mii_data = if_mii(rq);
2703 unsigned int duplex_chg;
2704
2705 if (cmd == SIOCSMIIREG) {
2706 u16 val = mii_data->val_in;
2707 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2708 (val & BMCR_SPEED1000))
2709 return -EINVAL;
2710 }
2711
2712 spin_lock_bh(&jme->phy_lock);
2713 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2714 spin_unlock_bh(&jme->phy_lock);
2715
2716 if (!rc && (cmd == SIOCSMIIREG)) {
2717 if (duplex_chg)
2718 jme_reset_link(jme);
2719 jme_get_settings(netdev, &jme->old_ecmd);
2720 set_bit(JME_FLAG_SSET, &jme->flags);
2721 }
2722
2723 return rc;
2724}
2725
2726static u32
2727jme_get_link(struct net_device *netdev)
2728{
2729 struct jme_adapter *jme = netdev_priv(netdev);
2730 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2731}
2732
2733static u32
2734jme_get_msglevel(struct net_device *netdev)
2735{
2736 struct jme_adapter *jme = netdev_priv(netdev);
2737 return jme->msg_enable;
2738}
2739
2740static void
2741jme_set_msglevel(struct net_device *netdev, u32 value)
2742{
2743 struct jme_adapter *jme = netdev_priv(netdev);
2744 jme->msg_enable = value;
2745}
2746
2747static netdev_features_t
2748jme_fix_features(struct net_device *netdev, netdev_features_t features)
2749{
2750 if (netdev->mtu > 1900)
2751 features &= ~(NETIF_F_ALL_TSO | NETIF_F_CSUM_MASK);
2752 return features;
2753}
2754
2755static int
2756jme_set_features(struct net_device *netdev, netdev_features_t features)
2757{
2758 struct jme_adapter *jme = netdev_priv(netdev);
2759
2760 spin_lock_bh(&jme->rxmcs_lock);
2761 if (features & NETIF_F_RXCSUM)
2762 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2763 else
2764 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2765 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2766 spin_unlock_bh(&jme->rxmcs_lock);
2767
2768 return 0;
2769}
2770
2771#ifdef CONFIG_NET_POLL_CONTROLLER
2772static void jme_netpoll(struct net_device *dev)
2773{
2774 unsigned long flags;
2775
2776 local_irq_save(flags);
2777 jme_intr(dev->irq, dev);
2778 local_irq_restore(flags);
2779}
2780#endif
2781
2782static int
2783jme_nway_reset(struct net_device *netdev)
2784{
2785 struct jme_adapter *jme = netdev_priv(netdev);
2786 jme_restart_an(jme);
2787 return 0;
2788}
2789
2790static u8
2791jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2792{
2793 u32 val;
2794 int to;
2795
2796 val = jread32(jme, JME_SMBCSR);
2797 to = JME_SMB_BUSY_TIMEOUT;
2798 while ((val & SMBCSR_BUSY) && --to) {
2799 msleep(1);
2800 val = jread32(jme, JME_SMBCSR);
2801 }
2802 if (!to) {
2803 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2804 return 0xFF;
2805 }
2806
2807 jwrite32(jme, JME_SMBINTF,
2808 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2809 SMBINTF_HWRWN_READ |
2810 SMBINTF_HWCMD);
2811
2812 val = jread32(jme, JME_SMBINTF);
2813 to = JME_SMB_BUSY_TIMEOUT;
2814 while ((val & SMBINTF_HWCMD) && --to) {
2815 msleep(1);
2816 val = jread32(jme, JME_SMBINTF);
2817 }
2818 if (!to) {
2819 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2820 return 0xFF;
2821 }
2822
2823 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2824}
2825
2826static void
2827jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2828{
2829 u32 val;
2830 int to;
2831
2832 val = jread32(jme, JME_SMBCSR);
2833 to = JME_SMB_BUSY_TIMEOUT;
2834 while ((val & SMBCSR_BUSY) && --to) {
2835 msleep(1);
2836 val = jread32(jme, JME_SMBCSR);
2837 }
2838 if (!to) {
2839 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2840 return;
2841 }
2842
2843 jwrite32(jme, JME_SMBINTF,
2844 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2845 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2846 SMBINTF_HWRWN_WRITE |
2847 SMBINTF_HWCMD);
2848
2849 val = jread32(jme, JME_SMBINTF);
2850 to = JME_SMB_BUSY_TIMEOUT;
2851 while ((val & SMBINTF_HWCMD) && --to) {
2852 msleep(1);
2853 val = jread32(jme, JME_SMBINTF);
2854 }
2855 if (!to) {
2856 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2857 return;
2858 }
2859
2860 mdelay(2);
2861}
2862
2863static int
2864jme_get_eeprom_len(struct net_device *netdev)
2865{
2866 struct jme_adapter *jme = netdev_priv(netdev);
2867 u32 val;
2868 val = jread32(jme, JME_SMBCSR);
2869 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2870}
2871
2872static int
2873jme_get_eeprom(struct net_device *netdev,
2874 struct ethtool_eeprom *eeprom, u8 *data)
2875{
2876 struct jme_adapter *jme = netdev_priv(netdev);
2877 int i, offset = eeprom->offset, len = eeprom->len;
2878
2879 /*
2880 * ethtool will check the boundary for us
2881 */
2882 eeprom->magic = JME_EEPROM_MAGIC;
2883 for (i = 0 ; i < len ; ++i)
2884 data[i] = jme_smb_read(jme, i + offset);
2885
2886 return 0;
2887}
2888
2889static int
2890jme_set_eeprom(struct net_device *netdev,
2891 struct ethtool_eeprom *eeprom, u8 *data)
2892{
2893 struct jme_adapter *jme = netdev_priv(netdev);
2894 int i, offset = eeprom->offset, len = eeprom->len;
2895
2896 if (eeprom->magic != JME_EEPROM_MAGIC)
2897 return -EINVAL;
2898
2899 /*
2900 * ethtool will check the boundary for us
2901 */
2902 for (i = 0 ; i < len ; ++i)
2903 jme_smb_write(jme, i + offset, data[i]);
2904
2905 return 0;
2906}
2907
2908static const struct ethtool_ops jme_ethtool_ops = {
2909 .get_drvinfo = jme_get_drvinfo,
2910 .get_regs_len = jme_get_regs_len,
2911 .get_regs = jme_get_regs,
2912 .get_coalesce = jme_get_coalesce,
2913 .set_coalesce = jme_set_coalesce,
2914 .get_pauseparam = jme_get_pauseparam,
2915 .set_pauseparam = jme_set_pauseparam,
2916 .get_wol = jme_get_wol,
2917 .set_wol = jme_set_wol,
2918 .get_settings = jme_get_settings,
2919 .set_settings = jme_set_settings,
2920 .get_link = jme_get_link,
2921 .get_msglevel = jme_get_msglevel,
2922 .set_msglevel = jme_set_msglevel,
2923 .nway_reset = jme_nway_reset,
2924 .get_eeprom_len = jme_get_eeprom_len,
2925 .get_eeprom = jme_get_eeprom,
2926 .set_eeprom = jme_set_eeprom,
2927};
2928
2929static int
2930jme_pci_dma64(struct pci_dev *pdev)
2931{
2932 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2933 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2934 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2935 return 1;
2936
2937 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2938 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2939 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2940 return 1;
2941
2942 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2943 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2944 return 0;
2945
2946 return -1;
2947}
2948
2949static inline void
2950jme_phy_init(struct jme_adapter *jme)
2951{
2952 u16 reg26;
2953
2954 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2955 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2956}
2957
2958static inline void
2959jme_check_hw_ver(struct jme_adapter *jme)
2960{
2961 u32 chipmode;
2962
2963 chipmode = jread32(jme, JME_CHIPMODE);
2964
2965 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2966 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2967 jme->chip_main_rev = jme->chiprev & 0xF;
2968 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2969}
2970
2971static const struct net_device_ops jme_netdev_ops = {
2972 .ndo_open = jme_open,
2973 .ndo_stop = jme_close,
2974 .ndo_validate_addr = eth_validate_addr,
2975 .ndo_do_ioctl = jme_ioctl,
2976 .ndo_start_xmit = jme_start_xmit,
2977 .ndo_set_mac_address = jme_set_macaddr,
2978 .ndo_set_rx_mode = jme_set_multi,
2979 .ndo_change_mtu = jme_change_mtu,
2980 .ndo_tx_timeout = jme_tx_timeout,
2981 .ndo_fix_features = jme_fix_features,
2982 .ndo_set_features = jme_set_features,
2983#ifdef CONFIG_NET_POLL_CONTROLLER
2984 .ndo_poll_controller = jme_netpoll,
2985#endif
2986};
2987
2988static int
2989jme_init_one(struct pci_dev *pdev,
2990 const struct pci_device_id *ent)
2991{
2992 int rc = 0, using_dac, i;
2993 struct net_device *netdev;
2994 struct jme_adapter *jme;
2995 u16 bmcr, bmsr;
2996 u32 apmc;
2997
2998 /*
2999 * set up PCI device basics
3000 */
3001 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3002 PCIE_LINK_STATE_CLKPM);
3003
3004 rc = pci_enable_device(pdev);
3005 if (rc) {
3006 pr_err("Cannot enable PCI device\n");
3007 goto err_out;
3008 }
3009
3010 using_dac = jme_pci_dma64(pdev);
3011 if (using_dac < 0) {
3012 pr_err("Cannot set PCI DMA Mask\n");
3013 rc = -EIO;
3014 goto err_out_disable_pdev;
3015 }
3016
3017 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3018 pr_err("No PCI resource region found\n");
3019 rc = -ENOMEM;
3020 goto err_out_disable_pdev;
3021 }
3022
3023 rc = pci_request_regions(pdev, DRV_NAME);
3024 if (rc) {
3025 pr_err("Cannot obtain PCI resource region\n");
3026 goto err_out_disable_pdev;
3027 }
3028
3029 pci_set_master(pdev);
3030
3031 /*
3032 * alloc and init net device
3033 */
3034 netdev = alloc_etherdev(sizeof(*jme));
3035 if (!netdev) {
3036 rc = -ENOMEM;
3037 goto err_out_release_regions;
3038 }
3039 netdev->netdev_ops = &jme_netdev_ops;
3040 netdev->ethtool_ops = &jme_ethtool_ops;
3041 netdev->watchdog_timeo = TX_TIMEOUT;
3042 netdev->hw_features = NETIF_F_IP_CSUM |
3043 NETIF_F_IPV6_CSUM |
3044 NETIF_F_SG |
3045 NETIF_F_TSO |
3046 NETIF_F_TSO6 |
3047 NETIF_F_RXCSUM;
3048 netdev->features = NETIF_F_IP_CSUM |
3049 NETIF_F_IPV6_CSUM |
3050 NETIF_F_SG |
3051 NETIF_F_TSO |
3052 NETIF_F_TSO6 |
3053 NETIF_F_HW_VLAN_CTAG_TX |
3054 NETIF_F_HW_VLAN_CTAG_RX;
3055 if (using_dac)
3056 netdev->features |= NETIF_F_HIGHDMA;
3057
3058 /* MTU range: 1280 - 9202*/
3059 netdev->min_mtu = IPV6_MIN_MTU;
3060 netdev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE - ETH_HLEN;
3061
3062 SET_NETDEV_DEV(netdev, &pdev->dev);
3063 pci_set_drvdata(pdev, netdev);
3064
3065 /*
3066 * init adapter info
3067 */
3068 jme = netdev_priv(netdev);
3069 jme->pdev = pdev;
3070 jme->dev = netdev;
3071 jme->jme_rx = netif_rx;
3072 jme->old_mtu = netdev->mtu = 1500;
3073 jme->phylink = 0;
3074 jme->tx_ring_size = 1 << 10;
3075 jme->tx_ring_mask = jme->tx_ring_size - 1;
3076 jme->tx_wake_threshold = 1 << 9;
3077 jme->rx_ring_size = 1 << 9;
3078 jme->rx_ring_mask = jme->rx_ring_size - 1;
3079 jme->msg_enable = JME_DEF_MSG_ENABLE;
3080 jme->regs = ioremap(pci_resource_start(pdev, 0),
3081 pci_resource_len(pdev, 0));
3082 if (!(jme->regs)) {
3083 pr_err("Mapping PCI resource region error\n");
3084 rc = -ENOMEM;
3085 goto err_out_free_netdev;
3086 }
3087
3088 if (no_pseudohp) {
3089 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3090 jwrite32(jme, JME_APMC, apmc);
3091 } else if (force_pseudohp) {
3092 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3093 jwrite32(jme, JME_APMC, apmc);
3094 }
3095
3096 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, NAPI_POLL_WEIGHT)
3097
3098 spin_lock_init(&jme->phy_lock);
3099 spin_lock_init(&jme->macaddr_lock);
3100 spin_lock_init(&jme->rxmcs_lock);
3101
3102 atomic_set(&jme->link_changing, 1);
3103 atomic_set(&jme->rx_cleaning, 1);
3104 atomic_set(&jme->tx_cleaning, 1);
3105 atomic_set(&jme->rx_empty, 1);
3106
3107 tasklet_init(&jme->pcc_task,
3108 jme_pcc_tasklet,
3109 (unsigned long) jme);
3110 jme->dpi.cur = PCC_P1;
3111
3112 jme->reg_ghc = 0;
3113 jme->reg_rxcs = RXCS_DEFAULT;
3114 jme->reg_rxmcs = RXMCS_DEFAULT;
3115 jme->reg_txpfc = 0;
3116 jme->reg_pmcs = PMCS_MFEN;
3117 jme->reg_gpreg1 = GPREG1_DEFAULT;
3118
3119 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3120 netdev->features |= NETIF_F_RXCSUM;
3121
3122 /*
3123 * Get Max Read Req Size from PCI Config Space
3124 */
3125 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3126 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3127 switch (jme->mrrs) {
3128 case MRRS_128B:
3129 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3130 break;
3131 case MRRS_256B:
3132 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3133 break;
3134 default:
3135 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3136 break;
3137 }
3138
3139 /*
3140 * Must check before reset_mac_processor
3141 */
3142 jme_check_hw_ver(jme);
3143 jme->mii_if.dev = netdev;
3144 if (jme->fpgaver) {
3145 jme->mii_if.phy_id = 0;
3146 for (i = 1 ; i < 32 ; ++i) {
3147 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3148 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3149 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3150 jme->mii_if.phy_id = i;
3151 break;
3152 }
3153 }
3154
3155 if (!jme->mii_if.phy_id) {
3156 rc = -EIO;
3157 pr_err("Can not find phy_id\n");
3158 goto err_out_unmap;
3159 }
3160
3161 jme->reg_ghc |= GHC_LINK_POLL;
3162 } else {
3163 jme->mii_if.phy_id = 1;
3164 }
3165 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3166 jme->mii_if.supports_gmii = true;
3167 else
3168 jme->mii_if.supports_gmii = false;
3169 jme->mii_if.phy_id_mask = 0x1F;
3170 jme->mii_if.reg_num_mask = 0x1F;
3171 jme->mii_if.mdio_read = jme_mdio_read;
3172 jme->mii_if.mdio_write = jme_mdio_write;
3173
3174 jme_clear_pm_disable_wol(jme);
3175 device_init_wakeup(&pdev->dev, true);
3176
3177 jme_set_phyfifo_5level(jme);
3178 jme->pcirev = pdev->revision;
3179 if (!jme->fpgaver)
3180 jme_phy_init(jme);
3181 jme_phy_off(jme);
3182
3183 /*
3184 * Reset MAC processor and reload EEPROM for MAC Address
3185 */
3186 jme_reset_mac_processor(jme);
3187 rc = jme_reload_eeprom(jme);
3188 if (rc) {
3189 pr_err("Reload eeprom for reading MAC Address error\n");
3190 goto err_out_unmap;
3191 }
3192 jme_load_macaddr(netdev);
3193
3194 /*
3195 * Tell stack that we are not ready to work until open()
3196 */
3197 netif_carrier_off(netdev);
3198
3199 rc = register_netdev(netdev);
3200 if (rc) {
3201 pr_err("Cannot register net device\n");
3202 goto err_out_unmap;
3203 }
3204
3205 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3206 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3207 "JMC250 Gigabit Ethernet" :
3208 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3209 "JMC260 Fast Ethernet" : "Unknown",
3210 (jme->fpgaver != 0) ? " (FPGA)" : "",
3211 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3212 jme->pcirev, netdev->dev_addr);
3213
3214 return 0;
3215
3216err_out_unmap:
3217 iounmap(jme->regs);
3218err_out_free_netdev:
3219 free_netdev(netdev);
3220err_out_release_regions:
3221 pci_release_regions(pdev);
3222err_out_disable_pdev:
3223 pci_disable_device(pdev);
3224err_out:
3225 return rc;
3226}
3227
3228static void
3229jme_remove_one(struct pci_dev *pdev)
3230{
3231 struct net_device *netdev = pci_get_drvdata(pdev);
3232 struct jme_adapter *jme = netdev_priv(netdev);
3233
3234 unregister_netdev(netdev);
3235 iounmap(jme->regs);
3236 free_netdev(netdev);
3237 pci_release_regions(pdev);
3238 pci_disable_device(pdev);
3239
3240}
3241
3242static void
3243jme_shutdown(struct pci_dev *pdev)
3244{
3245 struct net_device *netdev = pci_get_drvdata(pdev);
3246 struct jme_adapter *jme = netdev_priv(netdev);
3247
3248 jme_powersave_phy(jme);
3249 pci_pme_active(pdev, true);
3250}
3251
3252#ifdef CONFIG_PM_SLEEP
3253static int
3254jme_suspend(struct device *dev)
3255{
3256 struct pci_dev *pdev = to_pci_dev(dev);
3257 struct net_device *netdev = pci_get_drvdata(pdev);
3258 struct jme_adapter *jme = netdev_priv(netdev);
3259
3260 if (!netif_running(netdev))
3261 return 0;
3262
3263 atomic_dec(&jme->link_changing);
3264
3265 netif_device_detach(netdev);
3266 netif_stop_queue(netdev);
3267 jme_stop_irq(jme);
3268
3269 tasklet_disable(&jme->txclean_task);
3270 tasklet_disable(&jme->rxclean_task);
3271 tasklet_disable(&jme->rxempty_task);
3272
3273 if (netif_carrier_ok(netdev)) {
3274 if (test_bit(JME_FLAG_POLL, &jme->flags))
3275 jme_polling_mode(jme);
3276
3277 jme_stop_pcc_timer(jme);
3278 jme_disable_rx_engine(jme);
3279 jme_disable_tx_engine(jme);
3280 jme_reset_mac_processor(jme);
3281 jme_free_rx_resources(jme);
3282 jme_free_tx_resources(jme);
3283 netif_carrier_off(netdev);
3284 jme->phylink = 0;
3285 }
3286
3287 tasklet_enable(&jme->txclean_task);
3288 tasklet_enable(&jme->rxclean_task);
3289 tasklet_enable(&jme->rxempty_task);
3290
3291 jme_powersave_phy(jme);
3292
3293 return 0;
3294}
3295
3296static int
3297jme_resume(struct device *dev)
3298{
3299 struct pci_dev *pdev = to_pci_dev(dev);
3300 struct net_device *netdev = pci_get_drvdata(pdev);
3301 struct jme_adapter *jme = netdev_priv(netdev);
3302
3303 if (!netif_running(netdev))
3304 return 0;
3305
3306 jme_clear_pm_disable_wol(jme);
3307 jme_phy_on(jme);
3308 if (test_bit(JME_FLAG_SSET, &jme->flags))
3309 jme_set_settings(netdev, &jme->old_ecmd);
3310 else
3311 jme_reset_phy_processor(jme);
3312 jme_phy_calibration(jme);
3313 jme_phy_setEA(jme);
3314 netif_device_attach(netdev);
3315
3316 atomic_inc(&jme->link_changing);
3317
3318 jme_reset_link(jme);
3319
3320 jme_start_irq(jme);
3321
3322 return 0;
3323}
3324
3325static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3326#define JME_PM_OPS (&jme_pm_ops)
3327
3328#else
3329
3330#define JME_PM_OPS NULL
3331#endif
3332
3333static const struct pci_device_id jme_pci_tbl[] = {
3334 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3335 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3336 { }
3337};
3338
3339static struct pci_driver jme_driver = {
3340 .name = DRV_NAME,
3341 .id_table = jme_pci_tbl,
3342 .probe = jme_init_one,
3343 .remove = jme_remove_one,
3344 .shutdown = jme_shutdown,
3345 .driver.pm = JME_PM_OPS,
3346};
3347
3348static int __init
3349jme_init_module(void)
3350{
3351 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3352 return pci_register_driver(&jme_driver);
3353}
3354
3355static void __exit
3356jme_cleanup_module(void)
3357{
3358 pci_unregister_driver(&jme_driver);
3359}
3360
3361module_init(jme_init_module);
3362module_exit(jme_cleanup_module);
3363
3364MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3365MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3366MODULE_LICENSE("GPL");
3367MODULE_VERSION(DRV_VERSION);
3368MODULE_DEVICE_TABLE(pci, jme_pci_tbl);