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1// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
2/*
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
4 */
5
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8#include "fman_memac.h"
9#include "fman.h"
10#include "mac.h"
11
12#include <linux/slab.h>
13#include <linux/io.h>
14#include <linux/pcs-lynx.h>
15#include <linux/phy.h>
16#include <linux/phy_fixed.h>
17#include <linux/phy/phy.h>
18#include <linux/of_mdio.h>
19
20/* Num of additional exact match MAC adr regs */
21#define MEMAC_NUM_OF_PADDRS 7
22
23/* Control and Configuration Register (COMMAND_CONFIG) */
24#define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */
25#define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */
26#define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */
27#define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */
28#define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */
29#define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */
30#define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */
31#define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */
32#define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */
33#define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */
34#define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */
35#define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */
36
37/* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */
38#define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000
39#define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF
40#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000
41#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000
42#define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019
43#define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020
44#define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060
45
46#define GET_TX_EMPTY_DEFAULT_VALUE(_val) \
47do { \
48 _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \
49 ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \
50 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\
51 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\
52} while (0)
53
54/* Interface Mode Register (IF_MODE) */
55
56#define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
57#define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
58#define IF_MODE_MII 0x00000001 /* 30-31 MII interface */
59#define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
60#define IF_MODE_RGMII 0x00000004
61#define IF_MODE_RGMII_AUTO 0x00008000
62#define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
63#define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
64#define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
65#define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */
66#define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */
67#define IF_MODE_HD 0x00000040 /* Half duplex operation */
68
69/* Hash table Control Register (HASHTABLE_CTRL) */
70#define HASH_CTRL_MCAST_EN 0x00000100
71/* 26-31 Hash table address code */
72#define HASH_CTRL_ADDR_MASK 0x0000003F
73/* MAC mcast indication */
74#define GROUP_ADDRESS 0x0000010000000000LL
75#define HASH_TABLE_SIZE 64 /* Hash tbl size */
76
77/* Interrupt Mask Register (IMASK) */
78#define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */
79#define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */
80#define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */
81#define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */
82
83#define MEMAC_ALL_ERRS_IMASK \
84 ((u32)(MEMAC_IMASK_TSECC_ER | \
85 MEMAC_IMASK_TECC_ER | \
86 MEMAC_IMASK_RECC_ER | \
87 MEMAC_IMASK_MGI))
88
89#define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */
90#define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */
91#define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */
92#define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */
93#define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error*/
94#define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */
95#define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
96#define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */
97#define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */
98#define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */
99#define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */
100#define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */
101#define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */
102#define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */
103#define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */
104#define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */
105#define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */
106
107#define DEFAULT_PAUSE_QUANTA 0xf000
108#define DEFAULT_FRAME_LENGTH 0x600
109#define DEFAULT_TX_IPG_LENGTH 12
110
111#define CLXY_PAUSE_QUANTA_CLX_PQNT 0x0000FFFF
112#define CLXY_PAUSE_QUANTA_CLY_PQNT 0xFFFF0000
113#define CLXY_PAUSE_THRESH_CLX_QTH 0x0000FFFF
114#define CLXY_PAUSE_THRESH_CLY_QTH 0xFFFF0000
115
116struct mac_addr {
117 /* Lower 32 bits of 48-bit MAC address */
118 u32 mac_addr_l;
119 /* Upper 16 bits of 48-bit MAC address */
120 u32 mac_addr_u;
121};
122
123/* memory map */
124struct memac_regs {
125 u32 res0000[2]; /* General Control and Status */
126 u32 command_config; /* 0x008 Ctrl and cfg */
127 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */
128 u32 maxfrm; /* 0x014 Max frame length */
129 u32 res0018[1];
130 u32 rx_fifo_sections; /* Receive FIFO configuration reg */
131 u32 tx_fifo_sections; /* Transmit FIFO configuration reg */
132 u32 res0024[2];
133 u32 hashtable_ctrl; /* 0x02C Hash table control */
134 u32 res0030[4];
135 u32 ievent; /* 0x040 Interrupt event */
136 u32 tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */
137 u32 res0048;
138 u32 imask; /* 0x04C Interrupt mask */
139 u32 res0050;
140 u32 pause_quanta[4]; /* 0x054 Pause quanta */
141 u32 pause_thresh[4]; /* 0x064 Pause quanta threshold */
142 u32 rx_pause_status; /* 0x074 Receive pause status */
143 u32 res0078[2];
144 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */
145 u32 lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */
146 u32 sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */
147 u32 res00c0[8];
148 u32 statn_config; /* 0x0E0 Statistics configuration */
149 u32 res00e4[7];
150 /* Rx Statistics Counter */
151 u32 reoct_l;
152 u32 reoct_u;
153 u32 roct_l;
154 u32 roct_u;
155 u32 raln_l;
156 u32 raln_u;
157 u32 rxpf_l;
158 u32 rxpf_u;
159 u32 rfrm_l;
160 u32 rfrm_u;
161 u32 rfcs_l;
162 u32 rfcs_u;
163 u32 rvlan_l;
164 u32 rvlan_u;
165 u32 rerr_l;
166 u32 rerr_u;
167 u32 ruca_l;
168 u32 ruca_u;
169 u32 rmca_l;
170 u32 rmca_u;
171 u32 rbca_l;
172 u32 rbca_u;
173 u32 rdrp_l;
174 u32 rdrp_u;
175 u32 rpkt_l;
176 u32 rpkt_u;
177 u32 rund_l;
178 u32 rund_u;
179 u32 r64_l;
180 u32 r64_u;
181 u32 r127_l;
182 u32 r127_u;
183 u32 r255_l;
184 u32 r255_u;
185 u32 r511_l;
186 u32 r511_u;
187 u32 r1023_l;
188 u32 r1023_u;
189 u32 r1518_l;
190 u32 r1518_u;
191 u32 r1519x_l;
192 u32 r1519x_u;
193 u32 rovr_l;
194 u32 rovr_u;
195 u32 rjbr_l;
196 u32 rjbr_u;
197 u32 rfrg_l;
198 u32 rfrg_u;
199 u32 rcnp_l;
200 u32 rcnp_u;
201 u32 rdrntp_l;
202 u32 rdrntp_u;
203 u32 res01d0[12];
204 /* Tx Statistics Counter */
205 u32 teoct_l;
206 u32 teoct_u;
207 u32 toct_l;
208 u32 toct_u;
209 u32 res0210[2];
210 u32 txpf_l;
211 u32 txpf_u;
212 u32 tfrm_l;
213 u32 tfrm_u;
214 u32 tfcs_l;
215 u32 tfcs_u;
216 u32 tvlan_l;
217 u32 tvlan_u;
218 u32 terr_l;
219 u32 terr_u;
220 u32 tuca_l;
221 u32 tuca_u;
222 u32 tmca_l;
223 u32 tmca_u;
224 u32 tbca_l;
225 u32 tbca_u;
226 u32 res0258[2];
227 u32 tpkt_l;
228 u32 tpkt_u;
229 u32 tund_l;
230 u32 tund_u;
231 u32 t64_l;
232 u32 t64_u;
233 u32 t127_l;
234 u32 t127_u;
235 u32 t255_l;
236 u32 t255_u;
237 u32 t511_l;
238 u32 t511_u;
239 u32 t1023_l;
240 u32 t1023_u;
241 u32 t1518_l;
242 u32 t1518_u;
243 u32 t1519x_l;
244 u32 t1519x_u;
245 u32 res02a8[6];
246 u32 tcnp_l;
247 u32 tcnp_u;
248 u32 res02c8[14];
249 /* Line Interface Control */
250 u32 if_mode; /* 0x300 Interface Mode Control */
251 u32 if_status; /* 0x304 Interface Status */
252 u32 res0308[14];
253 /* HiGig/2 */
254 u32 hg_config; /* 0x340 Control and cfg */
255 u32 res0344[3];
256 u32 hg_pause_quanta; /* 0x350 Pause quanta */
257 u32 res0354[3];
258 u32 hg_pause_thresh; /* 0x360 Pause quanta threshold */
259 u32 res0364[3];
260 u32 hgrx_pause_status; /* 0x370 Receive pause status */
261 u32 hg_fifos_status; /* 0x374 fifos status */
262 u32 rhm; /* 0x378 rx messages counter */
263 u32 thm; /* 0x37C tx messages counter */
264};
265
266struct memac_cfg {
267 bool reset_on_init;
268 bool pause_ignore;
269 bool promiscuous_mode_enable;
270 struct fixed_phy_status *fixed_link;
271 u16 max_frame_length;
272 u16 pause_quanta;
273 u32 tx_ipg_length;
274};
275
276struct fman_mac {
277 /* Pointer to MAC memory mapped registers */
278 struct memac_regs __iomem *regs;
279 /* MAC address of device */
280 u64 addr;
281 struct mac_device *dev_id; /* device cookie used by the exception cbs */
282 fman_mac_exception_cb *exception_cb;
283 fman_mac_exception_cb *event_cb;
284 /* Pointer to driver's global address hash table */
285 struct eth_hash_t *multicast_addr_hash;
286 /* Pointer to driver's individual address hash table */
287 struct eth_hash_t *unicast_addr_hash;
288 u8 mac_id;
289 u32 exceptions;
290 struct memac_cfg *memac_drv_param;
291 void *fm;
292 struct fman_rev_info fm_rev_info;
293 struct phy *serdes;
294 struct phylink_pcs *sgmii_pcs;
295 struct phylink_pcs *qsgmii_pcs;
296 struct phylink_pcs *xfi_pcs;
297 bool allmulti_enabled;
298 bool rgmii_no_half_duplex;
299};
300
301static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr,
302 u8 paddr_num)
303{
304 u32 tmp0, tmp1;
305
306 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
307 tmp1 = (u32)(adr[4] | adr[5] << 8);
308
309 if (paddr_num == 0) {
310 iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l);
311 iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u);
312 } else {
313 iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l);
314 iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u);
315 }
316}
317
318static int reset(struct memac_regs __iomem *regs)
319{
320 u32 tmp;
321 int count;
322
323 tmp = ioread32be(®s->command_config);
324
325 tmp |= CMD_CFG_SW_RESET;
326
327 iowrite32be(tmp, ®s->command_config);
328
329 count = 100;
330 do {
331 udelay(1);
332 } while ((ioread32be(®s->command_config) & CMD_CFG_SW_RESET) &&
333 --count);
334
335 if (count == 0)
336 return -EBUSY;
337
338 return 0;
339}
340
341static void set_exception(struct memac_regs __iomem *regs, u32 val,
342 bool enable)
343{
344 u32 tmp;
345
346 tmp = ioread32be(®s->imask);
347 if (enable)
348 tmp |= val;
349 else
350 tmp &= ~val;
351
352 iowrite32be(tmp, ®s->imask);
353}
354
355static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,
356 u32 exceptions)
357{
358 u32 tmp;
359
360 /* Config */
361 tmp = 0;
362 if (cfg->promiscuous_mode_enable)
363 tmp |= CMD_CFG_PROMIS_EN;
364 if (cfg->pause_ignore)
365 tmp |= CMD_CFG_PAUSE_IGNORE;
366
367 /* Payload length check disable */
368 tmp |= CMD_CFG_NO_LEN_CHK;
369 /* Enable padding of frames in transmit direction */
370 tmp |= CMD_CFG_TX_PAD_EN;
371
372 tmp |= CMD_CFG_CRC_FWD;
373
374 iowrite32be(tmp, ®s->command_config);
375
376 /* Max Frame Length */
377 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm);
378
379 /* Pause Time */
380 iowrite32be((u32)cfg->pause_quanta, ®s->pause_quanta[0]);
381 iowrite32be((u32)0, ®s->pause_thresh[0]);
382
383 /* clear all pending events and set-up interrupts */
384 iowrite32be(0xffffffff, ®s->ievent);
385 set_exception(regs, exceptions, true);
386
387 return 0;
388}
389
390static void set_dflts(struct memac_cfg *cfg)
391{
392 cfg->reset_on_init = false;
393 cfg->promiscuous_mode_enable = false;
394 cfg->pause_ignore = false;
395 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
396 cfg->max_frame_length = DEFAULT_FRAME_LENGTH;
397 cfg->pause_quanta = DEFAULT_PAUSE_QUANTA;
398}
399
400static u32 get_mac_addr_hash_code(u64 eth_addr)
401{
402 u64 mask1, mask2;
403 u32 xor_val = 0;
404 u8 i, j;
405
406 for (i = 0; i < 6; i++) {
407 mask1 = eth_addr & (u64)0x01;
408 eth_addr >>= 1;
409
410 for (j = 0; j < 7; j++) {
411 mask2 = eth_addr & (u64)0x01;
412 mask1 ^= mask2;
413 eth_addr >>= 1;
414 }
415
416 xor_val |= (mask1 << (5 - i));
417 }
418
419 return xor_val;
420}
421
422static int check_init_parameters(struct fman_mac *memac)
423{
424 if (!memac->exception_cb) {
425 pr_err("Uninitialized exception handler\n");
426 return -EINVAL;
427 }
428 if (!memac->event_cb) {
429 pr_warn("Uninitialize event handler\n");
430 return -EINVAL;
431 }
432
433 return 0;
434}
435
436static int get_exception_flag(enum fman_mac_exceptions exception)
437{
438 u32 bit_mask;
439
440 switch (exception) {
441 case FM_MAC_EX_10G_TX_ECC_ER:
442 bit_mask = MEMAC_IMASK_TECC_ER;
443 break;
444 case FM_MAC_EX_10G_RX_ECC_ER:
445 bit_mask = MEMAC_IMASK_RECC_ER;
446 break;
447 case FM_MAC_EX_TS_FIFO_ECC_ERR:
448 bit_mask = MEMAC_IMASK_TSECC_ER;
449 break;
450 case FM_MAC_EX_MAGIC_PACKET_INDICATION:
451 bit_mask = MEMAC_IMASK_MGI;
452 break;
453 default:
454 bit_mask = 0;
455 break;
456 }
457
458 return bit_mask;
459}
460
461static void memac_err_exception(void *handle)
462{
463 struct fman_mac *memac = (struct fman_mac *)handle;
464 struct memac_regs __iomem *regs = memac->regs;
465 u32 event, imask;
466
467 event = ioread32be(®s->ievent);
468 imask = ioread32be(®s->imask);
469
470 /* Imask include both error and notification/event bits.
471 * Leaving only error bits enabled by imask.
472 * The imask error bits are shifted by 16 bits offset from
473 * their corresponding location in the ievent - hence the >> 16
474 */
475 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
476
477 iowrite32be(event, ®s->ievent);
478
479 if (event & MEMAC_IEVNT_TS_ECC_ER)
480 memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR);
481 if (event & MEMAC_IEVNT_TX_ECC_ER)
482 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER);
483 if (event & MEMAC_IEVNT_RX_ECC_ER)
484 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER);
485}
486
487static void memac_exception(void *handle)
488{
489 struct fman_mac *memac = (struct fman_mac *)handle;
490 struct memac_regs __iomem *regs = memac->regs;
491 u32 event, imask;
492
493 event = ioread32be(®s->ievent);
494 imask = ioread32be(®s->imask);
495
496 /* Imask include both error and notification/event bits.
497 * Leaving only error bits enabled by imask.
498 * The imask error bits are shifted by 16 bits offset from
499 * their corresponding location in the ievent - hence the >> 16
500 */
501 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
502
503 iowrite32be(event, ®s->ievent);
504
505 if (event & MEMAC_IEVNT_MGI)
506 memac->exception_cb(memac->dev_id,
507 FM_MAC_EX_MAGIC_PACKET_INDICATION);
508}
509
510static void free_init_resources(struct fman_mac *memac)
511{
512 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
513 FMAN_INTR_TYPE_ERR);
514
515 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
516 FMAN_INTR_TYPE_NORMAL);
517
518 /* release the driver's group hash table */
519 free_hash_table(memac->multicast_addr_hash);
520 memac->multicast_addr_hash = NULL;
521
522 /* release the driver's individual hash table */
523 free_hash_table(memac->unicast_addr_hash);
524 memac->unicast_addr_hash = NULL;
525}
526
527static int memac_enable(struct fman_mac *memac)
528{
529 int ret;
530
531 ret = phy_init(memac->serdes);
532 if (ret) {
533 dev_err(memac->dev_id->dev,
534 "could not initialize serdes: %pe\n", ERR_PTR(ret));
535 return ret;
536 }
537
538 ret = phy_power_on(memac->serdes);
539 if (ret) {
540 dev_err(memac->dev_id->dev,
541 "could not power on serdes: %pe\n", ERR_PTR(ret));
542 phy_exit(memac->serdes);
543 }
544
545 return ret;
546}
547
548static void memac_disable(struct fman_mac *memac)
549{
550 phy_power_off(memac->serdes);
551 phy_exit(memac->serdes);
552}
553
554static int memac_set_promiscuous(struct fman_mac *memac, bool new_val)
555{
556 struct memac_regs __iomem *regs = memac->regs;
557 u32 tmp;
558
559 tmp = ioread32be(®s->command_config);
560 if (new_val)
561 tmp |= CMD_CFG_PROMIS_EN;
562 else
563 tmp &= ~CMD_CFG_PROMIS_EN;
564
565 iowrite32be(tmp, ®s->command_config);
566
567 return 0;
568}
569
570static int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,
571 u16 pause_time, u16 thresh_time)
572{
573 struct memac_regs __iomem *regs = memac->regs;
574 u32 tmp;
575
576 tmp = ioread32be(®s->tx_fifo_sections);
577
578 GET_TX_EMPTY_DEFAULT_VALUE(tmp);
579 iowrite32be(tmp, ®s->tx_fifo_sections);
580
581 tmp = ioread32be(®s->command_config);
582 tmp &= ~CMD_CFG_PFC_MODE;
583
584 iowrite32be(tmp, ®s->command_config);
585
586 tmp = ioread32be(®s->pause_quanta[priority / 2]);
587 if (priority % 2)
588 tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT;
589 else
590 tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT;
591 tmp |= ((u32)pause_time << (16 * (priority % 2)));
592 iowrite32be(tmp, ®s->pause_quanta[priority / 2]);
593
594 tmp = ioread32be(®s->pause_thresh[priority / 2]);
595 if (priority % 2)
596 tmp &= CLXY_PAUSE_THRESH_CLX_QTH;
597 else
598 tmp &= CLXY_PAUSE_THRESH_CLY_QTH;
599 tmp |= ((u32)thresh_time << (16 * (priority % 2)));
600 iowrite32be(tmp, ®s->pause_thresh[priority / 2]);
601
602 return 0;
603}
604
605static int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en)
606{
607 struct memac_regs __iomem *regs = memac->regs;
608 u32 tmp;
609
610 tmp = ioread32be(®s->command_config);
611 if (en)
612 tmp &= ~CMD_CFG_PAUSE_IGNORE;
613 else
614 tmp |= CMD_CFG_PAUSE_IGNORE;
615
616 iowrite32be(tmp, ®s->command_config);
617
618 return 0;
619}
620
621static unsigned long memac_get_caps(struct phylink_config *config,
622 phy_interface_t interface)
623{
624 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
625 unsigned long caps = config->mac_capabilities;
626
627 if (phy_interface_mode_is_rgmii(interface) &&
628 memac->rgmii_no_half_duplex)
629 caps &= ~(MAC_10HD | MAC_100HD);
630
631 return caps;
632}
633
634/**
635 * memac_if_mode() - Convert an interface mode into an IF_MODE config
636 * @interface: A phy interface mode
637 *
638 * Return: A configuration word, suitable for programming into the lower bits
639 * of %IF_MODE.
640 */
641static u32 memac_if_mode(phy_interface_t interface)
642{
643 switch (interface) {
644 case PHY_INTERFACE_MODE_MII:
645 return IF_MODE_MII;
646 case PHY_INTERFACE_MODE_RGMII:
647 case PHY_INTERFACE_MODE_RGMII_ID:
648 case PHY_INTERFACE_MODE_RGMII_RXID:
649 case PHY_INTERFACE_MODE_RGMII_TXID:
650 return IF_MODE_GMII | IF_MODE_RGMII;
651 case PHY_INTERFACE_MODE_SGMII:
652 case PHY_INTERFACE_MODE_1000BASEX:
653 case PHY_INTERFACE_MODE_QSGMII:
654 return IF_MODE_GMII;
655 case PHY_INTERFACE_MODE_10GBASER:
656 return IF_MODE_10G;
657 default:
658 WARN_ON_ONCE(1);
659 return 0;
660 }
661}
662
663static struct phylink_pcs *memac_select_pcs(struct phylink_config *config,
664 phy_interface_t iface)
665{
666 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
667
668 switch (iface) {
669 case PHY_INTERFACE_MODE_SGMII:
670 case PHY_INTERFACE_MODE_1000BASEX:
671 return memac->sgmii_pcs;
672 case PHY_INTERFACE_MODE_QSGMII:
673 return memac->qsgmii_pcs;
674 case PHY_INTERFACE_MODE_10GBASER:
675 return memac->xfi_pcs;
676 default:
677 return NULL;
678 }
679}
680
681static int memac_prepare(struct phylink_config *config, unsigned int mode,
682 phy_interface_t iface)
683{
684 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
685
686 switch (iface) {
687 case PHY_INTERFACE_MODE_SGMII:
688 case PHY_INTERFACE_MODE_1000BASEX:
689 case PHY_INTERFACE_MODE_QSGMII:
690 case PHY_INTERFACE_MODE_10GBASER:
691 return phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
692 iface);
693 default:
694 return 0;
695 }
696}
697
698static void memac_mac_config(struct phylink_config *config, unsigned int mode,
699 const struct phylink_link_state *state)
700{
701 struct mac_device *mac_dev = fman_config_to_mac(config);
702 struct memac_regs __iomem *regs = mac_dev->fman_mac->regs;
703 u32 tmp = ioread32be(®s->if_mode);
704
705 tmp &= ~(IF_MODE_MASK | IF_MODE_RGMII);
706 tmp |= memac_if_mode(state->interface);
707 if (phylink_autoneg_inband(mode))
708 tmp |= IF_MODE_RGMII_AUTO;
709 iowrite32be(tmp, ®s->if_mode);
710}
711
712static void memac_link_up(struct phylink_config *config, struct phy_device *phy,
713 unsigned int mode, phy_interface_t interface,
714 int speed, int duplex, bool tx_pause, bool rx_pause)
715{
716 struct mac_device *mac_dev = fman_config_to_mac(config);
717 struct fman_mac *memac = mac_dev->fman_mac;
718 struct memac_regs __iomem *regs = memac->regs;
719 u32 tmp = memac_if_mode(interface);
720 u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
721 FSL_FM_PAUSE_TIME_DISABLE;
722
723 memac_set_tx_pause_frames(memac, 0, pause_time, 0);
724 memac_accept_rx_pause_frames(memac, rx_pause);
725
726 if (duplex == DUPLEX_HALF)
727 tmp |= IF_MODE_HD;
728
729 switch (speed) {
730 case SPEED_1000:
731 tmp |= IF_MODE_RGMII_1000;
732 break;
733 case SPEED_100:
734 tmp |= IF_MODE_RGMII_100;
735 break;
736 case SPEED_10:
737 tmp |= IF_MODE_RGMII_10;
738 break;
739 }
740 iowrite32be(tmp, ®s->if_mode);
741
742 /* TODO: EEE? */
743
744 if (speed == SPEED_10000) {
745 if (memac->fm_rev_info.major == 6 &&
746 memac->fm_rev_info.minor == 4)
747 tmp = TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G;
748 else
749 tmp = TX_FIFO_SECTIONS_TX_AVAIL_10G;
750 tmp |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G;
751 } else {
752 tmp = TX_FIFO_SECTIONS_TX_AVAIL_1G |
753 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G;
754 }
755 iowrite32be(tmp, ®s->tx_fifo_sections);
756
757 mac_dev->update_speed(mac_dev, speed);
758
759 tmp = ioread32be(®s->command_config);
760 tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
761 iowrite32be(tmp, ®s->command_config);
762}
763
764static void memac_link_down(struct phylink_config *config, unsigned int mode,
765 phy_interface_t interface)
766{
767 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
768 struct memac_regs __iomem *regs = memac->regs;
769 u32 tmp;
770
771 /* TODO: graceful */
772 tmp = ioread32be(®s->command_config);
773 tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
774 iowrite32be(tmp, ®s->command_config);
775}
776
777static const struct phylink_mac_ops memac_mac_ops = {
778 .mac_get_caps = memac_get_caps,
779 .mac_select_pcs = memac_select_pcs,
780 .mac_prepare = memac_prepare,
781 .mac_config = memac_mac_config,
782 .mac_link_up = memac_link_up,
783 .mac_link_down = memac_link_down,
784};
785
786static int memac_modify_mac_address(struct fman_mac *memac,
787 const enet_addr_t *enet_addr)
788{
789 add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0);
790
791 return 0;
792}
793
794static int memac_add_hash_mac_address(struct fman_mac *memac,
795 enet_addr_t *eth_addr)
796{
797 struct memac_regs __iomem *regs = memac->regs;
798 struct eth_hash_entry *hash_entry;
799 u32 hash;
800 u64 addr;
801
802 addr = ENET_ADDR_TO_UINT64(*eth_addr);
803
804 if (!(addr & GROUP_ADDRESS)) {
805 /* Unicast addresses not supported in hash */
806 pr_err("Unicast Address\n");
807 return -EINVAL;
808 }
809 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
810
811 /* Create element to be added to the driver hash table */
812 hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC);
813 if (!hash_entry)
814 return -ENOMEM;
815 hash_entry->addr = addr;
816 INIT_LIST_HEAD(&hash_entry->node);
817
818 list_add_tail(&hash_entry->node,
819 &memac->multicast_addr_hash->lsts[hash]);
820 iowrite32be(hash | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl);
821
822 return 0;
823}
824
825static int memac_set_allmulti(struct fman_mac *memac, bool enable)
826{
827 u32 entry;
828 struct memac_regs __iomem *regs = memac->regs;
829
830 if (enable) {
831 for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
832 iowrite32be(entry | HASH_CTRL_MCAST_EN,
833 ®s->hashtable_ctrl);
834 } else {
835 for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
836 iowrite32be(entry & ~HASH_CTRL_MCAST_EN,
837 ®s->hashtable_ctrl);
838 }
839
840 memac->allmulti_enabled = enable;
841
842 return 0;
843}
844
845static int memac_set_tstamp(struct fman_mac *memac, bool enable)
846{
847 return 0; /* Always enabled. */
848}
849
850static int memac_del_hash_mac_address(struct fman_mac *memac,
851 enet_addr_t *eth_addr)
852{
853 struct memac_regs __iomem *regs = memac->regs;
854 struct eth_hash_entry *hash_entry = NULL;
855 struct list_head *pos;
856 u32 hash;
857 u64 addr;
858
859 addr = ENET_ADDR_TO_UINT64(*eth_addr);
860
861 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
862
863 list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) {
864 hash_entry = ETH_HASH_ENTRY_OBJ(pos);
865 if (hash_entry && hash_entry->addr == addr) {
866 list_del_init(&hash_entry->node);
867 kfree(hash_entry);
868 break;
869 }
870 }
871
872 if (!memac->allmulti_enabled) {
873 if (list_empty(&memac->multicast_addr_hash->lsts[hash]))
874 iowrite32be(hash & ~HASH_CTRL_MCAST_EN,
875 ®s->hashtable_ctrl);
876 }
877
878 return 0;
879}
880
881static int memac_set_exception(struct fman_mac *memac,
882 enum fman_mac_exceptions exception, bool enable)
883{
884 u32 bit_mask = 0;
885
886 bit_mask = get_exception_flag(exception);
887 if (bit_mask) {
888 if (enable)
889 memac->exceptions |= bit_mask;
890 else
891 memac->exceptions &= ~bit_mask;
892 } else {
893 pr_err("Undefined exception\n");
894 return -EINVAL;
895 }
896 set_exception(memac->regs, bit_mask, enable);
897
898 return 0;
899}
900
901static int memac_init(struct fman_mac *memac)
902{
903 struct memac_cfg *memac_drv_param;
904 enet_addr_t eth_addr;
905 int err;
906 u32 reg32 = 0;
907
908 err = check_init_parameters(memac);
909 if (err)
910 return err;
911
912 memac_drv_param = memac->memac_drv_param;
913
914 /* First, reset the MAC if desired. */
915 if (memac_drv_param->reset_on_init) {
916 err = reset(memac->regs);
917 if (err) {
918 pr_err("mEMAC reset failed\n");
919 return err;
920 }
921 }
922
923 /* MAC Address */
924 if (memac->addr != 0) {
925 MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr);
926 add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0);
927 }
928
929 init(memac->regs, memac->memac_drv_param, memac->exceptions);
930
931 /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround
932 * Exists only in FMan 6.0 and 6.3.
933 */
934 if ((memac->fm_rev_info.major == 6) &&
935 ((memac->fm_rev_info.minor == 0) ||
936 (memac->fm_rev_info.minor == 3))) {
937 /* MAC strips CRC from received frames - this workaround
938 * should decrease the likelihood of bug appearance
939 */
940 reg32 = ioread32be(&memac->regs->command_config);
941 reg32 &= ~CMD_CFG_CRC_FWD;
942 iowrite32be(reg32, &memac->regs->command_config);
943 }
944
945 /* Max Frame Length */
946 err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
947 memac_drv_param->max_frame_length);
948 if (err) {
949 pr_err("settings Mac max frame length is FAILED\n");
950 return err;
951 }
952
953 memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
954 if (!memac->multicast_addr_hash) {
955 free_init_resources(memac);
956 pr_err("allocation hash table is FAILED\n");
957 return -ENOMEM;
958 }
959
960 memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
961 if (!memac->unicast_addr_hash) {
962 free_init_resources(memac);
963 pr_err("allocation hash table is FAILED\n");
964 return -ENOMEM;
965 }
966
967 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
968 FMAN_INTR_TYPE_ERR, memac_err_exception, memac);
969
970 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
971 FMAN_INTR_TYPE_NORMAL, memac_exception, memac);
972
973 return 0;
974}
975
976static void pcs_put(struct phylink_pcs *pcs)
977{
978 if (IS_ERR_OR_NULL(pcs))
979 return;
980
981 lynx_pcs_destroy(pcs);
982}
983
984static int memac_free(struct fman_mac *memac)
985{
986 free_init_resources(memac);
987
988 pcs_put(memac->sgmii_pcs);
989 pcs_put(memac->qsgmii_pcs);
990 pcs_put(memac->xfi_pcs);
991 kfree(memac->memac_drv_param);
992 kfree(memac);
993
994 return 0;
995}
996
997static struct fman_mac *memac_config(struct mac_device *mac_dev,
998 struct fman_mac_params *params)
999{
1000 struct fman_mac *memac;
1001 struct memac_cfg *memac_drv_param;
1002
1003 /* allocate memory for the m_emac data structure */
1004 memac = kzalloc(sizeof(*memac), GFP_KERNEL);
1005 if (!memac)
1006 return NULL;
1007
1008 /* allocate memory for the m_emac driver parameters data structure */
1009 memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL);
1010 if (!memac_drv_param) {
1011 memac_free(memac);
1012 return NULL;
1013 }
1014
1015 /* Plant parameter structure pointer */
1016 memac->memac_drv_param = memac_drv_param;
1017
1018 set_dflts(memac_drv_param);
1019
1020 memac->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
1021
1022 memac->regs = mac_dev->vaddr;
1023 memac->mac_id = params->mac_id;
1024 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |
1025 MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);
1026 memac->exception_cb = params->exception_cb;
1027 memac->event_cb = params->event_cb;
1028 memac->dev_id = mac_dev;
1029 memac->fm = params->fm;
1030
1031 /* Save FMan revision */
1032 fman_get_revision(memac->fm, &memac->fm_rev_info);
1033
1034 return memac;
1035}
1036
1037static struct phylink_pcs *memac_pcs_create(struct device_node *mac_node,
1038 int index)
1039{
1040 struct device_node *node;
1041 struct phylink_pcs *pcs;
1042
1043 node = of_parse_phandle(mac_node, "pcsphy-handle", index);
1044 if (!node)
1045 return ERR_PTR(-ENODEV);
1046
1047 pcs = lynx_pcs_create_fwnode(of_fwnode_handle(node));
1048 of_node_put(node);
1049
1050 return pcs;
1051}
1052
1053static bool memac_supports(struct mac_device *mac_dev, phy_interface_t iface)
1054{
1055 /* If there's no serdes device, assume that it's been configured for
1056 * whatever the default interface mode is.
1057 */
1058 if (!mac_dev->fman_mac->serdes)
1059 return mac_dev->phy_if == iface;
1060 /* Otherwise, ask the serdes */
1061 return !phy_validate(mac_dev->fman_mac->serdes, PHY_MODE_ETHERNET,
1062 iface, NULL);
1063}
1064
1065int memac_initialization(struct mac_device *mac_dev,
1066 struct device_node *mac_node,
1067 struct fman_mac_params *params)
1068{
1069 int err;
1070 struct device_node *fixed;
1071 struct phylink_pcs *pcs;
1072 struct fman_mac *memac;
1073 unsigned long capabilities;
1074 unsigned long *supported;
1075
1076 /* The internal connection to the serdes is XGMII, but this isn't
1077 * really correct for the phy mode (which is the external connection).
1078 * However, this is how all older device trees say that they want
1079 * 10GBASE-R (aka XFI), so just convert it for them.
1080 */
1081 if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
1082 mac_dev->phy_if = PHY_INTERFACE_MODE_10GBASER;
1083
1084 mac_dev->phylink_ops = &memac_mac_ops;
1085 mac_dev->set_promisc = memac_set_promiscuous;
1086 mac_dev->change_addr = memac_modify_mac_address;
1087 mac_dev->add_hash_mac_addr = memac_add_hash_mac_address;
1088 mac_dev->remove_hash_mac_addr = memac_del_hash_mac_address;
1089 mac_dev->set_exception = memac_set_exception;
1090 mac_dev->set_allmulti = memac_set_allmulti;
1091 mac_dev->set_tstamp = memac_set_tstamp;
1092 mac_dev->set_multi = fman_set_multi;
1093 mac_dev->enable = memac_enable;
1094 mac_dev->disable = memac_disable;
1095
1096 mac_dev->fman_mac = memac_config(mac_dev, params);
1097 if (!mac_dev->fman_mac)
1098 return -EINVAL;
1099
1100 memac = mac_dev->fman_mac;
1101 memac->memac_drv_param->max_frame_length = fman_get_max_frm();
1102 memac->memac_drv_param->reset_on_init = true;
1103
1104 err = of_property_match_string(mac_node, "pcs-handle-names", "xfi");
1105 if (err >= 0) {
1106 memac->xfi_pcs = memac_pcs_create(mac_node, err);
1107 if (IS_ERR(memac->xfi_pcs)) {
1108 err = PTR_ERR(memac->xfi_pcs);
1109 dev_err_probe(mac_dev->dev, err, "missing xfi pcs\n");
1110 goto _return_fm_mac_free;
1111 }
1112 } else if (err != -EINVAL && err != -ENODATA) {
1113 goto _return_fm_mac_free;
1114 }
1115
1116 err = of_property_match_string(mac_node, "pcs-handle-names", "qsgmii");
1117 if (err >= 0) {
1118 memac->qsgmii_pcs = memac_pcs_create(mac_node, err);
1119 if (IS_ERR(memac->qsgmii_pcs)) {
1120 err = PTR_ERR(memac->qsgmii_pcs);
1121 dev_err_probe(mac_dev->dev, err,
1122 "missing qsgmii pcs\n");
1123 goto _return_fm_mac_free;
1124 }
1125 } else if (err != -EINVAL && err != -ENODATA) {
1126 goto _return_fm_mac_free;
1127 }
1128
1129 /* For compatibility, if pcs-handle-names is missing, we assume this
1130 * phy is the first one in pcsphy-handle
1131 */
1132 err = of_property_match_string(mac_node, "pcs-handle-names", "sgmii");
1133 if (err == -EINVAL || err == -ENODATA)
1134 pcs = memac_pcs_create(mac_node, 0);
1135 else if (err < 0)
1136 goto _return_fm_mac_free;
1137 else
1138 pcs = memac_pcs_create(mac_node, err);
1139
1140 if (IS_ERR(pcs)) {
1141 err = PTR_ERR(pcs);
1142 dev_err_probe(mac_dev->dev, err, "missing pcs\n");
1143 goto _return_fm_mac_free;
1144 }
1145
1146 /* If err is set here, it means that pcs-handle-names was missing above
1147 * (and therefore that xfi_pcs cannot be set). If we are defaulting to
1148 * XGMII, assume this is for XFI. Otherwise, assume it is for SGMII.
1149 */
1150 if (err && mac_dev->phy_if == PHY_INTERFACE_MODE_10GBASER)
1151 memac->xfi_pcs = pcs;
1152 else
1153 memac->sgmii_pcs = pcs;
1154
1155 memac->serdes = devm_of_phy_optional_get(mac_dev->dev, mac_node,
1156 "serdes");
1157 if (!memac->serdes) {
1158 dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");
1159 } else if (IS_ERR(memac->serdes)) {
1160 err = PTR_ERR(memac->serdes);
1161 goto _return_fm_mac_free;
1162 }
1163
1164 /* TODO: The following interface modes are supported by (some) hardware
1165 * but not by this driver:
1166 * - 1000BASE-KX
1167 * - 10GBASE-KR
1168 * - XAUI/HiGig
1169 */
1170 supported = mac_dev->phylink_config.supported_interfaces;
1171
1172 /* Note that half duplex is only supported on 10/100M interfaces. */
1173
1174 if (memac->sgmii_pcs &&
1175 (memac_supports(mac_dev, PHY_INTERFACE_MODE_SGMII) ||
1176 memac_supports(mac_dev, PHY_INTERFACE_MODE_1000BASEX))) {
1177 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
1178 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
1179 }
1180
1181 if (memac->sgmii_pcs &&
1182 memac_supports(mac_dev, PHY_INTERFACE_MODE_2500BASEX))
1183 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
1184
1185 if (memac->qsgmii_pcs &&
1186 memac_supports(mac_dev, PHY_INTERFACE_MODE_QSGMII))
1187 __set_bit(PHY_INTERFACE_MODE_QSGMII, supported);
1188 else if (mac_dev->phy_if == PHY_INTERFACE_MODE_QSGMII)
1189 dev_warn(mac_dev->dev, "no QSGMII pcs specified\n");
1190
1191 if (memac->xfi_pcs &&
1192 memac_supports(mac_dev, PHY_INTERFACE_MODE_10GBASER)) {
1193 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
1194 } else {
1195 /* From what I can tell, no 10g macs support RGMII. */
1196 phy_interface_set_rgmii(supported);
1197 __set_bit(PHY_INTERFACE_MODE_MII, supported);
1198 }
1199
1200 capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10 | MAC_100;
1201 capabilities |= MAC_1000FD | MAC_2500FD | MAC_10000FD;
1202
1203 /* These SoCs don't support half duplex at all; there's no different
1204 * FMan version or compatible, so we just have to check the machine
1205 * compatible instead
1206 */
1207 if (of_machine_is_compatible("fsl,ls1043a") ||
1208 of_machine_is_compatible("fsl,ls1046a") ||
1209 of_machine_is_compatible("fsl,B4QDS"))
1210 capabilities &= ~(MAC_10HD | MAC_100HD);
1211
1212 mac_dev->phylink_config.mac_capabilities = capabilities;
1213
1214 /* The T2080 and T4240 don't support half duplex RGMII. There is no
1215 * other way to identify these SoCs, so just use the machine
1216 * compatible.
1217 */
1218 if (of_machine_is_compatible("fsl,T2080QDS") ||
1219 of_machine_is_compatible("fsl,T2080RDB") ||
1220 of_machine_is_compatible("fsl,T2081QDS") ||
1221 of_machine_is_compatible("fsl,T4240QDS") ||
1222 of_machine_is_compatible("fsl,T4240RDB"))
1223 memac->rgmii_no_half_duplex = true;
1224
1225 /* Most boards should use MLO_AN_INBAND, but existing boards don't have
1226 * a managed property. Default to MLO_AN_INBAND if nothing else is
1227 * specified. We need to be careful and not enable this if we have a
1228 * fixed link or if we are using MII or RGMII, since those
1229 * configurations modes don't use in-band autonegotiation.
1230 */
1231 fixed = of_get_child_by_name(mac_node, "fixed-link");
1232 if (!fixed && !of_property_read_bool(mac_node, "fixed-link") &&
1233 !of_property_read_bool(mac_node, "managed") &&
1234 mac_dev->phy_if != PHY_INTERFACE_MODE_MII &&
1235 !phy_interface_mode_is_rgmii(mac_dev->phy_if))
1236 mac_dev->phylink_config.ovr_an_inband = true;
1237 of_node_put(fixed);
1238
1239 err = memac_init(mac_dev->fman_mac);
1240 if (err < 0)
1241 goto _return_fm_mac_free;
1242
1243 dev_info(mac_dev->dev, "FMan MEMAC\n");
1244
1245 return 0;
1246
1247_return_fm_mac_free:
1248 memac_free(mac_dev->fman_mac);
1249 return err;
1250}
1/*
2 * Copyright 2008-2015 Freescale Semiconductor Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution.
11 * * Neither the name of Freescale Semiconductor nor the
12 * names of its contributors may be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 *
16 * ALTERNATIVELY, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
19 * later version.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35#include "fman_memac.h"
36#include "fman.h"
37
38#include <linux/slab.h>
39#include <linux/io.h>
40#include <linux/phy.h>
41#include <linux/of_mdio.h>
42
43/* PCS registers */
44#define MDIO_SGMII_CR 0x00
45#define MDIO_SGMII_DEV_ABIL_SGMII 0x04
46#define MDIO_SGMII_LINK_TMR_L 0x12
47#define MDIO_SGMII_LINK_TMR_H 0x13
48#define MDIO_SGMII_IF_MODE 0x14
49
50/* SGMII Control defines */
51#define SGMII_CR_AN_EN 0x1000
52#define SGMII_CR_RESTART_AN 0x0200
53#define SGMII_CR_FD 0x0100
54#define SGMII_CR_SPEED_SEL1_1G 0x0040
55#define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \
56 SGMII_CR_SPEED_SEL1_1G)
57
58/* SGMII Device Ability for SGMII defines */
59#define MDIO_SGMII_DEV_ABIL_SGMII_MODE 0x4001
60#define MDIO_SGMII_DEV_ABIL_BASEX_MODE 0x01A0
61
62/* Link timer define */
63#define LINK_TMR_L 0xa120
64#define LINK_TMR_H 0x0007
65#define LINK_TMR_L_BASEX 0xaf08
66#define LINK_TMR_H_BASEX 0x002f
67
68/* SGMII IF Mode defines */
69#define IF_MODE_USE_SGMII_AN 0x0002
70#define IF_MODE_SGMII_EN 0x0001
71#define IF_MODE_SGMII_SPEED_100M 0x0004
72#define IF_MODE_SGMII_SPEED_1G 0x0008
73#define IF_MODE_SGMII_DUPLEX_HALF 0x0010
74
75/* Num of additional exact match MAC adr regs */
76#define MEMAC_NUM_OF_PADDRS 7
77
78/* Control and Configuration Register (COMMAND_CONFIG) */
79#define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */
80#define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */
81#define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */
82#define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */
83#define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */
84#define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */
85#define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */
86#define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */
87#define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */
88#define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */
89#define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */
90#define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */
91
92/* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */
93#define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000
94#define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF
95#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000
96#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000
97#define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019
98#define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020
99#define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060
100
101#define GET_TX_EMPTY_DEFAULT_VALUE(_val) \
102do { \
103 _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \
104 ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \
105 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\
106 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\
107} while (0)
108
109/* Interface Mode Register (IF_MODE) */
110
111#define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
112#define IF_MODE_XGMII 0x00000000 /* 30-31 XGMII (10G) interface */
113#define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
114#define IF_MODE_RGMII 0x00000004
115#define IF_MODE_RGMII_AUTO 0x00008000
116#define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
117#define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
118#define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
119#define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */
120#define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */
121#define IF_MODE_HD 0x00000040 /* Half duplex operation */
122
123/* Hash table Control Register (HASHTABLE_CTRL) */
124#define HASH_CTRL_MCAST_EN 0x00000100
125/* 26-31 Hash table address code */
126#define HASH_CTRL_ADDR_MASK 0x0000003F
127/* MAC mcast indication */
128#define GROUP_ADDRESS 0x0000010000000000LL
129#define HASH_TABLE_SIZE 64 /* Hash tbl size */
130
131/* Interrupt Mask Register (IMASK) */
132#define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */
133#define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */
134#define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */
135#define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */
136
137#define MEMAC_ALL_ERRS_IMASK \
138 ((u32)(MEMAC_IMASK_TSECC_ER | \
139 MEMAC_IMASK_TECC_ER | \
140 MEMAC_IMASK_RECC_ER | \
141 MEMAC_IMASK_MGI))
142
143#define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */
144#define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */
145#define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */
146#define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */
147#define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error*/
148#define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */
149#define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
150#define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */
151#define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */
152#define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */
153#define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */
154#define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */
155#define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */
156#define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */
157#define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */
158#define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */
159#define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */
160
161#define DEFAULT_PAUSE_QUANTA 0xf000
162#define DEFAULT_FRAME_LENGTH 0x600
163#define DEFAULT_TX_IPG_LENGTH 12
164
165#define CLXY_PAUSE_QUANTA_CLX_PQNT 0x0000FFFF
166#define CLXY_PAUSE_QUANTA_CLY_PQNT 0xFFFF0000
167#define CLXY_PAUSE_THRESH_CLX_QTH 0x0000FFFF
168#define CLXY_PAUSE_THRESH_CLY_QTH 0xFFFF0000
169
170struct mac_addr {
171 /* Lower 32 bits of 48-bit MAC address */
172 u32 mac_addr_l;
173 /* Upper 16 bits of 48-bit MAC address */
174 u32 mac_addr_u;
175};
176
177/* memory map */
178struct memac_regs {
179 u32 res0000[2]; /* General Control and Status */
180 u32 command_config; /* 0x008 Ctrl and cfg */
181 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */
182 u32 maxfrm; /* 0x014 Max frame length */
183 u32 res0018[1];
184 u32 rx_fifo_sections; /* Receive FIFO configuration reg */
185 u32 tx_fifo_sections; /* Transmit FIFO configuration reg */
186 u32 res0024[2];
187 u32 hashtable_ctrl; /* 0x02C Hash table control */
188 u32 res0030[4];
189 u32 ievent; /* 0x040 Interrupt event */
190 u32 tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */
191 u32 res0048;
192 u32 imask; /* 0x04C Interrupt mask */
193 u32 res0050;
194 u32 pause_quanta[4]; /* 0x054 Pause quanta */
195 u32 pause_thresh[4]; /* 0x064 Pause quanta threshold */
196 u32 rx_pause_status; /* 0x074 Receive pause status */
197 u32 res0078[2];
198 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */
199 u32 lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */
200 u32 sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */
201 u32 res00c0[8];
202 u32 statn_config; /* 0x0E0 Statistics configuration */
203 u32 res00e4[7];
204 /* Rx Statistics Counter */
205 u32 reoct_l;
206 u32 reoct_u;
207 u32 roct_l;
208 u32 roct_u;
209 u32 raln_l;
210 u32 raln_u;
211 u32 rxpf_l;
212 u32 rxpf_u;
213 u32 rfrm_l;
214 u32 rfrm_u;
215 u32 rfcs_l;
216 u32 rfcs_u;
217 u32 rvlan_l;
218 u32 rvlan_u;
219 u32 rerr_l;
220 u32 rerr_u;
221 u32 ruca_l;
222 u32 ruca_u;
223 u32 rmca_l;
224 u32 rmca_u;
225 u32 rbca_l;
226 u32 rbca_u;
227 u32 rdrp_l;
228 u32 rdrp_u;
229 u32 rpkt_l;
230 u32 rpkt_u;
231 u32 rund_l;
232 u32 rund_u;
233 u32 r64_l;
234 u32 r64_u;
235 u32 r127_l;
236 u32 r127_u;
237 u32 r255_l;
238 u32 r255_u;
239 u32 r511_l;
240 u32 r511_u;
241 u32 r1023_l;
242 u32 r1023_u;
243 u32 r1518_l;
244 u32 r1518_u;
245 u32 r1519x_l;
246 u32 r1519x_u;
247 u32 rovr_l;
248 u32 rovr_u;
249 u32 rjbr_l;
250 u32 rjbr_u;
251 u32 rfrg_l;
252 u32 rfrg_u;
253 u32 rcnp_l;
254 u32 rcnp_u;
255 u32 rdrntp_l;
256 u32 rdrntp_u;
257 u32 res01d0[12];
258 /* Tx Statistics Counter */
259 u32 teoct_l;
260 u32 teoct_u;
261 u32 toct_l;
262 u32 toct_u;
263 u32 res0210[2];
264 u32 txpf_l;
265 u32 txpf_u;
266 u32 tfrm_l;
267 u32 tfrm_u;
268 u32 tfcs_l;
269 u32 tfcs_u;
270 u32 tvlan_l;
271 u32 tvlan_u;
272 u32 terr_l;
273 u32 terr_u;
274 u32 tuca_l;
275 u32 tuca_u;
276 u32 tmca_l;
277 u32 tmca_u;
278 u32 tbca_l;
279 u32 tbca_u;
280 u32 res0258[2];
281 u32 tpkt_l;
282 u32 tpkt_u;
283 u32 tund_l;
284 u32 tund_u;
285 u32 t64_l;
286 u32 t64_u;
287 u32 t127_l;
288 u32 t127_u;
289 u32 t255_l;
290 u32 t255_u;
291 u32 t511_l;
292 u32 t511_u;
293 u32 t1023_l;
294 u32 t1023_u;
295 u32 t1518_l;
296 u32 t1518_u;
297 u32 t1519x_l;
298 u32 t1519x_u;
299 u32 res02a8[6];
300 u32 tcnp_l;
301 u32 tcnp_u;
302 u32 res02c8[14];
303 /* Line Interface Control */
304 u32 if_mode; /* 0x300 Interface Mode Control */
305 u32 if_status; /* 0x304 Interface Status */
306 u32 res0308[14];
307 /* HiGig/2 */
308 u32 hg_config; /* 0x340 Control and cfg */
309 u32 res0344[3];
310 u32 hg_pause_quanta; /* 0x350 Pause quanta */
311 u32 res0354[3];
312 u32 hg_pause_thresh; /* 0x360 Pause quanta threshold */
313 u32 res0364[3];
314 u32 hgrx_pause_status; /* 0x370 Receive pause status */
315 u32 hg_fifos_status; /* 0x374 fifos status */
316 u32 rhm; /* 0x378 rx messages counter */
317 u32 thm; /* 0x37C tx messages counter */
318};
319
320struct memac_cfg {
321 bool reset_on_init;
322 bool pause_ignore;
323 bool promiscuous_mode_enable;
324 struct fixed_phy_status *fixed_link;
325 u16 max_frame_length;
326 u16 pause_quanta;
327 u32 tx_ipg_length;
328};
329
330struct fman_mac {
331 /* Pointer to MAC memory mapped registers */
332 struct memac_regs __iomem *regs;
333 /* MAC address of device */
334 u64 addr;
335 /* Ethernet physical interface */
336 phy_interface_t phy_if;
337 u16 max_speed;
338 void *dev_id; /* device cookie used by the exception cbs */
339 fman_mac_exception_cb *exception_cb;
340 fman_mac_exception_cb *event_cb;
341 /* Pointer to driver's global address hash table */
342 struct eth_hash_t *multicast_addr_hash;
343 /* Pointer to driver's individual address hash table */
344 struct eth_hash_t *unicast_addr_hash;
345 u8 mac_id;
346 u32 exceptions;
347 struct memac_cfg *memac_drv_param;
348 void *fm;
349 struct fman_rev_info fm_rev_info;
350 bool basex_if;
351 struct phy_device *pcsphy;
352};
353
354static void add_addr_in_paddr(struct memac_regs __iomem *regs, u8 *adr,
355 u8 paddr_num)
356{
357 u32 tmp0, tmp1;
358
359 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
360 tmp1 = (u32)(adr[4] | adr[5] << 8);
361
362 if (paddr_num == 0) {
363 iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l);
364 iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u);
365 } else {
366 iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l);
367 iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u);
368 }
369}
370
371static int reset(struct memac_regs __iomem *regs)
372{
373 u32 tmp;
374 int count;
375
376 tmp = ioread32be(®s->command_config);
377
378 tmp |= CMD_CFG_SW_RESET;
379
380 iowrite32be(tmp, ®s->command_config);
381
382 count = 100;
383 do {
384 udelay(1);
385 } while ((ioread32be(®s->command_config) & CMD_CFG_SW_RESET) &&
386 --count);
387
388 if (count == 0)
389 return -EBUSY;
390
391 return 0;
392}
393
394static void set_exception(struct memac_regs __iomem *regs, u32 val,
395 bool enable)
396{
397 u32 tmp;
398
399 tmp = ioread32be(®s->imask);
400 if (enable)
401 tmp |= val;
402 else
403 tmp &= ~val;
404
405 iowrite32be(tmp, ®s->imask);
406}
407
408static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,
409 phy_interface_t phy_if, u16 speed, bool slow_10g_if,
410 u32 exceptions)
411{
412 u32 tmp;
413
414 /* Config */
415 tmp = 0;
416 if (cfg->promiscuous_mode_enable)
417 tmp |= CMD_CFG_PROMIS_EN;
418 if (cfg->pause_ignore)
419 tmp |= CMD_CFG_PAUSE_IGNORE;
420
421 /* Payload length check disable */
422 tmp |= CMD_CFG_NO_LEN_CHK;
423 /* Enable padding of frames in transmit direction */
424 tmp |= CMD_CFG_TX_PAD_EN;
425
426 tmp |= CMD_CFG_CRC_FWD;
427
428 iowrite32be(tmp, ®s->command_config);
429
430 /* Max Frame Length */
431 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm);
432
433 /* Pause Time */
434 iowrite32be((u32)cfg->pause_quanta, ®s->pause_quanta[0]);
435 iowrite32be((u32)0, ®s->pause_thresh[0]);
436
437 /* IF_MODE */
438 tmp = 0;
439 switch (phy_if) {
440 case PHY_INTERFACE_MODE_XGMII:
441 tmp |= IF_MODE_XGMII;
442 break;
443 default:
444 tmp |= IF_MODE_GMII;
445 if (phy_if == PHY_INTERFACE_MODE_RGMII)
446 tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
447 }
448 iowrite32be(tmp, ®s->if_mode);
449
450 /* TX_FIFO_SECTIONS */
451 tmp = 0;
452 if (phy_if == PHY_INTERFACE_MODE_XGMII) {
453 if (slow_10g_if) {
454 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G |
455 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
456 } else {
457 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
458 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
459 }
460 } else {
461 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
462 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
463 }
464 iowrite32be(tmp, ®s->tx_fifo_sections);
465
466 /* clear all pending events and set-up interrupts */
467 iowrite32be(0xffffffff, ®s->ievent);
468 set_exception(regs, exceptions, true);
469
470 return 0;
471}
472
473static void set_dflts(struct memac_cfg *cfg)
474{
475 cfg->reset_on_init = false;
476 cfg->promiscuous_mode_enable = false;
477 cfg->pause_ignore = false;
478 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
479 cfg->max_frame_length = DEFAULT_FRAME_LENGTH;
480 cfg->pause_quanta = DEFAULT_PAUSE_QUANTA;
481}
482
483static u32 get_mac_addr_hash_code(u64 eth_addr)
484{
485 u64 mask1, mask2;
486 u32 xor_val = 0;
487 u8 i, j;
488
489 for (i = 0; i < 6; i++) {
490 mask1 = eth_addr & (u64)0x01;
491 eth_addr >>= 1;
492
493 for (j = 0; j < 7; j++) {
494 mask2 = eth_addr & (u64)0x01;
495 mask1 ^= mask2;
496 eth_addr >>= 1;
497 }
498
499 xor_val |= (mask1 << (5 - i));
500 }
501
502 return xor_val;
503}
504
505static void setup_sgmii_internal_phy(struct fman_mac *memac,
506 struct fixed_phy_status *fixed_link)
507{
508 u16 tmp_reg16;
509
510 if (WARN_ON(!memac->pcsphy))
511 return;
512
513 /* SGMII mode */
514 tmp_reg16 = IF_MODE_SGMII_EN;
515 if (!fixed_link)
516 /* AN enable */
517 tmp_reg16 |= IF_MODE_USE_SGMII_AN;
518 else {
519 switch (fixed_link->speed) {
520 case 10:
521 /* For 10M: IF_MODE[SPEED_10M] = 0 */
522 break;
523 case 100:
524 tmp_reg16 |= IF_MODE_SGMII_SPEED_100M;
525 break;
526 case 1000: /* fallthrough */
527 default:
528 tmp_reg16 |= IF_MODE_SGMII_SPEED_1G;
529 break;
530 }
531 if (!fixed_link->duplex)
532 tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF;
533 }
534 phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16);
535
536 /* Device ability according to SGMII specification */
537 tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE;
538 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
539
540 /* Adjust link timer for SGMII -
541 * According to Cisco SGMII specification the timer should be 1.6 ms.
542 * The link_timer register is configured in units of the clock.
543 * - When running as 1G SGMII, Serdes clock is 125 MHz, so
544 * unit = 1 / (125*10^6 Hz) = 8 ns.
545 * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40
546 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
547 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
548 * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120.
549 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
550 * we always set up here a value of 2.5 SGMII.
551 */
552 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H);
553 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L);
554
555 if (!fixed_link)
556 /* Restart AN */
557 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
558 else
559 /* AN disabled */
560 tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN;
561 phy_write(memac->pcsphy, 0x0, tmp_reg16);
562}
563
564static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac)
565{
566 u16 tmp_reg16;
567
568 /* AN Device capability */
569 tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE;
570 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
571
572 /* Adjust link timer for SGMII -
573 * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms.
574 * The link_timer register is configured in units of the clock.
575 * - When running as 1G SGMII, Serdes clock is 125 MHz, so
576 * unit = 1 / (125*10^6 Hz) = 8 ns.
577 * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0
578 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
579 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
580 * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08.
581 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
582 * we always set up here a value of 2.5 SGMII.
583 */
584 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX);
585 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX);
586
587 /* Restart AN */
588 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
589 phy_write(memac->pcsphy, 0x0, tmp_reg16);
590}
591
592static int check_init_parameters(struct fman_mac *memac)
593{
594 if (memac->addr == 0) {
595 pr_err("Ethernet MAC must have a valid MAC address\n");
596 return -EINVAL;
597 }
598 if (!memac->exception_cb) {
599 pr_err("Uninitialized exception handler\n");
600 return -EINVAL;
601 }
602 if (!memac->event_cb) {
603 pr_warn("Uninitialize event handler\n");
604 return -EINVAL;
605 }
606
607 return 0;
608}
609
610static int get_exception_flag(enum fman_mac_exceptions exception)
611{
612 u32 bit_mask;
613
614 switch (exception) {
615 case FM_MAC_EX_10G_TX_ECC_ER:
616 bit_mask = MEMAC_IMASK_TECC_ER;
617 break;
618 case FM_MAC_EX_10G_RX_ECC_ER:
619 bit_mask = MEMAC_IMASK_RECC_ER;
620 break;
621 case FM_MAC_EX_TS_FIFO_ECC_ERR:
622 bit_mask = MEMAC_IMASK_TSECC_ER;
623 break;
624 case FM_MAC_EX_MAGIC_PACKET_INDICATION:
625 bit_mask = MEMAC_IMASK_MGI;
626 break;
627 default:
628 bit_mask = 0;
629 break;
630 }
631
632 return bit_mask;
633}
634
635static void memac_err_exception(void *handle)
636{
637 struct fman_mac *memac = (struct fman_mac *)handle;
638 struct memac_regs __iomem *regs = memac->regs;
639 u32 event, imask;
640
641 event = ioread32be(®s->ievent);
642 imask = ioread32be(®s->imask);
643
644 /* Imask include both error and notification/event bits.
645 * Leaving only error bits enabled by imask.
646 * The imask error bits are shifted by 16 bits offset from
647 * their corresponding location in the ievent - hence the >> 16
648 */
649 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
650
651 iowrite32be(event, ®s->ievent);
652
653 if (event & MEMAC_IEVNT_TS_ECC_ER)
654 memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR);
655 if (event & MEMAC_IEVNT_TX_ECC_ER)
656 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER);
657 if (event & MEMAC_IEVNT_RX_ECC_ER)
658 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER);
659}
660
661static void memac_exception(void *handle)
662{
663 struct fman_mac *memac = (struct fman_mac *)handle;
664 struct memac_regs __iomem *regs = memac->regs;
665 u32 event, imask;
666
667 event = ioread32be(®s->ievent);
668 imask = ioread32be(®s->imask);
669
670 /* Imask include both error and notification/event bits.
671 * Leaving only error bits enabled by imask.
672 * The imask error bits are shifted by 16 bits offset from
673 * their corresponding location in the ievent - hence the >> 16
674 */
675 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
676
677 iowrite32be(event, ®s->ievent);
678
679 if (event & MEMAC_IEVNT_MGI)
680 memac->exception_cb(memac->dev_id,
681 FM_MAC_EX_MAGIC_PACKET_INDICATION);
682}
683
684static void free_init_resources(struct fman_mac *memac)
685{
686 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
687 FMAN_INTR_TYPE_ERR);
688
689 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
690 FMAN_INTR_TYPE_NORMAL);
691
692 /* release the driver's group hash table */
693 free_hash_table(memac->multicast_addr_hash);
694 memac->multicast_addr_hash = NULL;
695
696 /* release the driver's individual hash table */
697 free_hash_table(memac->unicast_addr_hash);
698 memac->unicast_addr_hash = NULL;
699}
700
701static bool is_init_done(struct memac_cfg *memac_drv_params)
702{
703 /* Checks if mEMAC driver parameters were initialized */
704 if (!memac_drv_params)
705 return true;
706
707 return false;
708}
709
710int memac_enable(struct fman_mac *memac, enum comm_mode mode)
711{
712 struct memac_regs __iomem *regs = memac->regs;
713 u32 tmp;
714
715 if (!is_init_done(memac->memac_drv_param))
716 return -EINVAL;
717
718 tmp = ioread32be(®s->command_config);
719 if (mode & COMM_MODE_RX)
720 tmp |= CMD_CFG_RX_EN;
721 if (mode & COMM_MODE_TX)
722 tmp |= CMD_CFG_TX_EN;
723
724 iowrite32be(tmp, ®s->command_config);
725
726 return 0;
727}
728
729int memac_disable(struct fman_mac *memac, enum comm_mode mode)
730{
731 struct memac_regs __iomem *regs = memac->regs;
732 u32 tmp;
733
734 if (!is_init_done(memac->memac_drv_param))
735 return -EINVAL;
736
737 tmp = ioread32be(®s->command_config);
738 if (mode & COMM_MODE_RX)
739 tmp &= ~CMD_CFG_RX_EN;
740 if (mode & COMM_MODE_TX)
741 tmp &= ~CMD_CFG_TX_EN;
742
743 iowrite32be(tmp, ®s->command_config);
744
745 return 0;
746}
747
748int memac_set_promiscuous(struct fman_mac *memac, bool new_val)
749{
750 struct memac_regs __iomem *regs = memac->regs;
751 u32 tmp;
752
753 if (!is_init_done(memac->memac_drv_param))
754 return -EINVAL;
755
756 tmp = ioread32be(®s->command_config);
757 if (new_val)
758 tmp |= CMD_CFG_PROMIS_EN;
759 else
760 tmp &= ~CMD_CFG_PROMIS_EN;
761
762 iowrite32be(tmp, ®s->command_config);
763
764 return 0;
765}
766
767int memac_adjust_link(struct fman_mac *memac, u16 speed)
768{
769 struct memac_regs __iomem *regs = memac->regs;
770 u32 tmp;
771
772 if (!is_init_done(memac->memac_drv_param))
773 return -EINVAL;
774
775 tmp = ioread32be(®s->if_mode);
776
777 /* Set full duplex */
778 tmp &= ~IF_MODE_HD;
779
780 if (memac->phy_if == PHY_INTERFACE_MODE_RGMII) {
781 /* Configure RGMII in manual mode */
782 tmp &= ~IF_MODE_RGMII_AUTO;
783 tmp &= ~IF_MODE_RGMII_SP_MASK;
784 /* Full duplex */
785 tmp |= IF_MODE_RGMII_FD;
786
787 switch (speed) {
788 case SPEED_1000:
789 tmp |= IF_MODE_RGMII_1000;
790 break;
791 case SPEED_100:
792 tmp |= IF_MODE_RGMII_100;
793 break;
794 case SPEED_10:
795 tmp |= IF_MODE_RGMII_10;
796 break;
797 default:
798 break;
799 }
800 }
801
802 iowrite32be(tmp, ®s->if_mode);
803
804 return 0;
805}
806
807int memac_cfg_max_frame_len(struct fman_mac *memac, u16 new_val)
808{
809 if (is_init_done(memac->memac_drv_param))
810 return -EINVAL;
811
812 memac->memac_drv_param->max_frame_length = new_val;
813
814 return 0;
815}
816
817int memac_cfg_reset_on_init(struct fman_mac *memac, bool enable)
818{
819 if (is_init_done(memac->memac_drv_param))
820 return -EINVAL;
821
822 memac->memac_drv_param->reset_on_init = enable;
823
824 return 0;
825}
826
827int memac_cfg_fixed_link(struct fman_mac *memac,
828 struct fixed_phy_status *fixed_link)
829{
830 if (is_init_done(memac->memac_drv_param))
831 return -EINVAL;
832
833 memac->memac_drv_param->fixed_link = fixed_link;
834
835 return 0;
836}
837
838int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,
839 u16 pause_time, u16 thresh_time)
840{
841 struct memac_regs __iomem *regs = memac->regs;
842 u32 tmp;
843
844 if (!is_init_done(memac->memac_drv_param))
845 return -EINVAL;
846
847 tmp = ioread32be(®s->tx_fifo_sections);
848
849 GET_TX_EMPTY_DEFAULT_VALUE(tmp);
850 iowrite32be(tmp, ®s->tx_fifo_sections);
851
852 tmp = ioread32be(®s->command_config);
853 tmp &= ~CMD_CFG_PFC_MODE;
854 priority = 0;
855
856 iowrite32be(tmp, ®s->command_config);
857
858 tmp = ioread32be(®s->pause_quanta[priority / 2]);
859 if (priority % 2)
860 tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT;
861 else
862 tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT;
863 tmp |= ((u32)pause_time << (16 * (priority % 2)));
864 iowrite32be(tmp, ®s->pause_quanta[priority / 2]);
865
866 tmp = ioread32be(®s->pause_thresh[priority / 2]);
867 if (priority % 2)
868 tmp &= CLXY_PAUSE_THRESH_CLX_QTH;
869 else
870 tmp &= CLXY_PAUSE_THRESH_CLY_QTH;
871 tmp |= ((u32)thresh_time << (16 * (priority % 2)));
872 iowrite32be(tmp, ®s->pause_thresh[priority / 2]);
873
874 return 0;
875}
876
877int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en)
878{
879 struct memac_regs __iomem *regs = memac->regs;
880 u32 tmp;
881
882 if (!is_init_done(memac->memac_drv_param))
883 return -EINVAL;
884
885 tmp = ioread32be(®s->command_config);
886 if (en)
887 tmp &= ~CMD_CFG_PAUSE_IGNORE;
888 else
889 tmp |= CMD_CFG_PAUSE_IGNORE;
890
891 iowrite32be(tmp, ®s->command_config);
892
893 return 0;
894}
895
896int memac_modify_mac_address(struct fman_mac *memac, enet_addr_t *enet_addr)
897{
898 if (!is_init_done(memac->memac_drv_param))
899 return -EINVAL;
900
901 add_addr_in_paddr(memac->regs, (u8 *)(*enet_addr), 0);
902
903 return 0;
904}
905
906int memac_add_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr)
907{
908 struct memac_regs __iomem *regs = memac->regs;
909 struct eth_hash_entry *hash_entry;
910 u32 hash;
911 u64 addr;
912
913 if (!is_init_done(memac->memac_drv_param))
914 return -EINVAL;
915
916 addr = ENET_ADDR_TO_UINT64(*eth_addr);
917
918 if (!(addr & GROUP_ADDRESS)) {
919 /* Unicast addresses not supported in hash */
920 pr_err("Unicast Address\n");
921 return -EINVAL;
922 }
923 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
924
925 /* Create element to be added to the driver hash table */
926 hash_entry = kmalloc(sizeof(*hash_entry), GFP_KERNEL);
927 if (!hash_entry)
928 return -ENOMEM;
929 hash_entry->addr = addr;
930 INIT_LIST_HEAD(&hash_entry->node);
931
932 list_add_tail(&hash_entry->node,
933 &memac->multicast_addr_hash->lsts[hash]);
934 iowrite32be(hash | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl);
935
936 return 0;
937}
938
939int memac_del_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr)
940{
941 struct memac_regs __iomem *regs = memac->regs;
942 struct eth_hash_entry *hash_entry = NULL;
943 struct list_head *pos;
944 u32 hash;
945 u64 addr;
946
947 if (!is_init_done(memac->memac_drv_param))
948 return -EINVAL;
949
950 addr = ENET_ADDR_TO_UINT64(*eth_addr);
951
952 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
953
954 list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) {
955 hash_entry = ETH_HASH_ENTRY_OBJ(pos);
956 if (hash_entry->addr == addr) {
957 list_del_init(&hash_entry->node);
958 kfree(hash_entry);
959 break;
960 }
961 }
962 if (list_empty(&memac->multicast_addr_hash->lsts[hash]))
963 iowrite32be(hash & ~HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl);
964
965 return 0;
966}
967
968int memac_set_exception(struct fman_mac *memac,
969 enum fman_mac_exceptions exception, bool enable)
970{
971 u32 bit_mask = 0;
972
973 if (!is_init_done(memac->memac_drv_param))
974 return -EINVAL;
975
976 bit_mask = get_exception_flag(exception);
977 if (bit_mask) {
978 if (enable)
979 memac->exceptions |= bit_mask;
980 else
981 memac->exceptions &= ~bit_mask;
982 } else {
983 pr_err("Undefined exception\n");
984 return -EINVAL;
985 }
986 set_exception(memac->regs, bit_mask, enable);
987
988 return 0;
989}
990
991int memac_init(struct fman_mac *memac)
992{
993 struct memac_cfg *memac_drv_param;
994 u8 i;
995 enet_addr_t eth_addr;
996 bool slow_10g_if = false;
997 struct fixed_phy_status *fixed_link;
998 int err;
999 u32 reg32 = 0;
1000
1001 if (is_init_done(memac->memac_drv_param))
1002 return -EINVAL;
1003
1004 err = check_init_parameters(memac);
1005 if (err)
1006 return err;
1007
1008 memac_drv_param = memac->memac_drv_param;
1009
1010 if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4)
1011 slow_10g_if = true;
1012
1013 /* First, reset the MAC if desired. */
1014 if (memac_drv_param->reset_on_init) {
1015 err = reset(memac->regs);
1016 if (err) {
1017 pr_err("mEMAC reset failed\n");
1018 return err;
1019 }
1020 }
1021
1022 /* MAC Address */
1023 MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr);
1024 add_addr_in_paddr(memac->regs, (u8 *)eth_addr, 0);
1025
1026 fixed_link = memac_drv_param->fixed_link;
1027
1028 init(memac->regs, memac->memac_drv_param, memac->phy_if,
1029 memac->max_speed, slow_10g_if, memac->exceptions);
1030
1031 /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround
1032 * Exists only in FMan 6.0 and 6.3.
1033 */
1034 if ((memac->fm_rev_info.major == 6) &&
1035 ((memac->fm_rev_info.minor == 0) ||
1036 (memac->fm_rev_info.minor == 3))) {
1037 /* MAC strips CRC from received frames - this workaround
1038 * should decrease the likelihood of bug appearance
1039 */
1040 reg32 = ioread32be(&memac->regs->command_config);
1041 reg32 &= ~CMD_CFG_CRC_FWD;
1042 iowrite32be(reg32, &memac->regs->command_config);
1043 }
1044
1045 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) {
1046 /* Configure internal SGMII PHY */
1047 if (memac->basex_if)
1048 setup_sgmii_internal_phy_base_x(memac);
1049 else
1050 setup_sgmii_internal_phy(memac, fixed_link);
1051 } else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
1052 /* Configure 4 internal SGMII PHYs */
1053 for (i = 0; i < 4; i++) {
1054 u8 qsmgii_phy_addr, phy_addr;
1055 /* QSGMII PHY address occupies 3 upper bits of 5-bit
1056 * phy_address; the lower 2 bits are used to extend
1057 * register address space and access each one of 4
1058 * ports inside QSGMII.
1059 */
1060 phy_addr = memac->pcsphy->mdio.addr;
1061 qsmgii_phy_addr = (u8)((phy_addr << 2) | i);
1062 memac->pcsphy->mdio.addr = qsmgii_phy_addr;
1063 if (memac->basex_if)
1064 setup_sgmii_internal_phy_base_x(memac);
1065 else
1066 setup_sgmii_internal_phy(memac, fixed_link);
1067
1068 memac->pcsphy->mdio.addr = phy_addr;
1069 }
1070 }
1071
1072 /* Max Frame Length */
1073 err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
1074 memac_drv_param->max_frame_length);
1075 if (err) {
1076 pr_err("settings Mac max frame length is FAILED\n");
1077 return err;
1078 }
1079
1080 memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
1081 if (!memac->multicast_addr_hash) {
1082 free_init_resources(memac);
1083 pr_err("allocation hash table is FAILED\n");
1084 return -ENOMEM;
1085 }
1086
1087 memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
1088 if (!memac->unicast_addr_hash) {
1089 free_init_resources(memac);
1090 pr_err("allocation hash table is FAILED\n");
1091 return -ENOMEM;
1092 }
1093
1094 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
1095 FMAN_INTR_TYPE_ERR, memac_err_exception, memac);
1096
1097 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
1098 FMAN_INTR_TYPE_NORMAL, memac_exception, memac);
1099
1100 kfree(memac_drv_param);
1101 memac->memac_drv_param = NULL;
1102
1103 return 0;
1104}
1105
1106int memac_free(struct fman_mac *memac)
1107{
1108 free_init_resources(memac);
1109
1110 if (memac->pcsphy)
1111 put_device(&memac->pcsphy->mdio.dev);
1112
1113 kfree(memac->memac_drv_param);
1114 kfree(memac);
1115
1116 return 0;
1117}
1118
1119struct fman_mac *memac_config(struct fman_mac_params *params)
1120{
1121 struct fman_mac *memac;
1122 struct memac_cfg *memac_drv_param;
1123 void __iomem *base_addr;
1124
1125 base_addr = params->base_addr;
1126 /* allocate memory for the m_emac data structure */
1127 memac = kzalloc(sizeof(*memac), GFP_KERNEL);
1128 if (!memac)
1129 return NULL;
1130
1131 /* allocate memory for the m_emac driver parameters data structure */
1132 memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL);
1133 if (!memac_drv_param) {
1134 memac_free(memac);
1135 return NULL;
1136 }
1137
1138 /* Plant parameter structure pointer */
1139 memac->memac_drv_param = memac_drv_param;
1140
1141 set_dflts(memac_drv_param);
1142
1143 memac->addr = ENET_ADDR_TO_UINT64(params->addr);
1144
1145 memac->regs = base_addr;
1146 memac->max_speed = params->max_speed;
1147 memac->phy_if = params->phy_if;
1148 memac->mac_id = params->mac_id;
1149 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |
1150 MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);
1151 memac->exception_cb = params->exception_cb;
1152 memac->event_cb = params->event_cb;
1153 memac->dev_id = params->dev_id;
1154 memac->fm = params->fm;
1155 memac->basex_if = params->basex_if;
1156
1157 /* Save FMan revision */
1158 fman_get_revision(memac->fm, &memac->fm_rev_info);
1159
1160 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
1161 memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
1162 if (!params->internal_phy_node) {
1163 pr_err("PCS PHY node is not available\n");
1164 memac_free(memac);
1165 return NULL;
1166 }
1167
1168 memac->pcsphy = of_phy_find_device(params->internal_phy_node);
1169 if (!memac->pcsphy) {
1170 pr_err("of_phy_find_device (PCS PHY) failed\n");
1171 memac_free(memac);
1172 return NULL;
1173 }
1174 }
1175
1176 return memac;
1177}