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1/*
2 * Marvell 88e6xxx common definitions
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __MV88E6XXX_H
13#define __MV88E6XXX_H
14
15#include <linux/if_vlan.h>
16#include <linux/irq.h>
17#include <linux/gpio/consumer.h>
18
19#ifndef UINT64_MAX
20#define UINT64_MAX (u64)(~((u64)0))
21#endif
22
23#define SMI_CMD 0x00
24#define SMI_CMD_BUSY BIT(15)
25#define SMI_CMD_CLAUSE_22 BIT(12)
26#define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
27#define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
28#define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
29#define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
30#define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
31#define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
32#define SMI_DATA 0x01
33
34/* PHY Registers */
35#define PHY_PAGE 0x16
36#define PHY_PAGE_COPPER 0x00
37
38#define ADDR_SERDES 0x0f
39#define SERDES_PAGE_FIBER 0x01
40
41#define PORT_STATUS 0x00
42#define PORT_STATUS_PAUSE_EN BIT(15)
43#define PORT_STATUS_MY_PAUSE BIT(14)
44#define PORT_STATUS_HD_FLOW BIT(13)
45#define PORT_STATUS_PHY_DETECT BIT(12)
46#define PORT_STATUS_LINK BIT(11)
47#define PORT_STATUS_DUPLEX BIT(10)
48#define PORT_STATUS_SPEED_MASK 0x0300
49#define PORT_STATUS_SPEED_10 0x0000
50#define PORT_STATUS_SPEED_100 0x0100
51#define PORT_STATUS_SPEED_1000 0x0200
52#define PORT_STATUS_EEE BIT(6) /* 6352 */
53#define PORT_STATUS_AM_DIS BIT(6) /* 6165 */
54#define PORT_STATUS_MGMII BIT(6) /* 6185 */
55#define PORT_STATUS_TX_PAUSED BIT(5)
56#define PORT_STATUS_FLOW_CTRL BIT(4)
57#define PORT_STATUS_CMODE_MASK 0x0f
58#define PORT_STATUS_CMODE_100BASE_X 0x8
59#define PORT_STATUS_CMODE_1000BASE_X 0x9
60#define PORT_STATUS_CMODE_SGMII 0xa
61#define PORT_PCS_CTRL 0x01
62#define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15)
63#define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14)
64#define PORT_PCS_CTRL_FORCE_SPEED BIT(13) /* 6390 */
65#define PORT_PCS_CTRL_ALTSPEED BIT(12) /* 6390 */
66#define PORT_PCS_CTRL_200BASE BIT(12) /* 6352 */
67#define PORT_PCS_CTRL_FC BIT(7)
68#define PORT_PCS_CTRL_FORCE_FC BIT(6)
69#define PORT_PCS_CTRL_LINK_UP BIT(5)
70#define PORT_PCS_CTRL_FORCE_LINK BIT(4)
71#define PORT_PCS_CTRL_DUPLEX_FULL BIT(3)
72#define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2)
73#define PORT_PCS_CTRL_SPEED_MASK (0x03)
74#define PORT_PCS_CTRL_SPEED_10 (0x00)
75#define PORT_PCS_CTRL_SPEED_100 (0x01)
76#define PORT_PCS_CTRL_SPEED_200 (0x02) /* 6065 and non Gb chips */
77#define PORT_PCS_CTRL_SPEED_1000 (0x02)
78#define PORT_PCS_CTRL_SPEED_10000 (0x03) /* 6390X */
79#define PORT_PCS_CTRL_SPEED_UNFORCED (0x03)
80#define PORT_PAUSE_CTRL 0x02
81#define PORT_FLOW_CTRL_LIMIT_IN ((0x00 << 8) | BIT(15))
82#define PORT_FLOW_CTRL_LIMIT_OUT ((0x01 << 8) | BIT(15))
83#define PORT_SWITCH_ID 0x03
84#define PORT_SWITCH_ID_PROD_NUM_6085 0x04a
85#define PORT_SWITCH_ID_PROD_NUM_6095 0x095
86#define PORT_SWITCH_ID_PROD_NUM_6097 0x099
87#define PORT_SWITCH_ID_PROD_NUM_6131 0x106
88#define PORT_SWITCH_ID_PROD_NUM_6320 0x115
89#define PORT_SWITCH_ID_PROD_NUM_6123 0x121
90#define PORT_SWITCH_ID_PROD_NUM_6161 0x161
91#define PORT_SWITCH_ID_PROD_NUM_6165 0x165
92#define PORT_SWITCH_ID_PROD_NUM_6171 0x171
93#define PORT_SWITCH_ID_PROD_NUM_6172 0x172
94#define PORT_SWITCH_ID_PROD_NUM_6175 0x175
95#define PORT_SWITCH_ID_PROD_NUM_6176 0x176
96#define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7
97#define PORT_SWITCH_ID_PROD_NUM_6190 0x190
98#define PORT_SWITCH_ID_PROD_NUM_6190X 0x0a0
99#define PORT_SWITCH_ID_PROD_NUM_6191 0x191
100#define PORT_SWITCH_ID_PROD_NUM_6240 0x240
101#define PORT_SWITCH_ID_PROD_NUM_6290 0x290
102#define PORT_SWITCH_ID_PROD_NUM_6321 0x310
103#define PORT_SWITCH_ID_PROD_NUM_6352 0x352
104#define PORT_SWITCH_ID_PROD_NUM_6350 0x371
105#define PORT_SWITCH_ID_PROD_NUM_6351 0x375
106#define PORT_SWITCH_ID_PROD_NUM_6390 0x390
107#define PORT_SWITCH_ID_PROD_NUM_6390X 0x0a1
108#define PORT_CONTROL 0x04
109#define PORT_CONTROL_USE_CORE_TAG BIT(15)
110#define PORT_CONTROL_DROP_ON_LOCK BIT(14)
111#define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12)
112#define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12)
113#define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12)
114#define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12)
115#define PORT_CONTROL_EGRESS_MASK (0x3 << 12)
116#define PORT_CONTROL_HEADER BIT(11)
117#define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10)
118#define PORT_CONTROL_DOUBLE_TAG BIT(9)
119#define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8)
120#define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8)
121#define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8)
122#define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8)
123#define PORT_CONTROL_FRAME_MASK (0x3 << 8)
124#define PORT_CONTROL_DSA_TAG BIT(8)
125#define PORT_CONTROL_VLAN_TUNNEL BIT(7)
126#define PORT_CONTROL_TAG_IF_BOTH BIT(6)
127#define PORT_CONTROL_USE_IP BIT(5)
128#define PORT_CONTROL_USE_TAG BIT(4)
129#define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3)
130#define PORT_CONTROL_FORWARD_UNKNOWN BIT(2)
131#define PORT_CONTROL_NOT_EGRESS_UNKNOWN_DA (0x0 << 2)
132#define PORT_CONTROL_NOT_EGRESS_UNKNOWN_MULTICAST_DA (0x1 << 2)
133#define PORT_CONTROL_NOT_EGRESS_UNKNOWN_UNITCAST_DA (0x2 << 2)
134#define PORT_CONTROL_EGRESS_ALL_UNKNOWN_DA (0x3 << 2)
135#define PORT_CONTROL_STATE_MASK 0x03
136#define PORT_CONTROL_STATE_DISABLED 0x00
137#define PORT_CONTROL_STATE_BLOCKING 0x01
138#define PORT_CONTROL_STATE_LEARNING 0x02
139#define PORT_CONTROL_STATE_FORWARDING 0x03
140#define PORT_CONTROL_1 0x05
141#define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0)
142#define PORT_BASE_VLAN 0x06
143#define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12)
144#define PORT_DEFAULT_VLAN 0x07
145#define PORT_DEFAULT_VLAN_MASK 0xfff
146#define PORT_CONTROL_2 0x08
147#define PORT_CONTROL_2_IGNORE_FCS BIT(15)
148#define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
149#define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
150#define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
151#define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12)
152#define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12)
153#define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12)
154#define PORT_CONTROL_2_8021Q_MASK (0x03 << 10)
155#define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10)
156#define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10)
157#define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10)
158#define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10)
159#define PORT_CONTROL_2_DISCARD_TAGGED BIT(9)
160#define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
161#define PORT_CONTROL_2_MAP_DA BIT(7)
162#define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6)
163#define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6)
164#define PORT_CONTROL_2_EGRESS_MONITOR BIT(5)
165#define PORT_CONTROL_2_INGRESS_MONITOR BIT(4)
166#define PORT_RATE_CONTROL 0x09
167#define PORT_RATE_CONTROL_2 0x0a
168#define PORT_ASSOC_VECTOR 0x0b
169#define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15)
170#define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14)
171#define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13)
172#define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12)
173#define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11)
174#define PORT_ATU_CONTROL 0x0c
175#define PORT_PRI_OVERRIDE 0x0d
176#define PORT_ETH_TYPE 0x0f
177#define PORT_IN_DISCARD_LO 0x10
178#define PORT_IN_DISCARD_HI 0x11
179#define PORT_IN_FILTERED 0x12
180#define PORT_OUT_FILTERED 0x13
181#define PORT_TAG_REGMAP_0123 0x18
182#define PORT_TAG_REGMAP_4567 0x19
183#define PORT_IEEE_PRIO_MAP_TABLE 0x18 /* 6390 */
184#define PORT_IEEE_PRIO_MAP_TABLE_UPDATE BIT(15)
185#define PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP (0x0 << 12)
186#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP (0x1 << 12)
187#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP (0x2 << 12)
188#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP (0x3 << 12)
189#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP (0x5 << 12)
190#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP (0x6 << 12)
191#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP (0x7 << 12)
192#define PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT 9
193
194#define GLOBAL_STATUS 0x00
195#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
196#define GLOBAL_STATUS_PPU_STATE_MASK (0x3 << 14) /* 6165 6185 */
197#define GLOBAL_STATUS_PPU_STATE_DISABLED_RST (0x0 << 14)
198#define GLOBAL_STATUS_PPU_STATE_INITIALIZING (0x1 << 14)
199#define GLOBAL_STATUS_PPU_STATE_DISABLED (0x2 << 14)
200#define GLOBAL_STATUS_PPU_STATE_POLLING (0x3 << 14)
201#define GLOBAL_STATUS_INIT_READY BIT(11)
202#define GLOBAL_STATUS_IRQ_AVB 8
203#define GLOBAL_STATUS_IRQ_DEVICE 7
204#define GLOBAL_STATUS_IRQ_STATS 6
205#define GLOBAL_STATUS_IRQ_VTU_PROBLEM 5
206#define GLOBAL_STATUS_IRQ_VTU_DONE 4
207#define GLOBAL_STATUS_IRQ_ATU_PROBLEM 3
208#define GLOBAL_STATUS_IRQ_ATU_DONE 2
209#define GLOBAL_STATUS_IRQ_TCAM_DONE 1
210#define GLOBAL_STATUS_IRQ_EEPROM_DONE 0
211#define GLOBAL_MAC_01 0x01
212#define GLOBAL_MAC_23 0x02
213#define GLOBAL_MAC_45 0x03
214#define GLOBAL_ATU_FID 0x01
215#define GLOBAL_VTU_FID 0x02
216#define GLOBAL_VTU_FID_MASK 0xfff
217#define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */
218#define GLOBAL_VTU_SID_MASK 0x3f
219#define GLOBAL_CONTROL 0x04
220#define GLOBAL_CONTROL_SW_RESET BIT(15)
221#define GLOBAL_CONTROL_PPU_ENABLE BIT(14)
222#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */
223#define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */
224#define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */
225#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */
226#define GLOBAL_CONTROL_DEVICE_EN BIT(7)
227#define GLOBAL_CONTROL_STATS_DONE_EN BIT(6)
228#define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5)
229#define GLOBAL_CONTROL_VTU_DONE_EN BIT(4)
230#define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3)
231#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
232#define GLOBAL_CONTROL_TCAM_EN BIT(1)
233#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
234#define GLOBAL_VTU_OP 0x05
235#define GLOBAL_VTU_OP_BUSY BIT(15)
236#define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY)
237#define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY)
238#define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY)
239#define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY)
240#define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY)
241#define GLOBAL_VTU_VID 0x06
242#define GLOBAL_VTU_VID_MASK 0xfff
243#define GLOBAL_VTU_VID_VALID BIT(12)
244#define GLOBAL_VTU_DATA_0_3 0x07
245#define GLOBAL_VTU_DATA_4_7 0x08
246#define GLOBAL_VTU_DATA_8_11 0x09
247#define GLOBAL_VTU_STU_DATA_MASK 0x03
248#define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00
249#define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01
250#define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02
251#define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03
252#define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00
253#define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01
254#define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02
255#define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03
256#define GLOBAL_ATU_CONTROL 0x0a
257#define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3)
258#define GLOBAL_ATU_OP 0x0b
259#define GLOBAL_ATU_OP_BUSY BIT(15)
260#define GLOBAL_ATU_OP_NOP (0 << 12)
261#define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
262#define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY)
263#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
264#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
265#define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
266#define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
267#define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY)
268#define GLOBAL_ATU_DATA 0x0c
269#define GLOBAL_ATU_DATA_TRUNK BIT(15)
270#define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0
271#define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4
272#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
273#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
274#define GLOBAL_ATU_DATA_STATE_MASK 0x0f
275#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
276#define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d
277#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
278#define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f
279#define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05
280#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
281#define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e
282#define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f
283#define GLOBAL_ATU_MAC_01 0x0d
284#define GLOBAL_ATU_MAC_23 0x0e
285#define GLOBAL_ATU_MAC_45 0x0f
286#define GLOBAL_IP_PRI_0 0x10
287#define GLOBAL_IP_PRI_1 0x11
288#define GLOBAL_IP_PRI_2 0x12
289#define GLOBAL_IP_PRI_3 0x13
290#define GLOBAL_IP_PRI_4 0x14
291#define GLOBAL_IP_PRI_5 0x15
292#define GLOBAL_IP_PRI_6 0x16
293#define GLOBAL_IP_PRI_7 0x17
294#define GLOBAL_IEEE_PRI 0x18
295#define GLOBAL_CORE_TAG_TYPE 0x19
296#define GLOBAL_MONITOR_CONTROL 0x1a
297#define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12
298#define GLOBAL_MONITOR_CONTROL_INGRESS_MASK (0xf << 12)
299#define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8
300#define GLOBAL_MONITOR_CONTROL_EGRESS_MASK (0xf << 8)
301#define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4
302#define GLOBAL_MONITOR_CONTROL_ARP_MASK (0xf << 4)
303#define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0
304#define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0)
305#define GLOBAL_MONITOR_CONTROL_UPDATE BIT(15)
306#define GLOBAL_MONITOR_CONTROL_0180C280000000XLO (0x00 << 8)
307#define GLOBAL_MONITOR_CONTROL_0180C280000000XHI (0x01 << 8)
308#define GLOBAL_MONITOR_CONTROL_0180C280000002XLO (0x02 << 8)
309#define GLOBAL_MONITOR_CONTROL_0180C280000002XHI (0x03 << 8)
310#define GLOBAL_MONITOR_CONTROL_INGRESS (0x20 << 8)
311#define GLOBAL_MONITOR_CONTROL_EGRESS (0x21 << 8)
312#define GLOBAL_MONITOR_CONTROL_CPU_DEST (0x30 << 8)
313#define GLOBAL_CONTROL_2 0x1c
314#define GLOBAL_CONTROL_2_NO_CASCADE 0xe000
315#define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000
316#define GLOBAL_CONTROL_2_HIST_RX (0x1 << 6)
317#define GLOBAL_CONTROL_2_HIST_TX (0x2 << 6)
318#define GLOBAL_CONTROL_2_HIST_RX_TX (0x3 << 6)
319#define GLOBAL_STATS_OP 0x1d
320#define GLOBAL_STATS_OP_BUSY BIT(15)
321#define GLOBAL_STATS_OP_NOP (0 << 12)
322#define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY)
323#define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY)
324#define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY)
325#define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY)
326#define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY)
327#define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY)
328#define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY)
329#define GLOBAL_STATS_OP_BANK_1_BIT_9 BIT(9)
330#define GLOBAL_STATS_OP_BANK_1_BIT_10 BIT(10)
331#define GLOBAL_STATS_COUNTER_32 0x1e
332#define GLOBAL_STATS_COUNTER_01 0x1f
333
334#define GLOBAL2_INT_SOURCE 0x00
335#define GLOBAL2_INT_MASK 0x01
336#define GLOBAL2_MGMT_EN_2X 0x02
337#define GLOBAL2_MGMT_EN_0X 0x03
338#define GLOBAL2_FLOW_CONTROL 0x04
339#define GLOBAL2_SWITCH_MGMT 0x05
340#define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
341#define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14)
342#define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13)
343#define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
344#define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3)
345#define GLOBAL2_DEVICE_MAPPING 0x06
346#define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15)
347#define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8
348#define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f
349#define GLOBAL2_TRUNK_MASK 0x07
350#define GLOBAL2_TRUNK_MASK_UPDATE BIT(15)
351#define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12
352#define GLOBAL2_TRUNK_MASK_HASK BIT(11)
353#define GLOBAL2_TRUNK_MAPPING 0x08
354#define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15)
355#define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11
356#define GLOBAL2_IRL_CMD 0x09
357#define GLOBAL2_IRL_CMD_BUSY BIT(15)
358#define GLOBAL2_IRL_CMD_OP_INIT_ALL ((0x001 << 12) | GLOBAL2_IRL_CMD_BUSY)
359#define GLOBAL2_IRL_CMD_OP_INIT_SEL ((0x010 << 12) | GLOBAL2_IRL_CMD_BUSY)
360#define GLOBAL2_IRL_CMD_OP_WRITE_SEL ((0x011 << 12) | GLOBAL2_IRL_CMD_BUSY)
361#define GLOBAL2_IRL_CMD_OP_READ_SEL ((0x100 << 12) | GLOBAL2_IRL_CMD_BUSY)
362#define GLOBAL2_IRL_DATA 0x0a
363#define GLOBAL2_PVT_ADDR 0x0b
364#define GLOBAL2_PVT_ADDR_BUSY BIT(15)
365#define GLOBAL2_PVT_ADDR_OP_INIT_ONES ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY)
366#define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN ((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY)
367#define GLOBAL2_PVT_ADDR_OP_READ ((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY)
368#define GLOBAL2_PVT_DATA 0x0c
369#define GLOBAL2_SWITCH_MAC 0x0d
370#define GLOBAL2_ATU_STATS 0x0e
371#define GLOBAL2_PRIO_OVERRIDE 0x0f
372#define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7)
373#define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4
374#define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3)
375#define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0
376#define GLOBAL2_EEPROM_CMD 0x14
377#define GLOBAL2_EEPROM_CMD_BUSY BIT(15)
378#define GLOBAL2_EEPROM_CMD_OP_WRITE ((0x3 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
379#define GLOBAL2_EEPROM_CMD_OP_READ ((0x4 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
380#define GLOBAL2_EEPROM_CMD_OP_LOAD ((0x6 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
381#define GLOBAL2_EEPROM_CMD_RUNNING BIT(11)
382#define GLOBAL2_EEPROM_CMD_WRITE_EN BIT(10)
383#define GLOBAL2_EEPROM_CMD_ADDR_MASK 0xff
384#define GLOBAL2_EEPROM_DATA 0x15
385#define GLOBAL2_PTP_AVB_OP 0x16
386#define GLOBAL2_PTP_AVB_DATA 0x17
387#define GLOBAL2_SMI_PHY_CMD 0x18
388#define GLOBAL2_SMI_PHY_CMD_BUSY BIT(15)
389#define GLOBAL2_SMI_PHY_CMD_MODE_22 BIT(12)
390#define GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA ((0x1 << 10) | \
391 GLOBAL2_SMI_PHY_CMD_MODE_22 | \
392 GLOBAL2_SMI_PHY_CMD_BUSY)
393#define GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA ((0x2 << 10) | \
394 GLOBAL2_SMI_PHY_CMD_MODE_22 | \
395 GLOBAL2_SMI_PHY_CMD_BUSY)
396#define GLOBAL2_SMI_PHY_DATA 0x19
397#define GLOBAL2_SCRATCH_MISC 0x1a
398#define GLOBAL2_SCRATCH_BUSY BIT(15)
399#define GLOBAL2_SCRATCH_REGISTER_SHIFT 8
400#define GLOBAL2_SCRATCH_VALUE_MASK 0xff
401#define GLOBAL2_WDOG_CONTROL 0x1b
402#define GLOBAL2_QOS_WEIGHT 0x1c
403#define GLOBAL2_MISC 0x1d
404
405#define MV88E6XXX_N_FID 4096
406
407enum mv88e6xxx_frame_mode {
408 MV88E6XXX_FRAME_MODE_NORMAL,
409 MV88E6XXX_FRAME_MODE_DSA,
410 MV88E6XXX_FRAME_MODE_PROVIDER,
411 MV88E6XXX_FRAME_MODE_ETHERTYPE,
412};
413
414/* List of supported models */
415enum mv88e6xxx_model {
416 MV88E6085,
417 MV88E6095,
418 MV88E6097,
419 MV88E6123,
420 MV88E6131,
421 MV88E6161,
422 MV88E6165,
423 MV88E6171,
424 MV88E6172,
425 MV88E6175,
426 MV88E6176,
427 MV88E6185,
428 MV88E6190,
429 MV88E6190X,
430 MV88E6191,
431 MV88E6240,
432 MV88E6290,
433 MV88E6320,
434 MV88E6321,
435 MV88E6350,
436 MV88E6351,
437 MV88E6352,
438 MV88E6390,
439 MV88E6390X,
440};
441
442enum mv88e6xxx_family {
443 MV88E6XXX_FAMILY_NONE,
444 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
445 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
446 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
447 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
448 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
449 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
450 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
451 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
452 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
453};
454
455enum mv88e6xxx_cap {
456 /* Energy Efficient Ethernet.
457 */
458 MV88E6XXX_CAP_EEE,
459
460 /* Multi-chip Addressing Mode.
461 * Some chips respond to only 2 registers of its own SMI device address
462 * when it is non-zero, and use indirect access to internal registers.
463 */
464 MV88E6XXX_CAP_SMI_CMD, /* (0x00) SMI Command */
465 MV88E6XXX_CAP_SMI_DATA, /* (0x01) SMI Data */
466
467 /* PHY Registers.
468 */
469 MV88E6XXX_CAP_PHY_PAGE, /* (0x16) Page Register */
470
471 /* Fiber/SERDES Registers (SMI address F).
472 */
473 MV88E6XXX_CAP_SERDES,
474
475 /* Switch Global (1) Registers.
476 */
477 MV88E6XXX_CAP_G1_ATU_FID, /* (0x01) ATU FID Register */
478 MV88E6XXX_CAP_G1_VTU_FID, /* (0x02) VTU FID Register */
479
480 /* Switch Global 2 Registers.
481 * The device contains a second set of global 16-bit registers.
482 */
483 MV88E6XXX_CAP_GLOBAL2,
484 MV88E6XXX_CAP_G2_INT, /* (0x00) Interrupt Status */
485 MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */
486 MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */
487 MV88E6XXX_CAP_G2_IRL_CMD, /* (0x09) Ingress Rate Command */
488 MV88E6XXX_CAP_G2_IRL_DATA, /* (0x0a) Ingress Rate Data */
489 MV88E6XXX_CAP_G2_PVT_ADDR, /* (0x0b) Cross Chip Port VLAN Addr */
490 MV88E6XXX_CAP_G2_PVT_DATA, /* (0x0c) Cross Chip Port VLAN Data */
491 MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */
492
493 /* Per VLAN Spanning Tree Unit (STU).
494 * The Port State database, if present, is accessed through VTU
495 * operations and dedicated SID registers. See GLOBAL_VTU_SID.
496 */
497 MV88E6XXX_CAP_STU,
498
499 /* Internal temperature sensor.
500 * Available from any enabled port's PHY register 26, page 6.
501 */
502 MV88E6XXX_CAP_TEMP,
503 MV88E6XXX_CAP_TEMP_LIMIT,
504
505 /* VLAN Table Unit.
506 * The VTU is used to program 802.1Q VLANs. See GLOBAL_VTU_OP.
507 */
508 MV88E6XXX_CAP_VTU,
509};
510
511/* Bitmask of capabilities */
512#define MV88E6XXX_FLAG_EEE BIT_ULL(MV88E6XXX_CAP_EEE)
513
514#define MV88E6XXX_FLAG_SMI_CMD BIT_ULL(MV88E6XXX_CAP_SMI_CMD)
515#define MV88E6XXX_FLAG_SMI_DATA BIT_ULL(MV88E6XXX_CAP_SMI_DATA)
516
517#define MV88E6XXX_FLAG_PHY_PAGE BIT_ULL(MV88E6XXX_CAP_PHY_PAGE)
518
519#define MV88E6XXX_FLAG_SERDES BIT_ULL(MV88E6XXX_CAP_SERDES)
520
521#define MV88E6XXX_FLAG_G1_ATU_FID BIT_ULL(MV88E6XXX_CAP_G1_ATU_FID)
522#define MV88E6XXX_FLAG_G1_VTU_FID BIT_ULL(MV88E6XXX_CAP_G1_VTU_FID)
523
524#define MV88E6XXX_FLAG_GLOBAL2 BIT_ULL(MV88E6XXX_CAP_GLOBAL2)
525#define MV88E6XXX_FLAG_G2_INT BIT_ULL(MV88E6XXX_CAP_G2_INT)
526#define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_2X)
527#define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_0X)
528#define MV88E6XXX_FLAG_G2_IRL_CMD BIT_ULL(MV88E6XXX_CAP_G2_IRL_CMD)
529#define MV88E6XXX_FLAG_G2_IRL_DATA BIT_ULL(MV88E6XXX_CAP_G2_IRL_DATA)
530#define MV88E6XXX_FLAG_G2_PVT_ADDR BIT_ULL(MV88E6XXX_CAP_G2_PVT_ADDR)
531#define MV88E6XXX_FLAG_G2_PVT_DATA BIT_ULL(MV88E6XXX_CAP_G2_PVT_DATA)
532#define MV88E6XXX_FLAG_G2_POT BIT_ULL(MV88E6XXX_CAP_G2_POT)
533
534#define MV88E6XXX_FLAG_STU BIT_ULL(MV88E6XXX_CAP_STU)
535#define MV88E6XXX_FLAG_TEMP BIT_ULL(MV88E6XXX_CAP_TEMP)
536#define MV88E6XXX_FLAG_TEMP_LIMIT BIT_ULL(MV88E6XXX_CAP_TEMP_LIMIT)
537#define MV88E6XXX_FLAG_VTU BIT_ULL(MV88E6XXX_CAP_VTU)
538
539/* Ingress Rate Limit unit */
540#define MV88E6XXX_FLAGS_IRL \
541 (MV88E6XXX_FLAG_G2_IRL_CMD | \
542 MV88E6XXX_FLAG_G2_IRL_DATA)
543
544/* Multi-chip Addressing Mode */
545#define MV88E6XXX_FLAGS_MULTI_CHIP \
546 (MV88E6XXX_FLAG_SMI_CMD | \
547 MV88E6XXX_FLAG_SMI_DATA)
548
549/* Cross-chip Port VLAN Table */
550#define MV88E6XXX_FLAGS_PVT \
551 (MV88E6XXX_FLAG_G2_PVT_ADDR | \
552 MV88E6XXX_FLAG_G2_PVT_DATA)
553
554/* Fiber/SERDES Registers at SMI address F, page 1 */
555#define MV88E6XXX_FLAGS_SERDES \
556 (MV88E6XXX_FLAG_PHY_PAGE | \
557 MV88E6XXX_FLAG_SERDES)
558
559#define MV88E6XXX_FLAGS_FAMILY_6095 \
560 (MV88E6XXX_FLAG_GLOBAL2 | \
561 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
562 MV88E6XXX_FLAG_VTU | \
563 MV88E6XXX_FLAGS_MULTI_CHIP)
564
565#define MV88E6XXX_FLAGS_FAMILY_6097 \
566 (MV88E6XXX_FLAG_G1_ATU_FID | \
567 MV88E6XXX_FLAG_G1_VTU_FID | \
568 MV88E6XXX_FLAG_GLOBAL2 | \
569 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
570 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
571 MV88E6XXX_FLAG_G2_POT | \
572 MV88E6XXX_FLAG_STU | \
573 MV88E6XXX_FLAG_VTU | \
574 MV88E6XXX_FLAGS_IRL | \
575 MV88E6XXX_FLAGS_MULTI_CHIP | \
576 MV88E6XXX_FLAGS_PVT)
577
578#define MV88E6XXX_FLAGS_FAMILY_6165 \
579 (MV88E6XXX_FLAG_G1_ATU_FID | \
580 MV88E6XXX_FLAG_G1_VTU_FID | \
581 MV88E6XXX_FLAG_GLOBAL2 | \
582 MV88E6XXX_FLAG_G2_INT | \
583 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
584 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
585 MV88E6XXX_FLAG_G2_POT | \
586 MV88E6XXX_FLAG_STU | \
587 MV88E6XXX_FLAG_TEMP | \
588 MV88E6XXX_FLAG_VTU | \
589 MV88E6XXX_FLAGS_IRL | \
590 MV88E6XXX_FLAGS_MULTI_CHIP | \
591 MV88E6XXX_FLAGS_PVT)
592
593#define MV88E6XXX_FLAGS_FAMILY_6185 \
594 (MV88E6XXX_FLAG_GLOBAL2 | \
595 MV88E6XXX_FLAG_G2_INT | \
596 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
597 MV88E6XXX_FLAGS_MULTI_CHIP | \
598 MV88E6XXX_FLAG_VTU)
599
600#define MV88E6XXX_FLAGS_FAMILY_6320 \
601 (MV88E6XXX_FLAG_EEE | \
602 MV88E6XXX_FLAG_GLOBAL2 | \
603 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
604 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
605 MV88E6XXX_FLAG_G2_POT | \
606 MV88E6XXX_FLAG_TEMP | \
607 MV88E6XXX_FLAG_TEMP_LIMIT | \
608 MV88E6XXX_FLAG_VTU | \
609 MV88E6XXX_FLAGS_IRL | \
610 MV88E6XXX_FLAGS_MULTI_CHIP | \
611 MV88E6XXX_FLAGS_PVT)
612
613#define MV88E6XXX_FLAGS_FAMILY_6351 \
614 (MV88E6XXX_FLAG_G1_ATU_FID | \
615 MV88E6XXX_FLAG_G1_VTU_FID | \
616 MV88E6XXX_FLAG_GLOBAL2 | \
617 MV88E6XXX_FLAG_G2_INT | \
618 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
619 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
620 MV88E6XXX_FLAG_G2_POT | \
621 MV88E6XXX_FLAG_STU | \
622 MV88E6XXX_FLAG_TEMP | \
623 MV88E6XXX_FLAG_VTU | \
624 MV88E6XXX_FLAGS_IRL | \
625 MV88E6XXX_FLAGS_MULTI_CHIP | \
626 MV88E6XXX_FLAGS_PVT)
627
628#define MV88E6XXX_FLAGS_FAMILY_6352 \
629 (MV88E6XXX_FLAG_EEE | \
630 MV88E6XXX_FLAG_G1_ATU_FID | \
631 MV88E6XXX_FLAG_G1_VTU_FID | \
632 MV88E6XXX_FLAG_GLOBAL2 | \
633 MV88E6XXX_FLAG_G2_INT | \
634 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
635 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
636 MV88E6XXX_FLAG_G2_POT | \
637 MV88E6XXX_FLAG_STU | \
638 MV88E6XXX_FLAG_TEMP | \
639 MV88E6XXX_FLAG_TEMP_LIMIT | \
640 MV88E6XXX_FLAG_VTU | \
641 MV88E6XXX_FLAGS_IRL | \
642 MV88E6XXX_FLAGS_MULTI_CHIP | \
643 MV88E6XXX_FLAGS_PVT | \
644 MV88E6XXX_FLAGS_SERDES)
645
646struct mv88e6xxx_ops;
647
648#define MV88E6XXX_FLAGS_FAMILY_6390 \
649 (MV88E6XXX_FLAG_EEE | \
650 MV88E6XXX_FLAG_GLOBAL2 | \
651 MV88E6XXX_FLAG_STU | \
652 MV88E6XXX_FLAG_TEMP | \
653 MV88E6XXX_FLAG_TEMP_LIMIT | \
654 MV88E6XXX_FLAG_VTU | \
655 MV88E6XXX_FLAGS_IRL | \
656 MV88E6XXX_FLAGS_MULTI_CHIP | \
657 MV88E6XXX_FLAGS_PVT)
658
659struct mv88e6xxx_info {
660 enum mv88e6xxx_family family;
661 u16 prod_num;
662 const char *name;
663 unsigned int num_databases;
664 unsigned int num_ports;
665 unsigned int port_base_addr;
666 unsigned int global1_addr;
667 unsigned int age_time_coeff;
668 unsigned int g1_irqs;
669 enum dsa_tag_protocol tag_protocol;
670 unsigned long long flags;
671 const struct mv88e6xxx_ops *ops;
672};
673
674struct mv88e6xxx_atu_entry {
675 u16 fid;
676 u8 state;
677 bool trunk;
678 u16 portv_trunkid;
679 u8 mac[ETH_ALEN];
680};
681
682struct mv88e6xxx_vtu_entry {
683 u16 vid;
684 u16 fid;
685 u8 sid;
686 bool valid;
687 u8 data[DSA_MAX_PORTS];
688};
689
690struct mv88e6xxx_bus_ops;
691
692struct mv88e6xxx_priv_port {
693 struct net_device *bridge_dev;
694};
695
696struct mv88e6xxx_irq {
697 u16 masked;
698 struct irq_chip chip;
699 struct irq_domain *domain;
700 unsigned int nirqs;
701};
702
703struct mv88e6xxx_chip {
704 const struct mv88e6xxx_info *info;
705
706 /* The dsa_switch this private structure is related to */
707 struct dsa_switch *ds;
708
709 /* The device this structure is associated to */
710 struct device *dev;
711
712 /* This mutex protects the access to the switch registers */
713 struct mutex reg_lock;
714
715 /* The MII bus and the address on the bus that is used to
716 * communication with the switch
717 */
718 const struct mv88e6xxx_bus_ops *smi_ops;
719 struct mii_bus *bus;
720 int sw_addr;
721
722 /* Handles automatic disabling and re-enabling of the PHY
723 * polling unit.
724 */
725 const struct mv88e6xxx_bus_ops *phy_ops;
726 struct mutex ppu_mutex;
727 int ppu_disabled;
728 struct work_struct ppu_work;
729 struct timer_list ppu_timer;
730
731 /* This mutex serialises access to the statistics unit.
732 * Hold this mutex over snapshot + dump sequences.
733 */
734 struct mutex stats_mutex;
735
736 struct mv88e6xxx_priv_port ports[DSA_MAX_PORTS];
737
738 /* A switch may have a GPIO line tied to its reset pin. Parse
739 * this from the device tree, and use it before performing
740 * switch soft reset.
741 */
742 struct gpio_desc *reset;
743
744 /* set to size of eeprom if supported by the switch */
745 int eeprom_len;
746
747 /* Device node for the MDIO bus */
748 struct device_node *mdio_np;
749
750 /* And the MDIO bus itself */
751 struct mii_bus *mdio_bus;
752
753 /* There can be two interrupt controllers, which are chained
754 * off a GPIO as interrupt source
755 */
756 struct mv88e6xxx_irq g1_irq;
757 struct mv88e6xxx_irq g2_irq;
758 int irq;
759 int device_irq;
760};
761
762struct mv88e6xxx_bus_ops {
763 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
764 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
765};
766
767struct mv88e6xxx_ops {
768 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
769 struct ethtool_eeprom *eeprom, u8 *data);
770 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
771 struct ethtool_eeprom *eeprom, u8 *data);
772
773 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
774
775 int (*phy_read)(struct mv88e6xxx_chip *chip, int addr, int reg,
776 u16 *val);
777 int (*phy_write)(struct mv88e6xxx_chip *chip, int addr, int reg,
778 u16 val);
779
780 /* PHY Polling Unit (PPU) operations */
781 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
782 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
783
784 /* Switch Software Reset */
785 int (*reset)(struct mv88e6xxx_chip *chip);
786
787 /* RGMII Receive/Transmit Timing Control
788 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
789 */
790 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
791 phy_interface_t mode);
792
793#define LINK_FORCED_DOWN 0
794#define LINK_FORCED_UP 1
795#define LINK_UNFORCED -2
796
797 /* Port's MAC link state
798 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
799 * or LINK_UNFORCED for normal link detection.
800 */
801 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
802
803#define DUPLEX_UNFORCED -2
804
805 /* Port's MAC duplex mode
806 *
807 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
808 * or DUPLEX_UNFORCED for normal duplex detection.
809 */
810 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
811
812#define SPEED_MAX INT_MAX
813#define SPEED_UNFORCED -2
814
815 /* Port's MAC speed (in Mbps)
816 *
817 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
818 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
819 */
820 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
821
822 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
823
824 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
825 enum mv88e6xxx_frame_mode mode);
826 int (*port_set_egress_unknowns)(struct mv88e6xxx_chip *chip, int port,
827 bool on);
828 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
829 u16 etype);
830 int (*port_jumbo_config)(struct mv88e6xxx_chip *chip, int port);
831
832 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
833 int (*port_pause_config)(struct mv88e6xxx_chip *chip, int port);
834
835 /* Snapshot the statistics for a port. The statistics can then
836 * be read back a leisure but still with a consistent view.
837 */
838 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
839
840 /* Set the histogram mode for statistics, when the control registers
841 * are separated out of the STATS_OP register.
842 */
843 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
844
845 /* Return the number of strings describing statistics */
846 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
847 void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
848 void (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
849 uint64_t *data);
850 int (*g1_set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
851 int (*g1_set_egress_port)(struct mv88e6xxx_chip *chip, int port);
852
853 /* Can be either in g1 or g2, so don't use a prefix */
854 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
855};
856
857#define STATS_TYPE_PORT BIT(0)
858#define STATS_TYPE_BANK0 BIT(1)
859#define STATS_TYPE_BANK1 BIT(2)
860
861struct mv88e6xxx_hw_stat {
862 char string[ETH_GSTRING_LEN];
863 int sizeof_stat;
864 int reg;
865 int type;
866};
867
868static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip,
869 unsigned long flags)
870{
871 return (chip->info->flags & flags) == flags;
872}
873
874static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
875{
876 return chip->info->num_databases;
877}
878
879static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
880{
881 return chip->info->num_ports;
882}
883
884int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
885int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
886int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
887 u16 update);
888int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
889
890#endif