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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Marvell 88E6xxx Switch Global (1) Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 */
10
11#include <linux/bitfield.h>
12
13#include "chip.h"
14#include "global1.h"
15
16int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
17{
18 int addr = chip->info->global1_addr;
19
20 return mv88e6xxx_read(chip, addr, reg, val);
21}
22
23int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
24{
25 int addr = chip->info->global1_addr;
26
27 return mv88e6xxx_write(chip, addr, reg, val);
28}
29
30int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
31 bit, int val)
32{
33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
34 bit, val);
35}
36
37int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
38 u16 mask, u16 val)
39{
40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
41 mask, val);
42}
43
44/* Offset 0x00: Switch Global Status Register */
45
46static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
47{
48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
49 MV88E6185_G1_STS_PPU_STATE_MASK,
50 MV88E6185_G1_STS_PPU_STATE_DISABLED);
51}
52
53static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
54{
55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
56 MV88E6185_G1_STS_PPU_STATE_MASK,
57 MV88E6185_G1_STS_PPU_STATE_POLLING);
58}
59
60static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
61{
62 int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
63
64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
65}
66
67static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
68{
69 int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
70
71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11
72 * is set to a one when all units inside the device (ATU, VTU, etc.)
73 * have finished their initialization and are ready to accept frames.
74 */
75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
76}
77
78/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
79 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
80 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
81 */
82int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
83{
84 u16 reg;
85 int err;
86
87 reg = (addr[0] << 8) | addr[1];
88 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
89 if (err)
90 return err;
91
92 reg = (addr[2] << 8) | addr[3];
93 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
94 if (err)
95 return err;
96
97 reg = (addr[4] << 8) | addr[5];
98 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
99 if (err)
100 return err;
101
102 return 0;
103}
104
105/* Offset 0x04: Switch Global Control Register */
106
107int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
108{
109 u16 val;
110 int err;
111
112 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
113 * the PPU, including re-doing PHY detection and initialization
114 */
115 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
116 if (err)
117 return err;
118
119 val |= MV88E6XXX_G1_CTL1_SW_RESET;
120 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
121
122 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
123 if (err)
124 return err;
125
126 err = mv88e6xxx_g1_wait_init_ready(chip);
127 if (err)
128 return err;
129
130 return mv88e6185_g1_wait_ppu_polling(chip);
131}
132
133int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
134{
135 u16 val;
136 int err;
137
138 /* Set the SWReset bit 15 */
139 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
140 if (err)
141 return err;
142
143 val |= MV88E6XXX_G1_CTL1_SW_RESET;
144
145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
146 if (err)
147 return err;
148
149 return mv88e6xxx_g1_wait_init_ready(chip);
150}
151
152int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
153{
154 int err;
155
156 err = mv88e6250_g1_reset(chip);
157 if (err)
158 return err;
159
160 return mv88e6352_g1_wait_ppu_polling(chip);
161}
162
163int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
164{
165 u16 val;
166 int err;
167
168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
169 if (err)
170 return err;
171
172 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
173
174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
175 if (err)
176 return err;
177
178 return mv88e6185_g1_wait_ppu_polling(chip);
179}
180
181int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
182{
183 u16 val;
184 int err;
185
186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
187 if (err)
188 return err;
189
190 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
191
192 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
193 if (err)
194 return err;
195
196 return mv88e6185_g1_wait_ppu_disabled(chip);
197}
198
199int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu)
200{
201 u16 val;
202 int err;
203
204 mtu += ETH_HLEN + ETH_FCS_LEN;
205
206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
207 if (err)
208 return err;
209
210 val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632;
211
212 if (mtu > 1518)
213 val |= MV88E6185_G1_CTL1_MAX_FRAME_1632;
214
215 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
216}
217
218/* Offset 0x10: IP-PRI Mapping Register 0
219 * Offset 0x11: IP-PRI Mapping Register 1
220 * Offset 0x12: IP-PRI Mapping Register 2
221 * Offset 0x13: IP-PRI Mapping Register 3
222 * Offset 0x14: IP-PRI Mapping Register 4
223 * Offset 0x15: IP-PRI Mapping Register 5
224 * Offset 0x16: IP-PRI Mapping Register 6
225 * Offset 0x17: IP-PRI Mapping Register 7
226 */
227
228int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
229{
230 int err;
231
232 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
233 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
234 if (err)
235 return err;
236
237 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
238 if (err)
239 return err;
240
241 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
242 if (err)
243 return err;
244
245 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
246 if (err)
247 return err;
248
249 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
250 if (err)
251 return err;
252
253 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
254 if (err)
255 return err;
256
257 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
258 if (err)
259 return err;
260
261 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
262 if (err)
263 return err;
264
265 return 0;
266}
267
268/* Offset 0x18: IEEE-PRI Register */
269
270int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
271{
272 /* Reset the IEEE Tag priorities to defaults */
273 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
274}
275
276int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
277{
278 /* Reset the IEEE Tag priorities to defaults */
279 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
280}
281
282/* Offset 0x1a: Monitor Control */
283/* Offset 0x1a: Monitor & MGMT Control on some devices */
284
285int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
286 enum mv88e6xxx_egress_direction direction,
287 int port)
288{
289 u16 reg;
290 int err;
291
292 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
293 if (err)
294 return err;
295
296 switch (direction) {
297 case MV88E6XXX_EGRESS_DIR_INGRESS:
298 reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
299 reg |= port <<
300 __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
301 break;
302 case MV88E6XXX_EGRESS_DIR_EGRESS:
303 reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
304 reg |= port <<
305 __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
306 break;
307 default:
308 return -EINVAL;
309 }
310
311 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
312}
313
314/* Older generations also call this the ARP destination. It has been
315 * generalized in more modern devices such that more than ARP can
316 * egress it
317 */
318int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
319{
320 u16 reg;
321 int err;
322
323 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
324 if (err)
325 return err;
326
327 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
328 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
329
330 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
331}
332
333static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
334 u16 pointer, u8 data)
335{
336 u16 reg;
337
338 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
339
340 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
341}
342
343int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
344 enum mv88e6xxx_egress_direction direction,
345 int port)
346{
347 u16 ptr;
348
349 switch (direction) {
350 case MV88E6XXX_EGRESS_DIR_INGRESS:
351 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
352 break;
353 case MV88E6XXX_EGRESS_DIR_EGRESS:
354 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
355 break;
356 default:
357 return -EINVAL;
358 }
359
360 return mv88e6390_g1_monitor_write(chip, ptr, port);
361}
362
363int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
364{
365 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
366
367 /* Use the default high priority for management frames sent to
368 * the CPU.
369 */
370 port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
371
372 return mv88e6390_g1_monitor_write(chip, ptr, port);
373}
374
375int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port)
376{
377 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_PTP_CPU_DEST;
378
379 /* Use the default high priority for PTP frames sent to
380 * the CPU.
381 */
382 port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
383
384 return mv88e6390_g1_monitor_write(chip, ptr, port);
385}
386
387int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
388{
389 u16 ptr;
390 int err;
391
392 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
393 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
394 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
395 if (err)
396 return err;
397
398 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
399 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
400 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
401 if (err)
402 return err;
403
404 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
405 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
406 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
407 if (err)
408 return err;
409
410 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
411 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
412 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
413 if (err)
414 return err;
415
416 return 0;
417}
418
419/* Offset 0x1c: Global Control 2 */
420
421static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
422 u16 val)
423{
424 u16 reg;
425 int err;
426
427 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®);
428 if (err)
429 return err;
430
431 reg &= ~mask;
432 reg |= val & mask;
433
434 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
435}
436
437int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
438{
439 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
440
441 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
442}
443
444int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
445{
446 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
447 MV88E6085_G1_CTL2_RM_ENABLE, 0);
448}
449
450int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
451{
452 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
453 MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
454}
455
456int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
457{
458 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
459 MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
460}
461
462int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
463{
464 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
465 MV88E6390_G1_CTL2_HIST_MODE_RX);
466}
467
468int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
469{
470 return mv88e6xxx_g1_ctl2_mask(chip,
471 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
472 index);
473}
474
475/* Offset 0x1d: Statistics Operation 2 */
476
477static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
478{
479 int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
480
481 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
482}
483
484int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
485{
486 u16 val;
487 int err;
488
489 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
490 if (err)
491 return err;
492
493 val |= MV88E6XXX_G1_STATS_OP_HIST_RX;
494
495 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
496
497 return err;
498}
499
500int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
501{
502 int err;
503
504 /* Snapshot the hardware statistics counters for this port. */
505 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
506 MV88E6XXX_G1_STATS_OP_BUSY |
507 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
508 MV88E6XXX_G1_STATS_OP_HIST_RX | port);
509 if (err)
510 return err;
511
512 /* Wait for the snapshotting to complete. */
513 return mv88e6xxx_g1_stats_wait(chip);
514}
515
516int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
517{
518 port = (port + 1) << 5;
519
520 return mv88e6xxx_g1_stats_snapshot(chip, port);
521}
522
523int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
524{
525 int err;
526
527 port = (port + 1) << 5;
528
529 /* Snapshot the hardware statistics counters for this port. */
530 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
531 MV88E6XXX_G1_STATS_OP_BUSY |
532 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
533 if (err)
534 return err;
535
536 /* Wait for the snapshotting to complete. */
537 return mv88e6xxx_g1_stats_wait(chip);
538}
539
540void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
541{
542 u32 value;
543 u16 reg;
544 int err;
545
546 *val = 0;
547
548 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
549 MV88E6XXX_G1_STATS_OP_BUSY |
550 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
551 if (err)
552 return;
553
554 err = mv88e6xxx_g1_stats_wait(chip);
555 if (err)
556 return;
557
558 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®);
559 if (err)
560 return;
561
562 value = reg << 16;
563
564 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®);
565 if (err)
566 return;
567
568 *val = value | reg;
569}
570
571int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
572{
573 int err;
574 u16 val;
575
576 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
577 if (err)
578 return err;
579
580 /* Keep the histogram mode bits */
581 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
582 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
583
584 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
585 if (err)
586 return err;
587
588 /* Wait for the flush to complete. */
589 return mv88e6xxx_g1_stats_wait(chip);
590}
1/*
2 * Marvell 88E6xxx Switch Global (1) Registers support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include "mv88e6xxx.h"
15#include "global1.h"
16
17int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
18{
19 int addr = chip->info->global1_addr;
20
21 return mv88e6xxx_read(chip, addr, reg, val);
22}
23
24int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
25{
26 int addr = chip->info->global1_addr;
27
28 return mv88e6xxx_write(chip, addr, reg, val);
29}
30
31int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
32{
33 return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask);
34}
35
36/* Offset 0x00: Switch Global Status Register */
37
38static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
39{
40 u16 state;
41 int i, err;
42
43 for (i = 0; i < 16; i++) {
44 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &state);
45 if (err)
46 return err;
47
48 /* Check the value of the PPUState bits 15:14 */
49 state &= GLOBAL_STATUS_PPU_STATE_MASK;
50 if (state != GLOBAL_STATUS_PPU_STATE_POLLING)
51 return 0;
52
53 usleep_range(1000, 2000);
54 }
55
56 return -ETIMEDOUT;
57}
58
59static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
60{
61 u16 state;
62 int i, err;
63
64 for (i = 0; i < 16; ++i) {
65 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &state);
66 if (err)
67 return err;
68
69 /* Check the value of the PPUState bits 15:14 */
70 state &= GLOBAL_STATUS_PPU_STATE_MASK;
71 if (state == GLOBAL_STATUS_PPU_STATE_POLLING)
72 return 0;
73
74 usleep_range(1000, 2000);
75 }
76
77 return -ETIMEDOUT;
78}
79
80static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
81{
82 u16 state;
83 int i, err;
84
85 for (i = 0; i < 16; ++i) {
86 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &state);
87 if (err)
88 return err;
89
90 /* Check the value of the PPUState (or InitState) bit 15 */
91 if (state & GLOBAL_STATUS_PPU_STATE)
92 return 0;
93
94 usleep_range(1000, 2000);
95 }
96
97 return -ETIMEDOUT;
98}
99
100static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
101{
102 const unsigned long timeout = jiffies + 1 * HZ;
103 u16 val;
104 int err;
105
106 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11
107 * is set to a one when all units inside the device (ATU, VTU, etc.)
108 * have finished their initialization and are ready to accept frames.
109 */
110 while (time_before(jiffies, timeout)) {
111 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
112 if (err)
113 return err;
114
115 if (val & GLOBAL_STATUS_INIT_READY)
116 break;
117
118 usleep_range(1000, 2000);
119 }
120
121 if (time_after(jiffies, timeout))
122 return -ETIMEDOUT;
123
124 return 0;
125}
126
127/* Offset 0x04: Switch Global Control Register */
128
129int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
130{
131 u16 val;
132 int err;
133
134 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
135 * the PPU, including re-doing PHY detection and initialization
136 */
137 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
138 if (err)
139 return err;
140
141 val |= GLOBAL_CONTROL_SW_RESET;
142 val |= GLOBAL_CONTROL_PPU_ENABLE;
143
144 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
145 if (err)
146 return err;
147
148 err = mv88e6xxx_g1_wait_init_ready(chip);
149 if (err)
150 return err;
151
152 return mv88e6185_g1_wait_ppu_polling(chip);
153}
154
155int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
156{
157 u16 val;
158 int err;
159
160 /* Set the SWReset bit 15 */
161 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
162 if (err)
163 return err;
164
165 val |= GLOBAL_CONTROL_SW_RESET;
166
167 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
168 if (err)
169 return err;
170
171 err = mv88e6xxx_g1_wait_init_ready(chip);
172 if (err)
173 return err;
174
175 return mv88e6352_g1_wait_ppu_polling(chip);
176}
177
178int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
179{
180 u16 val;
181 int err;
182
183 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
184 if (err)
185 return err;
186
187 val |= GLOBAL_CONTROL_PPU_ENABLE;
188
189 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
190 if (err)
191 return err;
192
193 return mv88e6185_g1_wait_ppu_polling(chip);
194}
195
196int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
197{
198 u16 val;
199 int err;
200
201 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
202 if (err)
203 return err;
204
205 val &= ~GLOBAL_CONTROL_PPU_ENABLE;
206
207 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
208 if (err)
209 return err;
210
211 return mv88e6185_g1_wait_ppu_disabled(chip);
212}
213
214/* Offset 0x1a: Monitor Control */
215/* Offset 0x1a: Monitor & MGMT Control on some devices */
216
217int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
218{
219 u16 reg;
220 int err;
221
222 err = mv88e6xxx_g1_read(chip, GLOBAL_MONITOR_CONTROL, ®);
223 if (err)
224 return err;
225
226 reg &= ~(GLOBAL_MONITOR_CONTROL_INGRESS_MASK |
227 GLOBAL_MONITOR_CONTROL_EGRESS_MASK);
228
229 reg |= port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
230 port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT;
231
232 return mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
233}
234
235/* Older generations also call this the ARP destination. It has been
236 * generalized in more modern devices such that more than ARP can
237 * egress it
238 */
239int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
240{
241 u16 reg;
242 int err;
243
244 err = mv88e6xxx_g1_read(chip, GLOBAL_MONITOR_CONTROL, ®);
245 if (err)
246 return err;
247
248 reg &= ~GLOBAL_MONITOR_CONTROL_ARP_MASK;
249 reg |= port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
250
251 return mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
252}
253
254static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
255 u16 pointer, u8 data)
256{
257 u16 reg;
258
259 reg = GLOBAL_MONITOR_CONTROL_UPDATE | pointer | data;
260
261 return mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
262}
263
264int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
265{
266 int err;
267
268 err = mv88e6390_g1_monitor_write(chip, GLOBAL_MONITOR_CONTROL_INGRESS,
269 port);
270 if (err)
271 return err;
272
273 return mv88e6390_g1_monitor_write(chip, GLOBAL_MONITOR_CONTROL_EGRESS,
274 port);
275}
276
277int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
278{
279 return mv88e6390_g1_monitor_write(chip, GLOBAL_MONITOR_CONTROL_CPU_DEST,
280 port);
281}
282
283int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
284{
285 int err;
286
287 /* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */
288 err = mv88e6390_g1_monitor_write(
289 chip, GLOBAL_MONITOR_CONTROL_0180C280000000XLO, 0xff);
290 if (err)
291 return err;
292
293 /* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */
294 err = mv88e6390_g1_monitor_write(
295 chip, GLOBAL_MONITOR_CONTROL_0180C280000000XHI, 0xff);
296 if (err)
297 return err;
298
299 /* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */
300 err = mv88e6390_g1_monitor_write(
301 chip, GLOBAL_MONITOR_CONTROL_0180C280000002XLO, 0xff);
302 if (err)
303 return err;
304
305 /* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */
306 return mv88e6390_g1_monitor_write(
307 chip, GLOBAL_MONITOR_CONTROL_0180C280000002XHI, 0xff);
308}
309
310/* Offset 0x1c: Global Control 2 */
311
312int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
313{
314 u16 val;
315 int err;
316
317 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL_2, &val);
318 if (err)
319 return err;
320
321 val |= GLOBAL_CONTROL_2_HIST_RX_TX;
322
323 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, val);
324
325 return err;
326}
327
328/* Offset 0x1d: Statistics Operation 2 */
329
330int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
331{
332 return mv88e6xxx_g1_wait(chip, GLOBAL_STATS_OP, GLOBAL_STATS_OP_BUSY);
333}
334
335int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
336{
337 int err;
338
339 /* Snapshot the hardware statistics counters for this port. */
340 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
341 GLOBAL_STATS_OP_CAPTURE_PORT |
342 GLOBAL_STATS_OP_HIST_RX_TX | port);
343 if (err)
344 return err;
345
346 /* Wait for the snapshotting to complete. */
347 return mv88e6xxx_g1_stats_wait(chip);
348}
349
350int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
351{
352 port = (port + 1) << 5;
353
354 return mv88e6xxx_g1_stats_snapshot(chip, port);
355}
356
357int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
358{
359 int err;
360
361 port = (port + 1) << 5;
362
363 /* Snapshot the hardware statistics counters for this port. */
364 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
365 GLOBAL_STATS_OP_CAPTURE_PORT | port);
366 if (err)
367 return err;
368
369 /* Wait for the snapshotting to complete. */
370 return mv88e6xxx_g1_stats_wait(chip);
371}
372
373void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
374{
375 u32 value;
376 u16 reg;
377 int err;
378
379 *val = 0;
380
381 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
382 GLOBAL_STATS_OP_READ_CAPTURED | stat);
383 if (err)
384 return;
385
386 err = mv88e6xxx_g1_stats_wait(chip);
387 if (err)
388 return;
389
390 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, ®);
391 if (err)
392 return;
393
394 value = reg << 16;
395
396 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, ®);
397 if (err)
398 return;
399
400 *val = value | reg;
401}