Loading...
Note: File does not exist in v4.10.11.
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*******************************************************************************
3 *
4 * CTU CAN FD IP Core
5 *
6 * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
7 * Copyright (C) 2018-2022 Ondrej Ille <ondrej.ille@gmail.com> self-funded
8 * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
9 * Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
10 *
11 * Project advisors:
12 * Jiri Novak <jnovak@fel.cvut.cz>
13 * Pavel Pisa <pisa@cmp.felk.cvut.cz>
14 *
15 * Department of Measurement (http://meas.fel.cvut.cz/)
16 * Faculty of Electrical Engineering (http://www.fel.cvut.cz)
17 * Czech Technical University (http://www.cvut.cz/)
18 ******************************************************************************/
19
20/* This file is autogenerated, DO NOT EDIT! */
21
22#ifndef __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
23#define __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
24
25#include <linux/bits.h>
26
27/* CAN_Registers memory map */
28enum ctu_can_fd_can_registers {
29 CTUCANFD_DEVICE_ID = 0x0,
30 CTUCANFD_VERSION = 0x2,
31 CTUCANFD_MODE = 0x4,
32 CTUCANFD_SETTINGS = 0x6,
33 CTUCANFD_STATUS = 0x8,
34 CTUCANFD_COMMAND = 0xc,
35 CTUCANFD_INT_STAT = 0x10,
36 CTUCANFD_INT_ENA_SET = 0x14,
37 CTUCANFD_INT_ENA_CLR = 0x18,
38 CTUCANFD_INT_MASK_SET = 0x1c,
39 CTUCANFD_INT_MASK_CLR = 0x20,
40 CTUCANFD_BTR = 0x24,
41 CTUCANFD_BTR_FD = 0x28,
42 CTUCANFD_EWL = 0x2c,
43 CTUCANFD_ERP = 0x2d,
44 CTUCANFD_FAULT_STATE = 0x2e,
45 CTUCANFD_REC = 0x30,
46 CTUCANFD_TEC = 0x32,
47 CTUCANFD_ERR_NORM = 0x34,
48 CTUCANFD_ERR_FD = 0x36,
49 CTUCANFD_CTR_PRES = 0x38,
50 CTUCANFD_FILTER_A_MASK = 0x3c,
51 CTUCANFD_FILTER_A_VAL = 0x40,
52 CTUCANFD_FILTER_B_MASK = 0x44,
53 CTUCANFD_FILTER_B_VAL = 0x48,
54 CTUCANFD_FILTER_C_MASK = 0x4c,
55 CTUCANFD_FILTER_C_VAL = 0x50,
56 CTUCANFD_FILTER_RAN_LOW = 0x54,
57 CTUCANFD_FILTER_RAN_HIGH = 0x58,
58 CTUCANFD_FILTER_CONTROL = 0x5c,
59 CTUCANFD_FILTER_STATUS = 0x5e,
60 CTUCANFD_RX_MEM_INFO = 0x60,
61 CTUCANFD_RX_POINTERS = 0x64,
62 CTUCANFD_RX_STATUS = 0x68,
63 CTUCANFD_RX_SETTINGS = 0x6a,
64 CTUCANFD_RX_DATA = 0x6c,
65 CTUCANFD_TX_STATUS = 0x70,
66 CTUCANFD_TX_COMMAND = 0x74,
67 CTUCANFD_TXTB_INFO = 0x76,
68 CTUCANFD_TX_PRIORITY = 0x78,
69 CTUCANFD_ERR_CAPT = 0x7c,
70 CTUCANFD_RETR_CTR = 0x7d,
71 CTUCANFD_ALC = 0x7e,
72 CTUCANFD_TS_INFO = 0x7f,
73 CTUCANFD_TRV_DELAY = 0x80,
74 CTUCANFD_SSP_CFG = 0x82,
75 CTUCANFD_RX_FR_CTR = 0x84,
76 CTUCANFD_TX_FR_CTR = 0x88,
77 CTUCANFD_DEBUG_REGISTER = 0x8c,
78 CTUCANFD_YOLO_REG = 0x90,
79 CTUCANFD_TIMESTAMP_LOW = 0x94,
80 CTUCANFD_TIMESTAMP_HIGH = 0x98,
81 CTUCANFD_TXTB1_DATA_1 = 0x100,
82 CTUCANFD_TXTB1_DATA_2 = 0x104,
83 CTUCANFD_TXTB1_DATA_20 = 0x14c,
84 CTUCANFD_TXTB2_DATA_1 = 0x200,
85 CTUCANFD_TXTB2_DATA_2 = 0x204,
86 CTUCANFD_TXTB2_DATA_20 = 0x24c,
87 CTUCANFD_TXTB3_DATA_1 = 0x300,
88 CTUCANFD_TXTB3_DATA_2 = 0x304,
89 CTUCANFD_TXTB3_DATA_20 = 0x34c,
90 CTUCANFD_TXTB4_DATA_1 = 0x400,
91 CTUCANFD_TXTB4_DATA_2 = 0x404,
92 CTUCANFD_TXTB4_DATA_20 = 0x44c,
93};
94
95/* Control_registers memory region */
96
97/* DEVICE_ID VERSION registers */
98#define REG_DEVICE_ID_DEVICE_ID GENMASK(15, 0)
99#define REG_DEVICE_ID_VER_MINOR GENMASK(23, 16)
100#define REG_DEVICE_ID_VER_MAJOR GENMASK(31, 24)
101
102/* MODE SETTINGS registers */
103#define REG_MODE_RST BIT(0)
104#define REG_MODE_BMM BIT(1)
105#define REG_MODE_STM BIT(2)
106#define REG_MODE_AFM BIT(3)
107#define REG_MODE_FDE BIT(4)
108#define REG_MODE_TTTM BIT(5)
109#define REG_MODE_ROM BIT(6)
110#define REG_MODE_ACF BIT(7)
111#define REG_MODE_TSTM BIT(8)
112#define REG_MODE_RXBAM BIT(9)
113#define REG_MODE_SAM BIT(11)
114#define REG_MODE_RTRLE BIT(16)
115#define REG_MODE_RTRTH GENMASK(20, 17)
116#define REG_MODE_ILBP BIT(21)
117#define REG_MODE_ENA BIT(22)
118#define REG_MODE_NISOFD BIT(23)
119#define REG_MODE_PEX BIT(24)
120#define REG_MODE_TBFBO BIT(25)
121#define REG_MODE_FDRF BIT(26)
122
123/* STATUS registers */
124#define REG_STATUS_RXNE BIT(0)
125#define REG_STATUS_DOR BIT(1)
126#define REG_STATUS_TXNF BIT(2)
127#define REG_STATUS_EFT BIT(3)
128#define REG_STATUS_RXS BIT(4)
129#define REG_STATUS_TXS BIT(5)
130#define REG_STATUS_EWL BIT(6)
131#define REG_STATUS_IDLE BIT(7)
132#define REG_STATUS_PEXS BIT(8)
133#define REG_STATUS_STCNT BIT(16)
134
135/* COMMAND registers */
136#define REG_COMMAND_RXRPMV BIT(1)
137#define REG_COMMAND_RRB BIT(2)
138#define REG_COMMAND_CDO BIT(3)
139#define REG_COMMAND_ERCRST BIT(4)
140#define REG_COMMAND_RXFCRST BIT(5)
141#define REG_COMMAND_TXFCRST BIT(6)
142#define REG_COMMAND_CPEXS BIT(7)
143
144/* INT_STAT registers */
145#define REG_INT_STAT_RXI BIT(0)
146#define REG_INT_STAT_TXI BIT(1)
147#define REG_INT_STAT_EWLI BIT(2)
148#define REG_INT_STAT_DOI BIT(3)
149#define REG_INT_STAT_FCSI BIT(4)
150#define REG_INT_STAT_ALI BIT(5)
151#define REG_INT_STAT_BEI BIT(6)
152#define REG_INT_STAT_OFI BIT(7)
153#define REG_INT_STAT_RXFI BIT(8)
154#define REG_INT_STAT_BSI BIT(9)
155#define REG_INT_STAT_RBNEI BIT(10)
156#define REG_INT_STAT_TXBHCI BIT(11)
157
158/* INT_ENA_SET registers */
159#define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0)
160
161/* INT_ENA_CLR registers */
162#define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0)
163
164/* INT_MASK_SET registers */
165#define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0)
166
167/* INT_MASK_CLR registers */
168#define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0)
169
170/* BTR registers */
171#define REG_BTR_PROP GENMASK(6, 0)
172#define REG_BTR_PH1 GENMASK(12, 7)
173#define REG_BTR_PH2 GENMASK(18, 13)
174#define REG_BTR_BRP GENMASK(26, 19)
175#define REG_BTR_SJW GENMASK(31, 27)
176
177/* BTR_FD registers */
178#define REG_BTR_FD_PROP_FD GENMASK(5, 0)
179#define REG_BTR_FD_PH1_FD GENMASK(11, 7)
180#define REG_BTR_FD_PH2_FD GENMASK(17, 13)
181#define REG_BTR_FD_BRP_FD GENMASK(26, 19)
182#define REG_BTR_FD_SJW_FD GENMASK(31, 27)
183
184/* EWL ERP FAULT_STATE registers */
185#define REG_EWL_EW_LIMIT GENMASK(7, 0)
186#define REG_EWL_ERP_LIMIT GENMASK(15, 8)
187#define REG_EWL_ERA BIT(16)
188#define REG_EWL_ERP BIT(17)
189#define REG_EWL_BOF BIT(18)
190
191/* REC TEC registers */
192#define REG_REC_REC_VAL GENMASK(8, 0)
193#define REG_REC_TEC_VAL GENMASK(24, 16)
194
195/* ERR_NORM ERR_FD registers */
196#define REG_ERR_NORM_ERR_NORM_VAL GENMASK(15, 0)
197#define REG_ERR_NORM_ERR_FD_VAL GENMASK(31, 16)
198
199/* CTR_PRES registers */
200#define REG_CTR_PRES_CTPV GENMASK(8, 0)
201#define REG_CTR_PRES_PTX BIT(9)
202#define REG_CTR_PRES_PRX BIT(10)
203#define REG_CTR_PRES_ENORM BIT(11)
204#define REG_CTR_PRES_EFD BIT(12)
205
206/* FILTER_A_MASK registers */
207#define REG_FILTER_A_MASK_BIT_MASK_A_VAL GENMASK(28, 0)
208
209/* FILTER_A_VAL registers */
210#define REG_FILTER_A_VAL_BIT_VAL_A_VAL GENMASK(28, 0)
211
212/* FILTER_B_MASK registers */
213#define REG_FILTER_B_MASK_BIT_MASK_B_VAL GENMASK(28, 0)
214
215/* FILTER_B_VAL registers */
216#define REG_FILTER_B_VAL_BIT_VAL_B_VAL GENMASK(28, 0)
217
218/* FILTER_C_MASK registers */
219#define REG_FILTER_C_MASK_BIT_MASK_C_VAL GENMASK(28, 0)
220
221/* FILTER_C_VAL registers */
222#define REG_FILTER_C_VAL_BIT_VAL_C_VAL GENMASK(28, 0)
223
224/* FILTER_RAN_LOW registers */
225#define REG_FILTER_RAN_LOW_BIT_RAN_LOW_VAL GENMASK(28, 0)
226
227/* FILTER_RAN_HIGH registers */
228#define REG_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL GENMASK(28, 0)
229
230/* FILTER_CONTROL FILTER_STATUS registers */
231#define REG_FILTER_CONTROL_FANB BIT(0)
232#define REG_FILTER_CONTROL_FANE BIT(1)
233#define REG_FILTER_CONTROL_FAFB BIT(2)
234#define REG_FILTER_CONTROL_FAFE BIT(3)
235#define REG_FILTER_CONTROL_FBNB BIT(4)
236#define REG_FILTER_CONTROL_FBNE BIT(5)
237#define REG_FILTER_CONTROL_FBFB BIT(6)
238#define REG_FILTER_CONTROL_FBFE BIT(7)
239#define REG_FILTER_CONTROL_FCNB BIT(8)
240#define REG_FILTER_CONTROL_FCNE BIT(9)
241#define REG_FILTER_CONTROL_FCFB BIT(10)
242#define REG_FILTER_CONTROL_FCFE BIT(11)
243#define REG_FILTER_CONTROL_FRNB BIT(12)
244#define REG_FILTER_CONTROL_FRNE BIT(13)
245#define REG_FILTER_CONTROL_FRFB BIT(14)
246#define REG_FILTER_CONTROL_FRFE BIT(15)
247#define REG_FILTER_CONTROL_SFA BIT(16)
248#define REG_FILTER_CONTROL_SFB BIT(17)
249#define REG_FILTER_CONTROL_SFC BIT(18)
250#define REG_FILTER_CONTROL_SFR BIT(19)
251
252/* RX_MEM_INFO registers */
253#define REG_RX_MEM_INFO_RX_BUFF_SIZE GENMASK(12, 0)
254#define REG_RX_MEM_INFO_RX_MEM_FREE GENMASK(28, 16)
255
256/* RX_POINTERS registers */
257#define REG_RX_POINTERS_RX_WPP GENMASK(11, 0)
258#define REG_RX_POINTERS_RX_RPP GENMASK(27, 16)
259
260/* RX_STATUS RX_SETTINGS registers */
261#define REG_RX_STATUS_RXE BIT(0)
262#define REG_RX_STATUS_RXF BIT(1)
263#define REG_RX_STATUS_RXMOF BIT(2)
264#define REG_RX_STATUS_RXFRC GENMASK(14, 4)
265#define REG_RX_STATUS_RTSOP BIT(16)
266
267/* RX_DATA registers */
268#define REG_RX_DATA_RX_DATA GENMASK(31, 0)
269
270/* TX_STATUS registers */
271#define REG_TX_STATUS_TX1S GENMASK(3, 0)
272#define REG_TX_STATUS_TX2S GENMASK(7, 4)
273#define REG_TX_STATUS_TX3S GENMASK(11, 8)
274#define REG_TX_STATUS_TX4S GENMASK(15, 12)
275#define REG_TX_STATUS_TX5S GENMASK(19, 16)
276#define REG_TX_STATUS_TX6S GENMASK(23, 20)
277#define REG_TX_STATUS_TX7S GENMASK(27, 24)
278#define REG_TX_STATUS_TX8S GENMASK(31, 28)
279
280/* TX_COMMAND TXTB_INFO registers */
281#define REG_TX_COMMAND_TXCE BIT(0)
282#define REG_TX_COMMAND_TXCR BIT(1)
283#define REG_TX_COMMAND_TXCA BIT(2)
284#define REG_TX_COMMAND_TXB1 BIT(8)
285#define REG_TX_COMMAND_TXB2 BIT(9)
286#define REG_TX_COMMAND_TXB3 BIT(10)
287#define REG_TX_COMMAND_TXB4 BIT(11)
288#define REG_TX_COMMAND_TXB5 BIT(12)
289#define REG_TX_COMMAND_TXB6 BIT(13)
290#define REG_TX_COMMAND_TXB7 BIT(14)
291#define REG_TX_COMMAND_TXB8 BIT(15)
292#define REG_TX_COMMAND_TXT_BUFFER_COUNT GENMASK(19, 16)
293
294/* TX_PRIORITY registers */
295#define REG_TX_PRIORITY_TXT1P GENMASK(2, 0)
296#define REG_TX_PRIORITY_TXT2P GENMASK(6, 4)
297#define REG_TX_PRIORITY_TXT3P GENMASK(10, 8)
298#define REG_TX_PRIORITY_TXT4P GENMASK(14, 12)
299#define REG_TX_PRIORITY_TXT5P GENMASK(18, 16)
300#define REG_TX_PRIORITY_TXT6P GENMASK(22, 20)
301#define REG_TX_PRIORITY_TXT7P GENMASK(26, 24)
302#define REG_TX_PRIORITY_TXT8P GENMASK(30, 28)
303
304/* ERR_CAPT RETR_CTR ALC TS_INFO registers */
305#define REG_ERR_CAPT_ERR_POS GENMASK(4, 0)
306#define REG_ERR_CAPT_ERR_TYPE GENMASK(7, 5)
307#define REG_ERR_CAPT_RETR_CTR_VAL GENMASK(11, 8)
308#define REG_ERR_CAPT_ALC_BIT GENMASK(20, 16)
309#define REG_ERR_CAPT_ALC_ID_FIELD GENMASK(23, 21)
310#define REG_ERR_CAPT_TS_BITS GENMASK(29, 24)
311
312/* TRV_DELAY SSP_CFG registers */
313#define REG_TRV_DELAY_TRV_DELAY_VALUE GENMASK(6, 0)
314#define REG_TRV_DELAY_SSP_OFFSET GENMASK(23, 16)
315#define REG_TRV_DELAY_SSP_SRC GENMASK(25, 24)
316
317/* RX_FR_CTR registers */
318#define REG_RX_FR_CTR_RX_FR_CTR_VAL GENMASK(31, 0)
319
320/* TX_FR_CTR registers */
321#define REG_TX_FR_CTR_TX_FR_CTR_VAL GENMASK(31, 0)
322
323/* DEBUG_REGISTER registers */
324#define REG_DEBUG_REGISTER_STUFF_COUNT GENMASK(2, 0)
325#define REG_DEBUG_REGISTER_DESTUFF_COUNT GENMASK(5, 3)
326#define REG_DEBUG_REGISTER_PC_ARB BIT(6)
327#define REG_DEBUG_REGISTER_PC_CON BIT(7)
328#define REG_DEBUG_REGISTER_PC_DAT BIT(8)
329#define REG_DEBUG_REGISTER_PC_STC BIT(9)
330#define REG_DEBUG_REGISTER_PC_CRC BIT(10)
331#define REG_DEBUG_REGISTER_PC_CRCD BIT(11)
332#define REG_DEBUG_REGISTER_PC_ACK BIT(12)
333#define REG_DEBUG_REGISTER_PC_ACKD BIT(13)
334#define REG_DEBUG_REGISTER_PC_EOF BIT(14)
335#define REG_DEBUG_REGISTER_PC_INT BIT(15)
336#define REG_DEBUG_REGISTER_PC_SUSP BIT(16)
337#define REG_DEBUG_REGISTER_PC_OVR BIT(17)
338#define REG_DEBUG_REGISTER_PC_SOF BIT(18)
339
340/* YOLO_REG registers */
341#define REG_YOLO_REG_YOLO_VAL GENMASK(31, 0)
342
343/* TIMESTAMP_LOW registers */
344#define REG_TIMESTAMP_LOW_TIMESTAMP_LOW GENMASK(31, 0)
345
346/* TIMESTAMP_HIGH registers */
347#define REG_TIMESTAMP_HIGH_TIMESTAMP_HIGH GENMASK(31, 0)
348
349#endif