Loading...
Note: File does not exist in v6.8.
1/*
2 * SPI-NOR driver for NXP SPI Flash Interface (SPIFI)
3 *
4 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
5 *
6 * Based on Freescale QuadSPI driver:
7 * Copyright (C) 2013 Freescale Semiconductor, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/iopoll.h>
19#include <linux/module.h>
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/partitions.h>
22#include <linux/mtd/spi-nor.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/platform_device.h>
26#include <linux/spi/spi.h>
27
28/* NXP SPIFI registers, bits and macros */
29#define SPIFI_CTRL 0x000
30#define SPIFI_CTRL_TIMEOUT(timeout) (timeout)
31#define SPIFI_CTRL_CSHIGH(cshigh) ((cshigh) << 16)
32#define SPIFI_CTRL_MODE3 BIT(23)
33#define SPIFI_CTRL_DUAL BIT(28)
34#define SPIFI_CTRL_FBCLK BIT(30)
35#define SPIFI_CMD 0x004
36#define SPIFI_CMD_DATALEN(dlen) ((dlen) & 0x3fff)
37#define SPIFI_CMD_DOUT BIT(15)
38#define SPIFI_CMD_INTLEN(ilen) ((ilen) << 16)
39#define SPIFI_CMD_FIELDFORM(field) ((field) << 19)
40#define SPIFI_CMD_FIELDFORM_ALL_SERIAL SPIFI_CMD_FIELDFORM(0x0)
41#define SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA SPIFI_CMD_FIELDFORM(0x1)
42#define SPIFI_CMD_FRAMEFORM(frame) ((frame) << 21)
43#define SPIFI_CMD_FRAMEFORM_OPCODE_ONLY SPIFI_CMD_FRAMEFORM(0x1)
44#define SPIFI_CMD_OPCODE(op) ((op) << 24)
45#define SPIFI_ADDR 0x008
46#define SPIFI_IDATA 0x00c
47#define SPIFI_CLIMIT 0x010
48#define SPIFI_DATA 0x014
49#define SPIFI_MCMD 0x018
50#define SPIFI_STAT 0x01c
51#define SPIFI_STAT_MCINIT BIT(0)
52#define SPIFI_STAT_CMD BIT(1)
53#define SPIFI_STAT_RESET BIT(4)
54
55#define SPI_NOR_MAX_ID_LEN 6
56
57struct nxp_spifi {
58 struct device *dev;
59 struct clk *clk_spifi;
60 struct clk *clk_reg;
61 void __iomem *io_base;
62 void __iomem *flash_base;
63 struct spi_nor nor;
64 bool memory_mode;
65 u32 mcmd;
66};
67
68static int nxp_spifi_wait_for_cmd(struct nxp_spifi *spifi)
69{
70 u8 stat;
71 int ret;
72
73 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
74 !(stat & SPIFI_STAT_CMD), 10, 30);
75 if (ret)
76 dev_warn(spifi->dev, "command timed out\n");
77
78 return ret;
79}
80
81static int nxp_spifi_reset(struct nxp_spifi *spifi)
82{
83 u8 stat;
84 int ret;
85
86 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT);
87 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
88 !(stat & SPIFI_STAT_RESET), 10, 30);
89 if (ret)
90 dev_warn(spifi->dev, "state reset timed out\n");
91
92 return ret;
93}
94
95static int nxp_spifi_set_memory_mode_off(struct nxp_spifi *spifi)
96{
97 int ret;
98
99 if (!spifi->memory_mode)
100 return 0;
101
102 ret = nxp_spifi_reset(spifi);
103 if (ret)
104 dev_err(spifi->dev, "unable to enter command mode\n");
105 else
106 spifi->memory_mode = false;
107
108 return ret;
109}
110
111static int nxp_spifi_set_memory_mode_on(struct nxp_spifi *spifi)
112{
113 u8 stat;
114 int ret;
115
116 if (spifi->memory_mode)
117 return 0;
118
119 writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD);
120 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
121 stat & SPIFI_STAT_MCINIT, 10, 30);
122 if (ret)
123 dev_err(spifi->dev, "unable to enter memory mode\n");
124 else
125 spifi->memory_mode = true;
126
127 return ret;
128}
129
130static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
131{
132 struct nxp_spifi *spifi = nor->priv;
133 u32 cmd;
134 int ret;
135
136 ret = nxp_spifi_set_memory_mode_off(spifi);
137 if (ret)
138 return ret;
139
140 cmd = SPIFI_CMD_DATALEN(len) |
141 SPIFI_CMD_OPCODE(opcode) |
142 SPIFI_CMD_FIELDFORM_ALL_SERIAL |
143 SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
144 writel(cmd, spifi->io_base + SPIFI_CMD);
145
146 while (len--)
147 *buf++ = readb(spifi->io_base + SPIFI_DATA);
148
149 return nxp_spifi_wait_for_cmd(spifi);
150}
151
152static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
153{
154 struct nxp_spifi *spifi = nor->priv;
155 u32 cmd;
156 int ret;
157
158 ret = nxp_spifi_set_memory_mode_off(spifi);
159 if (ret)
160 return ret;
161
162 cmd = SPIFI_CMD_DOUT |
163 SPIFI_CMD_DATALEN(len) |
164 SPIFI_CMD_OPCODE(opcode) |
165 SPIFI_CMD_FIELDFORM_ALL_SERIAL |
166 SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
167 writel(cmd, spifi->io_base + SPIFI_CMD);
168
169 while (len--)
170 writeb(*buf++, spifi->io_base + SPIFI_DATA);
171
172 return nxp_spifi_wait_for_cmd(spifi);
173}
174
175static ssize_t nxp_spifi_read(struct spi_nor *nor, loff_t from, size_t len,
176 u_char *buf)
177{
178 struct nxp_spifi *spifi = nor->priv;
179 int ret;
180
181 ret = nxp_spifi_set_memory_mode_on(spifi);
182 if (ret)
183 return ret;
184
185 memcpy_fromio(buf, spifi->flash_base + from, len);
186
187 return len;
188}
189
190static ssize_t nxp_spifi_write(struct spi_nor *nor, loff_t to, size_t len,
191 const u_char *buf)
192{
193 struct nxp_spifi *spifi = nor->priv;
194 u32 cmd;
195 int ret;
196 size_t i;
197
198 ret = nxp_spifi_set_memory_mode_off(spifi);
199 if (ret)
200 return ret;
201
202 writel(to, spifi->io_base + SPIFI_ADDR);
203
204 cmd = SPIFI_CMD_DOUT |
205 SPIFI_CMD_DATALEN(len) |
206 SPIFI_CMD_FIELDFORM_ALL_SERIAL |
207 SPIFI_CMD_OPCODE(nor->program_opcode) |
208 SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
209 writel(cmd, spifi->io_base + SPIFI_CMD);
210
211 for (i = 0; i < len; i++)
212 writeb(buf[i], spifi->io_base + SPIFI_DATA);
213
214 ret = nxp_spifi_wait_for_cmd(spifi);
215 if (ret)
216 return ret;
217
218 return len;
219}
220
221static int nxp_spifi_erase(struct spi_nor *nor, loff_t offs)
222{
223 struct nxp_spifi *spifi = nor->priv;
224 u32 cmd;
225 int ret;
226
227 ret = nxp_spifi_set_memory_mode_off(spifi);
228 if (ret)
229 return ret;
230
231 writel(offs, spifi->io_base + SPIFI_ADDR);
232
233 cmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL |
234 SPIFI_CMD_OPCODE(nor->erase_opcode) |
235 SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
236 writel(cmd, spifi->io_base + SPIFI_CMD);
237
238 return nxp_spifi_wait_for_cmd(spifi);
239}
240
241static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
242{
243 switch (spifi->nor.flash_read) {
244 case SPI_NOR_NORMAL:
245 case SPI_NOR_FAST:
246 spifi->mcmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL;
247 break;
248 case SPI_NOR_DUAL:
249 case SPI_NOR_QUAD:
250 spifi->mcmd = SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA;
251 break;
252 default:
253 dev_err(spifi->dev, "unsupported SPI read mode\n");
254 return -EINVAL;
255 }
256
257 /* Memory mode supports address length between 1 and 4 */
258 if (spifi->nor.addr_width < 1 || spifi->nor.addr_width > 4)
259 return -EINVAL;
260
261 spifi->mcmd |= SPIFI_CMD_OPCODE(spifi->nor.read_opcode) |
262 SPIFI_CMD_INTLEN(spifi->nor.read_dummy / 8) |
263 SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
264
265 return 0;
266}
267
268static void nxp_spifi_dummy_id_read(struct spi_nor *nor)
269{
270 u8 id[SPI_NOR_MAX_ID_LEN];
271 nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
272}
273
274static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
275 struct device_node *np)
276{
277 enum read_mode flash_read;
278 u32 ctrl, property;
279 u16 mode = 0;
280 int ret;
281
282 if (!of_property_read_u32(np, "spi-rx-bus-width", &property)) {
283 switch (property) {
284 case 1:
285 break;
286 case 2:
287 mode |= SPI_RX_DUAL;
288 break;
289 case 4:
290 mode |= SPI_RX_QUAD;
291 break;
292 default:
293 dev_err(spifi->dev, "unsupported rx-bus-width\n");
294 return -EINVAL;
295 }
296 }
297
298 if (of_find_property(np, "spi-cpha", NULL))
299 mode |= SPI_CPHA;
300
301 if (of_find_property(np, "spi-cpol", NULL))
302 mode |= SPI_CPOL;
303
304 /* Setup control register defaults */
305 ctrl = SPIFI_CTRL_TIMEOUT(1000) |
306 SPIFI_CTRL_CSHIGH(15) |
307 SPIFI_CTRL_FBCLK;
308
309 if (mode & SPI_RX_DUAL) {
310 ctrl |= SPIFI_CTRL_DUAL;
311 flash_read = SPI_NOR_DUAL;
312 } else if (mode & SPI_RX_QUAD) {
313 ctrl &= ~SPIFI_CTRL_DUAL;
314 flash_read = SPI_NOR_QUAD;
315 } else {
316 ctrl |= SPIFI_CTRL_DUAL;
317 flash_read = SPI_NOR_NORMAL;
318 }
319
320 switch (mode & (SPI_CPHA | SPI_CPOL)) {
321 case SPI_MODE_0:
322 ctrl &= ~SPIFI_CTRL_MODE3;
323 break;
324 case SPI_MODE_3:
325 ctrl |= SPIFI_CTRL_MODE3;
326 break;
327 default:
328 dev_err(spifi->dev, "only mode 0 and 3 supported\n");
329 return -EINVAL;
330 }
331
332 writel(ctrl, spifi->io_base + SPIFI_CTRL);
333
334 spifi->nor.dev = spifi->dev;
335 spi_nor_set_flash_node(&spifi->nor, np);
336 spifi->nor.priv = spifi;
337 spifi->nor.read = nxp_spifi_read;
338 spifi->nor.write = nxp_spifi_write;
339 spifi->nor.erase = nxp_spifi_erase;
340 spifi->nor.read_reg = nxp_spifi_read_reg;
341 spifi->nor.write_reg = nxp_spifi_write_reg;
342
343 /*
344 * The first read on a hard reset isn't reliable so do a
345 * dummy read of the id before calling spi_nor_scan().
346 * The reason for this problem is unknown.
347 *
348 * The official NXP spifilib uses more or less the same
349 * workaround that is applied here by reading the device
350 * id multiple times.
351 */
352 nxp_spifi_dummy_id_read(&spifi->nor);
353
354 ret = spi_nor_scan(&spifi->nor, NULL, flash_read);
355 if (ret) {
356 dev_err(spifi->dev, "device scan failed\n");
357 return ret;
358 }
359
360 ret = nxp_spifi_setup_memory_cmd(spifi);
361 if (ret) {
362 dev_err(spifi->dev, "memory command setup failed\n");
363 return ret;
364 }
365
366 ret = mtd_device_register(&spifi->nor.mtd, NULL, 0);
367 if (ret) {
368 dev_err(spifi->dev, "mtd device parse failed\n");
369 return ret;
370 }
371
372 return 0;
373}
374
375static int nxp_spifi_probe(struct platform_device *pdev)
376{
377 struct device_node *flash_np;
378 struct nxp_spifi *spifi;
379 struct resource *res;
380 int ret;
381
382 spifi = devm_kzalloc(&pdev->dev, sizeof(*spifi), GFP_KERNEL);
383 if (!spifi)
384 return -ENOMEM;
385
386 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spifi");
387 spifi->io_base = devm_ioremap_resource(&pdev->dev, res);
388 if (IS_ERR(spifi->io_base))
389 return PTR_ERR(spifi->io_base);
390
391 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash");
392 spifi->flash_base = devm_ioremap_resource(&pdev->dev, res);
393 if (IS_ERR(spifi->flash_base))
394 return PTR_ERR(spifi->flash_base);
395
396 spifi->clk_spifi = devm_clk_get(&pdev->dev, "spifi");
397 if (IS_ERR(spifi->clk_spifi)) {
398 dev_err(&pdev->dev, "spifi clock not found\n");
399 return PTR_ERR(spifi->clk_spifi);
400 }
401
402 spifi->clk_reg = devm_clk_get(&pdev->dev, "reg");
403 if (IS_ERR(spifi->clk_reg)) {
404 dev_err(&pdev->dev, "reg clock not found\n");
405 return PTR_ERR(spifi->clk_reg);
406 }
407
408 ret = clk_prepare_enable(spifi->clk_reg);
409 if (ret) {
410 dev_err(&pdev->dev, "unable to enable reg clock\n");
411 return ret;
412 }
413
414 ret = clk_prepare_enable(spifi->clk_spifi);
415 if (ret) {
416 dev_err(&pdev->dev, "unable to enable spifi clock\n");
417 goto dis_clk_reg;
418 }
419
420 spifi->dev = &pdev->dev;
421 platform_set_drvdata(pdev, spifi);
422
423 /* Initialize and reset device */
424 nxp_spifi_reset(spifi);
425 writel(0, spifi->io_base + SPIFI_IDATA);
426 writel(0, spifi->io_base + SPIFI_MCMD);
427 nxp_spifi_reset(spifi);
428
429 flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
430 if (!flash_np) {
431 dev_err(&pdev->dev, "no SPI flash device to configure\n");
432 ret = -ENODEV;
433 goto dis_clks;
434 }
435
436 ret = nxp_spifi_setup_flash(spifi, flash_np);
437 if (ret) {
438 dev_err(&pdev->dev, "unable to setup flash chip\n");
439 goto dis_clks;
440 }
441
442 return 0;
443
444dis_clks:
445 clk_disable_unprepare(spifi->clk_spifi);
446dis_clk_reg:
447 clk_disable_unprepare(spifi->clk_reg);
448 return ret;
449}
450
451static int nxp_spifi_remove(struct platform_device *pdev)
452{
453 struct nxp_spifi *spifi = platform_get_drvdata(pdev);
454
455 mtd_device_unregister(&spifi->nor.mtd);
456 clk_disable_unprepare(spifi->clk_spifi);
457 clk_disable_unprepare(spifi->clk_reg);
458
459 return 0;
460}
461
462static const struct of_device_id nxp_spifi_match[] = {
463 {.compatible = "nxp,lpc1773-spifi"},
464 { /* sentinel */ }
465};
466MODULE_DEVICE_TABLE(of, nxp_spifi_match);
467
468static struct platform_driver nxp_spifi_driver = {
469 .probe = nxp_spifi_probe,
470 .remove = nxp_spifi_remove,
471 .driver = {
472 .name = "nxp-spifi",
473 .of_match_table = nxp_spifi_match,
474 },
475};
476module_platform_driver(nxp_spifi_driver);
477
478MODULE_DESCRIPTION("NXP SPI Flash Interface driver");
479MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
480MODULE_LICENSE("GPL v2");