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1/*
2 * Toshiba TMIO NAND flash controller driver
3 *
4 * Slightly murky pre-git history of the driver:
5 *
6 * Copyright (c) Ian Molton 2004, 2005, 2008
7 * Original work, independent of sharps code. Included hardware ECC support.
8 * Hard ECC did not work for writes in the early revisions.
9 * Copyright (c) Dirk Opfer 2005.
10 * Modifications developed from sharps code but
11 * NOT containing any, ported onto Ians base.
12 * Copyright (c) Chris Humbert 2005
13 * Copyright (c) Dmitry Baryshkov 2008
14 * Minor fixes
15 *
16 * Parts copyright Sebastian Carlier
17 *
18 * This file is licensed under
19 * the terms of the GNU General Public License version 2. This program
20 * is licensed "as is" without any warranty of any kind, whether express
21 * or implied.
22 *
23 */
24
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/mfd/core.h>
30#include <linux/mfd/tmio.h>
31#include <linux/delay.h>
32#include <linux/io.h>
33#include <linux/irq.h>
34#include <linux/interrupt.h>
35#include <linux/ioport.h>
36#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h>
38#include <linux/mtd/nand_ecc.h>
39#include <linux/mtd/partitions.h>
40#include <linux/slab.h>
41
42/*--------------------------------------------------------------------------*/
43
44/*
45 * NAND Flash Host Controller Configuration Register
46 */
47#define CCR_COMMAND 0x04 /* w Command */
48#define CCR_BASE 0x10 /* l NAND Flash Control Reg Base Addr */
49#define CCR_INTP 0x3d /* b Interrupt Pin */
50#define CCR_INTE 0x48 /* b Interrupt Enable */
51#define CCR_EC 0x4a /* b Event Control */
52#define CCR_ICC 0x4c /* b Internal Clock Control */
53#define CCR_ECCC 0x5b /* b ECC Control */
54#define CCR_NFTC 0x60 /* b NAND Flash Transaction Control */
55#define CCR_NFM 0x61 /* b NAND Flash Monitor */
56#define CCR_NFPSC 0x62 /* b NAND Flash Power Supply Control */
57#define CCR_NFDC 0x63 /* b NAND Flash Detect Control */
58
59/*
60 * NAND Flash Control Register
61 */
62#define FCR_DATA 0x00 /* bwl Data Register */
63#define FCR_MODE 0x04 /* b Mode Register */
64#define FCR_STATUS 0x05 /* b Status Register */
65#define FCR_ISR 0x06 /* b Interrupt Status Register */
66#define FCR_IMR 0x07 /* b Interrupt Mask Register */
67
68/* FCR_MODE Register Command List */
69#define FCR_MODE_DATA 0x94 /* Data Data_Mode */
70#define FCR_MODE_COMMAND 0x95 /* Data Command_Mode */
71#define FCR_MODE_ADDRESS 0x96 /* Data Address_Mode */
72
73#define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */
74#define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calc result Read_Mode */
75#define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */
76
77#define FCR_MODE_POWER_ON 0x0C /* Power Supply ON to SSFDC card */
78#define FCR_MODE_POWER_OFF 0x08 /* Power Supply OFF to SSFDC card */
79
80#define FCR_MODE_LED_OFF 0x00 /* LED OFF */
81#define FCR_MODE_LED_ON 0x04 /* LED ON */
82
83#define FCR_MODE_EJECT_ON 0x68 /* Ejection events active */
84#define FCR_MODE_EJECT_OFF 0x08 /* Ejection events ignored */
85
86#define FCR_MODE_LOCK 0x6C /* Lock_Mode. Eject Switch Invalid */
87#define FCR_MODE_UNLOCK 0x0C /* UnLock_Mode. Eject Switch is valid */
88
89#define FCR_MODE_CONTROLLER_ID 0x40 /* Controller ID Read */
90#define FCR_MODE_STANDBY 0x00 /* SSFDC card Changes Standby State */
91
92#define FCR_MODE_WE 0x80
93#define FCR_MODE_ECC1 0x40
94#define FCR_MODE_ECC0 0x20
95#define FCR_MODE_CE 0x10
96#define FCR_MODE_PCNT1 0x08
97#define FCR_MODE_PCNT0 0x04
98#define FCR_MODE_ALE 0x02
99#define FCR_MODE_CLE 0x01
100
101#define FCR_STATUS_BUSY 0x80
102
103/*--------------------------------------------------------------------------*/
104
105struct tmio_nand {
106 struct nand_chip chip;
107
108 struct platform_device *dev;
109
110 void __iomem *ccr;
111 void __iomem *fcr;
112 unsigned long fcr_base;
113
114 unsigned int irq;
115
116 /* for tmio_nand_read_byte */
117 u8 read;
118 unsigned read_good:1;
119};
120
121static inline struct tmio_nand *mtd_to_tmio(struct mtd_info *mtd)
122{
123 return container_of(mtd_to_nand(mtd), struct tmio_nand, chip);
124}
125
126
127/*--------------------------------------------------------------------------*/
128
129static void tmio_nand_hwcontrol(struct mtd_info *mtd, int cmd,
130 unsigned int ctrl)
131{
132 struct tmio_nand *tmio = mtd_to_tmio(mtd);
133 struct nand_chip *chip = mtd_to_nand(mtd);
134
135 if (ctrl & NAND_CTRL_CHANGE) {
136 u8 mode;
137
138 if (ctrl & NAND_NCE) {
139 mode = FCR_MODE_DATA;
140
141 if (ctrl & NAND_CLE)
142 mode |= FCR_MODE_CLE;
143 else
144 mode &= ~FCR_MODE_CLE;
145
146 if (ctrl & NAND_ALE)
147 mode |= FCR_MODE_ALE;
148 else
149 mode &= ~FCR_MODE_ALE;
150 } else {
151 mode = FCR_MODE_STANDBY;
152 }
153
154 tmio_iowrite8(mode, tmio->fcr + FCR_MODE);
155 tmio->read_good = 0;
156 }
157
158 if (cmd != NAND_CMD_NONE)
159 tmio_iowrite8(cmd, chip->IO_ADDR_W);
160}
161
162static int tmio_nand_dev_ready(struct mtd_info *mtd)
163{
164 struct tmio_nand *tmio = mtd_to_tmio(mtd);
165
166 return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY);
167}
168
169static irqreturn_t tmio_irq(int irq, void *__tmio)
170{
171 struct tmio_nand *tmio = __tmio;
172 struct nand_chip *nand_chip = &tmio->chip;
173
174 /* disable RDYREQ interrupt */
175 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
176
177 if (unlikely(!waitqueue_active(&nand_chip->controller->wq)))
178 dev_warn(&tmio->dev->dev, "spurious interrupt\n");
179
180 wake_up(&nand_chip->controller->wq);
181 return IRQ_HANDLED;
182}
183
184/*
185 *The TMIO core has a RDYREQ interrupt on the posedge of #SMRB.
186 *This interrupt is normally disabled, but for long operations like
187 *erase and write, we enable it to wake us up. The irq handler
188 *disables the interrupt.
189 */
190static int
191tmio_nand_wait(struct mtd_info *mtd, struct nand_chip *nand_chip)
192{
193 struct tmio_nand *tmio = mtd_to_tmio(mtd);
194 long timeout;
195
196 /* enable RDYREQ interrupt */
197 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
198 tmio_iowrite8(0x81, tmio->fcr + FCR_IMR);
199
200 timeout = wait_event_timeout(nand_chip->controller->wq,
201 tmio_nand_dev_ready(mtd),
202 msecs_to_jiffies(nand_chip->state == FL_ERASING ? 400 : 20));
203
204 if (unlikely(!tmio_nand_dev_ready(mtd))) {
205 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
206 dev_warn(&tmio->dev->dev, "still busy with %s after %d ms\n",
207 nand_chip->state == FL_ERASING ? "erase" : "program",
208 nand_chip->state == FL_ERASING ? 400 : 20);
209
210 } else if (unlikely(!timeout)) {
211 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
212 dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n");
213 }
214
215 nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
216 return nand_chip->read_byte(mtd);
217}
218
219/*
220 *The TMIO controller combines two 8-bit data bytes into one 16-bit
221 *word. This function separates them so nand_base.c works as expected,
222 *especially its NAND_CMD_READID routines.
223 *
224 *To prevent stale data from being read, tmio_nand_hwcontrol() clears
225 *tmio->read_good.
226 */
227static u_char tmio_nand_read_byte(struct mtd_info *mtd)
228{
229 struct tmio_nand *tmio = mtd_to_tmio(mtd);
230 unsigned int data;
231
232 if (tmio->read_good--)
233 return tmio->read;
234
235 data = tmio_ioread16(tmio->fcr + FCR_DATA);
236 tmio->read = data >> 8;
237 return data;
238}
239
240/*
241 *The TMIO controller converts an 8-bit NAND interface to a 16-bit
242 *bus interface, so all data reads and writes must be 16-bit wide.
243 *Thus, we implement 16-bit versions of the read, write, and verify
244 *buffer functions.
245 */
246static void
247tmio_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
248{
249 struct tmio_nand *tmio = mtd_to_tmio(mtd);
250
251 tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
252}
253
254static void tmio_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
255{
256 struct tmio_nand *tmio = mtd_to_tmio(mtd);
257
258 tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
259}
260
261static void tmio_nand_enable_hwecc(struct mtd_info *mtd, int mode)
262{
263 struct tmio_nand *tmio = mtd_to_tmio(mtd);
264
265 tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE);
266 tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */
267 tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE);
268}
269
270static int tmio_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
271 u_char *ecc_code)
272{
273 struct tmio_nand *tmio = mtd_to_tmio(mtd);
274 unsigned int ecc;
275
276 tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE);
277
278 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
279 ecc_code[1] = ecc; /* 000-255 LP7-0 */
280 ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */
281 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
282 ecc_code[2] = ecc; /* 000-255 CP5-0,11b */
283 ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */
284 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
285 ecc_code[3] = ecc; /* 256-511 LP15-8 */
286 ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */
287
288 tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE);
289 return 0;
290}
291
292static int tmio_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
293 unsigned char *read_ecc, unsigned char *calc_ecc)
294{
295 int r0, r1;
296
297 /* assume ecc.size = 512 and ecc.bytes = 6 */
298 r0 = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
299 if (r0 < 0)
300 return r0;
301 r1 = __nand_correct_data(buf + 256, read_ecc + 3, calc_ecc + 3, 256);
302 if (r1 < 0)
303 return r1;
304 return r0 + r1;
305}
306
307static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio)
308{
309 const struct mfd_cell *cell = mfd_get_cell(dev);
310 int ret;
311
312 if (cell->enable) {
313 ret = cell->enable(dev);
314 if (ret)
315 return ret;
316 }
317
318 /* (4Ch) CLKRUN Enable 1st spcrunc */
319 tmio_iowrite8(0x81, tmio->ccr + CCR_ICC);
320
321 /* (10h)BaseAddress 0x1000 spba.spba2 */
322 tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE);
323 tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2);
324
325 /* (04h)Command Register I/O spcmd */
326 tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND);
327
328 /* (62h) Power Supply Control ssmpwc */
329 /* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */
330 tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC);
331
332 /* (63h) Detect Control ssmdtc */
333 tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC);
334
335 /* Interrupt status register clear sintst */
336 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
337
338 /* After power supply, Media are reset smode */
339 tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE);
340 tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE);
341 tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA);
342
343 /* Standby Mode smode */
344 tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE);
345
346 mdelay(5);
347
348 return 0;
349}
350
351static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio)
352{
353 const struct mfd_cell *cell = mfd_get_cell(dev);
354
355 tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE);
356 if (cell->disable)
357 cell->disable(dev);
358}
359
360static int tmio_probe(struct platform_device *dev)
361{
362 struct tmio_nand_data *data = dev_get_platdata(&dev->dev);
363 struct resource *fcr = platform_get_resource(dev,
364 IORESOURCE_MEM, 0);
365 struct resource *ccr = platform_get_resource(dev,
366 IORESOURCE_MEM, 1);
367 int irq = platform_get_irq(dev, 0);
368 struct tmio_nand *tmio;
369 struct mtd_info *mtd;
370 struct nand_chip *nand_chip;
371 int retval;
372
373 if (data == NULL)
374 dev_warn(&dev->dev, "NULL platform data!\n");
375
376 tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL);
377 if (!tmio)
378 return -ENOMEM;
379
380 tmio->dev = dev;
381
382 platform_set_drvdata(dev, tmio);
383 nand_chip = &tmio->chip;
384 mtd = nand_to_mtd(nand_chip);
385 mtd->name = "tmio-nand";
386 mtd->dev.parent = &dev->dev;
387
388 tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr));
389 if (!tmio->ccr)
390 return -EIO;
391
392 tmio->fcr_base = fcr->start & 0xfffff;
393 tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr));
394 if (!tmio->fcr)
395 return -EIO;
396
397 retval = tmio_hw_init(dev, tmio);
398 if (retval)
399 return retval;
400
401 /* Set address of NAND IO lines */
402 nand_chip->IO_ADDR_R = tmio->fcr;
403 nand_chip->IO_ADDR_W = tmio->fcr;
404
405 /* Set address of hardware control function */
406 nand_chip->cmd_ctrl = tmio_nand_hwcontrol;
407 nand_chip->dev_ready = tmio_nand_dev_ready;
408 nand_chip->read_byte = tmio_nand_read_byte;
409 nand_chip->write_buf = tmio_nand_write_buf;
410 nand_chip->read_buf = tmio_nand_read_buf;
411
412 /* set eccmode using hardware ECC */
413 nand_chip->ecc.mode = NAND_ECC_HW;
414 nand_chip->ecc.size = 512;
415 nand_chip->ecc.bytes = 6;
416 nand_chip->ecc.strength = 2;
417 nand_chip->ecc.hwctl = tmio_nand_enable_hwecc;
418 nand_chip->ecc.calculate = tmio_nand_calculate_ecc;
419 nand_chip->ecc.correct = tmio_nand_correct_data;
420
421 if (data)
422 nand_chip->badblock_pattern = data->badblock_pattern;
423
424 /* 15 us command delay time */
425 nand_chip->chip_delay = 15;
426
427 retval = devm_request_irq(&dev->dev, irq, &tmio_irq, 0,
428 dev_name(&dev->dev), tmio);
429 if (retval) {
430 dev_err(&dev->dev, "request_irq error %d\n", retval);
431 goto err_irq;
432 }
433
434 tmio->irq = irq;
435 nand_chip->waitfunc = tmio_nand_wait;
436
437 /* Scan to find existence of the device */
438 retval = nand_scan(mtd, 1);
439 if (retval)
440 goto err_irq;
441
442 /* Register the partitions */
443 retval = mtd_device_parse_register(mtd, NULL, NULL,
444 data ? data->partition : NULL,
445 data ? data->num_partitions : 0);
446 if (!retval)
447 return retval;
448
449 nand_release(mtd);
450
451err_irq:
452 tmio_hw_stop(dev, tmio);
453 return retval;
454}
455
456static int tmio_remove(struct platform_device *dev)
457{
458 struct tmio_nand *tmio = platform_get_drvdata(dev);
459
460 nand_release(nand_to_mtd(&tmio->chip));
461 tmio_hw_stop(dev, tmio);
462 return 0;
463}
464
465#ifdef CONFIG_PM
466static int tmio_suspend(struct platform_device *dev, pm_message_t state)
467{
468 const struct mfd_cell *cell = mfd_get_cell(dev);
469
470 if (cell->suspend)
471 cell->suspend(dev);
472
473 tmio_hw_stop(dev, platform_get_drvdata(dev));
474 return 0;
475}
476
477static int tmio_resume(struct platform_device *dev)
478{
479 const struct mfd_cell *cell = mfd_get_cell(dev);
480
481 /* FIXME - is this required or merely another attack of the broken
482 * SHARP platform? Looks suspicious.
483 */
484 tmio_hw_init(dev, platform_get_drvdata(dev));
485
486 if (cell->resume)
487 cell->resume(dev);
488
489 return 0;
490}
491#else
492#define tmio_suspend NULL
493#define tmio_resume NULL
494#endif
495
496static struct platform_driver tmio_driver = {
497 .driver.name = "tmio-nand",
498 .driver.owner = THIS_MODULE,
499 .probe = tmio_probe,
500 .remove = tmio_remove,
501 .suspend = tmio_suspend,
502 .resume = tmio_resume,
503};
504
505module_platform_driver(tmio_driver);
506
507MODULE_LICENSE("GPL v2");
508MODULE_AUTHOR("Ian Molton, Dirk Opfer, Chris Humbert, Dmitry Baryshkov");
509MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller");
510MODULE_ALIAS("platform:tmio-nand");