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1/*
2 * Copyright 2004-2008 Freescale Semiconductor, Inc.
3 * Copyright 2009 Semihalf.
4 *
5 * Approved as OSADL project by a majority of OSADL members and funded
6 * by OSADL membership fees in 2009; for details see www.osadl.org.
7 *
8 * Based on original driver from Freescale Semiconductor
9 * written by John Rigby <jrigby@freescale.com> on basis
10 * of drivers/mtd/nand/mxc_nand.c. Reworked and extended
11 * Piotr Ziecik <kosmo@semihalf.com>.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
25 * MA 02110-1301, USA.
26 */
27
28#include <linux/module.h>
29#include <linux/clk.h>
30#include <linux/gfp.h>
31#include <linux/delay.h>
32#include <linux/err.h>
33#include <linux/interrupt.h>
34#include <linux/io.h>
35#include <linux/mtd/mtd.h>
36#include <linux/mtd/nand.h>
37#include <linux/mtd/partitions.h>
38#include <linux/of_address.h>
39#include <linux/of_device.h>
40#include <linux/of_irq.h>
41#include <linux/of_platform.h>
42
43#include <asm/mpc5121.h>
44
45/* Addresses for NFC MAIN RAM BUFFER areas */
46#define NFC_MAIN_AREA(n) ((n) * 0x200)
47
48/* Addresses for NFC SPARE BUFFER areas */
49#define NFC_SPARE_BUFFERS 8
50#define NFC_SPARE_LEN 0x40
51#define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN))
52
53/* MPC5121 NFC registers */
54#define NFC_BUF_ADDR 0x1E04
55#define NFC_FLASH_ADDR 0x1E06
56#define NFC_FLASH_CMD 0x1E08
57#define NFC_CONFIG 0x1E0A
58#define NFC_ECC_STATUS1 0x1E0C
59#define NFC_ECC_STATUS2 0x1E0E
60#define NFC_SPAS 0x1E10
61#define NFC_WRPROT 0x1E12
62#define NFC_NF_WRPRST 0x1E18
63#define NFC_CONFIG1 0x1E1A
64#define NFC_CONFIG2 0x1E1C
65#define NFC_UNLOCKSTART_BLK0 0x1E20
66#define NFC_UNLOCKEND_BLK0 0x1E22
67#define NFC_UNLOCKSTART_BLK1 0x1E24
68#define NFC_UNLOCKEND_BLK1 0x1E26
69#define NFC_UNLOCKSTART_BLK2 0x1E28
70#define NFC_UNLOCKEND_BLK2 0x1E2A
71#define NFC_UNLOCKSTART_BLK3 0x1E2C
72#define NFC_UNLOCKEND_BLK3 0x1E2E
73
74/* Bit Definitions: NFC_BUF_ADDR */
75#define NFC_RBA_MASK (7 << 0)
76#define NFC_ACTIVE_CS_SHIFT 5
77#define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT)
78
79/* Bit Definitions: NFC_CONFIG */
80#define NFC_BLS_UNLOCKED (1 << 1)
81
82/* Bit Definitions: NFC_CONFIG1 */
83#define NFC_ECC_4BIT (1 << 0)
84#define NFC_FULL_PAGE_DMA (1 << 1)
85#define NFC_SPARE_ONLY (1 << 2)
86#define NFC_ECC_ENABLE (1 << 3)
87#define NFC_INT_MASK (1 << 4)
88#define NFC_BIG_ENDIAN (1 << 5)
89#define NFC_RESET (1 << 6)
90#define NFC_CE (1 << 7)
91#define NFC_ONE_CYCLE (1 << 8)
92#define NFC_PPB_32 (0 << 9)
93#define NFC_PPB_64 (1 << 9)
94#define NFC_PPB_128 (2 << 9)
95#define NFC_PPB_256 (3 << 9)
96#define NFC_PPB_MASK (3 << 9)
97#define NFC_FULL_PAGE_INT (1 << 11)
98
99/* Bit Definitions: NFC_CONFIG2 */
100#define NFC_COMMAND (1 << 0)
101#define NFC_ADDRESS (1 << 1)
102#define NFC_INPUT (1 << 2)
103#define NFC_OUTPUT (1 << 3)
104#define NFC_ID (1 << 4)
105#define NFC_STATUS (1 << 5)
106#define NFC_CMD_FAIL (1 << 15)
107#define NFC_INT (1 << 15)
108
109/* Bit Definitions: NFC_WRPROT */
110#define NFC_WPC_LOCK_TIGHT (1 << 0)
111#define NFC_WPC_LOCK (1 << 1)
112#define NFC_WPC_UNLOCK (1 << 2)
113
114#define DRV_NAME "mpc5121_nfc"
115
116/* Timeouts */
117#define NFC_RESET_TIMEOUT 1000 /* 1 ms */
118#define NFC_TIMEOUT (HZ / 10) /* 1/10 s */
119
120struct mpc5121_nfc_prv {
121 struct nand_chip chip;
122 int irq;
123 void __iomem *regs;
124 struct clk *clk;
125 wait_queue_head_t irq_waitq;
126 uint column;
127 int spareonly;
128 void __iomem *csreg;
129 struct device *dev;
130};
131
132static void mpc5121_nfc_done(struct mtd_info *mtd);
133
134/* Read NFC register */
135static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
136{
137 struct nand_chip *chip = mtd_to_nand(mtd);
138 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
139
140 return in_be16(prv->regs + reg);
141}
142
143/* Write NFC register */
144static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
145{
146 struct nand_chip *chip = mtd_to_nand(mtd);
147 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
148
149 out_be16(prv->regs + reg, val);
150}
151
152/* Set bits in NFC register */
153static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
154{
155 nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
156}
157
158/* Clear bits in NFC register */
159static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
160{
161 nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
162}
163
164/* Invoke address cycle */
165static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
166{
167 nfc_write(mtd, NFC_FLASH_ADDR, addr);
168 nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
169 mpc5121_nfc_done(mtd);
170}
171
172/* Invoke command cycle */
173static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
174{
175 nfc_write(mtd, NFC_FLASH_CMD, cmd);
176 nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
177 mpc5121_nfc_done(mtd);
178}
179
180/* Send data from NFC buffers to NAND flash */
181static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
182{
183 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
184 nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
185 mpc5121_nfc_done(mtd);
186}
187
188/* Receive data from NAND flash */
189static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
190{
191 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
192 nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
193 mpc5121_nfc_done(mtd);
194}
195
196/* Receive ID from NAND flash */
197static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
198{
199 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
200 nfc_write(mtd, NFC_CONFIG2, NFC_ID);
201 mpc5121_nfc_done(mtd);
202}
203
204/* Receive status from NAND flash */
205static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
206{
207 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
208 nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
209 mpc5121_nfc_done(mtd);
210}
211
212/* NFC interrupt handler */
213static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
214{
215 struct mtd_info *mtd = data;
216 struct nand_chip *chip = mtd_to_nand(mtd);
217 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
218
219 nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
220 wake_up(&prv->irq_waitq);
221
222 return IRQ_HANDLED;
223}
224
225/* Wait for operation complete */
226static void mpc5121_nfc_done(struct mtd_info *mtd)
227{
228 struct nand_chip *chip = mtd_to_nand(mtd);
229 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
230 int rv;
231
232 if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
233 nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
234 rv = wait_event_timeout(prv->irq_waitq,
235 (nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT);
236
237 if (!rv)
238 dev_warn(prv->dev,
239 "Timeout while waiting for interrupt.\n");
240 }
241
242 nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
243}
244
245/* Do address cycle(s) */
246static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
247{
248 struct nand_chip *chip = mtd_to_nand(mtd);
249 u32 pagemask = chip->pagemask;
250
251 if (column != -1) {
252 mpc5121_nfc_send_addr(mtd, column);
253 if (mtd->writesize > 512)
254 mpc5121_nfc_send_addr(mtd, column >> 8);
255 }
256
257 if (page != -1) {
258 do {
259 mpc5121_nfc_send_addr(mtd, page & 0xFF);
260 page >>= 8;
261 pagemask >>= 8;
262 } while (pagemask);
263 }
264}
265
266/* Control chip select signals */
267static void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
268{
269 if (chip < 0) {
270 nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
271 return;
272 }
273
274 nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
275 nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
276 NFC_ACTIVE_CS_MASK);
277 nfc_set(mtd, NFC_CONFIG1, NFC_CE);
278}
279
280/* Init external chip select logic on ADS5121 board */
281static int ads5121_chipselect_init(struct mtd_info *mtd)
282{
283 struct nand_chip *chip = mtd_to_nand(mtd);
284 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
285 struct device_node *dn;
286
287 dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
288 if (dn) {
289 prv->csreg = of_iomap(dn, 0);
290 of_node_put(dn);
291 if (!prv->csreg)
292 return -ENOMEM;
293
294 /* CPLD Register 9 controls NAND /CE Lines */
295 prv->csreg += 9;
296 return 0;
297 }
298
299 return -EINVAL;
300}
301
302/* Control chips select signal on ADS5121 board */
303static void ads5121_select_chip(struct mtd_info *mtd, int chip)
304{
305 struct nand_chip *nand = mtd_to_nand(mtd);
306 struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
307 u8 v;
308
309 v = in_8(prv->csreg);
310 v |= 0x0F;
311
312 if (chip >= 0) {
313 mpc5121_nfc_select_chip(mtd, 0);
314 v &= ~(1 << chip);
315 } else
316 mpc5121_nfc_select_chip(mtd, -1);
317
318 out_8(prv->csreg, v);
319}
320
321/* Read NAND Ready/Busy signal */
322static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
323{
324 /*
325 * NFC handles ready/busy signal internally. Therefore, this function
326 * always returns status as ready.
327 */
328 return 1;
329}
330
331/* Write command to NAND flash */
332static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
333 int column, int page)
334{
335 struct nand_chip *chip = mtd_to_nand(mtd);
336 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
337
338 prv->column = (column >= 0) ? column : 0;
339 prv->spareonly = 0;
340
341 switch (command) {
342 case NAND_CMD_PAGEPROG:
343 mpc5121_nfc_send_prog_page(mtd);
344 break;
345 /*
346 * NFC does not support sub-page reads and writes,
347 * so emulate them using full page transfers.
348 */
349 case NAND_CMD_READ0:
350 column = 0;
351 break;
352
353 case NAND_CMD_READ1:
354 prv->column += 256;
355 command = NAND_CMD_READ0;
356 column = 0;
357 break;
358
359 case NAND_CMD_READOOB:
360 prv->spareonly = 1;
361 command = NAND_CMD_READ0;
362 column = 0;
363 break;
364
365 case NAND_CMD_SEQIN:
366 mpc5121_nfc_command(mtd, NAND_CMD_READ0, column, page);
367 column = 0;
368 break;
369
370 case NAND_CMD_ERASE1:
371 case NAND_CMD_ERASE2:
372 case NAND_CMD_READID:
373 case NAND_CMD_STATUS:
374 break;
375
376 default:
377 return;
378 }
379
380 mpc5121_nfc_send_cmd(mtd, command);
381 mpc5121_nfc_addr_cycle(mtd, column, page);
382
383 switch (command) {
384 case NAND_CMD_READ0:
385 if (mtd->writesize > 512)
386 mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
387 mpc5121_nfc_send_read_page(mtd);
388 break;
389
390 case NAND_CMD_READID:
391 mpc5121_nfc_send_read_id(mtd);
392 break;
393
394 case NAND_CMD_STATUS:
395 mpc5121_nfc_send_read_status(mtd);
396 if (chip->options & NAND_BUSWIDTH_16)
397 prv->column = 1;
398 else
399 prv->column = 0;
400 break;
401 }
402}
403
404/* Copy data from/to NFC spare buffers. */
405static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
406 u8 *buffer, uint size, int wr)
407{
408 struct nand_chip *nand = mtd_to_nand(mtd);
409 struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
410 uint o, s, sbsize, blksize;
411
412 /*
413 * NAND spare area is available through NFC spare buffers.
414 * The NFC divides spare area into (page_size / 512) chunks.
415 * Each chunk is placed into separate spare memory area, using
416 * first (spare_size / num_of_chunks) bytes of the buffer.
417 *
418 * For NAND device in which the spare area is not divided fully
419 * by the number of chunks, number of used bytes in each spare
420 * buffer is rounded down to the nearest even number of bytes,
421 * and all remaining bytes are added to the last used spare area.
422 *
423 * For more information read section 26.6.10 of MPC5121e
424 * Microcontroller Reference Manual, Rev. 3.
425 */
426
427 /* Calculate number of valid bytes in each spare buffer */
428 sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
429
430 while (size) {
431 /* Calculate spare buffer number */
432 s = offset / sbsize;
433 if (s > NFC_SPARE_BUFFERS - 1)
434 s = NFC_SPARE_BUFFERS - 1;
435
436 /*
437 * Calculate offset to requested data block in selected spare
438 * buffer and its size.
439 */
440 o = offset - (s * sbsize);
441 blksize = min(sbsize - o, size);
442
443 if (wr)
444 memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
445 buffer, blksize);
446 else
447 memcpy_fromio(buffer,
448 prv->regs + NFC_SPARE_AREA(s) + o, blksize);
449
450 buffer += blksize;
451 offset += blksize;
452 size -= blksize;
453 };
454}
455
456/* Copy data from/to NFC main and spare buffers */
457static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
458 int wr)
459{
460 struct nand_chip *chip = mtd_to_nand(mtd);
461 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
462 uint c = prv->column;
463 uint l;
464
465 /* Handle spare area access */
466 if (prv->spareonly || c >= mtd->writesize) {
467 /* Calculate offset from beginning of spare area */
468 if (c >= mtd->writesize)
469 c -= mtd->writesize;
470
471 prv->column += len;
472 mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
473 return;
474 }
475
476 /*
477 * Handle main area access - limit copy length to prevent
478 * crossing main/spare boundary.
479 */
480 l = min((uint)len, mtd->writesize - c);
481 prv->column += l;
482
483 if (wr)
484 memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
485 else
486 memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
487
488 /* Handle crossing main/spare boundary */
489 if (l != len) {
490 buf += l;
491 len -= l;
492 mpc5121_nfc_buf_copy(mtd, buf, len, wr);
493 }
494}
495
496/* Read data from NFC buffers */
497static void mpc5121_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
498{
499 mpc5121_nfc_buf_copy(mtd, buf, len, 0);
500}
501
502/* Write data to NFC buffers */
503static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
504 const u_char *buf, int len)
505{
506 mpc5121_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
507}
508
509/* Read byte from NFC buffers */
510static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
511{
512 u8 tmp;
513
514 mpc5121_nfc_read_buf(mtd, &tmp, sizeof(tmp));
515
516 return tmp;
517}
518
519/* Read word from NFC buffers */
520static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
521{
522 u16 tmp;
523
524 mpc5121_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
525
526 return tmp;
527}
528
529/*
530 * Read NFC configuration from Reset Config Word
531 *
532 * NFC is configured during reset in basis of information stored
533 * in Reset Config Word. There is no other way to set NAND block
534 * size, spare size and bus width.
535 */
536static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
537{
538 struct nand_chip *chip = mtd_to_nand(mtd);
539 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
540 struct mpc512x_reset_module *rm;
541 struct device_node *rmnode;
542 uint rcw_pagesize = 0;
543 uint rcw_sparesize = 0;
544 uint rcw_width;
545 uint rcwh;
546 uint romloc, ps;
547 int ret = 0;
548
549 rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
550 if (!rmnode) {
551 dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' "
552 "node in device tree!\n");
553 return -ENODEV;
554 }
555
556 rm = of_iomap(rmnode, 0);
557 if (!rm) {
558 dev_err(prv->dev, "Error mapping reset module node!\n");
559 ret = -EBUSY;
560 goto out;
561 }
562
563 rcwh = in_be32(&rm->rcwhr);
564
565 /* Bit 6: NFC bus width */
566 rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
567
568 /* Bit 7: NFC Page/Spare size */
569 ps = (rcwh >> 7) & 0x1;
570
571 /* Bits [22:21]: ROM Location */
572 romloc = (rcwh >> 21) & 0x3;
573
574 /* Decode RCW bits */
575 switch ((ps << 2) | romloc) {
576 case 0x00:
577 case 0x01:
578 rcw_pagesize = 512;
579 rcw_sparesize = 16;
580 break;
581 case 0x02:
582 case 0x03:
583 rcw_pagesize = 4096;
584 rcw_sparesize = 128;
585 break;
586 case 0x04:
587 case 0x05:
588 rcw_pagesize = 2048;
589 rcw_sparesize = 64;
590 break;
591 case 0x06:
592 case 0x07:
593 rcw_pagesize = 4096;
594 rcw_sparesize = 218;
595 break;
596 }
597
598 mtd->writesize = rcw_pagesize;
599 mtd->oobsize = rcw_sparesize;
600 if (rcw_width == 2)
601 chip->options |= NAND_BUSWIDTH_16;
602
603 dev_notice(prv->dev, "Configured for "
604 "%u-bit NAND, page size %u "
605 "with %u spare.\n",
606 rcw_width * 8, rcw_pagesize,
607 rcw_sparesize);
608 iounmap(rm);
609out:
610 of_node_put(rmnode);
611 return ret;
612}
613
614/* Free driver resources */
615static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
616{
617 struct nand_chip *chip = mtd_to_nand(mtd);
618 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
619
620 if (prv->clk)
621 clk_disable_unprepare(prv->clk);
622
623 if (prv->csreg)
624 iounmap(prv->csreg);
625}
626
627static int mpc5121_nfc_probe(struct platform_device *op)
628{
629 struct device_node *dn = op->dev.of_node;
630 struct clk *clk;
631 struct device *dev = &op->dev;
632 struct mpc5121_nfc_prv *prv;
633 struct resource res;
634 struct mtd_info *mtd;
635 struct nand_chip *chip;
636 unsigned long regs_paddr, regs_size;
637 const __be32 *chips_no;
638 int resettime = 0;
639 int retval = 0;
640 int rev, len;
641
642 /*
643 * Check SoC revision. This driver supports only NFC
644 * in MPC5121 revision 2 and MPC5123 revision 3.
645 */
646 rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
647 if ((rev != 2) && (rev != 3)) {
648 dev_err(dev, "SoC revision %u is not supported!\n", rev);
649 return -ENXIO;
650 }
651
652 prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
653 if (!prv)
654 return -ENOMEM;
655
656 chip = &prv->chip;
657 mtd = nand_to_mtd(chip);
658
659 mtd->dev.parent = dev;
660 nand_set_controller_data(chip, prv);
661 nand_set_flash_node(chip, dn);
662 prv->dev = dev;
663
664 /* Read NFC configuration from Reset Config Word */
665 retval = mpc5121_nfc_read_hw_config(mtd);
666 if (retval) {
667 dev_err(dev, "Unable to read NFC config!\n");
668 return retval;
669 }
670
671 prv->irq = irq_of_parse_and_map(dn, 0);
672 if (prv->irq == NO_IRQ) {
673 dev_err(dev, "Error mapping IRQ!\n");
674 return -EINVAL;
675 }
676
677 retval = of_address_to_resource(dn, 0, &res);
678 if (retval) {
679 dev_err(dev, "Error parsing memory region!\n");
680 return retval;
681 }
682
683 chips_no = of_get_property(dn, "chips", &len);
684 if (!chips_no || len != sizeof(*chips_no)) {
685 dev_err(dev, "Invalid/missing 'chips' property!\n");
686 return -EINVAL;
687 }
688
689 regs_paddr = res.start;
690 regs_size = resource_size(&res);
691
692 if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
693 dev_err(dev, "Error requesting memory region!\n");
694 return -EBUSY;
695 }
696
697 prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
698 if (!prv->regs) {
699 dev_err(dev, "Error mapping memory region!\n");
700 return -ENOMEM;
701 }
702
703 mtd->name = "MPC5121 NAND";
704 chip->dev_ready = mpc5121_nfc_dev_ready;
705 chip->cmdfunc = mpc5121_nfc_command;
706 chip->read_byte = mpc5121_nfc_read_byte;
707 chip->read_word = mpc5121_nfc_read_word;
708 chip->read_buf = mpc5121_nfc_read_buf;
709 chip->write_buf = mpc5121_nfc_write_buf;
710 chip->select_chip = mpc5121_nfc_select_chip;
711 chip->bbt_options = NAND_BBT_USE_FLASH;
712 chip->ecc.mode = NAND_ECC_SOFT;
713 chip->ecc.algo = NAND_ECC_HAMMING;
714
715 /* Support external chip-select logic on ADS5121 board */
716 if (of_machine_is_compatible("fsl,mpc5121ads")) {
717 retval = ads5121_chipselect_init(mtd);
718 if (retval) {
719 dev_err(dev, "Chipselect init error!\n");
720 return retval;
721 }
722
723 chip->select_chip = ads5121_select_chip;
724 }
725
726 /* Enable NFC clock */
727 clk = devm_clk_get(dev, "ipg");
728 if (IS_ERR(clk)) {
729 dev_err(dev, "Unable to acquire NFC clock!\n");
730 retval = PTR_ERR(clk);
731 goto error;
732 }
733 retval = clk_prepare_enable(clk);
734 if (retval) {
735 dev_err(dev, "Unable to enable NFC clock!\n");
736 goto error;
737 }
738 prv->clk = clk;
739
740 /* Reset NAND Flash controller */
741 nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
742 while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
743 if (resettime++ >= NFC_RESET_TIMEOUT) {
744 dev_err(dev, "Timeout while resetting NFC!\n");
745 retval = -EINVAL;
746 goto error;
747 }
748
749 udelay(1);
750 }
751
752 /* Enable write to NFC memory */
753 nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
754
755 /* Enable write to all NAND pages */
756 nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
757 nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
758 nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
759
760 /*
761 * Setup NFC:
762 * - Big Endian transfers,
763 * - Interrupt after full page read/write.
764 */
765 nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
766 NFC_FULL_PAGE_INT);
767
768 /* Set spare area size */
769 nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
770
771 init_waitqueue_head(&prv->irq_waitq);
772 retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME,
773 mtd);
774 if (retval) {
775 dev_err(dev, "Error requesting IRQ!\n");
776 goto error;
777 }
778
779 /* Detect NAND chips */
780 retval = nand_scan(mtd, be32_to_cpup(chips_no));
781 if (retval) {
782 dev_err(dev, "NAND Flash not found !\n");
783 goto error;
784 }
785
786 /* Set erase block size */
787 switch (mtd->erasesize / mtd->writesize) {
788 case 32:
789 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
790 break;
791
792 case 64:
793 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
794 break;
795
796 case 128:
797 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
798 break;
799
800 case 256:
801 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
802 break;
803
804 default:
805 dev_err(dev, "Unsupported NAND flash!\n");
806 retval = -ENXIO;
807 goto error;
808 }
809
810 dev_set_drvdata(dev, mtd);
811
812 /* Register device in MTD */
813 retval = mtd_device_register(mtd, NULL, 0);
814 if (retval) {
815 dev_err(dev, "Error adding MTD device!\n");
816 goto error;
817 }
818
819 return 0;
820error:
821 mpc5121_nfc_free(dev, mtd);
822 return retval;
823}
824
825static int mpc5121_nfc_remove(struct platform_device *op)
826{
827 struct device *dev = &op->dev;
828 struct mtd_info *mtd = dev_get_drvdata(dev);
829
830 nand_release(mtd);
831 mpc5121_nfc_free(dev, mtd);
832
833 return 0;
834}
835
836static const struct of_device_id mpc5121_nfc_match[] = {
837 { .compatible = "fsl,mpc5121-nfc", },
838 {},
839};
840MODULE_DEVICE_TABLE(of, mpc5121_nfc_match);
841
842static struct platform_driver mpc5121_nfc_driver = {
843 .probe = mpc5121_nfc_probe,
844 .remove = mpc5121_nfc_remove,
845 .driver = {
846 .name = DRV_NAME,
847 .of_match_table = mpc5121_nfc_match,
848 },
849};
850
851module_platform_driver(mpc5121_nfc_driver);
852
853MODULE_AUTHOR("Freescale Semiconductor, Inc.");
854MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
855MODULE_LICENSE("GPL");