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1/*
2 * Hisilicon NAND Flash controller driver
3 *
4 * Copyright © 2012-2014 HiSilicon Technologies Co., Ltd.
5 * http://www.hisilicon.com
6 *
7 * Author: Zhou Wang <wangzhou.bry@gmail.com>
8 * The initial developer of the original code is Zhiyong Cai
9 * <caizhiyong@huawei.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21#include <linux/of.h>
22#include <linux/mtd/mtd.h>
23#include <linux/sizes.h>
24#include <linux/clk.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <linux/delay.h>
28#include <linux/interrupt.h>
29#include <linux/mtd/nand.h>
30#include <linux/dma-mapping.h>
31#include <linux/platform_device.h>
32#include <linux/mtd/partitions.h>
33
34#define HINFC504_MAX_CHIP (4)
35#define HINFC504_W_LATCH (5)
36#define HINFC504_R_LATCH (7)
37#define HINFC504_RW_LATCH (3)
38
39#define HINFC504_NFC_TIMEOUT (2 * HZ)
40#define HINFC504_NFC_PM_TIMEOUT (1 * HZ)
41#define HINFC504_NFC_DMA_TIMEOUT (5 * HZ)
42#define HINFC504_CHIP_DELAY (25)
43
44#define HINFC504_REG_BASE_ADDRESS_LEN (0x100)
45#define HINFC504_BUFFER_BASE_ADDRESS_LEN (2048 + 128)
46
47#define HINFC504_ADDR_CYCLE_MASK 0x4
48
49#define HINFC504_CON 0x00
50#define HINFC504_CON_OP_MODE_NORMAL BIT(0)
51#define HINFC504_CON_PAGEISZE_SHIFT (1)
52#define HINFC504_CON_PAGESIZE_MASK (0x07)
53#define HINFC504_CON_BUS_WIDTH BIT(4)
54#define HINFC504_CON_READY_BUSY_SEL BIT(8)
55#define HINFC504_CON_ECCTYPE_SHIFT (9)
56#define HINFC504_CON_ECCTYPE_MASK (0x07)
57
58#define HINFC504_PWIDTH 0x04
59#define SET_HINFC504_PWIDTH(_w_lcnt, _r_lcnt, _rw_hcnt) \
60 ((_w_lcnt) | (((_r_lcnt) & 0x0F) << 4) | (((_rw_hcnt) & 0x0F) << 8))
61
62#define HINFC504_CMD 0x0C
63#define HINFC504_ADDRL 0x10
64#define HINFC504_ADDRH 0x14
65#define HINFC504_DATA_NUM 0x18
66
67#define HINFC504_OP 0x1C
68#define HINFC504_OP_READ_DATA_EN BIT(1)
69#define HINFC504_OP_WAIT_READY_EN BIT(2)
70#define HINFC504_OP_CMD2_EN BIT(3)
71#define HINFC504_OP_WRITE_DATA_EN BIT(4)
72#define HINFC504_OP_ADDR_EN BIT(5)
73#define HINFC504_OP_CMD1_EN BIT(6)
74#define HINFC504_OP_NF_CS_SHIFT (7)
75#define HINFC504_OP_NF_CS_MASK (3)
76#define HINFC504_OP_ADDR_CYCLE_SHIFT (9)
77#define HINFC504_OP_ADDR_CYCLE_MASK (7)
78
79#define HINFC504_STATUS 0x20
80#define HINFC504_READY BIT(0)
81
82#define HINFC504_INTEN 0x24
83#define HINFC504_INTEN_DMA BIT(9)
84#define HINFC504_INTEN_UE BIT(6)
85#define HINFC504_INTEN_CE BIT(5)
86
87#define HINFC504_INTS 0x28
88#define HINFC504_INTS_DMA BIT(9)
89#define HINFC504_INTS_UE BIT(6)
90#define HINFC504_INTS_CE BIT(5)
91
92#define HINFC504_INTCLR 0x2C
93#define HINFC504_INTCLR_DMA BIT(9)
94#define HINFC504_INTCLR_UE BIT(6)
95#define HINFC504_INTCLR_CE BIT(5)
96
97#define HINFC504_ECC_STATUS 0x5C
98#define HINFC504_ECC_16_BIT_SHIFT 12
99
100#define HINFC504_DMA_CTRL 0x60
101#define HINFC504_DMA_CTRL_DMA_START BIT(0)
102#define HINFC504_DMA_CTRL_WE BIT(1)
103#define HINFC504_DMA_CTRL_DATA_AREA_EN BIT(2)
104#define HINFC504_DMA_CTRL_OOB_AREA_EN BIT(3)
105#define HINFC504_DMA_CTRL_BURST4_EN BIT(4)
106#define HINFC504_DMA_CTRL_BURST8_EN BIT(5)
107#define HINFC504_DMA_CTRL_BURST16_EN BIT(6)
108#define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT (7)
109#define HINFC504_DMA_CTRL_ADDR_NUM_MASK (1)
110#define HINFC504_DMA_CTRL_CS_SHIFT (8)
111#define HINFC504_DMA_CTRL_CS_MASK (0x03)
112
113#define HINFC504_DMA_ADDR_DATA 0x64
114#define HINFC504_DMA_ADDR_OOB 0x68
115
116#define HINFC504_DMA_LEN 0x6C
117#define HINFC504_DMA_LEN_OOB_SHIFT (16)
118#define HINFC504_DMA_LEN_OOB_MASK (0xFFF)
119
120#define HINFC504_DMA_PARA 0x70
121#define HINFC504_DMA_PARA_DATA_RW_EN BIT(0)
122#define HINFC504_DMA_PARA_OOB_RW_EN BIT(1)
123#define HINFC504_DMA_PARA_DATA_EDC_EN BIT(2)
124#define HINFC504_DMA_PARA_OOB_EDC_EN BIT(3)
125#define HINFC504_DMA_PARA_DATA_ECC_EN BIT(4)
126#define HINFC504_DMA_PARA_OOB_ECC_EN BIT(5)
127
128#define HINFC_VERSION 0x74
129#define HINFC504_LOG_READ_ADDR 0x7C
130#define HINFC504_LOG_READ_LEN 0x80
131
132#define HINFC504_NANDINFO_LEN 0x10
133
134struct hinfc_host {
135 struct nand_chip chip;
136 struct device *dev;
137 void __iomem *iobase;
138 void __iomem *mmio;
139 struct completion cmd_complete;
140 unsigned int offset;
141 unsigned int command;
142 int chipselect;
143 unsigned int addr_cycle;
144 u32 addr_value[2];
145 u32 cache_addr_value[2];
146 char *buffer;
147 dma_addr_t dma_buffer;
148 dma_addr_t dma_oob;
149 int version;
150 unsigned int irq_status; /* interrupt status */
151};
152
153static inline unsigned int hinfc_read(struct hinfc_host *host, unsigned int reg)
154{
155 return readl(host->iobase + reg);
156}
157
158static inline void hinfc_write(struct hinfc_host *host, unsigned int value,
159 unsigned int reg)
160{
161 writel(value, host->iobase + reg);
162}
163
164static void wait_controller_finished(struct hinfc_host *host)
165{
166 unsigned long timeout = jiffies + HINFC504_NFC_TIMEOUT;
167 int val;
168
169 while (time_before(jiffies, timeout)) {
170 val = hinfc_read(host, HINFC504_STATUS);
171 if (host->command == NAND_CMD_ERASE2) {
172 /* nfc is ready */
173 while (!(val & HINFC504_READY)) {
174 usleep_range(500, 1000);
175 val = hinfc_read(host, HINFC504_STATUS);
176 }
177 return;
178 }
179
180 if (val & HINFC504_READY)
181 return;
182 }
183
184 /* wait cmd timeout */
185 dev_err(host->dev, "Wait NAND controller exec cmd timeout.\n");
186}
187
188static void hisi_nfc_dma_transfer(struct hinfc_host *host, int todev)
189{
190 struct nand_chip *chip = &host->chip;
191 struct mtd_info *mtd = nand_to_mtd(chip);
192 unsigned long val;
193 int ret;
194
195 hinfc_write(host, host->dma_buffer, HINFC504_DMA_ADDR_DATA);
196 hinfc_write(host, host->dma_oob, HINFC504_DMA_ADDR_OOB);
197
198 if (chip->ecc.mode == NAND_ECC_NONE) {
199 hinfc_write(host, ((mtd->oobsize & HINFC504_DMA_LEN_OOB_MASK)
200 << HINFC504_DMA_LEN_OOB_SHIFT), HINFC504_DMA_LEN);
201
202 hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
203 | HINFC504_DMA_PARA_OOB_RW_EN, HINFC504_DMA_PARA);
204 } else {
205 if (host->command == NAND_CMD_READOOB)
206 hinfc_write(host, HINFC504_DMA_PARA_OOB_RW_EN
207 | HINFC504_DMA_PARA_OOB_EDC_EN
208 | HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
209 else
210 hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
211 | HINFC504_DMA_PARA_OOB_RW_EN
212 | HINFC504_DMA_PARA_DATA_EDC_EN
213 | HINFC504_DMA_PARA_OOB_EDC_EN
214 | HINFC504_DMA_PARA_DATA_ECC_EN
215 | HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
216
217 }
218
219 val = (HINFC504_DMA_CTRL_DMA_START | HINFC504_DMA_CTRL_BURST4_EN
220 | HINFC504_DMA_CTRL_BURST8_EN | HINFC504_DMA_CTRL_BURST16_EN
221 | HINFC504_DMA_CTRL_DATA_AREA_EN | HINFC504_DMA_CTRL_OOB_AREA_EN
222 | ((host->addr_cycle == 4 ? 1 : 0)
223 << HINFC504_DMA_CTRL_ADDR_NUM_SHIFT)
224 | ((host->chipselect & HINFC504_DMA_CTRL_CS_MASK)
225 << HINFC504_DMA_CTRL_CS_SHIFT));
226
227 if (todev)
228 val |= HINFC504_DMA_CTRL_WE;
229
230 init_completion(&host->cmd_complete);
231
232 hinfc_write(host, val, HINFC504_DMA_CTRL);
233 ret = wait_for_completion_timeout(&host->cmd_complete,
234 HINFC504_NFC_DMA_TIMEOUT);
235
236 if (!ret) {
237 dev_err(host->dev, "DMA operation(irq) timeout!\n");
238 /* sanity check */
239 val = hinfc_read(host, HINFC504_DMA_CTRL);
240 if (!(val & HINFC504_DMA_CTRL_DMA_START))
241 dev_err(host->dev, "DMA is already done but without irq ACK!\n");
242 else
243 dev_err(host->dev, "DMA is really timeout!\n");
244 }
245}
246
247static int hisi_nfc_send_cmd_pageprog(struct hinfc_host *host)
248{
249 host->addr_value[0] &= 0xffff0000;
250
251 hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
252 hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
253 hinfc_write(host, NAND_CMD_PAGEPROG << 8 | NAND_CMD_SEQIN,
254 HINFC504_CMD);
255
256 hisi_nfc_dma_transfer(host, 1);
257
258 return 0;
259}
260
261static int hisi_nfc_send_cmd_readstart(struct hinfc_host *host)
262{
263 struct mtd_info *mtd = nand_to_mtd(&host->chip);
264
265 if ((host->addr_value[0] == host->cache_addr_value[0]) &&
266 (host->addr_value[1] == host->cache_addr_value[1]))
267 return 0;
268
269 host->addr_value[0] &= 0xffff0000;
270
271 hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
272 hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
273 hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
274 HINFC504_CMD);
275
276 hinfc_write(host, 0, HINFC504_LOG_READ_ADDR);
277 hinfc_write(host, mtd->writesize + mtd->oobsize,
278 HINFC504_LOG_READ_LEN);
279
280 hisi_nfc_dma_transfer(host, 0);
281
282 host->cache_addr_value[0] = host->addr_value[0];
283 host->cache_addr_value[1] = host->addr_value[1];
284
285 return 0;
286}
287
288static int hisi_nfc_send_cmd_erase(struct hinfc_host *host)
289{
290 hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
291 hinfc_write(host, (NAND_CMD_ERASE2 << 8) | NAND_CMD_ERASE1,
292 HINFC504_CMD);
293
294 hinfc_write(host, HINFC504_OP_WAIT_READY_EN
295 | HINFC504_OP_CMD2_EN
296 | HINFC504_OP_CMD1_EN
297 | HINFC504_OP_ADDR_EN
298 | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
299 << HINFC504_OP_NF_CS_SHIFT)
300 | ((host->addr_cycle & HINFC504_OP_ADDR_CYCLE_MASK)
301 << HINFC504_OP_ADDR_CYCLE_SHIFT),
302 HINFC504_OP);
303
304 wait_controller_finished(host);
305
306 return 0;
307}
308
309static int hisi_nfc_send_cmd_readid(struct hinfc_host *host)
310{
311 hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
312 hinfc_write(host, NAND_CMD_READID, HINFC504_CMD);
313 hinfc_write(host, 0, HINFC504_ADDRL);
314
315 hinfc_write(host, HINFC504_OP_CMD1_EN | HINFC504_OP_ADDR_EN
316 | HINFC504_OP_READ_DATA_EN
317 | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
318 << HINFC504_OP_NF_CS_SHIFT)
319 | 1 << HINFC504_OP_ADDR_CYCLE_SHIFT, HINFC504_OP);
320
321 wait_controller_finished(host);
322
323 return 0;
324}
325
326static int hisi_nfc_send_cmd_status(struct hinfc_host *host)
327{
328 hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
329 hinfc_write(host, NAND_CMD_STATUS, HINFC504_CMD);
330 hinfc_write(host, HINFC504_OP_CMD1_EN
331 | HINFC504_OP_READ_DATA_EN
332 | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
333 << HINFC504_OP_NF_CS_SHIFT),
334 HINFC504_OP);
335
336 wait_controller_finished(host);
337
338 return 0;
339}
340
341static int hisi_nfc_send_cmd_reset(struct hinfc_host *host, int chipselect)
342{
343 hinfc_write(host, NAND_CMD_RESET, HINFC504_CMD);
344
345 hinfc_write(host, HINFC504_OP_CMD1_EN
346 | ((chipselect & HINFC504_OP_NF_CS_MASK)
347 << HINFC504_OP_NF_CS_SHIFT)
348 | HINFC504_OP_WAIT_READY_EN,
349 HINFC504_OP);
350
351 wait_controller_finished(host);
352
353 return 0;
354}
355
356static void hisi_nfc_select_chip(struct mtd_info *mtd, int chipselect)
357{
358 struct nand_chip *chip = mtd_to_nand(mtd);
359 struct hinfc_host *host = nand_get_controller_data(chip);
360
361 if (chipselect < 0)
362 return;
363
364 host->chipselect = chipselect;
365}
366
367static uint8_t hisi_nfc_read_byte(struct mtd_info *mtd)
368{
369 struct nand_chip *chip = mtd_to_nand(mtd);
370 struct hinfc_host *host = nand_get_controller_data(chip);
371
372 if (host->command == NAND_CMD_STATUS)
373 return *(uint8_t *)(host->mmio);
374
375 host->offset++;
376
377 if (host->command == NAND_CMD_READID)
378 return *(uint8_t *)(host->mmio + host->offset - 1);
379
380 return *(uint8_t *)(host->buffer + host->offset - 1);
381}
382
383static u16 hisi_nfc_read_word(struct mtd_info *mtd)
384{
385 struct nand_chip *chip = mtd_to_nand(mtd);
386 struct hinfc_host *host = nand_get_controller_data(chip);
387
388 host->offset += 2;
389 return *(u16 *)(host->buffer + host->offset - 2);
390}
391
392static void
393hisi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
394{
395 struct nand_chip *chip = mtd_to_nand(mtd);
396 struct hinfc_host *host = nand_get_controller_data(chip);
397
398 memcpy(host->buffer + host->offset, buf, len);
399 host->offset += len;
400}
401
402static void hisi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
403{
404 struct nand_chip *chip = mtd_to_nand(mtd);
405 struct hinfc_host *host = nand_get_controller_data(chip);
406
407 memcpy(buf, host->buffer + host->offset, len);
408 host->offset += len;
409}
410
411static void set_addr(struct mtd_info *mtd, int column, int page_addr)
412{
413 struct nand_chip *chip = mtd_to_nand(mtd);
414 struct hinfc_host *host = nand_get_controller_data(chip);
415 unsigned int command = host->command;
416
417 host->addr_cycle = 0;
418 host->addr_value[0] = 0;
419 host->addr_value[1] = 0;
420
421 /* Serially input address */
422 if (column != -1) {
423 /* Adjust columns for 16 bit buswidth */
424 if (chip->options & NAND_BUSWIDTH_16 &&
425 !nand_opcode_8bits(command))
426 column >>= 1;
427
428 host->addr_value[0] = column & 0xffff;
429 host->addr_cycle = 2;
430 }
431 if (page_addr != -1) {
432 host->addr_value[0] |= (page_addr & 0xffff)
433 << (host->addr_cycle * 8);
434 host->addr_cycle += 2;
435 /* One more address cycle for devices > 128MiB */
436 if (chip->chipsize > (128 << 20)) {
437 host->addr_cycle += 1;
438 if (host->command == NAND_CMD_ERASE1)
439 host->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16;
440 else
441 host->addr_value[1] |= ((page_addr >> 16) & 0xff);
442 }
443 }
444}
445
446static void hisi_nfc_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
447 int page_addr)
448{
449 struct nand_chip *chip = mtd_to_nand(mtd);
450 struct hinfc_host *host = nand_get_controller_data(chip);
451 int is_cache_invalid = 1;
452 unsigned int flag = 0;
453
454 host->command = command;
455
456 switch (command) {
457 case NAND_CMD_READ0:
458 case NAND_CMD_READOOB:
459 if (command == NAND_CMD_READ0)
460 host->offset = column;
461 else
462 host->offset = column + mtd->writesize;
463
464 is_cache_invalid = 0;
465 set_addr(mtd, column, page_addr);
466 hisi_nfc_send_cmd_readstart(host);
467 break;
468
469 case NAND_CMD_SEQIN:
470 host->offset = column;
471 set_addr(mtd, column, page_addr);
472 break;
473
474 case NAND_CMD_ERASE1:
475 set_addr(mtd, column, page_addr);
476 break;
477
478 case NAND_CMD_PAGEPROG:
479 hisi_nfc_send_cmd_pageprog(host);
480 break;
481
482 case NAND_CMD_ERASE2:
483 hisi_nfc_send_cmd_erase(host);
484 break;
485
486 case NAND_CMD_READID:
487 host->offset = column;
488 memset(host->mmio, 0, 0x10);
489 hisi_nfc_send_cmd_readid(host);
490 break;
491
492 case NAND_CMD_STATUS:
493 flag = hinfc_read(host, HINFC504_CON);
494 if (chip->ecc.mode == NAND_ECC_HW)
495 hinfc_write(host,
496 flag & ~(HINFC504_CON_ECCTYPE_MASK <<
497 HINFC504_CON_ECCTYPE_SHIFT), HINFC504_CON);
498
499 host->offset = 0;
500 memset(host->mmio, 0, 0x10);
501 hisi_nfc_send_cmd_status(host);
502 hinfc_write(host, flag, HINFC504_CON);
503 break;
504
505 case NAND_CMD_RESET:
506 hisi_nfc_send_cmd_reset(host, host->chipselect);
507 break;
508
509 default:
510 dev_err(host->dev, "Error: unsupported cmd(cmd=%x, col=%x, page=%x)\n",
511 command, column, page_addr);
512 }
513
514 if (is_cache_invalid) {
515 host->cache_addr_value[0] = ~0;
516 host->cache_addr_value[1] = ~0;
517 }
518}
519
520static irqreturn_t hinfc_irq_handle(int irq, void *devid)
521{
522 struct hinfc_host *host = devid;
523 unsigned int flag;
524
525 flag = hinfc_read(host, HINFC504_INTS);
526 /* store interrupts state */
527 host->irq_status |= flag;
528
529 if (flag & HINFC504_INTS_DMA) {
530 hinfc_write(host, HINFC504_INTCLR_DMA, HINFC504_INTCLR);
531 complete(&host->cmd_complete);
532 } else if (flag & HINFC504_INTS_CE) {
533 hinfc_write(host, HINFC504_INTCLR_CE, HINFC504_INTCLR);
534 } else if (flag & HINFC504_INTS_UE) {
535 hinfc_write(host, HINFC504_INTCLR_UE, HINFC504_INTCLR);
536 }
537
538 return IRQ_HANDLED;
539}
540
541static int hisi_nand_read_page_hwecc(struct mtd_info *mtd,
542 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
543{
544 struct hinfc_host *host = nand_get_controller_data(chip);
545 int max_bitflips = 0, stat = 0, stat_max = 0, status_ecc;
546 int stat_1, stat_2;
547
548 chip->read_buf(mtd, buf, mtd->writesize);
549 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
550
551 /* errors which can not be corrected by ECC */
552 if (host->irq_status & HINFC504_INTS_UE) {
553 mtd->ecc_stats.failed++;
554 } else if (host->irq_status & HINFC504_INTS_CE) {
555 /* TODO: need add other ECC modes! */
556 switch (chip->ecc.strength) {
557 case 16:
558 status_ecc = hinfc_read(host, HINFC504_ECC_STATUS) >>
559 HINFC504_ECC_16_BIT_SHIFT & 0x0fff;
560 stat_2 = status_ecc & 0x3f;
561 stat_1 = status_ecc >> 6 & 0x3f;
562 stat = stat_1 + stat_2;
563 stat_max = max_t(int, stat_1, stat_2);
564 }
565 mtd->ecc_stats.corrected += stat;
566 max_bitflips = max_t(int, max_bitflips, stat_max);
567 }
568 host->irq_status = 0;
569
570 return max_bitflips;
571}
572
573static int hisi_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
574 int page)
575{
576 struct hinfc_host *host = nand_get_controller_data(chip);
577
578 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
579 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
580
581 if (host->irq_status & HINFC504_INTS_UE) {
582 host->irq_status = 0;
583 return -EBADMSG;
584 }
585
586 host->irq_status = 0;
587 return 0;
588}
589
590static int hisi_nand_write_page_hwecc(struct mtd_info *mtd,
591 struct nand_chip *chip, const uint8_t *buf, int oob_required,
592 int page)
593{
594 chip->write_buf(mtd, buf, mtd->writesize);
595 if (oob_required)
596 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
597
598 return 0;
599}
600
601static void hisi_nfc_host_init(struct hinfc_host *host)
602{
603 struct nand_chip *chip = &host->chip;
604 unsigned int flag = 0;
605
606 host->version = hinfc_read(host, HINFC_VERSION);
607 host->addr_cycle = 0;
608 host->addr_value[0] = 0;
609 host->addr_value[1] = 0;
610 host->cache_addr_value[0] = ~0;
611 host->cache_addr_value[1] = ~0;
612 host->chipselect = 0;
613
614 /* default page size: 2K, ecc_none. need modify */
615 flag = HINFC504_CON_OP_MODE_NORMAL | HINFC504_CON_READY_BUSY_SEL
616 | ((0x001 & HINFC504_CON_PAGESIZE_MASK)
617 << HINFC504_CON_PAGEISZE_SHIFT)
618 | ((0x0 & HINFC504_CON_ECCTYPE_MASK)
619 << HINFC504_CON_ECCTYPE_SHIFT)
620 | ((chip->options & NAND_BUSWIDTH_16) ?
621 HINFC504_CON_BUS_WIDTH : 0);
622 hinfc_write(host, flag, HINFC504_CON);
623
624 memset(host->mmio, 0xff, HINFC504_BUFFER_BASE_ADDRESS_LEN);
625
626 hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
627 HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
628
629 /* enable DMA irq */
630 hinfc_write(host, HINFC504_INTEN_DMA, HINFC504_INTEN);
631}
632
633static int hisi_ooblayout_ecc(struct mtd_info *mtd, int section,
634 struct mtd_oob_region *oobregion)
635{
636 /* FIXME: add ECC bytes position */
637 return -ENOTSUPP;
638}
639
640static int hisi_ooblayout_free(struct mtd_info *mtd, int section,
641 struct mtd_oob_region *oobregion)
642{
643 if (section)
644 return -ERANGE;
645
646 oobregion->offset = 2;
647 oobregion->length = 6;
648
649 return 0;
650}
651
652static const struct mtd_ooblayout_ops hisi_ooblayout_ops = {
653 .ecc = hisi_ooblayout_ecc,
654 .free = hisi_ooblayout_free,
655};
656
657static int hisi_nfc_ecc_probe(struct hinfc_host *host)
658{
659 unsigned int flag;
660 int size, strength, ecc_bits;
661 struct device *dev = host->dev;
662 struct nand_chip *chip = &host->chip;
663 struct mtd_info *mtd = nand_to_mtd(chip);
664
665 size = chip->ecc.size;
666 strength = chip->ecc.strength;
667 if (size != 1024) {
668 dev_err(dev, "error ecc size: %d\n", size);
669 return -EINVAL;
670 }
671
672 if ((size == 1024) && ((strength != 8) && (strength != 16) &&
673 (strength != 24) && (strength != 40))) {
674 dev_err(dev, "ecc size and strength do not match\n");
675 return -EINVAL;
676 }
677
678 chip->ecc.size = size;
679 chip->ecc.strength = strength;
680
681 chip->ecc.read_page = hisi_nand_read_page_hwecc;
682 chip->ecc.read_oob = hisi_nand_read_oob;
683 chip->ecc.write_page = hisi_nand_write_page_hwecc;
684
685 switch (chip->ecc.strength) {
686 case 16:
687 ecc_bits = 6;
688 if (mtd->writesize == 2048)
689 mtd_set_ooblayout(mtd, &hisi_ooblayout_ops);
690
691 /* TODO: add more page size support */
692 break;
693
694 /* TODO: add more ecc strength support */
695 default:
696 dev_err(dev, "not support strength: %d\n", chip->ecc.strength);
697 return -EINVAL;
698 }
699
700 flag = hinfc_read(host, HINFC504_CON);
701 /* add ecc type configure */
702 flag |= ((ecc_bits & HINFC504_CON_ECCTYPE_MASK)
703 << HINFC504_CON_ECCTYPE_SHIFT);
704 hinfc_write(host, flag, HINFC504_CON);
705
706 /* enable ecc irq */
707 flag = hinfc_read(host, HINFC504_INTEN) & 0xfff;
708 hinfc_write(host, flag | HINFC504_INTEN_UE | HINFC504_INTEN_CE,
709 HINFC504_INTEN);
710
711 return 0;
712}
713
714static int hisi_nfc_probe(struct platform_device *pdev)
715{
716 int ret = 0, irq, flag, max_chips = HINFC504_MAX_CHIP;
717 struct device *dev = &pdev->dev;
718 struct hinfc_host *host;
719 struct nand_chip *chip;
720 struct mtd_info *mtd;
721 struct resource *res;
722 struct device_node *np = dev->of_node;
723
724 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
725 if (!host)
726 return -ENOMEM;
727 host->dev = dev;
728
729 platform_set_drvdata(pdev, host);
730 chip = &host->chip;
731 mtd = nand_to_mtd(chip);
732
733 irq = platform_get_irq(pdev, 0);
734 if (irq < 0) {
735 dev_err(dev, "no IRQ resource defined\n");
736 ret = -ENXIO;
737 goto err_res;
738 }
739
740 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
741 host->iobase = devm_ioremap_resource(dev, res);
742 if (IS_ERR(host->iobase)) {
743 ret = PTR_ERR(host->iobase);
744 goto err_res;
745 }
746
747 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
748 host->mmio = devm_ioremap_resource(dev, res);
749 if (IS_ERR(host->mmio)) {
750 ret = PTR_ERR(host->mmio);
751 dev_err(dev, "devm_ioremap_resource[1] fail\n");
752 goto err_res;
753 }
754
755 mtd->name = "hisi_nand";
756 mtd->dev.parent = &pdev->dev;
757
758 nand_set_controller_data(chip, host);
759 nand_set_flash_node(chip, np);
760 chip->cmdfunc = hisi_nfc_cmdfunc;
761 chip->select_chip = hisi_nfc_select_chip;
762 chip->read_byte = hisi_nfc_read_byte;
763 chip->read_word = hisi_nfc_read_word;
764 chip->write_buf = hisi_nfc_write_buf;
765 chip->read_buf = hisi_nfc_read_buf;
766 chip->chip_delay = HINFC504_CHIP_DELAY;
767
768 hisi_nfc_host_init(host);
769
770 ret = devm_request_irq(dev, irq, hinfc_irq_handle, 0x0, "nandc", host);
771 if (ret) {
772 dev_err(dev, "failed to request IRQ\n");
773 goto err_res;
774 }
775
776 ret = nand_scan_ident(mtd, max_chips, NULL);
777 if (ret)
778 goto err_res;
779
780 host->buffer = dmam_alloc_coherent(dev, mtd->writesize + mtd->oobsize,
781 &host->dma_buffer, GFP_KERNEL);
782 if (!host->buffer) {
783 ret = -ENOMEM;
784 goto err_res;
785 }
786
787 host->dma_oob = host->dma_buffer + mtd->writesize;
788 memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize);
789
790 flag = hinfc_read(host, HINFC504_CON);
791 flag &= ~(HINFC504_CON_PAGESIZE_MASK << HINFC504_CON_PAGEISZE_SHIFT);
792 switch (mtd->writesize) {
793 case 2048:
794 flag |= (0x001 << HINFC504_CON_PAGEISZE_SHIFT); break;
795 /*
796 * TODO: add more pagesize support,
797 * default pagesize has been set in hisi_nfc_host_init
798 */
799 default:
800 dev_err(dev, "NON-2KB page size nand flash\n");
801 ret = -EINVAL;
802 goto err_res;
803 }
804 hinfc_write(host, flag, HINFC504_CON);
805
806 if (chip->ecc.mode == NAND_ECC_HW)
807 hisi_nfc_ecc_probe(host);
808
809 ret = nand_scan_tail(mtd);
810 if (ret) {
811 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
812 goto err_res;
813 }
814
815 ret = mtd_device_register(mtd, NULL, 0);
816 if (ret) {
817 dev_err(dev, "Err MTD partition=%d\n", ret);
818 goto err_mtd;
819 }
820
821 return 0;
822
823err_mtd:
824 nand_release(mtd);
825err_res:
826 return ret;
827}
828
829static int hisi_nfc_remove(struct platform_device *pdev)
830{
831 struct hinfc_host *host = platform_get_drvdata(pdev);
832 struct mtd_info *mtd = nand_to_mtd(&host->chip);
833
834 nand_release(mtd);
835
836 return 0;
837}
838
839#ifdef CONFIG_PM_SLEEP
840static int hisi_nfc_suspend(struct device *dev)
841{
842 struct hinfc_host *host = dev_get_drvdata(dev);
843 unsigned long timeout = jiffies + HINFC504_NFC_PM_TIMEOUT;
844
845 while (time_before(jiffies, timeout)) {
846 if (((hinfc_read(host, HINFC504_STATUS) & 0x1) == 0x0) &&
847 (hinfc_read(host, HINFC504_DMA_CTRL) &
848 HINFC504_DMA_CTRL_DMA_START)) {
849 cond_resched();
850 return 0;
851 }
852 }
853
854 dev_err(host->dev, "nand controller suspend timeout.\n");
855
856 return -EAGAIN;
857}
858
859static int hisi_nfc_resume(struct device *dev)
860{
861 int cs;
862 struct hinfc_host *host = dev_get_drvdata(dev);
863 struct nand_chip *chip = &host->chip;
864
865 for (cs = 0; cs < chip->numchips; cs++)
866 hisi_nfc_send_cmd_reset(host, cs);
867 hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
868 HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
869
870 return 0;
871}
872#endif
873static SIMPLE_DEV_PM_OPS(hisi_nfc_pm_ops, hisi_nfc_suspend, hisi_nfc_resume);
874
875static const struct of_device_id nfc_id_table[] = {
876 { .compatible = "hisilicon,504-nfc" },
877 {}
878};
879MODULE_DEVICE_TABLE(of, nfc_id_table);
880
881static struct platform_driver hisi_nfc_driver = {
882 .driver = {
883 .name = "hisi_nand",
884 .of_match_table = nfc_id_table,
885 .pm = &hisi_nfc_pm_ops,
886 },
887 .probe = hisi_nfc_probe,
888 .remove = hisi_nfc_remove,
889};
890
891module_platform_driver(hisi_nfc_driver);
892
893MODULE_LICENSE("GPL");
894MODULE_AUTHOR("Zhou Wang");
895MODULE_AUTHOR("Zhiyong Cai");
896MODULE_DESCRIPTION("Hisilicon Nand Flash Controller Driver");