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1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/iopoll.h>
37#include <linux/kernel.h>
38#include <linux/types.h>
39#include <net/addrconf.h>
40#include <rdma/ib_addr.h>
41#include <rdma/ib_cache.h>
42#include <rdma/ib_umem.h>
43#include <rdma/uverbs_ioctl.h>
44
45#include "hnae3.h"
46#include "hns_roce_common.h"
47#include "hns_roce_device.h"
48#include "hns_roce_cmd.h"
49#include "hns_roce_hem.h"
50#include "hns_roce_hw_v2.h"
51
52enum {
53 CMD_RST_PRC_OTHERS,
54 CMD_RST_PRC_SUCCESS,
55 CMD_RST_PRC_EBUSY,
56};
57
58enum ecc_resource_type {
59 ECC_RESOURCE_QPC,
60 ECC_RESOURCE_CQC,
61 ECC_RESOURCE_MPT,
62 ECC_RESOURCE_SRQC,
63 ECC_RESOURCE_GMV,
64 ECC_RESOURCE_QPC_TIMER,
65 ECC_RESOURCE_CQC_TIMER,
66 ECC_RESOURCE_SCCC,
67 ECC_RESOURCE_COUNT,
68};
69
70static const struct {
71 const char *name;
72 u8 read_bt0_op;
73 u8 write_bt0_op;
74} fmea_ram_res[] = {
75 { "ECC_RESOURCE_QPC",
76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 },
77 { "ECC_RESOURCE_CQC",
78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 },
79 { "ECC_RESOURCE_MPT",
80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 },
81 { "ECC_RESOURCE_SRQC",
82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 },
83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */
84 { "ECC_RESOURCE_GMV",
85 0, 0 },
86 { "ECC_RESOURCE_QPC_TIMER",
87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 },
88 { "ECC_RESOURCE_CQC_TIMER",
89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 },
90 { "ECC_RESOURCE_SCCC",
91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 },
92};
93
94static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
95 struct ib_sge *sg)
96{
97 dseg->lkey = cpu_to_le32(sg->lkey);
98 dseg->addr = cpu_to_le64(sg->addr);
99 dseg->len = cpu_to_le32(sg->length);
100}
101
102/*
103 * mapped-value = 1 + real-value
104 * The hns wr opcode real value is start from 0, In order to distinguish between
105 * initialized and uninitialized map values, we plus 1 to the actual value when
106 * defining the mapping, so that the validity can be identified by checking the
107 * mapped value is greater than 0.
108 */
109#define HR_OPC_MAP(ib_key, hr_key) \
110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
111
112static const u32 hns_roce_op_code[] = {
113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
115 HR_OPC_MAP(SEND, SEND),
116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
117 HR_OPC_MAP(RDMA_READ, RDMA_READ),
118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
123 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
124};
125
126static u32 to_hr_opcode(u32 ib_opcode)
127{
128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
129 return HNS_ROCE_V2_WQE_OP_MASK;
130
131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
132 HNS_ROCE_V2_WQE_OP_MASK;
133}
134
135static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
136 const struct ib_reg_wr *wr)
137{
138 struct hns_roce_wqe_frmr_seg *fseg =
139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
140 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
141 u64 pbl_ba;
142
143 /* use ib_access_flags */
144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND);
145 hr_reg_write_bool(fseg, FRMR_ATOMIC,
146 wr->access & IB_ACCESS_REMOTE_ATOMIC);
147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ);
148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE);
149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE);
150
151 /* Data structure reuse may lead to confusion */
152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
155
156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
158 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
160
161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages);
162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ,
163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
164 hr_reg_clear(fseg, FRMR_BLK_MODE);
165}
166
167static void set_atomic_seg(const struct ib_send_wr *wr,
168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
169 unsigned int valid_num_sge)
170{
171 struct hns_roce_v2_wqe_data_seg *dseg =
172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
173 struct hns_roce_wqe_atomic_seg *aseg =
174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
175
176 set_data_seg_v2(dseg, wr->sg_list);
177
178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
181 } else {
182 aseg->fetchadd_swap_data =
183 cpu_to_le64(atomic_wr(wr)->compare_add);
184 aseg->cmp_data = 0;
185 }
186
187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
188}
189
190static int fill_ext_sge_inl_data(struct hns_roce_qp *qp,
191 const struct ib_send_wr *wr,
192 unsigned int *sge_idx, u32 msg_len)
193{
194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev;
195 unsigned int left_len_in_pg;
196 unsigned int idx = *sge_idx;
197 unsigned int i = 0;
198 unsigned int len;
199 void *addr;
200 void *dseg;
201
202 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) {
203 ibdev_err(ibdev,
204 "no enough extended sge space for inline data.\n");
205 return -EINVAL;
206 }
207
208 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
209 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg;
210 len = wr->sg_list[0].length;
211 addr = (void *)(unsigned long)(wr->sg_list[0].addr);
212
213 /* When copying data to extended sge space, the left length in page may
214 * not long enough for current user's sge. So the data should be
215 * splited into several parts, one in the first page, and the others in
216 * the subsequent pages.
217 */
218 while (1) {
219 if (len <= left_len_in_pg) {
220 memcpy(dseg, addr, len);
221
222 idx += len / HNS_ROCE_SGE_SIZE;
223
224 i++;
225 if (i >= wr->num_sge)
226 break;
227
228 left_len_in_pg -= len;
229 len = wr->sg_list[i].length;
230 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
231 dseg += len;
232 } else {
233 memcpy(dseg, addr, left_len_in_pg);
234
235 len -= left_len_in_pg;
236 addr += left_len_in_pg;
237 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE;
238 dseg = hns_roce_get_extend_sge(qp,
239 idx & (qp->sge.sge_cnt - 1));
240 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT;
241 }
242 }
243
244 *sge_idx = idx;
245
246 return 0;
247}
248
249static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge,
250 unsigned int *sge_ind, unsigned int cnt)
251{
252 struct hns_roce_v2_wqe_data_seg *dseg;
253 unsigned int idx = *sge_ind;
254
255 while (cnt > 0) {
256 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
257 if (likely(sge->length)) {
258 set_data_seg_v2(dseg, sge);
259 idx++;
260 cnt--;
261 }
262 sge++;
263 }
264
265 *sge_ind = idx;
266}
267
268static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
269{
270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
271 int mtu = ib_mtu_enum_to_int(qp->path_mtu);
272
273 if (mtu < 0 || len > qp->max_inline_data || len > mtu) {
274 ibdev_err(&hr_dev->ib_dev,
275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
276 len, qp->max_inline_data, mtu);
277 return false;
278 }
279
280 return true;
281}
282
283static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
284 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
285 unsigned int *sge_idx)
286{
287 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
288 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len);
289 struct ib_device *ibdev = &hr_dev->ib_dev;
290 unsigned int curr_idx = *sge_idx;
291 void *dseg = rc_sq_wqe;
292 unsigned int i;
293 int ret;
294
295 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
296 ibdev_err(ibdev, "invalid inline parameters!\n");
297 return -EINVAL;
298 }
299
300 if (!check_inl_data_len(qp, msg_len))
301 return -EINVAL;
302
303 dseg += sizeof(struct hns_roce_v2_rc_send_wqe);
304
305 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) {
306 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
307
308 for (i = 0; i < wr->num_sge; i++) {
309 memcpy(dseg, ((void *)wr->sg_list[i].addr),
310 wr->sg_list[i].length);
311 dseg += wr->sg_list[i].length;
312 }
313 } else {
314 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE);
315
316 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len);
317 if (ret)
318 return ret;
319
320 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx);
321 }
322
323 *sge_idx = curr_idx;
324
325 return 0;
326}
327
328static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
329 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
330 unsigned int *sge_ind,
331 unsigned int valid_num_sge)
332{
333 struct hns_roce_v2_wqe_data_seg *dseg =
334 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
335 struct hns_roce_qp *qp = to_hr_qp(ibqp);
336 int j = 0;
337 int i;
338
339 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX,
340 (*sge_ind) & (qp->sge.sge_cnt - 1));
341
342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE,
343 !!(wr->send_flags & IB_SEND_INLINE));
344 if (wr->send_flags & IB_SEND_INLINE)
345 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind);
346
347 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
348 for (i = 0; i < wr->num_sge; i++) {
349 if (likely(wr->sg_list[i].length)) {
350 set_data_seg_v2(dseg, wr->sg_list + i);
351 dseg++;
352 }
353 }
354 } else {
355 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) {
356 if (likely(wr->sg_list[i].length)) {
357 set_data_seg_v2(dseg, wr->sg_list + i);
358 dseg++;
359 j++;
360 }
361 }
362
363 set_extend_sge(qp, wr->sg_list + i, sge_ind,
364 valid_num_sge - HNS_ROCE_SGE_IN_WQE);
365 }
366
367 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge);
368
369 return 0;
370}
371
372static int check_send_valid(struct hns_roce_dev *hr_dev,
373 struct hns_roce_qp *hr_qp)
374{
375 struct ib_device *ibdev = &hr_dev->ib_dev;
376
377 if (unlikely(hr_qp->state == IB_QPS_RESET ||
378 hr_qp->state == IB_QPS_INIT ||
379 hr_qp->state == IB_QPS_RTR)) {
380 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n",
381 hr_qp->state);
382 return -EINVAL;
383 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) {
384 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n",
385 hr_dev->state);
386 return -EIO;
387 }
388
389 return 0;
390}
391
392static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
393 unsigned int *sge_len)
394{
395 unsigned int valid_num = 0;
396 unsigned int len = 0;
397 int i;
398
399 for (i = 0; i < wr->num_sge; i++) {
400 if (likely(wr->sg_list[i].length)) {
401 len += wr->sg_list[i].length;
402 valid_num++;
403 }
404 }
405
406 *sge_len = len;
407 return valid_num;
408}
409
410static __le32 get_immtdata(const struct ib_send_wr *wr)
411{
412 switch (wr->opcode) {
413 case IB_WR_SEND_WITH_IMM:
414 case IB_WR_RDMA_WRITE_WITH_IMM:
415 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
416 default:
417 return 0;
418 }
419}
420
421static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
422 const struct ib_send_wr *wr)
423{
424 u32 ib_op = wr->opcode;
425
426 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM)
427 return -EINVAL;
428
429 ud_sq_wqe->immtdata = get_immtdata(wr);
430
431 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
432
433 return 0;
434}
435
436static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
437 struct hns_roce_ah *ah)
438{
439 struct ib_device *ib_dev = ah->ibah.device;
440 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
441
442 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport);
443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit);
444 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass);
445 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel);
446
447 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL))
448 return -EINVAL;
449
450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl);
451
452 ud_sq_wqe->sgid_index = ah->av.gid_index;
453
454 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN);
455 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2);
456
457 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
458 return 0;
459
460 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en);
461 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id);
462
463 return 0;
464}
465
466static inline int set_ud_wqe(struct hns_roce_qp *qp,
467 const struct ib_send_wr *wr,
468 void *wqe, unsigned int *sge_idx,
469 unsigned int owner_bit)
470{
471 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
472 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
473 unsigned int curr_idx = *sge_idx;
474 unsigned int valid_num_sge;
475 u32 msg_len = 0;
476 int ret;
477
478 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
479
480 ret = set_ud_opcode(ud_sq_wqe, wr);
481 if (WARN_ON(ret))
482 return ret;
483
484 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
485
486 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE,
487 !!(wr->send_flags & IB_SEND_SIGNALED));
488 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE,
489 !!(wr->send_flags & IB_SEND_SOLICITED));
490
491 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn);
492 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge);
493 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX,
494 curr_idx & (qp->sge.sge_cnt - 1));
495
496 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
497 qp->qkey : ud_wr(wr)->remote_qkey);
498 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn);
499
500 ret = fill_ud_av(ud_sq_wqe, ah);
501 if (ret)
502 return ret;
503
504 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl;
505
506 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge);
507
508 /*
509 * The pipeline can sequentially post all valid WQEs into WQ buffer,
510 * including new WQEs waiting for the doorbell to update the PI again.
511 * Therefore, the owner bit of WQE MUST be updated after all fields
512 * and extSGEs have been written into DDR instead of cache.
513 */
514 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
515 dma_wmb();
516
517 *sge_idx = curr_idx;
518 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit);
519
520 return 0;
521}
522
523static int set_rc_opcode(struct hns_roce_dev *hr_dev,
524 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
525 const struct ib_send_wr *wr)
526{
527 u32 ib_op = wr->opcode;
528 int ret = 0;
529
530 rc_sq_wqe->immtdata = get_immtdata(wr);
531
532 switch (ib_op) {
533 case IB_WR_RDMA_READ:
534 case IB_WR_RDMA_WRITE:
535 case IB_WR_RDMA_WRITE_WITH_IMM:
536 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
537 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
538 break;
539 case IB_WR_SEND:
540 case IB_WR_SEND_WITH_IMM:
541 break;
542 case IB_WR_ATOMIC_CMP_AND_SWP:
543 case IB_WR_ATOMIC_FETCH_AND_ADD:
544 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
545 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
546 break;
547 case IB_WR_REG_MR:
548 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
549 set_frmr_seg(rc_sq_wqe, reg_wr(wr));
550 else
551 ret = -EOPNOTSUPP;
552 break;
553 case IB_WR_SEND_WITH_INV:
554 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
555 break;
556 default:
557 ret = -EINVAL;
558 }
559
560 if (unlikely(ret))
561 return ret;
562
563 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op));
564
565 return ret;
566}
567
568static inline int set_rc_wqe(struct hns_roce_qp *qp,
569 const struct ib_send_wr *wr,
570 void *wqe, unsigned int *sge_idx,
571 unsigned int owner_bit)
572{
573 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
574 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
575 unsigned int curr_idx = *sge_idx;
576 unsigned int valid_num_sge;
577 u32 msg_len = 0;
578 int ret;
579
580 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
581
582 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
583
584 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr);
585 if (WARN_ON(ret))
586 return ret;
587
588 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE,
589 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
590
591 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE,
592 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
593
594 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE,
595 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
596
597 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
598 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
599 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
600 else if (wr->opcode != IB_WR_REG_MR)
601 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
602 &curr_idx, valid_num_sge);
603
604 /*
605 * The pipeline can sequentially post all valid WQEs into WQ buffer,
606 * including new WQEs waiting for the doorbell to update the PI again.
607 * Therefore, the owner bit of WQE MUST be updated after all fields
608 * and extSGEs have been written into DDR instead of cache.
609 */
610 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
611 dma_wmb();
612
613 *sge_idx = curr_idx;
614 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit);
615
616 return ret;
617}
618
619static inline void update_sq_db(struct hns_roce_dev *hr_dev,
620 struct hns_roce_qp *qp)
621{
622 if (unlikely(qp->state == IB_QPS_ERR)) {
623 flush_cqe(hr_dev, qp);
624 } else {
625 struct hns_roce_v2_db sq_db = {};
626
627 hr_reg_write(&sq_db, DB_TAG, qp->qpn);
628 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB);
629 hr_reg_write(&sq_db, DB_PI, qp->sq.head);
630 hr_reg_write(&sq_db, DB_SL, qp->sl);
631
632 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg);
633 }
634}
635
636static inline void update_rq_db(struct hns_roce_dev *hr_dev,
637 struct hns_roce_qp *qp)
638{
639 if (unlikely(qp->state == IB_QPS_ERR)) {
640 flush_cqe(hr_dev, qp);
641 } else {
642 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) {
643 *qp->rdb.db_record =
644 qp->rq.head & V2_DB_PRODUCER_IDX_M;
645 } else {
646 struct hns_roce_v2_db rq_db = {};
647
648 hr_reg_write(&rq_db, DB_TAG, qp->qpn);
649 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB);
650 hr_reg_write(&rq_db, DB_PI, qp->rq.head);
651
652 hns_roce_write64(hr_dev, (__le32 *)&rq_db,
653 qp->rq.db_reg);
654 }
655 }
656}
657
658static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val,
659 u64 __iomem *dest)
660{
661#define HNS_ROCE_WRITE_TIMES 8
662 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
663 struct hnae3_handle *handle = priv->handle;
664 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
665 int i;
666
667 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
668 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++)
669 writeq_relaxed(*(val + i), dest + i);
670}
671
672static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
673 void *wqe)
674{
675#define HNS_ROCE_SL_SHIFT 2
676 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
677
678 /* All kinds of DirectWQE have the same header field layout */
679 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG);
680 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl);
681 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H,
682 qp->sl >> HNS_ROCE_SL_SHIFT);
683 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head);
684
685 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg);
686}
687
688static int hns_roce_v2_post_send(struct ib_qp *ibqp,
689 const struct ib_send_wr *wr,
690 const struct ib_send_wr **bad_wr)
691{
692 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
693 struct ib_device *ibdev = &hr_dev->ib_dev;
694 struct hns_roce_qp *qp = to_hr_qp(ibqp);
695 unsigned long flags = 0;
696 unsigned int owner_bit;
697 unsigned int sge_idx;
698 unsigned int wqe_idx;
699 void *wqe = NULL;
700 u32 nreq;
701 int ret;
702
703 spin_lock_irqsave(&qp->sq.lock, flags);
704
705 ret = check_send_valid(hr_dev, qp);
706 if (unlikely(ret)) {
707 *bad_wr = wr;
708 nreq = 0;
709 goto out;
710 }
711
712 sge_idx = qp->next_sge;
713
714 for (nreq = 0; wr; ++nreq, wr = wr->next) {
715 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
716 ret = -ENOMEM;
717 *bad_wr = wr;
718 goto out;
719 }
720
721 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
722
723 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
724 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n",
725 wr->num_sge, qp->sq.max_gs);
726 ret = -EINVAL;
727 *bad_wr = wr;
728 goto out;
729 }
730
731 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
732 qp->sq.wrid[wqe_idx] = wr->wr_id;
733 owner_bit =
734 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
735
736 /* Corresponding to the QP type, wqe process separately */
737 if (ibqp->qp_type == IB_QPT_RC)
738 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
739 else
740 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
741
742 if (unlikely(ret)) {
743 *bad_wr = wr;
744 goto out;
745 }
746 }
747
748out:
749 if (likely(nreq)) {
750 qp->sq.head += nreq;
751 qp->next_sge = sge_idx;
752
753 if (nreq == 1 && !ret &&
754 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE))
755 write_dwqe(hr_dev, qp, wqe);
756 else
757 update_sq_db(hr_dev, qp);
758 }
759
760 spin_unlock_irqrestore(&qp->sq.lock, flags);
761
762 return ret;
763}
764
765static int check_recv_valid(struct hns_roce_dev *hr_dev,
766 struct hns_roce_qp *hr_qp)
767{
768 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
769 return -EIO;
770
771 if (hr_qp->state == IB_QPS_RESET)
772 return -EINVAL;
773
774 return 0;
775}
776
777static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe,
778 u32 max_sge, bool rsv)
779{
780 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
781 u32 i, cnt;
782
783 for (i = 0, cnt = 0; i < wr->num_sge; i++) {
784 /* Skip zero-length sge */
785 if (!wr->sg_list[i].length)
786 continue;
787 set_data_seg_v2(dseg + cnt, wr->sg_list + i);
788 cnt++;
789 }
790
791 /* Fill a reserved sge to make hw stop reading remaining segments */
792 if (rsv) {
793 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
794 dseg[cnt].addr = 0;
795 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
796 } else {
797 /* Clear remaining segments to make ROCEE ignore sges */
798 if (cnt < max_sge)
799 memset(dseg + cnt, 0,
800 (max_sge - cnt) * HNS_ROCE_SGE_SIZE);
801 }
802}
803
804static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr,
805 u32 wqe_idx, u32 max_sge)
806{
807 void *wqe = NULL;
808
809 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
810 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge);
811}
812
813static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
814 const struct ib_recv_wr *wr,
815 const struct ib_recv_wr **bad_wr)
816{
817 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
818 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
819 struct ib_device *ibdev = &hr_dev->ib_dev;
820 u32 wqe_idx, nreq, max_sge;
821 unsigned long flags;
822 int ret;
823
824 spin_lock_irqsave(&hr_qp->rq.lock, flags);
825
826 ret = check_recv_valid(hr_dev, hr_qp);
827 if (unlikely(ret)) {
828 *bad_wr = wr;
829 nreq = 0;
830 goto out;
831 }
832
833 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
834 for (nreq = 0; wr; ++nreq, wr = wr->next) {
835 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
836 hr_qp->ibqp.recv_cq))) {
837 ret = -ENOMEM;
838 *bad_wr = wr;
839 goto out;
840 }
841
842 if (unlikely(wr->num_sge > max_sge)) {
843 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n",
844 wr->num_sge, max_sge);
845 ret = -EINVAL;
846 *bad_wr = wr;
847 goto out;
848 }
849
850 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
851 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge);
852 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
853 }
854
855out:
856 if (likely(nreq)) {
857 hr_qp->rq.head += nreq;
858
859 update_rq_db(hr_dev, hr_qp);
860 }
861 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
862
863 return ret;
864}
865
866static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n)
867{
868 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
869}
870
871static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n)
872{
873 return hns_roce_buf_offset(idx_que->mtr.kmem,
874 n << idx_que->entry_shift);
875}
876
877static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index)
878{
879 /* always called with interrupts disabled. */
880 spin_lock(&srq->lock);
881
882 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
883 srq->idx_que.tail++;
884
885 spin_unlock(&srq->lock);
886}
887
888static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq)
889{
890 struct hns_roce_idx_que *idx_que = &srq->idx_que;
891
892 return idx_que->head - idx_que->tail >= srq->wqe_cnt;
893}
894
895static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge,
896 const struct ib_recv_wr *wr)
897{
898 struct ib_device *ib_dev = srq->ibsrq.device;
899
900 if (unlikely(wr->num_sge > max_sge)) {
901 ibdev_err(ib_dev,
902 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n",
903 wr->num_sge, max_sge);
904 return -EINVAL;
905 }
906
907 if (unlikely(hns_roce_srqwq_overflow(srq))) {
908 ibdev_err(ib_dev,
909 "failed to check srqwq status, srqwq is full.\n");
910 return -ENOMEM;
911 }
912
913 return 0;
914}
915
916static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx)
917{
918 struct hns_roce_idx_que *idx_que = &srq->idx_que;
919 u32 pos;
920
921 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt);
922 if (unlikely(pos == srq->wqe_cnt))
923 return -ENOSPC;
924
925 bitmap_set(idx_que->bitmap, pos, 1);
926 *wqe_idx = pos;
927 return 0;
928}
929
930static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx)
931{
932 struct hns_roce_idx_que *idx_que = &srq->idx_que;
933 unsigned int head;
934 __le32 *buf;
935
936 head = idx_que->head & (srq->wqe_cnt - 1);
937
938 buf = get_idx_buf(idx_que, head);
939 *buf = cpu_to_le32(wqe_idx);
940
941 idx_que->head++;
942}
943
944static void update_srq_db(struct hns_roce_srq *srq)
945{
946 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device);
947 struct hns_roce_v2_db db;
948
949 hr_reg_write(&db, DB_TAG, srq->srqn);
950 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB);
951 hr_reg_write(&db, DB_PI, srq->idx_que.head);
952
953 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg);
954}
955
956static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
957 const struct ib_recv_wr *wr,
958 const struct ib_recv_wr **bad_wr)
959{
960 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
961 unsigned long flags;
962 int ret = 0;
963 u32 max_sge;
964 u32 wqe_idx;
965 void *wqe;
966 u32 nreq;
967
968 spin_lock_irqsave(&srq->lock, flags);
969
970 max_sge = srq->max_gs - srq->rsv_sge;
971 for (nreq = 0; wr; ++nreq, wr = wr->next) {
972 ret = check_post_srq_valid(srq, max_sge, wr);
973 if (ret) {
974 *bad_wr = wr;
975 break;
976 }
977
978 ret = get_srq_wqe_idx(srq, &wqe_idx);
979 if (unlikely(ret)) {
980 *bad_wr = wr;
981 break;
982 }
983
984 wqe = get_srq_wqe_buf(srq, wqe_idx);
985 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge);
986 fill_wqe_idx(srq, wqe_idx);
987 srq->wrid[wqe_idx] = wr->wr_id;
988 }
989
990 if (likely(nreq)) {
991 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB)
992 *srq->rdb.db_record = srq->idx_que.head &
993 V2_DB_PRODUCER_IDX_M;
994 else
995 update_srq_db(srq);
996 }
997
998 spin_unlock_irqrestore(&srq->lock, flags);
999
1000 return ret;
1001}
1002
1003static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
1004 unsigned long instance_stage,
1005 unsigned long reset_stage)
1006{
1007 /* When hardware reset has been completed once or more, we should stop
1008 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
1009 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
1010 * stage of soft reset process, we should exit with error, and then
1011 * HNAE3_INIT_CLIENT related process can rollback the operation like
1012 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
1013 * process will exit with error to notify NIC driver to reschedule soft
1014 * reset process once again.
1015 */
1016 hr_dev->is_reset = true;
1017 hr_dev->dis_db = true;
1018
1019 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
1020 instance_stage == HNS_ROCE_STATE_INIT)
1021 return CMD_RST_PRC_EBUSY;
1022
1023 return CMD_RST_PRC_SUCCESS;
1024}
1025
1026static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
1027 unsigned long instance_stage,
1028 unsigned long reset_stage)
1029{
1030#define HW_RESET_TIMEOUT_US 1000000
1031#define HW_RESET_SLEEP_US 1000
1032
1033 struct hns_roce_v2_priv *priv = hr_dev->priv;
1034 struct hnae3_handle *handle = priv->handle;
1035 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1036 unsigned long val;
1037 int ret;
1038
1039 /* When hardware reset is detected, we should stop sending mailbox&cmq&
1040 * doorbell to hardware. If now in .init_instance() function, we should
1041 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
1042 * process, we should exit with error, and then HNAE3_INIT_CLIENT
1043 * related process can rollback the operation like notifing hardware to
1044 * free resources, HNAE3_INIT_CLIENT related process will exit with
1045 * error to notify NIC driver to reschedule soft reset process once
1046 * again.
1047 */
1048 hr_dev->dis_db = true;
1049
1050 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val,
1051 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US,
1052 HW_RESET_TIMEOUT_US, false, handle);
1053 if (!ret)
1054 hr_dev->is_reset = true;
1055
1056 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
1057 instance_stage == HNS_ROCE_STATE_INIT)
1058 return CMD_RST_PRC_EBUSY;
1059
1060 return CMD_RST_PRC_SUCCESS;
1061}
1062
1063static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
1064{
1065 struct hns_roce_v2_priv *priv = hr_dev->priv;
1066 struct hnae3_handle *handle = priv->handle;
1067 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1068
1069 /* When software reset is detected at .init_instance() function, we
1070 * should stop sending mailbox&cmq&doorbell to hardware, and exit
1071 * with error.
1072 */
1073 hr_dev->dis_db = true;
1074 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
1075 hr_dev->is_reset = true;
1076
1077 return CMD_RST_PRC_EBUSY;
1078}
1079
1080static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev,
1081 struct hnae3_handle *handle)
1082{
1083 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1084 unsigned long instance_stage; /* the current instance stage */
1085 unsigned long reset_stage; /* the current reset stage */
1086 unsigned long reset_cnt;
1087 bool sw_resetting;
1088 bool hw_resetting;
1089
1090 /* Get information about reset from NIC driver or RoCE driver itself,
1091 * the meaning of the following variables from NIC driver are described
1092 * as below:
1093 * reset_cnt -- The count value of completed hardware reset.
1094 * hw_resetting -- Whether hardware device is resetting now.
1095 * sw_resetting -- Whether NIC's software reset process is running now.
1096 */
1097 instance_stage = handle->rinfo.instance_state;
1098 reset_stage = handle->rinfo.reset_state;
1099 reset_cnt = ops->ae_dev_reset_cnt(handle);
1100 if (reset_cnt != hr_dev->reset_cnt)
1101 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
1102 reset_stage);
1103
1104 hw_resetting = ops->get_cmdq_stat(handle);
1105 if (hw_resetting)
1106 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
1107 reset_stage);
1108
1109 sw_resetting = ops->ae_dev_resetting(handle);
1110 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
1111 return hns_roce_v2_cmd_sw_resetting(hr_dev);
1112
1113 return CMD_RST_PRC_OTHERS;
1114}
1115
1116static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev)
1117{
1118 struct hns_roce_v2_priv *priv = hr_dev->priv;
1119 struct hnae3_handle *handle = priv->handle;
1120 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1121
1122 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle))
1123 return true;
1124
1125 if (ops->get_hw_reset_stat(handle))
1126 return true;
1127
1128 if (ops->ae_dev_resetting(handle))
1129 return true;
1130
1131 return false;
1132}
1133
1134static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy)
1135{
1136 struct hns_roce_v2_priv *priv = hr_dev->priv;
1137 u32 status;
1138
1139 if (hr_dev->is_reset)
1140 status = CMD_RST_PRC_SUCCESS;
1141 else
1142 status = check_aedev_reset_status(hr_dev, priv->handle);
1143
1144 *busy = (status == CMD_RST_PRC_EBUSY);
1145
1146 return status == CMD_RST_PRC_OTHERS;
1147}
1148
1149static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
1150 struct hns_roce_v2_cmq_ring *ring)
1151{
1152 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
1153
1154 ring->desc = dma_alloc_coherent(hr_dev->dev, size,
1155 &ring->desc_dma_addr, GFP_KERNEL);
1156 if (!ring->desc)
1157 return -ENOMEM;
1158
1159 return 0;
1160}
1161
1162static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
1163 struct hns_roce_v2_cmq_ring *ring)
1164{
1165 dma_free_coherent(hr_dev->dev,
1166 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
1167 ring->desc, ring->desc_dma_addr);
1168
1169 ring->desc_dma_addr = 0;
1170}
1171
1172static int init_csq(struct hns_roce_dev *hr_dev,
1173 struct hns_roce_v2_cmq_ring *csq)
1174{
1175 dma_addr_t dma;
1176 int ret;
1177
1178 csq->desc_num = CMD_CSQ_DESC_NUM;
1179 spin_lock_init(&csq->lock);
1180 csq->flag = TYPE_CSQ;
1181 csq->head = 0;
1182
1183 ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1184 if (ret)
1185 return ret;
1186
1187 dma = csq->desc_dma_addr;
1188 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
1189 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
1190 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1191 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1192
1193 /* Make sure to write CI first and then PI */
1194 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1195 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1196
1197 return 0;
1198}
1199
1200static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1201{
1202 struct hns_roce_v2_priv *priv = hr_dev->priv;
1203 int ret;
1204
1205 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1206
1207 ret = init_csq(hr_dev, &priv->cmq.csq);
1208 if (ret)
1209 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
1210
1211 return ret;
1212}
1213
1214static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1215{
1216 struct hns_roce_v2_priv *priv = hr_dev->priv;
1217
1218 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1219}
1220
1221static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1222 enum hns_roce_opcode_type opcode,
1223 bool is_read)
1224{
1225 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1226 desc->opcode = cpu_to_le16(opcode);
1227 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1228 if (is_read)
1229 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1230 else
1231 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1232}
1233
1234static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1235{
1236 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1237 struct hns_roce_v2_priv *priv = hr_dev->priv;
1238
1239 return tail == priv->cmq.csq.head;
1240}
1241
1242static void update_cmdq_status(struct hns_roce_dev *hr_dev)
1243{
1244 struct hns_roce_v2_priv *priv = hr_dev->priv;
1245 struct hnae3_handle *handle = priv->handle;
1246
1247 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
1248 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT)
1249 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR;
1250}
1251
1252static int hns_roce_cmd_err_convert_errno(u16 desc_ret)
1253{
1254 struct hns_roce_cmd_errcode errcode_table[] = {
1255 {CMD_EXEC_SUCCESS, 0},
1256 {CMD_NO_AUTH, -EPERM},
1257 {CMD_NOT_EXIST, -EOPNOTSUPP},
1258 {CMD_CRQ_FULL, -EXFULL},
1259 {CMD_NEXT_ERR, -ENOSR},
1260 {CMD_NOT_EXEC, -ENOTBLK},
1261 {CMD_PARA_ERR, -EINVAL},
1262 {CMD_RESULT_ERR, -ERANGE},
1263 {CMD_TIMEOUT, -ETIME},
1264 {CMD_HILINK_ERR, -ENOLINK},
1265 {CMD_INFO_ILLEGAL, -ENXIO},
1266 {CMD_INVALID, -EBADR},
1267 };
1268 u16 i;
1269
1270 for (i = 0; i < ARRAY_SIZE(errcode_table); i++)
1271 if (desc_ret == errcode_table[i].return_status)
1272 return errcode_table[i].errno;
1273 return -EIO;
1274}
1275
1276static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1277 struct hns_roce_cmq_desc *desc, int num)
1278{
1279 struct hns_roce_v2_priv *priv = hr_dev->priv;
1280 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1281 u32 timeout = 0;
1282 u16 desc_ret;
1283 u32 tail;
1284 int ret;
1285 int i;
1286
1287 spin_lock_bh(&csq->lock);
1288
1289 tail = csq->head;
1290
1291 for (i = 0; i < num; i++) {
1292 csq->desc[csq->head++] = desc[i];
1293 if (csq->head == csq->desc_num)
1294 csq->head = 0;
1295 }
1296
1297 /* Write to hardware */
1298 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);
1299
1300 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]);
1301
1302 do {
1303 if (hns_roce_cmq_csq_done(hr_dev))
1304 break;
1305 udelay(1);
1306 } while (++timeout < priv->cmq.tx_timeout);
1307
1308 if (hns_roce_cmq_csq_done(hr_dev)) {
1309 ret = 0;
1310 for (i = 0; i < num; i++) {
1311 /* check the result of hardware write back */
1312 desc[i] = csq->desc[tail++];
1313 if (tail == csq->desc_num)
1314 tail = 0;
1315
1316 desc_ret = le16_to_cpu(desc[i].retval);
1317 if (likely(desc_ret == CMD_EXEC_SUCCESS))
1318 continue;
1319
1320 dev_err_ratelimited(hr_dev->dev,
1321 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n",
1322 desc->opcode, desc_ret);
1323 ret = hns_roce_cmd_err_convert_errno(desc_ret);
1324 }
1325 } else {
1326 /* FW/HW reset or incorrect number of desc */
1327 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG);
1328 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n",
1329 csq->head, tail);
1330 csq->head = tail;
1331
1332 update_cmdq_status(hr_dev);
1333
1334 ret = -EAGAIN;
1335 }
1336
1337 spin_unlock_bh(&csq->lock);
1338
1339 if (ret)
1340 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]);
1341
1342 return ret;
1343}
1344
1345static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1346 struct hns_roce_cmq_desc *desc, int num)
1347{
1348 bool busy;
1349 int ret;
1350
1351 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1352 return -EIO;
1353
1354 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1355 return busy ? -EBUSY : 0;
1356
1357 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1358 if (ret) {
1359 if (!v2_chk_mbox_is_avail(hr_dev, &busy))
1360 return busy ? -EBUSY : 0;
1361 }
1362
1363 return ret;
1364}
1365
1366static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev,
1367 dma_addr_t base_addr, u8 cmd, unsigned long tag)
1368{
1369 struct hns_roce_cmd_mailbox *mbox;
1370 int ret;
1371
1372 mbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1373 if (IS_ERR(mbox))
1374 return PTR_ERR(mbox);
1375
1376 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag);
1377 hns_roce_free_cmd_mailbox(hr_dev, mbox);
1378 return ret;
1379}
1380
1381static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
1382{
1383 struct hns_roce_query_version *resp;
1384 struct hns_roce_cmq_desc desc;
1385 int ret;
1386
1387 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1388 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1389 if (ret)
1390 return ret;
1391
1392 resp = (struct hns_roce_query_version *)desc.data;
1393 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
1394 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1395
1396 return 0;
1397}
1398
1399static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev,
1400 struct hnae3_handle *handle)
1401{
1402 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1403 unsigned long end;
1404
1405 hr_dev->dis_db = true;
1406
1407 dev_warn(hr_dev->dev,
1408 "func clear is pending, device in resetting state.\n");
1409 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1410 while (end) {
1411 if (!ops->get_hw_reset_stat(handle)) {
1412 hr_dev->is_reset = true;
1413 dev_info(hr_dev->dev,
1414 "func clear success after reset.\n");
1415 return;
1416 }
1417 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1418 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1419 }
1420
1421 dev_warn(hr_dev->dev, "func clear failed.\n");
1422}
1423
1424static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev,
1425 struct hnae3_handle *handle)
1426{
1427 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1428 unsigned long end;
1429
1430 hr_dev->dis_db = true;
1431
1432 dev_warn(hr_dev->dev,
1433 "func clear is pending, device in resetting state.\n");
1434 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1435 while (end) {
1436 if (ops->ae_dev_reset_cnt(handle) !=
1437 hr_dev->reset_cnt) {
1438 hr_dev->is_reset = true;
1439 dev_info(hr_dev->dev,
1440 "func clear success after sw reset\n");
1441 return;
1442 }
1443 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1444 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1445 }
1446
1447 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n");
1448}
1449
1450static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval,
1451 int flag)
1452{
1453 struct hns_roce_v2_priv *priv = hr_dev->priv;
1454 struct hnae3_handle *handle = priv->handle;
1455 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1456
1457 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) {
1458 hr_dev->dis_db = true;
1459 hr_dev->is_reset = true;
1460 dev_info(hr_dev->dev, "func clear success after reset.\n");
1461 return;
1462 }
1463
1464 if (ops->get_hw_reset_stat(handle)) {
1465 func_clr_hw_resetting_state(hr_dev, handle);
1466 return;
1467 }
1468
1469 if (ops->ae_dev_resetting(handle) &&
1470 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) {
1471 func_clr_sw_resetting_state(hr_dev, handle);
1472 return;
1473 }
1474
1475 if (retval && !flag)
1476 dev_warn(hr_dev->dev,
1477 "func clear read failed, ret = %d.\n", retval);
1478
1479 dev_warn(hr_dev->dev, "func clear failed.\n");
1480}
1481
1482static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id)
1483{
1484 bool fclr_write_fail_flag = false;
1485 struct hns_roce_func_clear *resp;
1486 struct hns_roce_cmq_desc desc;
1487 unsigned long end;
1488 int ret = 0;
1489
1490 if (check_device_is_in_reset(hr_dev))
1491 goto out;
1492
1493 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1494 resp = (struct hns_roce_func_clear *)desc.data;
1495 resp->rst_funcid_en = cpu_to_le32(vf_id);
1496
1497 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1498 if (ret) {
1499 fclr_write_fail_flag = true;
1500 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n",
1501 ret);
1502 goto out;
1503 }
1504
1505 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1506 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1507 while (end) {
1508 if (check_device_is_in_reset(hr_dev))
1509 goto out;
1510 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1511 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1512
1513 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1514 true);
1515
1516 resp->rst_funcid_en = cpu_to_le32(vf_id);
1517 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1518 if (ret)
1519 continue;
1520
1521 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) {
1522 if (vf_id == 0)
1523 hr_dev->is_reset = true;
1524 return;
1525 }
1526 }
1527
1528out:
1529 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag);
1530}
1531
1532static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id)
1533{
1534 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1535 struct hns_roce_cmq_desc desc[2];
1536 struct hns_roce_cmq_req *req_a;
1537
1538 req_a = (struct hns_roce_cmq_req *)desc[0].data;
1539 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1540 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1541 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1542 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id);
1543
1544 return hns_roce_cmq_send(hr_dev, desc, 2);
1545}
1546
1547static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1548{
1549 int ret;
1550 int i;
1551
1552 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
1553 return;
1554
1555 for (i = hr_dev->func_num - 1; i >= 0; i--) {
1556 __hns_roce_function_clear(hr_dev, i);
1557
1558 if (i == 0)
1559 continue;
1560
1561 ret = hns_roce_free_vf_resource(hr_dev, i);
1562 if (ret)
1563 ibdev_err(&hr_dev->ib_dev,
1564 "failed to free vf resource, vf_id = %d, ret = %d.\n",
1565 i, ret);
1566 }
1567}
1568
1569static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev)
1570{
1571 struct hns_roce_cmq_desc desc;
1572 int ret;
1573
1574 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO,
1575 false);
1576 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1577 if (ret)
1578 ibdev_err(&hr_dev->ib_dev,
1579 "failed to clear extended doorbell info, ret = %d.\n",
1580 ret);
1581
1582 return ret;
1583}
1584
1585static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1586{
1587 struct hns_roce_query_fw_info *resp;
1588 struct hns_roce_cmq_desc desc;
1589 int ret;
1590
1591 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1592 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1593 if (ret)
1594 return ret;
1595
1596 resp = (struct hns_roce_query_fw_info *)desc.data;
1597 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
1598
1599 return 0;
1600}
1601
1602static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev)
1603{
1604 struct hns_roce_cmq_desc desc;
1605 int ret;
1606
1607 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
1608 hr_dev->func_num = 1;
1609 return 0;
1610 }
1611
1612 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO,
1613 true);
1614 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1615 if (ret) {
1616 hr_dev->func_num = 1;
1617 return ret;
1618 }
1619
1620 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num);
1621 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id);
1622
1623 return 0;
1624}
1625
1626static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev,
1627 u64 *stats, u32 port, int *num_counters)
1628{
1629#define CNT_PER_DESC 3
1630 struct hns_roce_cmq_desc *desc;
1631 int bd_idx, cnt_idx;
1632 __le64 *cnt_data;
1633 int desc_num;
1634 int ret;
1635 int i;
1636
1637 if (port > hr_dev->caps.num_ports)
1638 return -EINVAL;
1639
1640 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC);
1641 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL);
1642 if (!desc)
1643 return -ENOMEM;
1644
1645 for (i = 0; i < desc_num; i++) {
1646 hns_roce_cmq_setup_basic_desc(&desc[i],
1647 HNS_ROCE_OPC_QUERY_COUNTER, true);
1648 if (i != desc_num - 1)
1649 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1650 }
1651
1652 ret = hns_roce_cmq_send(hr_dev, desc, desc_num);
1653 if (ret) {
1654 ibdev_err(&hr_dev->ib_dev,
1655 "failed to get counter, ret = %d.\n", ret);
1656 goto err_out;
1657 }
1658
1659 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) {
1660 bd_idx = i / CNT_PER_DESC;
1661 if (!(desc[bd_idx].flag & HNS_ROCE_CMD_FLAG_NEXT) &&
1662 bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC)
1663 break;
1664
1665 cnt_data = (__le64 *)&desc[bd_idx].data[0];
1666 cnt_idx = i % CNT_PER_DESC;
1667 stats[i] = le64_to_cpu(cnt_data[cnt_idx]);
1668 }
1669 *num_counters = i;
1670
1671err_out:
1672 kfree(desc);
1673 return ret;
1674}
1675
1676static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1677{
1678 struct hns_roce_cmq_desc desc;
1679 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1680 u32 clock_cycles_of_1us;
1681
1682 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1683 false);
1684
1685 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
1686 clock_cycles_of_1us = HNS_ROCE_1NS_CFG;
1687 else
1688 clock_cycles_of_1us = HNS_ROCE_1US_CFG;
1689
1690 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us);
1691 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT);
1692
1693 return hns_roce_cmq_send(hr_dev, &desc, 1);
1694}
1695
1696static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf)
1697{
1698 struct hns_roce_cmq_desc desc[2];
1699 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1700 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1701 struct hns_roce_caps *caps = &hr_dev->caps;
1702 enum hns_roce_opcode_type opcode;
1703 u32 func_num;
1704 int ret;
1705
1706 if (is_vf) {
1707 opcode = HNS_ROCE_OPC_QUERY_VF_RES;
1708 func_num = 1;
1709 } else {
1710 opcode = HNS_ROCE_OPC_QUERY_PF_RES;
1711 func_num = hr_dev->func_num;
1712 }
1713
1714 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true);
1715 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1716 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true);
1717
1718 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1719 if (ret)
1720 return ret;
1721
1722 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num;
1723 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num;
1724 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num;
1725 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num;
1726 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num;
1727 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num;
1728 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num;
1729 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num;
1730
1731 if (is_vf) {
1732 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num;
1733 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) /
1734 func_num;
1735 } else {
1736 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num;
1737 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) /
1738 func_num;
1739 }
1740
1741 return 0;
1742}
1743
1744static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev)
1745{
1746 struct hns_roce_cmq_desc desc;
1747 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1748 struct hns_roce_caps *caps = &hr_dev->caps;
1749 int ret;
1750
1751 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1752 true);
1753
1754 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1755 if (ret)
1756 return ret;
1757
1758 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM);
1759 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM);
1760
1761 return 0;
1762}
1763
1764static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1765{
1766 struct device *dev = hr_dev->dev;
1767 int ret;
1768
1769 ret = load_func_res_caps(hr_dev, false);
1770 if (ret) {
1771 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret);
1772 return ret;
1773 }
1774
1775 ret = load_pf_timer_res_caps(hr_dev);
1776 if (ret)
1777 dev_err(dev, "failed to load pf timer resource, ret = %d.\n",
1778 ret);
1779
1780 return ret;
1781}
1782
1783static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)
1784{
1785 struct device *dev = hr_dev->dev;
1786 int ret;
1787
1788 ret = load_func_res_caps(hr_dev, true);
1789 if (ret)
1790 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret);
1791
1792 return ret;
1793}
1794
1795static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1796 u32 vf_id)
1797{
1798 struct hns_roce_vf_switch *swt;
1799 struct hns_roce_cmq_desc desc;
1800 int ret;
1801
1802 swt = (struct hns_roce_vf_switch *)desc.data;
1803 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1804 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1805 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id);
1806 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1807 if (ret)
1808 return ret;
1809
1810 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);
1811 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1812 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK);
1813 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK);
1814 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD);
1815
1816 return hns_roce_cmq_send(hr_dev, &desc, 1);
1817}
1818
1819static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev)
1820{
1821 u32 vf_id;
1822 int ret;
1823
1824 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) {
1825 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id);
1826 if (ret)
1827 return ret;
1828 }
1829 return 0;
1830}
1831
1832static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id)
1833{
1834 struct hns_roce_cmq_desc desc[2];
1835 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
1836 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
1837 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES;
1838 struct hns_roce_caps *caps = &hr_dev->caps;
1839
1840 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
1841 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1842 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
1843
1844 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id);
1845
1846 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num);
1847 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num);
1848 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num);
1849 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num);
1850 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num);
1851 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num);
1852 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num);
1853 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num);
1854 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num);
1855 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num);
1856 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num);
1857 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num);
1858 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num);
1859 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num);
1860
1861 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1862 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num);
1863 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX,
1864 vf_id * caps->gmv_bt_num);
1865 } else {
1866 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num);
1867 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX,
1868 vf_id * caps->sgid_bt_num);
1869 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num);
1870 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX,
1871 vf_id * caps->smac_bt_num);
1872 }
1873
1874 return hns_roce_cmq_send(hr_dev, desc, 2);
1875}
1876
1877static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1878{
1879 u32 func_num = max_t(u32, 1, hr_dev->func_num);
1880 u32 vf_id;
1881 int ret;
1882
1883 for (vf_id = 0; vf_id < func_num; vf_id++) {
1884 ret = config_vf_hem_resource(hr_dev, vf_id);
1885 if (ret) {
1886 dev_err(hr_dev->dev,
1887 "failed to config vf-%u hem res, ret = %d.\n",
1888 vf_id, ret);
1889 return ret;
1890 }
1891 }
1892
1893 return 0;
1894}
1895
1896static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1897{
1898 struct hns_roce_cmq_desc desc;
1899 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
1900 struct hns_roce_caps *caps = &hr_dev->caps;
1901
1902 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1903
1904 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ,
1905 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET);
1906 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ,
1907 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET);
1908 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM,
1909 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps));
1910
1911 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ,
1912 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET);
1913 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ,
1914 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET);
1915 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM,
1916 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs));
1917
1918 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ,
1919 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET);
1920 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ,
1921 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET);
1922 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM,
1923 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs));
1924
1925 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ,
1926 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET);
1927 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ,
1928 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET);
1929 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM,
1930 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts));
1931
1932 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ,
1933 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1934 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ,
1935 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1936 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM,
1937 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps));
1938
1939 return hns_roce_cmq_send(hr_dev, &desc, 1);
1940}
1941
1942static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,
1943 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)
1944{
1945 u64 obj_per_chunk;
1946 u64 bt_chunk_size = PAGE_SIZE;
1947 u64 buf_chunk_size = PAGE_SIZE;
1948 u64 obj_per_chunk_default = buf_chunk_size / obj_size;
1949
1950 *buf_page_size = 0;
1951 *bt_page_size = 0;
1952
1953 switch (hop_num) {
1954 case 3:
1955 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1956 (bt_chunk_size / BA_BYTE_LEN) *
1957 (bt_chunk_size / BA_BYTE_LEN) *
1958 obj_per_chunk_default;
1959 break;
1960 case 2:
1961 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1962 (bt_chunk_size / BA_BYTE_LEN) *
1963 obj_per_chunk_default;
1964 break;
1965 case 1:
1966 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1967 obj_per_chunk_default;
1968 break;
1969 case HNS_ROCE_HOP_NUM_0:
1970 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
1971 break;
1972 default:
1973 pr_err("table %u not support hop_num = %u!\n", hem_type,
1974 hop_num);
1975 return;
1976 }
1977
1978 if (hem_type >= HEM_TYPE_MTT)
1979 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1980 else
1981 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1982}
1983
1984static void set_hem_page_size(struct hns_roce_dev *hr_dev)
1985{
1986 struct hns_roce_caps *caps = &hr_dev->caps;
1987
1988 /* EQ */
1989 caps->eqe_ba_pg_sz = 0;
1990 caps->eqe_buf_pg_sz = 0;
1991
1992 /* Link Table */
1993 caps->llm_buf_pg_sz = 0;
1994
1995 /* MR */
1996 caps->mpt_ba_pg_sz = 0;
1997 caps->mpt_buf_pg_sz = 0;
1998 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
1999 caps->pbl_buf_pg_sz = 0;
2000 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
2001 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
2002 HEM_TYPE_MTPT);
2003
2004 /* QP */
2005 caps->qpc_ba_pg_sz = 0;
2006 caps->qpc_buf_pg_sz = 0;
2007 caps->qpc_timer_ba_pg_sz = 0;
2008 caps->qpc_timer_buf_pg_sz = 0;
2009 caps->sccc_ba_pg_sz = 0;
2010 caps->sccc_buf_pg_sz = 0;
2011 caps->mtt_ba_pg_sz = 0;
2012 caps->mtt_buf_pg_sz = 0;
2013 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
2014 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2015 HEM_TYPE_QPC);
2016
2017 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
2018 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num,
2019 caps->sccc_bt_num, &caps->sccc_buf_pg_sz,
2020 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC);
2021
2022 /* CQ */
2023 caps->cqc_ba_pg_sz = 0;
2024 caps->cqc_buf_pg_sz = 0;
2025 caps->cqc_timer_ba_pg_sz = 0;
2026 caps->cqc_timer_buf_pg_sz = 0;
2027 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
2028 caps->cqe_buf_pg_sz = 0;
2029 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2030 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2031 HEM_TYPE_CQC);
2032 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num,
2033 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2034
2035 /* SRQ */
2036 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) {
2037 caps->srqc_ba_pg_sz = 0;
2038 caps->srqc_buf_pg_sz = 0;
2039 caps->srqwqe_ba_pg_sz = 0;
2040 caps->srqwqe_buf_pg_sz = 0;
2041 caps->idx_ba_pg_sz = 0;
2042 caps->idx_buf_pg_sz = 0;
2043 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz,
2044 caps->srqc_hop_num, caps->srqc_bt_num,
2045 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz,
2046 HEM_TYPE_SRQC);
2047 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2048 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2049 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2050 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz,
2051 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz,
2052 &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2053 }
2054
2055 /* GMV */
2056 caps->gmv_ba_pg_sz = 0;
2057 caps->gmv_buf_pg_sz = 0;
2058}
2059
2060/* Apply all loaded caps before setting to hardware */
2061static void apply_func_caps(struct hns_roce_dev *hr_dev)
2062{
2063#define MAX_GID_TBL_LEN 256
2064 struct hns_roce_caps *caps = &hr_dev->caps;
2065 struct hns_roce_v2_priv *priv = hr_dev->priv;
2066
2067 /* The following configurations don't need to be got from firmware. */
2068 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
2069 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
2070 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
2071
2072 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
2073 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2074 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2075
2076 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
2077 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
2078
2079 if (!caps->num_comp_vectors)
2080 caps->num_comp_vectors =
2081 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM,
2082 (u32)priv->handle->rinfo.num_vectors -
2083 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM));
2084
2085 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
2086 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
2087 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
2088 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
2089
2090 /* The following configurations will be overwritten */
2091 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
2092 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
2093 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;
2094
2095 /* The following configurations are not got from firmware */
2096 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ;
2097
2098 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0;
2099
2100 /* It's meaningless to support excessively large gid_table_len,
2101 * as the type of sgid_index in kernel struct ib_global_route
2102 * and userspace struct ibv_global_route are u8/uint8_t (0-255).
2103 */
2104 caps->gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN,
2105 caps->gmv_bt_num *
2106 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz));
2107
2108 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE /
2109 caps->gmv_entry_sz);
2110 } else {
2111 u32 func_num = max_t(u32, 1, hr_dev->func_num);
2112
2113 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM;
2114 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
2115 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
2116 caps->gid_table_len[0] /= func_num;
2117 }
2118
2119 if (hr_dev->is_vf) {
2120 caps->default_aeq_arm_st = 0x3;
2121 caps->default_ceq_arm_st = 0x3;
2122 caps->default_ceq_max_cnt = 0x1;
2123 caps->default_ceq_period = 0x10;
2124 caps->default_aeq_max_cnt = 0x1;
2125 caps->default_aeq_period = 0x10;
2126 }
2127
2128 set_hem_page_size(hr_dev);
2129}
2130
2131static int hns_roce_query_caps(struct hns_roce_dev *hr_dev)
2132{
2133 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
2134 struct hns_roce_caps *caps = &hr_dev->caps;
2135 struct hns_roce_query_pf_caps_a *resp_a;
2136 struct hns_roce_query_pf_caps_b *resp_b;
2137 struct hns_roce_query_pf_caps_c *resp_c;
2138 struct hns_roce_query_pf_caps_d *resp_d;
2139 struct hns_roce_query_pf_caps_e *resp_e;
2140 enum hns_roce_opcode_type cmd;
2141 int ctx_hop_num;
2142 int pbl_hop_num;
2143 int ret;
2144 int i;
2145
2146 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM :
2147 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM;
2148
2149 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
2150 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true);
2151 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
2152 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2153 else
2154 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2155 }
2156
2157 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
2158 if (ret)
2159 return ret;
2160
2161 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
2162 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
2163 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
2164 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
2165 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
2166
2167 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
2168 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
2169 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
2170 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
2171 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
2172 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
2173 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
2174 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
2175 caps->num_other_vectors = resp_a->num_other_vectors;
2176 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
2177 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
2178
2179 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
2180 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
2181 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
2182 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
2183 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
2184 caps->idx_entry_sz = resp_b->idx_entry_sz;
2185 caps->sccc_sz = resp_b->sccc_sz;
2186 caps->max_mtu = resp_b->max_mtu;
2187 caps->min_cqes = resp_b->min_cqes;
2188 caps->min_wqes = resp_b->min_wqes;
2189 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
2190 caps->pkey_table_len[0] = resp_b->pkey_table_len;
2191 caps->phy_num_uars = resp_b->phy_num_uars;
2192 ctx_hop_num = resp_b->ctx_hop_num;
2193 pbl_hop_num = resp_b->pbl_hop_num;
2194
2195 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS);
2196
2197 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS);
2198 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
2199 HNS_ROCE_CAP_FLAGS_EX_SHIFT;
2200
2201 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS);
2202 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID);
2203 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH);
2204 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS);
2205 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS);
2206 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS);
2207 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD);
2208 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
2209 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
2210
2211 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS);
2212 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE);
2213 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
2214 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);
2215 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);
2216 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);
2217 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);
2218 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);
2219 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);
2220 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS);
2221
2222 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS);
2223 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT);
2224 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);
2225 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS);
2226 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);
2227 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);
2228
2229 caps->qpc_hop_num = ctx_hop_num;
2230 caps->sccc_hop_num = ctx_hop_num;
2231 caps->srqc_hop_num = ctx_hop_num;
2232 caps->cqc_hop_num = ctx_hop_num;
2233 caps->mpt_hop_num = ctx_hop_num;
2234 caps->mtt_hop_num = pbl_hop_num;
2235 caps->cqe_hop_num = pbl_hop_num;
2236 caps->srqwqe_hop_num = pbl_hop_num;
2237 caps->idx_hop_num = pbl_hop_num;
2238 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM);
2239 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM);
2240 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM);
2241
2242 if (!(caps->page_size_cap & PAGE_SIZE))
2243 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
2244
2245 if (!hr_dev->is_vf) {
2246 caps->cqe_sz = resp_a->cqe_sz;
2247 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz);
2248 caps->default_aeq_arm_st =
2249 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);
2250 caps->default_ceq_arm_st =
2251 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);
2252 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
2253 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
2254 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
2255 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
2256 }
2257
2258 return 0;
2259}
2260
2261static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val)
2262{
2263 struct hns_roce_cmq_desc desc;
2264 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
2265
2266 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2267 false);
2268
2269 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type);
2270 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val);
2271
2272 return hns_roce_cmq_send(hr_dev, &desc, 1);
2273}
2274
2275static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2276{
2277 struct hns_roce_caps *caps = &hr_dev->caps;
2278 int ret;
2279
2280 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
2281 return 0;
2282
2283 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE,
2284 caps->qpc_sz);
2285 if (ret) {
2286 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2287 return ret;
2288 }
2289
2290 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE,
2291 caps->sccc_sz);
2292 if (ret)
2293 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);
2294
2295 return ret;
2296}
2297
2298static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev)
2299{
2300 struct device *dev = hr_dev->dev;
2301 int ret;
2302
2303 hr_dev->func_num = 1;
2304
2305 ret = hns_roce_query_caps(hr_dev);
2306 if (ret) {
2307 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret);
2308 return ret;
2309 }
2310
2311 ret = hns_roce_query_vf_resource(hr_dev);
2312 if (ret) {
2313 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret);
2314 return ret;
2315 }
2316
2317 apply_func_caps(hr_dev);
2318
2319 ret = hns_roce_v2_set_bt(hr_dev);
2320 if (ret)
2321 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret);
2322
2323 return ret;
2324}
2325
2326static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev)
2327{
2328 struct device *dev = hr_dev->dev;
2329 int ret;
2330
2331 ret = hns_roce_query_func_info(hr_dev);
2332 if (ret) {
2333 dev_err(dev, "failed to query func info, ret = %d.\n", ret);
2334 return ret;
2335 }
2336
2337 ret = hns_roce_config_global_param(hr_dev);
2338 if (ret) {
2339 dev_err(dev, "failed to config global param, ret = %d.\n", ret);
2340 return ret;
2341 }
2342
2343 ret = hns_roce_set_vf_switch_param(hr_dev);
2344 if (ret) {
2345 dev_err(dev, "failed to set switch param, ret = %d.\n", ret);
2346 return ret;
2347 }
2348
2349 ret = hns_roce_query_caps(hr_dev);
2350 if (ret) {
2351 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret);
2352 return ret;
2353 }
2354
2355 ret = hns_roce_query_pf_resource(hr_dev);
2356 if (ret) {
2357 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret);
2358 return ret;
2359 }
2360
2361 apply_func_caps(hr_dev);
2362
2363 ret = hns_roce_alloc_vf_resource(hr_dev);
2364 if (ret) {
2365 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret);
2366 return ret;
2367 }
2368
2369 ret = hns_roce_v2_set_bt(hr_dev);
2370 if (ret) {
2371 dev_err(dev, "failed to config BA table, ret = %d.\n", ret);
2372 return ret;
2373 }
2374
2375 /* Configure the size of QPC, SCCC, etc. */
2376 return hns_roce_config_entry_size(hr_dev);
2377}
2378
2379static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2380{
2381 struct device *dev = hr_dev->dev;
2382 int ret;
2383
2384 ret = hns_roce_cmq_query_hw_info(hr_dev);
2385 if (ret) {
2386 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret);
2387 return ret;
2388 }
2389
2390 ret = hns_roce_query_fw_ver(hr_dev);
2391 if (ret) {
2392 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret);
2393 return ret;
2394 }
2395
2396 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2397 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
2398
2399 if (hr_dev->is_vf)
2400 return hns_roce_v2_vf_profile(hr_dev);
2401 else
2402 return hns_roce_v2_pf_profile(hr_dev);
2403}
2404
2405static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf)
2406{
2407 u32 i, next_ptr, page_num;
2408 __le64 *entry = cfg_buf;
2409 dma_addr_t addr;
2410 u64 val;
2411
2412 page_num = data_buf->npages;
2413 for (i = 0; i < page_num; i++) {
2414 addr = hns_roce_buf_page(data_buf, i);
2415 if (i == (page_num - 1))
2416 next_ptr = 0;
2417 else
2418 next_ptr = i + 1;
2419
2420 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr);
2421 entry[i] = cpu_to_le64(val);
2422 }
2423}
2424
2425static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev,
2426 struct hns_roce_link_table *table)
2427{
2428 struct hns_roce_cmq_desc desc[2];
2429 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data;
2430 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data;
2431 struct hns_roce_buf *buf = table->buf;
2432 enum hns_roce_opcode_type opcode;
2433 dma_addr_t addr;
2434
2435 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2436 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false);
2437 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2438 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false);
2439
2440 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map));
2441 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map));
2442 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages);
2443 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift));
2444 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN);
2445
2446 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0));
2447 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr));
2448 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr));
2449 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1);
2450 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0);
2451
2452 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1));
2453 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr));
2454 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr));
2455 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1);
2456
2457 return hns_roce_cmq_send(hr_dev, desc, 2);
2458}
2459
2460static struct hns_roce_link_table *
2461alloc_link_table_buf(struct hns_roce_dev *hr_dev)
2462{
2463 struct hns_roce_v2_priv *priv = hr_dev->priv;
2464 struct hns_roce_link_table *link_tbl;
2465 u32 pg_shift, size, min_size;
2466
2467 link_tbl = &priv->ext_llm;
2468 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;
2469 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;
2470 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift;
2471
2472 /* Alloc data table */
2473 size = max(size, min_size);
2474 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0);
2475 if (IS_ERR(link_tbl->buf))
2476 return ERR_PTR(-ENOMEM);
2477
2478 /* Alloc config table */
2479 size = link_tbl->buf->npages * sizeof(u64);
2480 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size,
2481 &link_tbl->table.map,
2482 GFP_KERNEL);
2483 if (!link_tbl->table.buf) {
2484 hns_roce_buf_free(hr_dev, link_tbl->buf);
2485 return ERR_PTR(-ENOMEM);
2486 }
2487
2488 return link_tbl;
2489}
2490
2491static void free_link_table_buf(struct hns_roce_dev *hr_dev,
2492 struct hns_roce_link_table *tbl)
2493{
2494 if (tbl->buf) {
2495 u32 size = tbl->buf->npages * sizeof(u64);
2496
2497 dma_free_coherent(hr_dev->dev, size, tbl->table.buf,
2498 tbl->table.map);
2499 }
2500
2501 hns_roce_buf_free(hr_dev, tbl->buf);
2502}
2503
2504static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev)
2505{
2506 struct hns_roce_link_table *link_tbl;
2507 int ret;
2508
2509 link_tbl = alloc_link_table_buf(hr_dev);
2510 if (IS_ERR(link_tbl))
2511 return -ENOMEM;
2512
2513 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) {
2514 ret = -EINVAL;
2515 goto err_alloc;
2516 }
2517
2518 config_llm_table(link_tbl->buf, link_tbl->table.buf);
2519 ret = set_llm_cfg_to_hw(hr_dev, link_tbl);
2520 if (ret)
2521 goto err_alloc;
2522
2523 return 0;
2524
2525err_alloc:
2526 free_link_table_buf(hr_dev, link_tbl);
2527 return ret;
2528}
2529
2530static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev)
2531{
2532 struct hns_roce_v2_priv *priv = hr_dev->priv;
2533
2534 free_link_table_buf(hr_dev, &priv->ext_llm);
2535}
2536
2537static void free_dip_list(struct hns_roce_dev *hr_dev)
2538{
2539 struct hns_roce_dip *hr_dip;
2540 struct hns_roce_dip *tmp;
2541 unsigned long flags;
2542
2543 spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
2544
2545 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) {
2546 list_del(&hr_dip->node);
2547 kfree(hr_dip);
2548 }
2549
2550 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
2551}
2552
2553static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev)
2554{
2555 struct hns_roce_v2_priv *priv = hr_dev->priv;
2556 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2557 struct ib_device *ibdev = &hr_dev->ib_dev;
2558 struct hns_roce_pd *hr_pd;
2559 struct ib_pd *pd;
2560
2561 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL);
2562 if (ZERO_OR_NULL_PTR(hr_pd))
2563 return NULL;
2564 pd = &hr_pd->ibpd;
2565 pd->device = ibdev;
2566
2567 if (hns_roce_alloc_pd(pd, NULL)) {
2568 ibdev_err(ibdev, "failed to create pd for free mr.\n");
2569 kfree(hr_pd);
2570 return NULL;
2571 }
2572 free_mr->rsv_pd = to_hr_pd(pd);
2573 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev;
2574 free_mr->rsv_pd->ibpd.uobject = NULL;
2575 free_mr->rsv_pd->ibpd.__internal_mr = NULL;
2576 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0);
2577
2578 return pd;
2579}
2580
2581static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev)
2582{
2583 struct hns_roce_v2_priv *priv = hr_dev->priv;
2584 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2585 struct ib_device *ibdev = &hr_dev->ib_dev;
2586 struct ib_cq_init_attr cq_init_attr = {};
2587 struct hns_roce_cq *hr_cq;
2588 struct ib_cq *cq;
2589
2590 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM;
2591
2592 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL);
2593 if (ZERO_OR_NULL_PTR(hr_cq))
2594 return NULL;
2595
2596 cq = &hr_cq->ib_cq;
2597 cq->device = ibdev;
2598
2599 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) {
2600 ibdev_err(ibdev, "failed to create cq for free mr.\n");
2601 kfree(hr_cq);
2602 return NULL;
2603 }
2604 free_mr->rsv_cq = to_hr_cq(cq);
2605 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev;
2606 free_mr->rsv_cq->ib_cq.uobject = NULL;
2607 free_mr->rsv_cq->ib_cq.comp_handler = NULL;
2608 free_mr->rsv_cq->ib_cq.event_handler = NULL;
2609 free_mr->rsv_cq->ib_cq.cq_context = NULL;
2610 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0);
2611
2612 return cq;
2613}
2614
2615static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq,
2616 struct ib_qp_init_attr *init_attr, int i)
2617{
2618 struct hns_roce_v2_priv *priv = hr_dev->priv;
2619 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2620 struct ib_device *ibdev = &hr_dev->ib_dev;
2621 struct hns_roce_qp *hr_qp;
2622 struct ib_qp *qp;
2623 int ret;
2624
2625 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
2626 if (ZERO_OR_NULL_PTR(hr_qp))
2627 return -ENOMEM;
2628
2629 qp = &hr_qp->ibqp;
2630 qp->device = ibdev;
2631
2632 ret = hns_roce_create_qp(qp, init_attr, NULL);
2633 if (ret) {
2634 ibdev_err(ibdev, "failed to create qp for free mr.\n");
2635 kfree(hr_qp);
2636 return ret;
2637 }
2638
2639 free_mr->rsv_qp[i] = hr_qp;
2640 free_mr->rsv_qp[i]->ibqp.recv_cq = cq;
2641 free_mr->rsv_qp[i]->ibqp.send_cq = cq;
2642
2643 return 0;
2644}
2645
2646static void free_mr_exit(struct hns_roce_dev *hr_dev)
2647{
2648 struct hns_roce_v2_priv *priv = hr_dev->priv;
2649 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2650 struct ib_qp *qp;
2651 int i;
2652
2653 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2654 if (free_mr->rsv_qp[i]) {
2655 qp = &free_mr->rsv_qp[i]->ibqp;
2656 hns_roce_v2_destroy_qp(qp, NULL);
2657 kfree(free_mr->rsv_qp[i]);
2658 free_mr->rsv_qp[i] = NULL;
2659 }
2660 }
2661
2662 if (free_mr->rsv_cq) {
2663 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL);
2664 kfree(free_mr->rsv_cq);
2665 free_mr->rsv_cq = NULL;
2666 }
2667
2668 if (free_mr->rsv_pd) {
2669 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL);
2670 kfree(free_mr->rsv_pd);
2671 free_mr->rsv_pd = NULL;
2672 }
2673}
2674
2675static int free_mr_alloc_res(struct hns_roce_dev *hr_dev)
2676{
2677 struct hns_roce_v2_priv *priv = hr_dev->priv;
2678 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2679 struct ib_qp_init_attr qp_init_attr = {};
2680 struct ib_pd *pd;
2681 struct ib_cq *cq;
2682 int ret;
2683 int i;
2684
2685 pd = free_mr_init_pd(hr_dev);
2686 if (!pd)
2687 return -ENOMEM;
2688
2689 cq = free_mr_init_cq(hr_dev);
2690 if (!cq) {
2691 ret = -ENOMEM;
2692 goto create_failed_cq;
2693 }
2694
2695 qp_init_attr.qp_type = IB_QPT_RC;
2696 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
2697 qp_init_attr.send_cq = cq;
2698 qp_init_attr.recv_cq = cq;
2699 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2700 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM;
2701 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM;
2702 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM;
2703 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM;
2704
2705 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i);
2706 if (ret)
2707 goto create_failed_qp;
2708 }
2709
2710 return 0;
2711
2712create_failed_qp:
2713 for (i--; i >= 0; i--) {
2714 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL);
2715 kfree(free_mr->rsv_qp[i]);
2716 }
2717 hns_roce_destroy_cq(cq, NULL);
2718 kfree(cq);
2719
2720create_failed_cq:
2721 hns_roce_dealloc_pd(pd, NULL);
2722 kfree(pd);
2723
2724 return ret;
2725}
2726
2727static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev,
2728 struct ib_qp_attr *attr, int sl_num)
2729{
2730 struct hns_roce_v2_priv *priv = hr_dev->priv;
2731 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2732 struct ib_device *ibdev = &hr_dev->ib_dev;
2733 struct hns_roce_qp *hr_qp;
2734 int loopback;
2735 int mask;
2736 int ret;
2737
2738 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp);
2739 hr_qp->free_mr_en = 1;
2740 hr_qp->ibqp.device = ibdev;
2741 hr_qp->ibqp.qp_type = IB_QPT_RC;
2742
2743 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS;
2744 attr->qp_state = IB_QPS_INIT;
2745 attr->port_num = 1;
2746 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE;
2747 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2748 IB_QPS_INIT, NULL);
2749 if (ret) {
2750 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n",
2751 ret);
2752 return ret;
2753 }
2754
2755 loopback = hr_dev->loop_idc;
2756 /* Set qpc lbi = 1 incidate loopback IO */
2757 hr_dev->loop_idc = 1;
2758
2759 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN |
2760 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER;
2761 attr->qp_state = IB_QPS_RTR;
2762 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2763 attr->path_mtu = IB_MTU_256;
2764 attr->dest_qp_num = hr_qp->qpn;
2765 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2766
2767 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num);
2768
2769 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT,
2770 IB_QPS_RTR, NULL);
2771 hr_dev->loop_idc = loopback;
2772 if (ret) {
2773 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n",
2774 ret);
2775 return ret;
2776 }
2777
2778 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT |
2779 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC;
2780 attr->qp_state = IB_QPS_RTS;
2781 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN;
2782 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT;
2783 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT;
2784 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR,
2785 IB_QPS_RTS, NULL);
2786 if (ret)
2787 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n",
2788 ret);
2789
2790 return ret;
2791}
2792
2793static int free_mr_modify_qp(struct hns_roce_dev *hr_dev)
2794{
2795 struct hns_roce_v2_priv *priv = hr_dev->priv;
2796 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2797 struct ib_qp_attr attr = {};
2798 int ret;
2799 int i;
2800
2801 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
2802 rdma_ah_set_static_rate(&attr.ah_attr, 3);
2803 rdma_ah_set_port_num(&attr.ah_attr, 1);
2804
2805 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
2806 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i);
2807 if (ret)
2808 return ret;
2809 }
2810
2811 return 0;
2812}
2813
2814static int free_mr_init(struct hns_roce_dev *hr_dev)
2815{
2816 struct hns_roce_v2_priv *priv = hr_dev->priv;
2817 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
2818 int ret;
2819
2820 mutex_init(&free_mr->mutex);
2821
2822 ret = free_mr_alloc_res(hr_dev);
2823 if (ret)
2824 return ret;
2825
2826 ret = free_mr_modify_qp(hr_dev);
2827 if (ret)
2828 goto err_modify_qp;
2829
2830 return 0;
2831
2832err_modify_qp:
2833 free_mr_exit(hr_dev);
2834
2835 return ret;
2836}
2837
2838static int get_hem_table(struct hns_roce_dev *hr_dev)
2839{
2840 unsigned int qpc_count;
2841 unsigned int cqc_count;
2842 unsigned int gmv_count;
2843 int ret;
2844 int i;
2845
2846 /* Alloc memory for source address table buffer space chunk */
2847 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num;
2848 gmv_count++) {
2849 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count);
2850 if (ret)
2851 goto err_gmv_failed;
2852 }
2853
2854 if (hr_dev->is_vf)
2855 return 0;
2856
2857 /* Alloc memory for QPC Timer buffer space chunk */
2858 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2859 qpc_count++) {
2860 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2861 qpc_count);
2862 if (ret) {
2863 dev_err(hr_dev->dev, "QPC Timer get failed\n");
2864 goto err_qpc_timer_failed;
2865 }
2866 }
2867
2868 /* Alloc memory for CQC Timer buffer space chunk */
2869 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2870 cqc_count++) {
2871 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2872 cqc_count);
2873 if (ret) {
2874 dev_err(hr_dev->dev, "CQC Timer get failed\n");
2875 goto err_cqc_timer_failed;
2876 }
2877 }
2878
2879 return 0;
2880
2881err_cqc_timer_failed:
2882 for (i = 0; i < cqc_count; i++)
2883 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2884
2885err_qpc_timer_failed:
2886 for (i = 0; i < qpc_count; i++)
2887 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2888
2889err_gmv_failed:
2890 for (i = 0; i < gmv_count; i++)
2891 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2892
2893 return ret;
2894}
2895
2896static void put_hem_table(struct hns_roce_dev *hr_dev)
2897{
2898 int i;
2899
2900 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++)
2901 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i);
2902
2903 if (hr_dev->is_vf)
2904 return;
2905
2906 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++)
2907 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2908
2909 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++)
2910 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2911}
2912
2913static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2914{
2915 int ret;
2916
2917 /* The hns ROCEE requires the extdb info to be cleared before using */
2918 ret = hns_roce_clear_extdb_list_info(hr_dev);
2919 if (ret)
2920 return ret;
2921
2922 ret = get_hem_table(hr_dev);
2923 if (ret)
2924 return ret;
2925
2926 if (hr_dev->is_vf)
2927 return 0;
2928
2929 ret = hns_roce_init_link_table(hr_dev);
2930 if (ret) {
2931 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret);
2932 goto err_llm_init_failed;
2933 }
2934
2935 return 0;
2936
2937err_llm_init_failed:
2938 put_hem_table(hr_dev);
2939
2940 return ret;
2941}
2942
2943static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2944{
2945 hns_roce_function_clear(hr_dev);
2946
2947 if (!hr_dev->is_vf)
2948 hns_roce_free_link_table(hr_dev);
2949
2950 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09)
2951 free_dip_list(hr_dev);
2952}
2953
2954static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev,
2955 struct hns_roce_mbox_msg *mbox_msg)
2956{
2957 struct hns_roce_cmq_desc desc;
2958 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2959
2960 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2961
2962 mb->in_param_l = cpu_to_le32(mbox_msg->in_param);
2963 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32);
2964 mb->out_param_l = cpu_to_le32(mbox_msg->out_param);
2965 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32);
2966 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd);
2967 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 |
2968 mbox_msg->token);
2969
2970 return hns_roce_cmq_send(hr_dev, &desc, 1);
2971}
2972
2973static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout,
2974 u8 *complete_status)
2975{
2976 struct hns_roce_mbox_status *mb_st;
2977 struct hns_roce_cmq_desc desc;
2978 unsigned long end;
2979 int ret = -EBUSY;
2980 u32 status;
2981 bool busy;
2982
2983 mb_st = (struct hns_roce_mbox_status *)desc.data;
2984 end = msecs_to_jiffies(timeout) + jiffies;
2985 while (v2_chk_mbox_is_avail(hr_dev, &busy)) {
2986 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR)
2987 return -EIO;
2988
2989 status = 0;
2990 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST,
2991 true);
2992 ret = __hns_roce_cmq_send(hr_dev, &desc, 1);
2993 if (!ret) {
2994 status = le32_to_cpu(mb_st->mb_status_hw_run);
2995 /* No pending message exists in ROCEE mbox. */
2996 if (!(status & MB_ST_HW_RUN_M))
2997 break;
2998 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
2999 break;
3000 }
3001
3002 if (time_after(jiffies, end)) {
3003 dev_err_ratelimited(hr_dev->dev,
3004 "failed to wait mbox status 0x%x\n",
3005 status);
3006 return -ETIMEDOUT;
3007 }
3008
3009 cond_resched();
3010 ret = -EBUSY;
3011 }
3012
3013 if (!ret) {
3014 *complete_status = (u8)(status & MB_ST_COMPLETE_M);
3015 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) {
3016 /* Ignore all errors if the mbox is unavailable. */
3017 ret = 0;
3018 *complete_status = MB_ST_COMPLETE_M;
3019 }
3020
3021 return ret;
3022}
3023
3024static int v2_post_mbox(struct hns_roce_dev *hr_dev,
3025 struct hns_roce_mbox_msg *mbox_msg)
3026{
3027 u8 status = 0;
3028 int ret;
3029
3030 /* Waiting for the mbox to be idle */
3031 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS,
3032 &status);
3033 if (unlikely(ret)) {
3034 dev_err_ratelimited(hr_dev->dev,
3035 "failed to check post mbox status = 0x%x, ret = %d.\n",
3036 status, ret);
3037 return ret;
3038 }
3039
3040 /* Post new message to mbox */
3041 ret = hns_roce_mbox_post(hr_dev, mbox_msg);
3042 if (ret)
3043 dev_err_ratelimited(hr_dev->dev,
3044 "failed to post mailbox, ret = %d.\n", ret);
3045
3046 return ret;
3047}
3048
3049static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev)
3050{
3051 u8 status = 0;
3052 int ret;
3053
3054 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS,
3055 &status);
3056 if (!ret) {
3057 if (status != MB_ST_COMPLETE_SUCC)
3058 return -EBUSY;
3059 } else {
3060 dev_err_ratelimited(hr_dev->dev,
3061 "failed to check mbox status = 0x%x, ret = %d.\n",
3062 status, ret);
3063 }
3064
3065 return ret;
3066}
3067
3068static void copy_gid(void *dest, const union ib_gid *gid)
3069{
3070#define GID_SIZE 4
3071 const union ib_gid *src = gid;
3072 __le32 (*p)[GID_SIZE] = dest;
3073 int i;
3074
3075 if (!gid)
3076 src = &zgid;
3077
3078 for (i = 0; i < GID_SIZE; i++)
3079 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]);
3080}
3081
3082static int config_sgid_table(struct hns_roce_dev *hr_dev,
3083 int gid_index, const union ib_gid *gid,
3084 enum hns_roce_sgid_type sgid_type)
3085{
3086 struct hns_roce_cmq_desc desc;
3087 struct hns_roce_cfg_sgid_tb *sgid_tb =
3088 (struct hns_roce_cfg_sgid_tb *)desc.data;
3089
3090 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
3091
3092 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index);
3093 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type);
3094
3095 copy_gid(&sgid_tb->vf_sgid_l, gid);
3096
3097 return hns_roce_cmq_send(hr_dev, &desc, 1);
3098}
3099
3100static int config_gmv_table(struct hns_roce_dev *hr_dev,
3101 int gid_index, const union ib_gid *gid,
3102 enum hns_roce_sgid_type sgid_type,
3103 const struct ib_gid_attr *attr)
3104{
3105 struct hns_roce_cmq_desc desc[2];
3106 struct hns_roce_cfg_gmv_tb_a *tb_a =
3107 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data;
3108 struct hns_roce_cfg_gmv_tb_b *tb_b =
3109 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data;
3110
3111 u16 vlan_id = VLAN_CFI_MASK;
3112 u8 mac[ETH_ALEN] = {};
3113 int ret;
3114
3115 if (gid) {
3116 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac);
3117 if (ret)
3118 return ret;
3119 }
3120
3121 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3122 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
3123
3124 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false);
3125
3126 copy_gid(&tb_a->vf_sgid_l, gid);
3127
3128 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type);
3129 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK);
3130 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id);
3131
3132 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac);
3133
3134 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]);
3135 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index);
3136
3137 return hns_roce_cmq_send(hr_dev, desc, 2);
3138}
3139
3140static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index,
3141 const union ib_gid *gid,
3142 const struct ib_gid_attr *attr)
3143{
3144 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
3145 int ret;
3146
3147 if (gid) {
3148 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
3149 if (ipv6_addr_v4mapped((void *)gid))
3150 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
3151 else
3152 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
3153 } else if (attr->gid_type == IB_GID_TYPE_ROCE) {
3154 sgid_type = GID_TYPE_FLAG_ROCE_V1;
3155 }
3156 }
3157
3158 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
3159 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr);
3160 else
3161 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type);
3162
3163 if (ret)
3164 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n",
3165 ret);
3166
3167 return ret;
3168}
3169
3170static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
3171 const u8 *addr)
3172{
3173 struct hns_roce_cmq_desc desc;
3174 struct hns_roce_cfg_smac_tb *smac_tb =
3175 (struct hns_roce_cfg_smac_tb *)desc.data;
3176 u16 reg_smac_h;
3177 u32 reg_smac_l;
3178
3179 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
3180
3181 reg_smac_l = *(u32 *)(&addr[0]);
3182 reg_smac_h = *(u16 *)(&addr[4]);
3183
3184 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port);
3185 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h);
3186 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
3187
3188 return hns_roce_cmq_send(hr_dev, &desc, 1);
3189}
3190
3191static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
3192 struct hns_roce_v2_mpt_entry *mpt_entry,
3193 struct hns_roce_mr *mr)
3194{
3195 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
3196 struct ib_device *ibdev = &hr_dev->ib_dev;
3197 dma_addr_t pbl_ba;
3198 int i, count;
3199
3200 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
3201 min_t(int, ARRAY_SIZE(pages), mr->npages),
3202 &pbl_ba);
3203 if (count < 1) {
3204 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n",
3205 count);
3206 return -ENOBUFS;
3207 }
3208
3209 /* Aligned to the hardware address access unit */
3210 for (i = 0; i < count; i++)
3211 pages[i] >>= 6;
3212
3213 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3214 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);
3215 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3216
3217 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
3218 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0]));
3219
3220 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
3221 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1]));
3222 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3223 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3224
3225 return 0;
3226}
3227
3228static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
3229 void *mb_buf, struct hns_roce_mr *mr)
3230{
3231 struct hns_roce_v2_mpt_entry *mpt_entry;
3232
3233 mpt_entry = mb_buf;
3234 memset(mpt_entry, 0, sizeof(*mpt_entry));
3235
3236 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3237 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3238
3239 hr_reg_write_bool(mpt_entry, MPT_BIND_EN,
3240 mr->access & IB_ACCESS_MW_BIND);
3241 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN,
3242 mr->access & IB_ACCESS_REMOTE_ATOMIC);
3243 hr_reg_write_bool(mpt_entry, MPT_RR_EN,
3244 mr->access & IB_ACCESS_REMOTE_READ);
3245 hr_reg_write_bool(mpt_entry, MPT_RW_EN,
3246 mr->access & IB_ACCESS_REMOTE_WRITE);
3247 hr_reg_write_bool(mpt_entry, MPT_LW_EN,
3248 mr->access & IB_ACCESS_LOCAL_WRITE);
3249
3250 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3251 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3252 mpt_entry->lkey = cpu_to_le32(mr->key);
3253 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3254 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3255
3256 if (mr->type != MR_TYPE_MR)
3257 hr_reg_enable(mpt_entry, MPT_PA);
3258
3259 if (mr->type == MR_TYPE_DMA)
3260 return 0;
3261
3262 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0)
3263 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num);
3264
3265 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3266 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3267 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD);
3268
3269 return set_mtpt_pbl(hr_dev, mpt_entry, mr);
3270}
3271
3272static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
3273 struct hns_roce_mr *mr, int flags,
3274 void *mb_buf)
3275{
3276 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
3277 u32 mr_access_flags = mr->access;
3278 int ret = 0;
3279
3280 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID);
3281 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3282
3283 if (flags & IB_MR_REREG_ACCESS) {
3284 hr_reg_write(mpt_entry, MPT_BIND_EN,
3285 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
3286 hr_reg_write(mpt_entry, MPT_ATOMIC_EN,
3287 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3288 hr_reg_write(mpt_entry, MPT_RR_EN,
3289 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
3290 hr_reg_write(mpt_entry, MPT_RW_EN,
3291 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
3292 hr_reg_write(mpt_entry, MPT_LW_EN,
3293 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
3294 }
3295
3296 if (flags & IB_MR_REREG_TRANS) {
3297 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
3298 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
3299 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
3300 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
3301
3302 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3303 }
3304
3305 return ret;
3306}
3307
3308static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev,
3309 void *mb_buf, struct hns_roce_mr *mr)
3310{
3311 struct ib_device *ibdev = &hr_dev->ib_dev;
3312 struct hns_roce_v2_mpt_entry *mpt_entry;
3313 dma_addr_t pbl_ba = 0;
3314
3315 mpt_entry = mb_buf;
3316 memset(mpt_entry, 0, sizeof(*mpt_entry));
3317
3318 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) {
3319 ibdev_err(ibdev, "failed to find frmr mtr.\n");
3320 return -ENOBUFS;
3321 }
3322
3323 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3324 hr_reg_write(mpt_entry, MPT_PD, mr->pd);
3325
3326 hr_reg_enable(mpt_entry, MPT_RA_EN);
3327 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3328
3329 hr_reg_enable(mpt_entry, MPT_FRE);
3330 hr_reg_clear(mpt_entry, MPT_MR_MW);
3331 hr_reg_enable(mpt_entry, MPT_BPD);
3332 hr_reg_clear(mpt_entry, MPT_PA);
3333
3334 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1);
3335 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3336 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3337 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3338 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
3339
3340 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
3341
3342 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));
3343 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3));
3344
3345 return 0;
3346}
3347
3348static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
3349{
3350 struct hns_roce_v2_mpt_entry *mpt_entry;
3351
3352 mpt_entry = mb_buf;
3353 memset(mpt_entry, 0, sizeof(*mpt_entry));
3354
3355 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE);
3356 hr_reg_write(mpt_entry, MPT_PD, mw->pdn);
3357
3358 hr_reg_enable(mpt_entry, MPT_R_INV_EN);
3359 hr_reg_enable(mpt_entry, MPT_LW_EN);
3360
3361 hr_reg_enable(mpt_entry, MPT_MR_MW);
3362 hr_reg_enable(mpt_entry, MPT_BPD);
3363 hr_reg_clear(mpt_entry, MPT_PA);
3364 hr_reg_write(mpt_entry, MPT_BQP,
3365 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
3366
3367 mpt_entry->lkey = cpu_to_le32(mw->rkey);
3368
3369 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM,
3370 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
3371 mw->pbl_hop_num);
3372 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ,
3373 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3374 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ,
3375 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3376
3377 return 0;
3378}
3379
3380static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp)
3381{
3382 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
3383 struct ib_device *ibdev = &hr_dev->ib_dev;
3384 const struct ib_send_wr *bad_wr;
3385 struct ib_rdma_wr rdma_wr = {};
3386 struct ib_send_wr *send_wr;
3387 int ret;
3388
3389 send_wr = &rdma_wr.wr;
3390 send_wr->opcode = IB_WR_RDMA_WRITE;
3391
3392 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr);
3393 if (ret) {
3394 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n",
3395 ret);
3396 return ret;
3397 }
3398
3399 return 0;
3400}
3401
3402static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3403 struct ib_wc *wc);
3404
3405static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev)
3406{
3407 struct hns_roce_v2_priv *priv = hr_dev->priv;
3408 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr;
3409 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)];
3410 struct ib_device *ibdev = &hr_dev->ib_dev;
3411 struct hns_roce_qp *hr_qp;
3412 unsigned long end;
3413 int cqe_cnt = 0;
3414 int npolled;
3415 int ret;
3416 int i;
3417
3418 /*
3419 * If the device initialization is not complete or in the uninstall
3420 * process, then there is no need to execute free mr.
3421 */
3422 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT ||
3423 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT ||
3424 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT)
3425 return;
3426
3427 mutex_lock(&free_mr->mutex);
3428
3429 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) {
3430 hr_qp = free_mr->rsv_qp[i];
3431
3432 ret = free_mr_post_send_lp_wqe(hr_qp);
3433 if (ret) {
3434 ibdev_err(ibdev,
3435 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n",
3436 hr_qp->qpn, ret);
3437 break;
3438 }
3439
3440 cqe_cnt++;
3441 }
3442
3443 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies;
3444 while (cqe_cnt) {
3445 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc);
3446 if (npolled < 0) {
3447 ibdev_err(ibdev,
3448 "failed to poll cqe for free mr, remain %d cqe.\n",
3449 cqe_cnt);
3450 goto out;
3451 }
3452
3453 if (time_after(jiffies, end)) {
3454 ibdev_err(ibdev,
3455 "failed to poll cqe for free mr and timeout, remain %d cqe.\n",
3456 cqe_cnt);
3457 goto out;
3458 }
3459 cqe_cnt -= npolled;
3460 }
3461
3462out:
3463 mutex_unlock(&free_mr->mutex);
3464}
3465
3466static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev)
3467{
3468 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
3469 free_mr_send_cmd_to_hw(hr_dev);
3470}
3471
3472static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
3473{
3474 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
3475}
3476
3477static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n)
3478{
3479 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
3480
3481 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
3482 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe :
3483 NULL;
3484}
3485
3486static inline void update_cq_db(struct hns_roce_dev *hr_dev,
3487 struct hns_roce_cq *hr_cq)
3488{
3489 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) {
3490 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M;
3491 } else {
3492 struct hns_roce_v2_db cq_db = {};
3493
3494 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3495 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB);
3496 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3497 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1);
3498
3499 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3500 }
3501}
3502
3503static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3504 struct hns_roce_srq *srq)
3505{
3506 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3507 struct hns_roce_v2_cqe *cqe, *dest;
3508 u32 prod_index;
3509 int nfreed = 0;
3510 int wqe_index;
3511 u8 owner_bit;
3512
3513 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
3514 ++prod_index) {
3515 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
3516 break;
3517 }
3518
3519 /*
3520 * Now backwards through the CQ, removing CQ entries
3521 * that match our QP by overwriting them with next entries.
3522 */
3523 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
3524 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
3525 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) {
3526 if (srq && hr_reg_read(cqe, CQE_S_R)) {
3527 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX);
3528 hns_roce_free_srq_wqe(srq, wqe_index);
3529 }
3530 ++nfreed;
3531 } else if (nfreed) {
3532 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
3533 hr_cq->ib_cq.cqe);
3534 owner_bit = hr_reg_read(dest, CQE_OWNER);
3535 memcpy(dest, cqe, hr_cq->cqe_size);
3536 hr_reg_write(dest, CQE_OWNER, owner_bit);
3537 }
3538 }
3539
3540 if (nfreed) {
3541 hr_cq->cons_index += nfreed;
3542 update_cq_db(hr_dev, hr_cq);
3543 }
3544}
3545
3546static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
3547 struct hns_roce_srq *srq)
3548{
3549 spin_lock_irq(&hr_cq->lock);
3550 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
3551 spin_unlock_irq(&hr_cq->lock);
3552}
3553
3554static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
3555 struct hns_roce_cq *hr_cq, void *mb_buf,
3556 u64 *mtts, dma_addr_t dma_handle)
3557{
3558 struct hns_roce_v2_cq_context *cq_context;
3559
3560 cq_context = mb_buf;
3561 memset(cq_context, 0, sizeof(*cq_context));
3562
3563 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID);
3564 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED);
3565 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth));
3566 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector);
3567 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn);
3568
3569 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE)
3570 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B);
3571
3572 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
3573 hr_reg_enable(cq_context, CQC_STASH);
3574
3575 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L,
3576 to_hr_hw_page_addr(mtts[0]));
3577 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H,
3578 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
3579 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num ==
3580 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
3581 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L,
3582 to_hr_hw_page_addr(mtts[1]));
3583 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H,
3584 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
3585 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ,
3586 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
3587 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ,
3588 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
3589 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3);
3590 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3)));
3591 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN,
3592 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB);
3593 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L,
3594 ((u32)hr_cq->db.dma) >> 1);
3595 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H,
3596 hr_cq->db.dma >> 32);
3597 hr_reg_write(cq_context, CQC_CQ_MAX_CNT,
3598 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
3599 hr_reg_write(cq_context, CQC_CQ_PERIOD,
3600 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
3601}
3602
3603static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
3604 enum ib_cq_notify_flags flags)
3605{
3606 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3607 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3608 struct hns_roce_v2_db cq_db = {};
3609 u32 notify_flag;
3610
3611 /*
3612 * flags = 0, then notify_flag : next
3613 * flags = 1, then notify flag : solocited
3614 */
3615 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
3616 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
3617
3618 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn);
3619 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY);
3620 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index);
3621 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn);
3622 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag);
3623
3624 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg);
3625
3626 return 0;
3627}
3628
3629static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3630 int num_entries, struct ib_wc *wc)
3631{
3632 unsigned int left;
3633 int npolled = 0;
3634
3635 left = wq->head - wq->tail;
3636 if (left == 0)
3637 return 0;
3638
3639 left = min_t(unsigned int, (unsigned int)num_entries, left);
3640 while (npolled < left) {
3641 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3642 wc->status = IB_WC_WR_FLUSH_ERR;
3643 wc->vendor_err = 0;
3644 wc->qp = &hr_qp->ibqp;
3645
3646 wq->tail++;
3647 wc++;
3648 npolled++;
3649 }
3650
3651 return npolled;
3652}
3653
3654static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3655 struct ib_wc *wc)
3656{
3657 struct hns_roce_qp *hr_qp;
3658 int npolled = 0;
3659
3660 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3661 npolled += sw_comp(hr_qp, &hr_qp->sq,
3662 num_entries - npolled, wc + npolled);
3663 if (npolled >= num_entries)
3664 goto out;
3665 }
3666
3667 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3668 npolled += sw_comp(hr_qp, &hr_qp->rq,
3669 num_entries - npolled, wc + npolled);
3670 if (npolled >= num_entries)
3671 goto out;
3672 }
3673
3674out:
3675 return npolled;
3676}
3677
3678static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3679 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3680 struct ib_wc *wc)
3681{
3682 static const struct {
3683 u32 cqe_status;
3684 enum ib_wc_status wc_status;
3685 } map[] = {
3686 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3687 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3688 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3689 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3690 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3691 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3692 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3693 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3694 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3695 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3696 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3697 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3698 IB_WC_RETRY_EXC_ERR },
3699 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3700 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3701 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
3702 };
3703
3704 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS);
3705 int i;
3706
3707 wc->status = IB_WC_GENERAL_ERR;
3708 for (i = 0; i < ARRAY_SIZE(map); i++)
3709 if (cqe_status == map[i].cqe_status) {
3710 wc->status = map[i].wc_status;
3711 break;
3712 }
3713
3714 if (likely(wc->status == IB_WC_SUCCESS ||
3715 wc->status == IB_WC_WR_FLUSH_ERR))
3716 return;
3717
3718 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status);
3719 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3720 cq->cqe_size, false);
3721 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS);
3722
3723 /*
3724 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3725 * the standard protocol, the driver must ignore it and needn't to set
3726 * the QP to an error state.
3727 */
3728 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3729 return;
3730
3731 flush_cqe(hr_dev, qp);
3732}
3733
3734static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe,
3735 struct hns_roce_qp **cur_qp)
3736{
3737 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3738 struct hns_roce_qp *hr_qp = *cur_qp;
3739 u32 qpn;
3740
3741 qpn = hr_reg_read(cqe, CQE_LCL_QPN);
3742
3743 if (!hr_qp || qpn != hr_qp->qpn) {
3744 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3745 if (unlikely(!hr_qp)) {
3746 ibdev_err(&hr_dev->ib_dev,
3747 "CQ %06lx with entry for unknown QPN %06x\n",
3748 hr_cq->cqn, qpn);
3749 return -EINVAL;
3750 }
3751 *cur_qp = hr_qp;
3752 }
3753
3754 return 0;
3755}
3756
3757/*
3758 * mapped-value = 1 + real-value
3759 * The ib wc opcode's real value is start from 0, In order to distinguish
3760 * between initialized and uninitialized map values, we plus 1 to the actual
3761 * value when defining the mapping, so that the validity can be identified by
3762 * checking whether the mapped value is greater than 0.
3763 */
3764#define HR_WC_OP_MAP(hr_key, ib_key) \
3765 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key
3766
3767static const u32 wc_send_op_map[] = {
3768 HR_WC_OP_MAP(SEND, SEND),
3769 HR_WC_OP_MAP(SEND_WITH_INV, SEND),
3770 HR_WC_OP_MAP(SEND_WITH_IMM, SEND),
3771 HR_WC_OP_MAP(RDMA_READ, RDMA_READ),
3772 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE),
3773 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE),
3774 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP),
3775 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD),
3776 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP),
3777 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD),
3778 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR),
3779 HR_WC_OP_MAP(BIND_MW, REG_MR),
3780};
3781
3782static int to_ib_wc_send_op(u32 hr_opcode)
3783{
3784 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map))
3785 return -EINVAL;
3786
3787 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 :
3788 -EINVAL;
3789}
3790
3791static const u32 wc_recv_op_map[] = {
3792 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM),
3793 HR_WC_OP_MAP(SEND, RECV),
3794 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM),
3795 HR_WC_OP_MAP(SEND_WITH_INV, RECV),
3796};
3797
3798static int to_ib_wc_recv_op(u32 hr_opcode)
3799{
3800 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map))
3801 return -EINVAL;
3802
3803 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 :
3804 -EINVAL;
3805}
3806
3807static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3808{
3809 u32 hr_opcode;
3810 int ib_opcode;
3811
3812 wc->wc_flags = 0;
3813
3814 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3815 switch (hr_opcode) {
3816 case HNS_ROCE_V2_WQE_OP_RDMA_READ:
3817 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3818 break;
3819 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
3820 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
3821 wc->wc_flags |= IB_WC_WITH_IMM;
3822 break;
3823 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
3824 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
3825 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
3826 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
3827 wc->byte_len = 8;
3828 break;
3829 default:
3830 break;
3831 }
3832
3833 ib_opcode = to_ib_wc_send_op(hr_opcode);
3834 if (ib_opcode < 0)
3835 wc->status = IB_WC_GENERAL_ERR;
3836 else
3837 wc->opcode = ib_opcode;
3838}
3839
3840static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe)
3841{
3842 u32 hr_opcode;
3843 int ib_opcode;
3844
3845 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3846
3847 hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
3848 switch (hr_opcode) {
3849 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3850 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3851 wc->wc_flags = IB_WC_WITH_IMM;
3852 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata));
3853 break;
3854 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3855 wc->wc_flags = IB_WC_WITH_INVALIDATE;
3856 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
3857 break;
3858 default:
3859 wc->wc_flags = 0;
3860 }
3861
3862 ib_opcode = to_ib_wc_recv_op(hr_opcode);
3863 if (ib_opcode < 0)
3864 wc->status = IB_WC_GENERAL_ERR;
3865 else
3866 wc->opcode = ib_opcode;
3867
3868 wc->sl = hr_reg_read(cqe, CQE_SL);
3869 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
3870 wc->slid = 0;
3871 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0;
3872 wc->port_num = hr_reg_read(cqe, CQE_PORTN);
3873 wc->pkey_index = 0;
3874
3875 if (hr_reg_read(cqe, CQE_VID_VLD)) {
3876 wc->vlan_id = hr_reg_read(cqe, CQE_VID);
3877 wc->wc_flags |= IB_WC_WITH_VLAN;
3878 } else {
3879 wc->vlan_id = 0xffff;
3880 }
3881
3882 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE);
3883
3884 return 0;
3885}
3886
3887static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
3888 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
3889{
3890 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
3891 struct hns_roce_qp *qp = *cur_qp;
3892 struct hns_roce_srq *srq = NULL;
3893 struct hns_roce_v2_cqe *cqe;
3894 struct hns_roce_wq *wq;
3895 int is_send;
3896 u16 wqe_idx;
3897 int ret;
3898
3899 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
3900 if (!cqe)
3901 return -EAGAIN;
3902
3903 ++hr_cq->cons_index;
3904 /* Memory barrier */
3905 rmb();
3906
3907 ret = get_cur_qp(hr_cq, cqe, &qp);
3908 if (ret)
3909 return ret;
3910
3911 wc->qp = &qp->ibqp;
3912 wc->vendor_err = 0;
3913
3914 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
3915
3916 is_send = !hr_reg_read(cqe, CQE_S_R);
3917 if (is_send) {
3918 wq = &qp->sq;
3919
3920 /* If sg_signal_bit is set, tail pointer will be updated to
3921 * the WQE corresponding to the current CQE.
3922 */
3923 if (qp->sq_signal_bits)
3924 wq->tail += (wqe_idx - (u16)wq->tail) &
3925 (wq->wqe_cnt - 1);
3926
3927 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3928 ++wq->tail;
3929
3930 fill_send_wc(wc, cqe);
3931 } else {
3932 if (qp->ibqp.srq) {
3933 srq = to_hr_srq(qp->ibqp.srq);
3934 wc->wr_id = srq->wrid[wqe_idx];
3935 hns_roce_free_srq_wqe(srq, wqe_idx);
3936 } else {
3937 wq = &qp->rq;
3938 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3939 ++wq->tail;
3940 }
3941
3942 ret = fill_recv_wc(wc, cqe);
3943 }
3944
3945 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc);
3946 if (unlikely(wc->status != IB_WC_SUCCESS))
3947 return 0;
3948
3949 return ret;
3950}
3951
3952static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3953 struct ib_wc *wc)
3954{
3955 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3956 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3957 struct hns_roce_qp *cur_qp = NULL;
3958 unsigned long flags;
3959 int npolled;
3960
3961 spin_lock_irqsave(&hr_cq->lock, flags);
3962
3963 /*
3964 * When the device starts to reset, the state is RST_DOWN. At this time,
3965 * there may still be some valid CQEs in the hardware that are not
3966 * polled. Therefore, it is not allowed to switch to the software mode
3967 * immediately. When the state changes to UNINIT, CQE no longer exists
3968 * in the hardware, and then switch to software mode.
3969 */
3970 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
3971 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
3972 goto out;
3973 }
3974
3975 for (npolled = 0; npolled < num_entries; ++npolled) {
3976 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
3977 break;
3978 }
3979
3980 if (npolled)
3981 update_cq_db(hr_dev, hr_cq);
3982
3983out:
3984 spin_unlock_irqrestore(&hr_cq->lock, flags);
3985
3986 return npolled;
3987}
3988
3989static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
3990 u32 step_idx, u8 *mbox_cmd)
3991{
3992 u8 cmd;
3993
3994 switch (type) {
3995 case HEM_TYPE_QPC:
3996 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0;
3997 break;
3998 case HEM_TYPE_MTPT:
3999 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0;
4000 break;
4001 case HEM_TYPE_CQC:
4002 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0;
4003 break;
4004 case HEM_TYPE_SRQC:
4005 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0;
4006 break;
4007 case HEM_TYPE_SCCC:
4008 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0;
4009 break;
4010 case HEM_TYPE_QPC_TIMER:
4011 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
4012 break;
4013 case HEM_TYPE_CQC_TIMER:
4014 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
4015 break;
4016 default:
4017 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type);
4018 return -EINVAL;
4019 }
4020
4021 *mbox_cmd = cmd + step_idx;
4022
4023 return 0;
4024}
4025
4026static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj,
4027 dma_addr_t base_addr)
4028{
4029 struct hns_roce_cmq_desc desc;
4030 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
4031 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz);
4032 u64 addr = to_hr_hw_page_addr(base_addr);
4033
4034 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
4035
4036 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr));
4037 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr));
4038 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
4039
4040 return hns_roce_cmq_send(hr_dev, &desc, 1);
4041}
4042
4043static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj,
4044 dma_addr_t base_addr, u32 hem_type, u32 step_idx)
4045{
4046 int ret;
4047 u8 cmd;
4048
4049 if (unlikely(hem_type == HEM_TYPE_GMV))
4050 return config_gmv_ba_to_hw(hr_dev, obj, base_addr);
4051
4052 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx))
4053 return 0;
4054
4055 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd);
4056 if (ret < 0)
4057 return ret;
4058
4059 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj);
4060}
4061
4062static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
4063 struct hns_roce_hem_table *table, int obj,
4064 u32 step_idx)
4065{
4066 struct hns_roce_hem_iter iter;
4067 struct hns_roce_hem_mhop mhop;
4068 struct hns_roce_hem *hem;
4069 unsigned long mhop_obj = obj;
4070 int i, j, k;
4071 int ret = 0;
4072 u64 hem_idx = 0;
4073 u64 l1_idx = 0;
4074 u64 bt_ba = 0;
4075 u32 chunk_ba_num;
4076 u32 hop_num;
4077
4078 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4079 return 0;
4080
4081 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
4082 i = mhop.l0_idx;
4083 j = mhop.l1_idx;
4084 k = mhop.l2_idx;
4085 hop_num = mhop.hop_num;
4086 chunk_ba_num = mhop.bt_chunk_size / 8;
4087
4088 if (hop_num == 2) {
4089 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
4090 k;
4091 l1_idx = i * chunk_ba_num + j;
4092 } else if (hop_num == 1) {
4093 hem_idx = i * chunk_ba_num + j;
4094 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
4095 hem_idx = i;
4096 }
4097
4098 if (table->type == HEM_TYPE_SCCC)
4099 obj = mhop.l0_idx;
4100
4101 if (check_whether_last_step(hop_num, step_idx)) {
4102 hem = table->hem[hem_idx];
4103 for (hns_roce_hem_first(hem, &iter);
4104 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
4105 bt_ba = hns_roce_hem_addr(&iter);
4106 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type,
4107 step_idx);
4108 }
4109 } else {
4110 if (step_idx == 0)
4111 bt_ba = table->bt_l0_dma_addr[i];
4112 else if (step_idx == 1 && hop_num == 2)
4113 bt_ba = table->bt_l1_dma_addr[l1_idx];
4114
4115 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
4116 }
4117
4118 return ret;
4119}
4120
4121static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
4122 struct hns_roce_hem_table *table,
4123 int tag, u32 step_idx)
4124{
4125 struct hns_roce_cmd_mailbox *mailbox;
4126 struct device *dev = hr_dev->dev;
4127 u8 cmd = 0xff;
4128 int ret;
4129
4130 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
4131 return 0;
4132
4133 switch (table->type) {
4134 case HEM_TYPE_QPC:
4135 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0;
4136 break;
4137 case HEM_TYPE_MTPT:
4138 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0;
4139 break;
4140 case HEM_TYPE_CQC:
4141 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0;
4142 break;
4143 case HEM_TYPE_SRQC:
4144 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
4145 break;
4146 case HEM_TYPE_SCCC:
4147 case HEM_TYPE_QPC_TIMER:
4148 case HEM_TYPE_CQC_TIMER:
4149 case HEM_TYPE_GMV:
4150 return 0;
4151 default:
4152 dev_warn(dev, "table %u not to be destroyed by mailbox!\n",
4153 table->type);
4154 return 0;
4155 }
4156
4157 cmd += step_idx;
4158
4159 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4160 if (IS_ERR(mailbox))
4161 return PTR_ERR(mailbox);
4162
4163 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag);
4164
4165 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4166 return ret;
4167}
4168
4169static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
4170 struct hns_roce_v2_qp_context *context,
4171 struct hns_roce_v2_qp_context *qpc_mask,
4172 struct hns_roce_qp *hr_qp)
4173{
4174 struct hns_roce_cmd_mailbox *mailbox;
4175 int qpc_size;
4176 int ret;
4177
4178 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4179 if (IS_ERR(mailbox))
4180 return PTR_ERR(mailbox);
4181
4182 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
4183 qpc_size = hr_dev->caps.qpc_sz;
4184 memcpy(mailbox->buf, context, qpc_size);
4185 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
4186
4187 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
4188 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn);
4189
4190 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4191
4192 return ret;
4193}
4194
4195static void set_access_flags(struct hns_roce_qp *hr_qp,
4196 struct hns_roce_v2_qp_context *context,
4197 struct hns_roce_v2_qp_context *qpc_mask,
4198 const struct ib_qp_attr *attr, int attr_mask)
4199{
4200 u8 dest_rd_atomic;
4201 u32 access_flags;
4202
4203 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
4204 attr->max_dest_rd_atomic : hr_qp->resp_depth;
4205
4206 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
4207 attr->qp_access_flags : hr_qp->atomic_rd_en;
4208
4209 if (!dest_rd_atomic)
4210 access_flags &= IB_ACCESS_REMOTE_WRITE;
4211
4212 hr_reg_write_bool(context, QPC_RRE,
4213 access_flags & IB_ACCESS_REMOTE_READ);
4214 hr_reg_clear(qpc_mask, QPC_RRE);
4215
4216 hr_reg_write_bool(context, QPC_RWE,
4217 access_flags & IB_ACCESS_REMOTE_WRITE);
4218 hr_reg_clear(qpc_mask, QPC_RWE);
4219
4220 hr_reg_write_bool(context, QPC_ATE,
4221 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4222 hr_reg_clear(qpc_mask, QPC_ATE);
4223 hr_reg_write_bool(context, QPC_EXT_ATE,
4224 access_flags & IB_ACCESS_REMOTE_ATOMIC);
4225 hr_reg_clear(qpc_mask, QPC_EXT_ATE);
4226}
4227
4228static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
4229 struct hns_roce_v2_qp_context *context,
4230 struct hns_roce_v2_qp_context *qpc_mask)
4231{
4232 hr_reg_write(context, QPC_SGE_SHIFT,
4233 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
4234 hr_qp->sge.sge_shift));
4235
4236 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt));
4237
4238 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt));
4239}
4240
4241static inline int get_cqn(struct ib_cq *ib_cq)
4242{
4243 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0;
4244}
4245
4246static inline int get_pdn(struct ib_pd *ib_pd)
4247{
4248 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0;
4249}
4250
4251static void modify_qp_reset_to_init(struct ib_qp *ibqp,
4252 const struct ib_qp_attr *attr,
4253 struct hns_roce_v2_qp_context *context,
4254 struct hns_roce_v2_qp_context *qpc_mask)
4255{
4256 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4257 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4258
4259 /*
4260 * In v2 engine, software pass context and context mask to hardware
4261 * when modifying qp. If software need modify some fields in context,
4262 * we should set all bits of the relevant fields in context mask to
4263 * 0 at the same time, else set them to 0x1.
4264 */
4265 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4266
4267 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4268
4269 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs));
4270
4271 set_qpc_wqe_cnt(hr_qp, context, qpc_mask);
4272
4273 /* No VLAN need to set 0xFFF */
4274 hr_reg_write(context, QPC_VLAN_ID, 0xfff);
4275
4276 if (ibqp->qp_type == IB_QPT_XRC_TGT) {
4277 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn);
4278
4279 hr_reg_enable(context, QPC_XRC_QP_TYPE);
4280 }
4281
4282 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
4283 hr_reg_enable(context, QPC_RQ_RECORD_EN);
4284
4285 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB)
4286 hr_reg_enable(context, QPC_OWNER_MODE);
4287
4288 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L,
4289 lower_32_bits(hr_qp->rdb.dma) >> 1);
4290 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H,
4291 upper_32_bits(hr_qp->rdb.dma));
4292
4293 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4294
4295 if (ibqp->srq) {
4296 hr_reg_enable(context, QPC_SRQ_EN);
4297 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4298 }
4299
4300 hr_reg_enable(context, QPC_FRE);
4301
4302 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4303
4304 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ)
4305 return;
4306
4307 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH)
4308 hr_reg_enable(&context->ext, QPCEX_STASH);
4309}
4310
4311static void modify_qp_init_to_init(struct ib_qp *ibqp,
4312 const struct ib_qp_attr *attr,
4313 struct hns_roce_v2_qp_context *context,
4314 struct hns_roce_v2_qp_context *qpc_mask)
4315{
4316 /*
4317 * In v2 engine, software pass context and context mask to hardware
4318 * when modifying qp. If software need modify some fields in context,
4319 * we should set all bits of the relevant fields in context mask to
4320 * 0 at the same time, else set them to 0x1.
4321 */
4322 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type));
4323 hr_reg_clear(qpc_mask, QPC_TST);
4324
4325 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd));
4326 hr_reg_clear(qpc_mask, QPC_PD);
4327
4328 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq));
4329 hr_reg_clear(qpc_mask, QPC_RX_CQN);
4330
4331 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq));
4332 hr_reg_clear(qpc_mask, QPC_TX_CQN);
4333
4334 if (ibqp->srq) {
4335 hr_reg_enable(context, QPC_SRQ_EN);
4336 hr_reg_clear(qpc_mask, QPC_SRQ_EN);
4337 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn);
4338 hr_reg_clear(qpc_mask, QPC_SRQN);
4339 }
4340}
4341
4342static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
4343 struct hns_roce_qp *hr_qp,
4344 struct hns_roce_v2_qp_context *context,
4345 struct hns_roce_v2_qp_context *qpc_mask)
4346{
4347 u64 mtts[MTT_MIN_COUNT] = { 0 };
4348 u64 wqe_sge_ba;
4349 int count;
4350
4351 /* Search qp buf's mtts */
4352 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
4353 MTT_MIN_COUNT, &wqe_sge_ba);
4354 if (hr_qp->rq.wqe_cnt && count < 1) {
4355 ibdev_err(&hr_dev->ib_dev,
4356 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn);
4357 return -EINVAL;
4358 }
4359
4360 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
4361 qpc_mask->wqe_sge_ba = 0;
4362
4363 /*
4364 * In v2 engine, software pass context and context mask to hardware
4365 * when modifying qp. If software need modify some fields in context,
4366 * we should set all bits of the relevant fields in context mask to
4367 * 0 at the same time, else set them to 0x1.
4368 */
4369 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3));
4370 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H);
4371
4372 hr_reg_write(context, QPC_SQ_HOP_NUM,
4373 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
4374 hr_qp->sq.wqe_cnt));
4375 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM);
4376
4377 hr_reg_write(context, QPC_SGE_HOP_NUM,
4378 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
4379 hr_qp->sge.sge_cnt));
4380 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM);
4381
4382 hr_reg_write(context, QPC_RQ_HOP_NUM,
4383 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
4384 hr_qp->rq.wqe_cnt));
4385
4386 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM);
4387
4388 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ,
4389 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
4390 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ);
4391
4392 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ,
4393 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
4394 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ);
4395
4396 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
4397 qpc_mask->rq_cur_blk_addr = 0;
4398
4399 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H,
4400 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
4401 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H);
4402
4403 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
4404 qpc_mask->rq_nxt_blk_addr = 0;
4405
4406 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H,
4407 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
4408 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H);
4409
4410 return 0;
4411}
4412
4413static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
4414 struct hns_roce_qp *hr_qp,
4415 struct hns_roce_v2_qp_context *context,
4416 struct hns_roce_v2_qp_context *qpc_mask)
4417{
4418 struct ib_device *ibdev = &hr_dev->ib_dev;
4419 u64 sge_cur_blk = 0;
4420 u64 sq_cur_blk = 0;
4421 int count;
4422
4423 /* search qp buf's mtts */
4424 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL);
4425 if (count < 1) {
4426 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n",
4427 hr_qp->qpn);
4428 return -EINVAL;
4429 }
4430 if (hr_qp->sge.sge_cnt > 0) {
4431 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4432 hr_qp->sge.offset,
4433 &sge_cur_blk, 1, NULL);
4434 if (count < 1) {
4435 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n",
4436 hr_qp->qpn);
4437 return -EINVAL;
4438 }
4439 }
4440
4441 /*
4442 * In v2 engine, software pass context and context mask to hardware
4443 * when modifying qp. If software need modify some fields in context,
4444 * we should set all bits of the relevant fields in context mask to
4445 * 0 at the same time, else set them to 0x1.
4446 */
4447 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L,
4448 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4449 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H,
4450 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4451 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L);
4452 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H);
4453
4454 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L,
4455 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4456 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H,
4457 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
4458 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L);
4459 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H);
4460
4461 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L,
4462 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4463 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H,
4464 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
4465 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L);
4466 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H);
4467
4468 return 0;
4469}
4470
4471static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
4472 const struct ib_qp_attr *attr)
4473{
4474 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4475 return IB_MTU_4096;
4476
4477 return attr->path_mtu;
4478}
4479
4480static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4481 const struct ib_qp_attr *attr, int attr_mask,
4482 struct hns_roce_v2_qp_context *context,
4483 struct hns_roce_v2_qp_context *qpc_mask,
4484 struct ib_udata *udata)
4485{
4486 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata,
4487 struct hns_roce_ucontext, ibucontext);
4488 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4489 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4490 struct ib_device *ibdev = &hr_dev->ib_dev;
4491 dma_addr_t trrl_ba;
4492 dma_addr_t irrl_ba;
4493 enum ib_mtu ib_mtu;
4494 const u8 *smac;
4495 u8 lp_pktn_ini;
4496 u64 *mtts;
4497 u8 *dmac;
4498 u32 port;
4499 int mtu;
4500 int ret;
4501
4502 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4503 if (ret) {
4504 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4505 return ret;
4506 }
4507
4508 /* Search IRRL's mtts */
4509 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4510 hr_qp->qpn, &irrl_ba);
4511 if (!mtts) {
4512 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4513 return -EINVAL;
4514 }
4515
4516 /* Search TRRL's mtts */
4517 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4518 hr_qp->qpn, &trrl_ba);
4519 if (!mtts) {
4520 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4521 return -EINVAL;
4522 }
4523
4524 if (attr_mask & IB_QP_ALT_PATH) {
4525 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4526 attr_mask);
4527 return -EINVAL;
4528 }
4529
4530 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4);
4531 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L);
4532 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));
4533 qpc_mask->trrl_ba = 0;
4534 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4));
4535 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H);
4536
4537 context->irrl_ba = cpu_to_le32(irrl_ba >> 6);
4538 qpc_mask->irrl_ba = 0;
4539 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6));
4540 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H);
4541
4542 hr_reg_enable(context, QPC_RMT_E2E);
4543 hr_reg_clear(qpc_mask, QPC_RMT_E2E);
4544
4545 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits);
4546 hr_reg_clear(qpc_mask, QPC_SIG_TYPE);
4547
4548 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4549
4550 smac = (const u8 *)hr_dev->dev_addr[port];
4551 dmac = (u8 *)attr->ah_attr.roce.dmac;
4552 /* when dmac equals smac or loop_idc is 1, it should loopback */
4553 if (ether_addr_equal_unaligned(dmac, smac) ||
4554 hr_dev->loop_idc == 0x1) {
4555 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc);
4556 hr_reg_clear(qpc_mask, QPC_LBI);
4557 }
4558
4559 if (attr_mask & IB_QP_DEST_QPN) {
4560 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num);
4561 hr_reg_clear(qpc_mask, QPC_DQPN);
4562 }
4563
4564 memcpy(&context->dmac, dmac, sizeof(u32));
4565 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4])));
4566 qpc_mask->dmac = 0;
4567 hr_reg_clear(qpc_mask, QPC_DMAC_H);
4568
4569 ib_mtu = get_mtu(ibqp, attr);
4570 hr_qp->path_mtu = ib_mtu;
4571
4572 mtu = ib_mtu_enum_to_int(ib_mtu);
4573 if (WARN_ON(mtu <= 0))
4574 return -EINVAL;
4575#define MIN_LP_MSG_LEN 1024
4576 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */
4577 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu);
4578
4579 if (attr_mask & IB_QP_PATH_MTU) {
4580 hr_reg_write(context, QPC_MTU, ib_mtu);
4581 hr_reg_clear(qpc_mask, QPC_MTU);
4582 }
4583
4584 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini);
4585 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI);
4586
4587 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */
4588 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini);
4589 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ);
4590
4591 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR);
4592 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN);
4593 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE);
4594
4595 context->rq_rnr_timer = 0;
4596 qpc_mask->rq_rnr_timer = 0;
4597
4598 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX);
4599 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX);
4600
4601 /* rocee send 2^lp_sgen_ini segs every time */
4602 hr_reg_write(context, QPC_LP_SGEN_INI, 3);
4603 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI);
4604
4605 if (udata && ibqp->qp_type == IB_QPT_RC &&
4606 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) {
4607 hr_reg_write_bool(context, QPC_RQIE,
4608 hr_dev->caps.flags &
4609 HNS_ROCE_CAP_FLAG_RQ_INLINE);
4610 hr_reg_clear(qpc_mask, QPC_RQIE);
4611 }
4612
4613 if (udata &&
4614 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) &&
4615 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) {
4616 hr_reg_write_bool(context, QPC_CQEIE,
4617 hr_dev->caps.flags &
4618 HNS_ROCE_CAP_FLAG_CQE_INLINE);
4619 hr_reg_clear(qpc_mask, QPC_CQEIE);
4620
4621 hr_reg_write(context, QPC_CQEIS, 0);
4622 hr_reg_clear(qpc_mask, QPC_CQEIS);
4623 }
4624
4625 return 0;
4626}
4627
4628static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
4629 const struct ib_qp_attr *attr, int attr_mask,
4630 struct hns_roce_v2_qp_context *context,
4631 struct hns_roce_v2_qp_context *qpc_mask)
4632{
4633 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4634 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4635 struct ib_device *ibdev = &hr_dev->ib_dev;
4636 int ret;
4637
4638 /* Not support alternate path and path migration */
4639 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
4640 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
4641 return -EINVAL;
4642 }
4643
4644 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4645 if (ret) {
4646 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret);
4647 return ret;
4648 }
4649
4650 /*
4651 * Set some fields in context to zero, Because the default values
4652 * of all fields in context are zero, we need not set them to 0 again.
4653 * but we should set the relevant fields of context mask to 0.
4654 */
4655 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX);
4656
4657 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN);
4658
4659 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE);
4660 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD);
4661 hr_reg_clear(qpc_mask, QPC_IRRL_PSN);
4662
4663 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL);
4664
4665 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN);
4666
4667 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG);
4668
4669 hr_reg_clear(qpc_mask, QPC_CHECK_FLG);
4670
4671 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD);
4672
4673 return 0;
4674}
4675
4676static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4677 u32 *dip_idx)
4678{
4679 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4680 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4681 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx;
4682 u32 *head = &hr_dev->qp_table.idx_table.head;
4683 u32 *tail = &hr_dev->qp_table.idx_table.tail;
4684 struct hns_roce_dip *hr_dip;
4685 unsigned long flags;
4686 int ret = 0;
4687
4688 spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
4689
4690 spare_idx[*tail] = ibqp->qp_num;
4691 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1);
4692
4693 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) {
4694 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) {
4695 *dip_idx = hr_dip->dip_idx;
4696 goto out;
4697 }
4698 }
4699
4700 /* If no dgid is found, a new dip and a mapping between dgid and
4701 * dip_idx will be created.
4702 */
4703 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC);
4704 if (!hr_dip) {
4705 ret = -ENOMEM;
4706 goto out;
4707 }
4708
4709 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4710 hr_dip->dip_idx = *dip_idx = spare_idx[*head];
4711 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1);
4712 list_add_tail(&hr_dip->node, &hr_dev->dip_list);
4713
4714out:
4715 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
4716 return ret;
4717}
4718
4719enum {
4720 CONG_DCQCN,
4721 CONG_WINDOW,
4722};
4723
4724enum {
4725 UNSUPPORT_CONG_LEVEL,
4726 SUPPORT_CONG_LEVEL,
4727};
4728
4729enum {
4730 CONG_LDCP,
4731 CONG_HC3,
4732};
4733
4734enum {
4735 DIP_INVALID,
4736 DIP_VALID,
4737};
4738
4739enum {
4740 WND_LIMIT,
4741 WND_UNLIMIT,
4742};
4743
4744static int check_cong_type(struct ib_qp *ibqp,
4745 struct hns_roce_congestion_algorithm *cong_alg)
4746{
4747 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4748
4749 if (ibqp->qp_type == IB_QPT_UD)
4750 hr_dev->caps.cong_type = CONG_TYPE_DCQCN;
4751
4752 /* different congestion types match different configurations */
4753 switch (hr_dev->caps.cong_type) {
4754 case CONG_TYPE_DCQCN:
4755 cong_alg->alg_sel = CONG_DCQCN;
4756 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4757 cong_alg->dip_vld = DIP_INVALID;
4758 cong_alg->wnd_mode_sel = WND_LIMIT;
4759 break;
4760 case CONG_TYPE_LDCP:
4761 cong_alg->alg_sel = CONG_WINDOW;
4762 cong_alg->alg_sub_sel = CONG_LDCP;
4763 cong_alg->dip_vld = DIP_INVALID;
4764 cong_alg->wnd_mode_sel = WND_UNLIMIT;
4765 break;
4766 case CONG_TYPE_HC3:
4767 cong_alg->alg_sel = CONG_WINDOW;
4768 cong_alg->alg_sub_sel = CONG_HC3;
4769 cong_alg->dip_vld = DIP_INVALID;
4770 cong_alg->wnd_mode_sel = WND_LIMIT;
4771 break;
4772 case CONG_TYPE_DIP:
4773 cong_alg->alg_sel = CONG_DCQCN;
4774 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4775 cong_alg->dip_vld = DIP_VALID;
4776 cong_alg->wnd_mode_sel = WND_LIMIT;
4777 break;
4778 default:
4779 ibdev_warn(&hr_dev->ib_dev,
4780 "invalid type(%u) for congestion selection.\n",
4781 hr_dev->caps.cong_type);
4782 hr_dev->caps.cong_type = CONG_TYPE_DCQCN;
4783 cong_alg->alg_sel = CONG_DCQCN;
4784 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
4785 cong_alg->dip_vld = DIP_INVALID;
4786 cong_alg->wnd_mode_sel = WND_LIMIT;
4787 break;
4788 }
4789
4790 return 0;
4791}
4792
4793static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
4794 struct hns_roce_v2_qp_context *context,
4795 struct hns_roce_v2_qp_context *qpc_mask)
4796{
4797 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4798 struct hns_roce_congestion_algorithm cong_field;
4799 struct ib_device *ibdev = ibqp->device;
4800 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
4801 u32 dip_idx = 0;
4802 int ret;
4803
4804 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ||
4805 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE)
4806 return 0;
4807
4808 ret = check_cong_type(ibqp, &cong_field);
4809 if (ret)
4810 return ret;
4811
4812 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id +
4813 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE);
4814 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID);
4815 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel);
4816 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL);
4817 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL,
4818 cong_field.alg_sub_sel);
4819 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL);
4820 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld);
4821 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD);
4822 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN,
4823 cong_field.wnd_mode_sel);
4824 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN);
4825
4826 /* if dip is disabled, there is no need to set dip idx */
4827 if (cong_field.dip_vld == 0)
4828 return 0;
4829
4830 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx);
4831 if (ret) {
4832 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret);
4833 return ret;
4834 }
4835
4836 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx);
4837 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0);
4838
4839 return 0;
4840}
4841
4842static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4843 const struct ib_qp_attr *attr,
4844 int attr_mask,
4845 struct hns_roce_v2_qp_context *context,
4846 struct hns_roce_v2_qp_context *qpc_mask)
4847{
4848 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4849 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4850 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4851 struct ib_device *ibdev = &hr_dev->ib_dev;
4852 const struct ib_gid_attr *gid_attr = NULL;
4853 u8 sl = rdma_ah_get_sl(&attr->ah_attr);
4854 int is_roce_protocol;
4855 u16 vlan_id = 0xffff;
4856 bool is_udp = false;
4857 u32 max_sl;
4858 u8 ib_port;
4859 u8 hr_port;
4860 int ret;
4861
4862 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1);
4863 if (unlikely(sl > max_sl)) {
4864 ibdev_err_ratelimited(ibdev,
4865 "failed to fill QPC, sl (%u) shouldn't be larger than %u.\n",
4866 sl, max_sl);
4867 return -EINVAL;
4868 }
4869
4870 /*
4871 * If free_mr_en of qp is set, it means that this qp comes from
4872 * free mr. This qp will perform the loopback operation.
4873 * In the loopback scenario, only sl needs to be set.
4874 */
4875 if (hr_qp->free_mr_en) {
4876 hr_reg_write(context, QPC_SL, sl);
4877 hr_reg_clear(qpc_mask, QPC_SL);
4878 hr_qp->sl = sl;
4879 return 0;
4880 }
4881
4882 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4883 hr_port = ib_port - 1;
4884 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4885 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4886
4887 if (is_roce_protocol) {
4888 gid_attr = attr->ah_attr.grh.sgid_attr;
4889 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
4890 if (ret)
4891 return ret;
4892
4893 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
4894 }
4895
4896 /* Only HIP08 needs to set the vlan_en bits in QPC */
4897 if (vlan_id < VLAN_N_VID &&
4898 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
4899 hr_reg_enable(context, QPC_RQ_VLAN_EN);
4900 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN);
4901 hr_reg_enable(context, QPC_SQ_VLAN_EN);
4902 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN);
4903 }
4904
4905 hr_reg_write(context, QPC_VLAN_ID, vlan_id);
4906 hr_reg_clear(qpc_mask, QPC_VLAN_ID);
4907
4908 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
4909 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4910 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
4911 return -EINVAL;
4912 }
4913
4914 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
4915 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
4916 return -EINVAL;
4917 }
4918
4919 hr_reg_write(context, QPC_UDPSPN,
4920 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num,
4921 attr->dest_qp_num) :
4922 0);
4923
4924 hr_reg_clear(qpc_mask, QPC_UDPSPN);
4925
4926 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index);
4927
4928 hr_reg_clear(qpc_mask, QPC_GMV_IDX);
4929
4930 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit);
4931 hr_reg_clear(qpc_mask, QPC_HOPLIMIT);
4932
4933 ret = fill_cong_field(ibqp, attr, context, qpc_mask);
4934 if (ret)
4935 return ret;
4936
4937 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh));
4938 hr_reg_clear(qpc_mask, QPC_TC);
4939
4940 hr_reg_write(context, QPC_FL, grh->flow_label);
4941 hr_reg_clear(qpc_mask, QPC_FL);
4942 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4943 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4944
4945 hr_qp->sl = sl;
4946 hr_reg_write(context, QPC_SL, hr_qp->sl);
4947 hr_reg_clear(qpc_mask, QPC_SL);
4948
4949 return 0;
4950}
4951
4952static bool check_qp_state(enum ib_qp_state cur_state,
4953 enum ib_qp_state new_state)
4954{
4955 static const bool sm[][IB_QPS_ERR + 1] = {
4956 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
4957 [IB_QPS_INIT] = true },
4958 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
4959 [IB_QPS_INIT] = true,
4960 [IB_QPS_RTR] = true,
4961 [IB_QPS_ERR] = true },
4962 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
4963 [IB_QPS_RTS] = true,
4964 [IB_QPS_ERR] = true },
4965 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
4966 [IB_QPS_RTS] = true,
4967 [IB_QPS_ERR] = true },
4968 [IB_QPS_SQD] = {},
4969 [IB_QPS_SQE] = {},
4970 [IB_QPS_ERR] = { [IB_QPS_RESET] = true,
4971 [IB_QPS_ERR] = true }
4972 };
4973
4974 return sm[cur_state][new_state];
4975}
4976
4977static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4978 const struct ib_qp_attr *attr,
4979 int attr_mask,
4980 enum ib_qp_state cur_state,
4981 enum ib_qp_state new_state,
4982 struct hns_roce_v2_qp_context *context,
4983 struct hns_roce_v2_qp_context *qpc_mask,
4984 struct ib_udata *udata)
4985{
4986 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4987 int ret = 0;
4988
4989 if (!check_qp_state(cur_state, new_state)) {
4990 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n");
4991 return -EINVAL;
4992 }
4993
4994 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
4995 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
4996 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask);
4997 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4998 modify_qp_init_to_init(ibqp, attr, context, qpc_mask);
4999 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
5000 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
5001 qpc_mask, udata);
5002 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
5003 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
5004 qpc_mask);
5005 }
5006
5007 return ret;
5008}
5009
5010static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout)
5011{
5012#define QP_ACK_TIMEOUT_MAX_HIP08 20
5013#define QP_ACK_TIMEOUT_MAX 31
5014
5015 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5016 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) {
5017 ibdev_warn(&hr_dev->ib_dev,
5018 "local ACK timeout shall be 0 to 20.\n");
5019 return false;
5020 }
5021 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5022 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) {
5023 if (*timeout > QP_ACK_TIMEOUT_MAX) {
5024 ibdev_warn(&hr_dev->ib_dev,
5025 "local ACK timeout shall be 0 to 31.\n");
5026 return false;
5027 }
5028 }
5029
5030 return true;
5031}
5032
5033static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
5034 const struct ib_qp_attr *attr,
5035 int attr_mask,
5036 struct hns_roce_v2_qp_context *context,
5037 struct hns_roce_v2_qp_context *qpc_mask)
5038{
5039 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5040 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5041 int ret = 0;
5042 u8 timeout;
5043
5044 if (attr_mask & IB_QP_AV) {
5045 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
5046 qpc_mask);
5047 if (ret)
5048 return ret;
5049 }
5050
5051 if (attr_mask & IB_QP_TIMEOUT) {
5052 timeout = attr->timeout;
5053 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) {
5054 hr_reg_write(context, QPC_AT, timeout);
5055 hr_reg_clear(qpc_mask, QPC_AT);
5056 }
5057 }
5058
5059 if (attr_mask & IB_QP_RETRY_CNT) {
5060 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt);
5061 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT);
5062
5063 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt);
5064 hr_reg_clear(qpc_mask, QPC_RETRY_CNT);
5065 }
5066
5067 if (attr_mask & IB_QP_RNR_RETRY) {
5068 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry);
5069 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT);
5070
5071 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry);
5072 hr_reg_clear(qpc_mask, QPC_RNR_CNT);
5073 }
5074
5075 if (attr_mask & IB_QP_SQ_PSN) {
5076 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn);
5077 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN);
5078
5079 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn);
5080 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN);
5081
5082 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn);
5083 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L);
5084
5085 hr_reg_write(context, QPC_RETRY_MSG_PSN_H,
5086 attr->sq_psn >> RETRY_MSG_PSN_SHIFT);
5087 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H);
5088
5089 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn);
5090 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN);
5091
5092 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn);
5093 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN);
5094 }
5095
5096 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
5097 attr->max_dest_rd_atomic) {
5098 hr_reg_write(context, QPC_RR_MAX,
5099 fls(attr->max_dest_rd_atomic - 1));
5100 hr_reg_clear(qpc_mask, QPC_RR_MAX);
5101 }
5102
5103 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
5104 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1));
5105 hr_reg_clear(qpc_mask, QPC_SR_MAX);
5106 }
5107
5108 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
5109 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
5110
5111 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
5112 hr_reg_write(context, QPC_MIN_RNR_TIME,
5113 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ?
5114 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer);
5115 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME);
5116 }
5117
5118 if (attr_mask & IB_QP_RQ_PSN) {
5119 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn);
5120 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN);
5121
5122 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1);
5123 hr_reg_clear(qpc_mask, QPC_RAQ_PSN);
5124 }
5125
5126 if (attr_mask & IB_QP_QKEY) {
5127 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5128 qpc_mask->qkey_xrcd = 0;
5129 hr_qp->qkey = attr->qkey;
5130 }
5131
5132 return ret;
5133}
5134
5135static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
5136 const struct ib_qp_attr *attr,
5137 int attr_mask)
5138{
5139 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5140 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5141
5142 if (attr_mask & IB_QP_ACCESS_FLAGS)
5143 hr_qp->atomic_rd_en = attr->qp_access_flags;
5144
5145 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
5146 hr_qp->resp_depth = attr->max_dest_rd_atomic;
5147 if (attr_mask & IB_QP_PORT) {
5148 hr_qp->port = attr->port_num - 1;
5149 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
5150 }
5151}
5152
5153static void clear_qp(struct hns_roce_qp *hr_qp)
5154{
5155 struct ib_qp *ibqp = &hr_qp->ibqp;
5156
5157 if (ibqp->send_cq)
5158 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
5159 hr_qp->qpn, NULL);
5160
5161 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq)
5162 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq),
5163 hr_qp->qpn, ibqp->srq ?
5164 to_hr_srq(ibqp->srq) : NULL);
5165
5166 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
5167 *hr_qp->rdb.db_record = 0;
5168
5169 hr_qp->rq.head = 0;
5170 hr_qp->rq.tail = 0;
5171 hr_qp->sq.head = 0;
5172 hr_qp->sq.tail = 0;
5173 hr_qp->next_sge = 0;
5174}
5175
5176static void v2_set_flushed_fields(struct ib_qp *ibqp,
5177 struct hns_roce_v2_qp_context *context,
5178 struct hns_roce_v2_qp_context *qpc_mask)
5179{
5180 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5181 unsigned long sq_flag = 0;
5182 unsigned long rq_flag = 0;
5183
5184 if (ibqp->qp_type == IB_QPT_XRC_TGT)
5185 return;
5186
5187 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
5188 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head);
5189 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX);
5190 hr_qp->state = IB_QPS_ERR;
5191 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
5192
5193 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */
5194 return;
5195
5196 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
5197 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head);
5198 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX);
5199 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
5200}
5201
5202static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
5203 const struct ib_qp_attr *attr,
5204 int attr_mask, enum ib_qp_state cur_state,
5205 enum ib_qp_state new_state, struct ib_udata *udata)
5206{
5207 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5208 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5209 struct hns_roce_v2_qp_context ctx[2];
5210 struct hns_roce_v2_qp_context *context = ctx;
5211 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
5212 struct ib_device *ibdev = &hr_dev->ib_dev;
5213 int ret;
5214
5215 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
5216 return -EOPNOTSUPP;
5217
5218 /*
5219 * In v2 engine, software pass context and context mask to hardware
5220 * when modifying qp. If software need modify some fields in context,
5221 * we should set all bits of the relevant fields in context mask to
5222 * 0 at the same time, else set them to 0x1.
5223 */
5224 memset(context, 0, hr_dev->caps.qpc_sz);
5225 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
5226
5227 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
5228 new_state, context, qpc_mask, udata);
5229 if (ret)
5230 goto out;
5231
5232 /* When QP state is err, SQ and RQ WQE should be flushed */
5233 if (new_state == IB_QPS_ERR)
5234 v2_set_flushed_fields(ibqp, context, qpc_mask);
5235
5236 /* Configure the optional fields */
5237 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
5238 qpc_mask);
5239 if (ret)
5240 goto out;
5241
5242 hr_reg_write_bool(context, QPC_INV_CREDIT,
5243 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC ||
5244 ibqp->srq);
5245 hr_reg_clear(qpc_mask, QPC_INV_CREDIT);
5246
5247 /* Every status migrate must change state */
5248 hr_reg_write(context, QPC_QP_ST, new_state);
5249 hr_reg_clear(qpc_mask, QPC_QP_ST);
5250
5251 /* SW pass context to HW */
5252 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
5253 if (ret) {
5254 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret);
5255 goto out;
5256 }
5257
5258 hr_qp->state = new_state;
5259
5260 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
5261
5262 if (new_state == IB_QPS_RESET && !ibqp->uobject)
5263 clear_qp(hr_qp);
5264
5265out:
5266 return ret;
5267}
5268
5269static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
5270{
5271 static const enum ib_qp_state map[] = {
5272 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
5273 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
5274 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
5275 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
5276 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
5277 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
5278 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
5279 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
5280 };
5281
5282 return (state < ARRAY_SIZE(map)) ? map[state] : -1;
5283}
5284
5285static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn,
5286 void *buffer)
5287{
5288 struct hns_roce_cmd_mailbox *mailbox;
5289 int ret;
5290
5291 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5292 if (IS_ERR(mailbox))
5293 return PTR_ERR(mailbox);
5294
5295 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC,
5296 qpn);
5297 if (ret)
5298 goto out;
5299
5300 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz);
5301
5302out:
5303 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5304 return ret;
5305}
5306
5307static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn,
5308 void *buffer)
5309{
5310 struct hns_roce_srq_context *context;
5311 struct hns_roce_cmd_mailbox *mailbox;
5312 int ret;
5313
5314 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5315 if (IS_ERR(mailbox))
5316 return PTR_ERR(mailbox);
5317
5318 context = mailbox->buf;
5319 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC,
5320 srqn);
5321 if (ret)
5322 goto out;
5323
5324 memcpy(buffer, context, sizeof(*context));
5325
5326out:
5327 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5328 return ret;
5329}
5330
5331static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev,
5332 struct hns_roce_v2_qp_context *context)
5333{
5334 u8 timeout;
5335
5336 timeout = (u8)hr_reg_read(context, QPC_AT);
5337 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
5338 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08;
5339
5340 return timeout;
5341}
5342
5343static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5344 int qp_attr_mask,
5345 struct ib_qp_init_attr *qp_init_attr)
5346{
5347 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5348 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5349 struct hns_roce_v2_qp_context context = {};
5350 struct ib_device *ibdev = &hr_dev->ib_dev;
5351 int tmp_qp_state;
5352 int state;
5353 int ret;
5354
5355 memset(qp_attr, 0, sizeof(*qp_attr));
5356 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5357
5358 mutex_lock(&hr_qp->mutex);
5359
5360 if (hr_qp->state == IB_QPS_RESET) {
5361 qp_attr->qp_state = IB_QPS_RESET;
5362 ret = 0;
5363 goto done;
5364 }
5365
5366 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context);
5367 if (ret) {
5368 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret);
5369 ret = -EINVAL;
5370 goto out;
5371 }
5372
5373 state = hr_reg_read(&context, QPC_QP_ST);
5374 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
5375 if (tmp_qp_state == -1) {
5376 ibdev_err(ibdev, "Illegal ib_qp_state\n");
5377 ret = -EINVAL;
5378 goto out;
5379 }
5380 hr_qp->state = (u8)tmp_qp_state;
5381 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
5382 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU);
5383 qp_attr->path_mig_state = IB_MIG_ARMED;
5384 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
5385 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
5386 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
5387
5388 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
5389 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
5390 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN);
5391 qp_attr->qp_access_flags =
5392 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
5393 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |
5394 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S);
5395
5396 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
5397 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5398 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
5399 struct ib_global_route *grh =
5400 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
5401
5402 rdma_ah_set_sl(&qp_attr->ah_attr,
5403 hr_reg_read(&context, QPC_SL));
5404 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1);
5405 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
5406 grh->flow_label = hr_reg_read(&context, QPC_FL);
5407 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX);
5408 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT);
5409 grh->traffic_class = hr_reg_read(&context, QPC_TC);
5410
5411 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
5412 }
5413
5414 qp_attr->port_num = hr_qp->port + 1;
5415 qp_attr->sq_draining = 0;
5416 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX);
5417 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);
5418
5419 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);
5420 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context);
5421 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);
5422 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);
5423
5424done:
5425 qp_attr->cur_qp_state = qp_attr->qp_state;
5426 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
5427 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge;
5428 qp_attr->cap.max_inline_data = hr_qp->max_inline_data;
5429
5430 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
5431 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
5432
5433 qp_init_attr->qp_context = ibqp->qp_context;
5434 qp_init_attr->qp_type = ibqp->qp_type;
5435 qp_init_attr->recv_cq = ibqp->recv_cq;
5436 qp_init_attr->send_cq = ibqp->send_cq;
5437 qp_init_attr->srq = ibqp->srq;
5438 qp_init_attr->cap = qp_attr->cap;
5439 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits;
5440
5441out:
5442 mutex_unlock(&hr_qp->mutex);
5443 return ret;
5444}
5445
5446static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp)
5447{
5448 return ((hr_qp->ibqp.qp_type == IB_QPT_RC ||
5449 hr_qp->ibqp.qp_type == IB_QPT_UD ||
5450 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
5451 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
5452 hr_qp->state != IB_QPS_RESET);
5453}
5454
5455static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
5456 struct hns_roce_qp *hr_qp,
5457 struct ib_udata *udata)
5458{
5459 struct ib_device *ibdev = &hr_dev->ib_dev;
5460 struct hns_roce_cq *send_cq, *recv_cq;
5461 unsigned long flags;
5462 int ret = 0;
5463
5464 if (modify_qp_is_ok(hr_qp)) {
5465 /* Modify qp to reset before destroying qp */
5466 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
5467 hr_qp->state, IB_QPS_RESET, udata);
5468 if (ret)
5469 ibdev_err(ibdev,
5470 "failed to modify QP to RST, ret = %d.\n",
5471 ret);
5472 }
5473
5474 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
5475 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
5476
5477 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
5478 hns_roce_lock_cqs(send_cq, recv_cq);
5479
5480 if (!udata) {
5481 if (recv_cq)
5482 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
5483 (hr_qp->ibqp.srq ?
5484 to_hr_srq(hr_qp->ibqp.srq) :
5485 NULL));
5486
5487 if (send_cq && send_cq != recv_cq)
5488 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
5489 }
5490
5491 hns_roce_qp_remove(hr_dev, hr_qp);
5492
5493 hns_roce_unlock_cqs(send_cq, recv_cq);
5494 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
5495
5496 return ret;
5497}
5498
5499int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
5500{
5501 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
5502 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
5503 int ret;
5504
5505 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
5506 if (ret)
5507 ibdev_err(&hr_dev->ib_dev,
5508 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n",
5509 hr_qp->qpn, ret);
5510
5511 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
5512
5513 return 0;
5514}
5515
5516static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
5517 struct hns_roce_qp *hr_qp)
5518{
5519 struct ib_device *ibdev = &hr_dev->ib_dev;
5520 struct hns_roce_sccc_clr_done *resp;
5521 struct hns_roce_sccc_clr *clr;
5522 struct hns_roce_cmq_desc desc;
5523 int ret, i;
5524
5525 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
5526 return 0;
5527
5528 mutex_lock(&hr_dev->qp_table.scc_mutex);
5529
5530 /* set scc ctx clear done flag */
5531 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
5532 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5533 if (ret) {
5534 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret);
5535 goto out;
5536 }
5537
5538 /* clear scc context */
5539 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
5540 clr = (struct hns_roce_sccc_clr *)desc.data;
5541 clr->qpn = cpu_to_le32(hr_qp->qpn);
5542 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5543 if (ret) {
5544 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret);
5545 goto out;
5546 }
5547
5548 /* query scc context clear is done or not */
5549 resp = (struct hns_roce_sccc_clr_done *)desc.data;
5550 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
5551 hns_roce_cmq_setup_basic_desc(&desc,
5552 HNS_ROCE_OPC_QUERY_SCCC, true);
5553 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
5554 if (ret) {
5555 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5556 ret);
5557 goto out;
5558 }
5559
5560 if (resp->clr_done)
5561 goto out;
5562
5563 msleep(20);
5564 }
5565
5566 ibdev_err(ibdev, "query SCC clr done flag overtime.\n");
5567 ret = -ETIMEDOUT;
5568
5569out:
5570 mutex_unlock(&hr_dev->qp_table.scc_mutex);
5571 return ret;
5572}
5573
5574#define DMA_IDX_SHIFT 3
5575#define DMA_WQE_SHIFT 3
5576
5577static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq,
5578 struct hns_roce_srq_context *ctx)
5579{
5580 struct hns_roce_idx_que *idx_que = &srq->idx_que;
5581 struct ib_device *ibdev = srq->ibsrq.device;
5582 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5583 u64 mtts_idx[MTT_MIN_COUNT] = {};
5584 dma_addr_t dma_handle_idx = 0;
5585 int ret;
5586
5587 /* Get physical address of idx que buf */
5588 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx,
5589 ARRAY_SIZE(mtts_idx), &dma_handle_idx);
5590 if (ret < 1) {
5591 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n",
5592 ret);
5593 return -ENOBUFS;
5594 }
5595
5596 hr_reg_write(ctx, SRQC_IDX_HOP_NUM,
5597 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt));
5598
5599 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT);
5600 hr_reg_write(ctx, SRQC_IDX_BT_BA_H,
5601 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT));
5602
5603 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ,
5604 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift));
5605 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ,
5606 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift));
5607
5608 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L,
5609 to_hr_hw_page_addr(mtts_idx[0]));
5610 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H,
5611 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5612
5613 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L,
5614 to_hr_hw_page_addr(mtts_idx[1]));
5615 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H,
5616 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5617
5618 return 0;
5619}
5620
5621static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf)
5622{
5623 struct ib_device *ibdev = srq->ibsrq.device;
5624 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);
5625 struct hns_roce_srq_context *ctx = mb_buf;
5626 u64 mtts_wqe[MTT_MIN_COUNT] = {};
5627 dma_addr_t dma_handle_wqe = 0;
5628 int ret;
5629
5630 memset(ctx, 0, sizeof(*ctx));
5631
5632 /* Get the physical address of srq buf */
5633 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe,
5634 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe);
5635 if (ret < 1) {
5636 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n",
5637 ret);
5638 return -ENOBUFS;
5639 }
5640
5641 hr_reg_write(ctx, SRQC_SRQ_ST, 1);
5642 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE,
5643 srq->ibsrq.srq_type == IB_SRQT_XRC);
5644 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn);
5645 hr_reg_write(ctx, SRQC_SRQN, srq->srqn);
5646 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn);
5647 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn);
5648 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt));
5649 hr_reg_write(ctx, SRQC_RQWS,
5650 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1));
5651
5652 hr_reg_write(ctx, SRQC_WQE_HOP_NUM,
5653 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
5654 srq->wqe_cnt));
5655
5656 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT);
5657 hr_reg_write(ctx, SRQC_WQE_BT_BA_H,
5658 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT));
5659
5660 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ,
5661 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5662 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ,
5663 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5664
5665 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) {
5666 hr_reg_enable(ctx, SRQC_DB_RECORD_EN);
5667 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L,
5668 lower_32_bits(srq->rdb.dma) >> 1);
5669 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H,
5670 upper_32_bits(srq->rdb.dma));
5671 }
5672
5673 return hns_roce_v2_write_srqc_index_queue(srq, ctx);
5674}
5675
5676static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5677 struct ib_srq_attr *srq_attr,
5678 enum ib_srq_attr_mask srq_attr_mask,
5679 struct ib_udata *udata)
5680{
5681 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5682 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5683 struct hns_roce_srq_context *srq_context;
5684 struct hns_roce_srq_context *srqc_mask;
5685 struct hns_roce_cmd_mailbox *mailbox;
5686 int ret = 0;
5687
5688 /* Resizing SRQs is not supported yet */
5689 if (srq_attr_mask & IB_SRQ_MAX_WR) {
5690 ret = -EOPNOTSUPP;
5691 goto out;
5692 }
5693
5694 if (srq_attr_mask & IB_SRQ_LIMIT) {
5695 if (srq_attr->srq_limit > srq->wqe_cnt) {
5696 ret = -EINVAL;
5697 goto out;
5698 }
5699
5700 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5701 if (IS_ERR(mailbox)) {
5702 ret = PTR_ERR(mailbox);
5703 goto out;
5704 }
5705
5706 srq_context = mailbox->buf;
5707 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5708
5709 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5710
5711 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit);
5712 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL);
5713
5714 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5715 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn);
5716 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5717 if (ret)
5718 ibdev_err(&hr_dev->ib_dev,
5719 "failed to handle cmd of modifying SRQ, ret = %d.\n",
5720 ret);
5721 }
5722
5723out:
5724 if (ret)
5725 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]);
5726
5727 return ret;
5728}
5729
5730static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5731{
5732 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5733 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5734 struct hns_roce_srq_context *srq_context;
5735 struct hns_roce_cmd_mailbox *mailbox;
5736 int ret;
5737
5738 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5739 if (IS_ERR(mailbox))
5740 return PTR_ERR(mailbox);
5741
5742 srq_context = mailbox->buf;
5743 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5744 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn);
5745 if (ret) {
5746 ibdev_err(&hr_dev->ib_dev,
5747 "failed to process cmd of querying SRQ, ret = %d.\n",
5748 ret);
5749 goto out;
5750 }
5751
5752 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL);
5753 attr->max_wr = srq->wqe_cnt;
5754 attr->max_sge = srq->max_gs - srq->rsv_sge;
5755
5756out:
5757 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5758 return ret;
5759}
5760
5761static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5762{
5763 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5764 struct hns_roce_v2_cq_context *cq_context;
5765 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5766 struct hns_roce_v2_cq_context *cqc_mask;
5767 struct hns_roce_cmd_mailbox *mailbox;
5768 int ret;
5769
5770 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5771 ret = PTR_ERR_OR_ZERO(mailbox);
5772 if (ret)
5773 goto err_out;
5774
5775 cq_context = mailbox->buf;
5776 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
5777
5778 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
5779
5780 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count);
5781 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT);
5782
5783 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
5784 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
5785 dev_info(hr_dev->dev,
5786 "cq_period(%u) reached the upper limit, adjusted to 65.\n",
5787 cq_period);
5788 cq_period = HNS_ROCE_MAX_CQ_PERIOD;
5789 }
5790 cq_period *= HNS_ROCE_CLOCK_ADJUST;
5791 }
5792 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period);
5793 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD);
5794
5795 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0,
5796 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn);
5797 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5798 if (ret)
5799 ibdev_err(&hr_dev->ib_dev,
5800 "failed to process cmd when modifying CQ, ret = %d.\n",
5801 ret);
5802
5803err_out:
5804 if (ret)
5805 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]);
5806
5807 return ret;
5808}
5809
5810static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn,
5811 void *buffer)
5812{
5813 struct hns_roce_v2_cq_context *context;
5814 struct hns_roce_cmd_mailbox *mailbox;
5815 int ret;
5816
5817 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5818 if (IS_ERR(mailbox))
5819 return PTR_ERR(mailbox);
5820
5821 context = mailbox->buf;
5822 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma,
5823 HNS_ROCE_CMD_QUERY_CQC, cqn);
5824 if (ret) {
5825 ibdev_err(&hr_dev->ib_dev,
5826 "failed to process cmd when querying CQ, ret = %d.\n",
5827 ret);
5828 goto err_mailbox;
5829 }
5830
5831 memcpy(buffer, context, sizeof(*context));
5832
5833err_mailbox:
5834 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5835
5836 return ret;
5837}
5838
5839static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key,
5840 void *buffer)
5841{
5842 struct hns_roce_v2_mpt_entry *context;
5843 struct hns_roce_cmd_mailbox *mailbox;
5844 int ret;
5845
5846 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5847 if (IS_ERR(mailbox))
5848 return PTR_ERR(mailbox);
5849
5850 context = mailbox->buf;
5851 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT,
5852 key_to_hw_index(key));
5853 if (ret) {
5854 ibdev_err(&hr_dev->ib_dev,
5855 "failed to process cmd when querying MPT, ret = %d.\n",
5856 ret);
5857 goto err_mailbox;
5858 }
5859
5860 memcpy(buffer, context, sizeof(*context));
5861
5862err_mailbox:
5863 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5864
5865 return ret;
5866}
5867
5868static void hns_roce_irq_work_handle(struct work_struct *work)
5869{
5870 struct hns_roce_work *irq_work =
5871 container_of(work, struct hns_roce_work, work);
5872 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;
5873
5874 switch (irq_work->event_type) {
5875 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5876 ibdev_info(ibdev, "path migrated succeeded.\n");
5877 break;
5878 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5879 ibdev_warn(ibdev, "path migration failed.\n");
5880 break;
5881 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5882 break;
5883 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5884 ibdev_dbg(ibdev, "send queue drained.\n");
5885 break;
5886 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5887 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n",
5888 irq_work->queue_num, irq_work->sub_type);
5889 break;
5890 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5891 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n",
5892 irq_work->queue_num);
5893 break;
5894 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5895 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n",
5896 irq_work->queue_num, irq_work->sub_type);
5897 break;
5898 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5899 ibdev_dbg(ibdev, "SRQ limit reach.\n");
5900 break;
5901 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5902 ibdev_dbg(ibdev, "SRQ last wqe reach.\n");
5903 break;
5904 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5905 ibdev_err(ibdev, "SRQ catas error.\n");
5906 break;
5907 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5908 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num);
5909 break;
5910 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5911 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num);
5912 break;
5913 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5914 ibdev_warn(ibdev, "DB overflow.\n");
5915 break;
5916 case HNS_ROCE_EVENT_TYPE_FLR:
5917 ibdev_warn(ibdev, "function level reset.\n");
5918 break;
5919 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
5920 ibdev_err(ibdev, "xrc domain violation error.\n");
5921 break;
5922 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
5923 ibdev_err(ibdev, "invalid xrceth error.\n");
5924 break;
5925 default:
5926 break;
5927 }
5928
5929 kfree(irq_work);
5930}
5931
5932static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
5933 struct hns_roce_eq *eq, u32 queue_num)
5934{
5935 struct hns_roce_work *irq_work;
5936
5937 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
5938 if (!irq_work)
5939 return;
5940
5941 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle);
5942 irq_work->hr_dev = hr_dev;
5943 irq_work->event_type = eq->event_type;
5944 irq_work->sub_type = eq->sub_type;
5945 irq_work->queue_num = queue_num;
5946 queue_work(hr_dev->irq_workq, &irq_work->work);
5947}
5948
5949static void update_eq_db(struct hns_roce_eq *eq)
5950{
5951 struct hns_roce_dev *hr_dev = eq->hr_dev;
5952 struct hns_roce_v2_db eq_db = {};
5953
5954 if (eq->type_flag == HNS_ROCE_AEQ) {
5955 hr_reg_write(&eq_db, EQ_DB_CMD,
5956 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5957 HNS_ROCE_EQ_DB_CMD_AEQ :
5958 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
5959 } else {
5960 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn);
5961
5962 hr_reg_write(&eq_db, EQ_DB_CMD,
5963 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5964 HNS_ROCE_EQ_DB_CMD_CEQ :
5965 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
5966 }
5967
5968 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index);
5969
5970 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg);
5971}
5972
5973static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
5974{
5975 struct hns_roce_aeqe *aeqe;
5976
5977 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
5978 (eq->cons_index & (eq->entries - 1)) *
5979 eq->eqe_size);
5980
5981 return (hr_reg_read(aeqe, AEQE_OWNER) ^
5982 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
5983}
5984
5985static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
5986 struct hns_roce_eq *eq)
5987{
5988 struct device *dev = hr_dev->dev;
5989 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
5990 irqreturn_t aeqe_found = IRQ_NONE;
5991 int event_type;
5992 u32 queue_num;
5993 int sub_type;
5994
5995 while (aeqe) {
5996 /* Make sure we read AEQ entry after we have checked the
5997 * ownership bit
5998 */
5999 dma_rmb();
6000
6001 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE);
6002 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE);
6003 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);
6004
6005 switch (event_type) {
6006 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
6007 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
6008 case HNS_ROCE_EVENT_TYPE_COMM_EST:
6009 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
6010 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
6011 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
6012 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
6013 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
6014 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION:
6015 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH:
6016 hns_roce_qp_event(hr_dev, queue_num, event_type);
6017 break;
6018 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
6019 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
6020 hns_roce_srq_event(hr_dev, queue_num, event_type);
6021 break;
6022 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
6023 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
6024 hns_roce_cq_event(hr_dev, queue_num, event_type);
6025 break;
6026 case HNS_ROCE_EVENT_TYPE_MB:
6027 hns_roce_cmd_event(hr_dev,
6028 le16_to_cpu(aeqe->event.cmd.token),
6029 aeqe->event.cmd.status,
6030 le64_to_cpu(aeqe->event.cmd.out_param));
6031 break;
6032 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
6033 case HNS_ROCE_EVENT_TYPE_FLR:
6034 break;
6035 default:
6036 dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n",
6037 event_type, eq->eqn, eq->cons_index);
6038 break;
6039 }
6040
6041 eq->event_type = event_type;
6042 eq->sub_type = sub_type;
6043 ++eq->cons_index;
6044 aeqe_found = IRQ_HANDLED;
6045
6046 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]);
6047
6048 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);
6049
6050 aeqe = next_aeqe_sw_v2(eq);
6051 }
6052
6053 update_eq_db(eq);
6054
6055 return IRQ_RETVAL(aeqe_found);
6056}
6057
6058static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
6059{
6060 struct hns_roce_ceqe *ceqe;
6061
6062 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
6063 (eq->cons_index & (eq->entries - 1)) *
6064 eq->eqe_size);
6065
6066 return (hr_reg_read(ceqe, CEQE_OWNER) ^
6067 !!(eq->cons_index & eq->entries)) ? ceqe : NULL;
6068}
6069
6070static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
6071 struct hns_roce_eq *eq)
6072{
6073 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
6074 irqreturn_t ceqe_found = IRQ_NONE;
6075 u32 cqn;
6076
6077 while (ceqe) {
6078 /* Make sure we read CEQ entry after we have checked the
6079 * ownership bit
6080 */
6081 dma_rmb();
6082
6083 cqn = hr_reg_read(ceqe, CEQE_CQN);
6084
6085 hns_roce_cq_completion(hr_dev, cqn);
6086
6087 ++eq->cons_index;
6088 ceqe_found = IRQ_HANDLED;
6089 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]);
6090
6091 ceqe = next_ceqe_sw_v2(eq);
6092 }
6093
6094 update_eq_db(eq);
6095
6096 return IRQ_RETVAL(ceqe_found);
6097}
6098
6099static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
6100{
6101 struct hns_roce_eq *eq = eq_ptr;
6102 struct hns_roce_dev *hr_dev = eq->hr_dev;
6103 irqreturn_t int_work;
6104
6105 if (eq->type_flag == HNS_ROCE_CEQ)
6106 /* Completion event interrupt */
6107 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
6108 else
6109 /* Asynchronous event interrupt */
6110 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
6111
6112 return IRQ_RETVAL(int_work);
6113}
6114
6115static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev,
6116 u32 int_st)
6117{
6118 struct pci_dev *pdev = hr_dev->pci_dev;
6119 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
6120 const struct hnae3_ae_ops *ops = ae_dev->ops;
6121 irqreturn_t int_work = IRQ_NONE;
6122 u32 int_en;
6123
6124 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
6125
6126 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
6127 dev_err(hr_dev->dev, "AEQ overflow!\n");
6128
6129 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,
6130 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
6131
6132 /* Set reset level for reset_event() */
6133 if (ops->set_default_reset_request)
6134 ops->set_default_reset_request(ae_dev,
6135 HNAE3_FUNC_RESET);
6136 if (ops->reset_event)
6137 ops->reset_event(pdev, NULL);
6138
6139 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
6140 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
6141
6142 int_work = IRQ_HANDLED;
6143 } else {
6144 dev_err(hr_dev->dev, "there is no basic abn irq found.\n");
6145 }
6146
6147 return IRQ_RETVAL(int_work);
6148}
6149
6150static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev,
6151 struct fmea_ram_ecc *ecc_info)
6152{
6153 struct hns_roce_cmq_desc desc;
6154 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6155 int ret;
6156
6157 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true);
6158 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6159 if (ret)
6160 return ret;
6161
6162 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR);
6163 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE);
6164 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG);
6165
6166 return 0;
6167}
6168
6169static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx)
6170{
6171 struct hns_roce_cmq_desc desc;
6172 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;
6173 u32 addr_upper;
6174 u32 addr_low;
6175 int ret;
6176
6177 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true);
6178 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6179
6180 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
6181 if (ret) {
6182 dev_err(hr_dev->dev,
6183 "failed to execute cmd to read gmv, ret = %d.\n", ret);
6184 return ret;
6185 }
6186
6187 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L);
6188 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H);
6189
6190 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false);
6191 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low);
6192 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper);
6193 hr_reg_write(req, CFG_GMV_BT_IDX, idx);
6194
6195 return hns_roce_cmq_send(hr_dev, &desc, 1);
6196}
6197
6198static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data)
6199{
6200 if (res_type == ECC_RESOURCE_QPC_TIMER ||
6201 res_type == ECC_RESOURCE_CQC_TIMER ||
6202 res_type == ECC_RESOURCE_SCCC)
6203 return le64_to_cpu(*data);
6204
6205 return le64_to_cpu(*data) << PAGE_SHIFT;
6206}
6207
6208static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type,
6209 u32 index)
6210{
6211 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op;
6212 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op;
6213 struct hns_roce_cmd_mailbox *mailbox;
6214 u64 addr;
6215 int ret;
6216
6217 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6218 if (IS_ERR(mailbox))
6219 return PTR_ERR(mailbox);
6220
6221 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index);
6222 if (ret) {
6223 dev_err(hr_dev->dev,
6224 "failed to execute cmd to read fmea ram, ret = %d.\n",
6225 ret);
6226 goto out;
6227 }
6228
6229 addr = fmea_get_ram_res_addr(res_type, mailbox->buf);
6230
6231 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index);
6232 if (ret)
6233 dev_err(hr_dev->dev,
6234 "failed to execute cmd to write fmea ram, ret = %d.\n",
6235 ret);
6236
6237out:
6238 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6239 return ret;
6240}
6241
6242static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev,
6243 struct fmea_ram_ecc *ecc_info)
6244{
6245 u32 res_type = ecc_info->res_type;
6246 u32 index = ecc_info->index;
6247 int ret;
6248
6249 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT);
6250
6251 if (res_type >= ECC_RESOURCE_COUNT) {
6252 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n",
6253 res_type);
6254 return;
6255 }
6256
6257 if (res_type == ECC_RESOURCE_GMV)
6258 ret = fmea_recover_gmv(hr_dev, index);
6259 else
6260 ret = fmea_recover_others(hr_dev, res_type, index);
6261 if (ret)
6262 dev_err(hr_dev->dev,
6263 "failed to recover %s, index = %u, ret = %d.\n",
6264 fmea_ram_res[res_type].name, index, ret);
6265}
6266
6267static void fmea_ram_ecc_work(struct work_struct *ecc_work)
6268{
6269 struct hns_roce_dev *hr_dev =
6270 container_of(ecc_work, struct hns_roce_dev, ecc_work);
6271 struct fmea_ram_ecc ecc_info = {};
6272
6273 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) {
6274 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n");
6275 return;
6276 }
6277
6278 if (!ecc_info.is_ecc_err) {
6279 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n");
6280 return;
6281 }
6282
6283 fmea_ram_ecc_recover(hr_dev, &ecc_info);
6284}
6285
6286static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
6287{
6288 struct hns_roce_dev *hr_dev = dev_id;
6289 irqreturn_t int_work = IRQ_NONE;
6290 u32 int_st;
6291
6292 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
6293
6294 if (int_st) {
6295 int_work = abnormal_interrupt_basic(hr_dev, int_st);
6296 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
6297 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work);
6298 int_work = IRQ_HANDLED;
6299 } else {
6300 dev_err(hr_dev->dev, "there is no abnormal irq found.\n");
6301 }
6302
6303 return IRQ_RETVAL(int_work);
6304}
6305
6306static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
6307 int eq_num, u32 enable_flag)
6308{
6309 int i;
6310
6311 for (i = 0; i < eq_num; i++)
6312 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
6313 i * EQ_REG_OFFSET, enable_flag);
6314
6315 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag);
6316 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);
6317}
6318
6319static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn)
6320{
6321 struct device *dev = hr_dev->dev;
6322 int ret;
6323 u8 cmd;
6324
6325 if (eqn < hr_dev->caps.num_comp_vectors)
6326 cmd = HNS_ROCE_CMD_DESTROY_CEQC;
6327 else
6328 cmd = HNS_ROCE_CMD_DESTROY_AEQC;
6329
6330 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);
6331 if (ret)
6332 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn);
6333}
6334
6335static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6336{
6337 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
6338}
6339
6340static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6341{
6342 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
6343 eq->cons_index = 0;
6344 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
6345 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
6346 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
6347 eq->shift = ilog2((unsigned int)eq->entries);
6348}
6349
6350static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
6351 void *mb_buf)
6352{
6353 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
6354 struct hns_roce_eq_context *eqc;
6355 u64 bt_ba = 0;
6356 int count;
6357
6358 eqc = mb_buf;
6359 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
6360
6361 init_eq_config(hr_dev, eq);
6362
6363 /* if not multi-hop, eqe buffer only use one trunk */
6364 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
6365 &bt_ba);
6366 if (count < 1) {
6367 dev_err(hr_dev->dev, "failed to find EQE mtr\n");
6368 return -ENOBUFS;
6369 }
6370
6371 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
6372 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
6373 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
6374 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
6375 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
6376 hr_reg_write(eqc, EQC_EQN, eq->eqn);
6377 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
6378 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
6379 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
6380 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
6381 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
6382 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
6383 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
6384
6385 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6386 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) {
6387 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n",
6388 eq->eq_period);
6389 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD;
6390 }
6391 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST;
6392 }
6393
6394 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
6395 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
6396 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
6397 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
6398 hr_reg_write(eqc, EQC_SHIFT, eq->shift);
6399 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
6400 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
6401 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
6402 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
6403 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
6404 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
6405 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
6406 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE);
6407
6408 return 0;
6409}
6410
6411static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
6412{
6413 struct hns_roce_buf_attr buf_attr = {};
6414 int err;
6415
6416 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
6417 eq->hop_num = 0;
6418 else
6419 eq->hop_num = hr_dev->caps.eqe_hop_num;
6420
6421 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT;
6422 buf_attr.region[0].size = eq->entries * eq->eqe_size;
6423 buf_attr.region[0].hopnum = eq->hop_num;
6424 buf_attr.region_count = 1;
6425
6426 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
6427 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL,
6428 0);
6429 if (err)
6430 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err);
6431
6432 return err;
6433}
6434
6435static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
6436 struct hns_roce_eq *eq, u8 eq_cmd)
6437{
6438 struct hns_roce_cmd_mailbox *mailbox;
6439 int ret;
6440
6441 /* Allocate mailbox memory */
6442 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
6443 if (IS_ERR(mailbox))
6444 return PTR_ERR(mailbox);
6445
6446 ret = alloc_eq_buf(hr_dev, eq);
6447 if (ret)
6448 goto free_cmd_mbox;
6449
6450 ret = config_eqc(hr_dev, eq, mailbox->buf);
6451 if (ret)
6452 goto err_cmd_mbox;
6453
6454 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn);
6455 if (ret) {
6456 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
6457 goto err_cmd_mbox;
6458 }
6459
6460 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6461
6462 return 0;
6463
6464err_cmd_mbox:
6465 free_eq_buf(hr_dev, eq);
6466
6467free_cmd_mbox:
6468 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
6469
6470 return ret;
6471}
6472
6473static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
6474 int comp_num, int aeq_num, int other_num)
6475{
6476 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6477 int i, j;
6478 int ret;
6479
6480 for (i = 0; i < irq_num; i++) {
6481 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
6482 GFP_KERNEL);
6483 if (!hr_dev->irq_names[i]) {
6484 ret = -ENOMEM;
6485 goto err_kzalloc_failed;
6486 }
6487 }
6488
6489 /* irq contains: abnormal + AEQ + CEQ */
6490 for (j = 0; j < other_num; j++)
6491 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6492 "hns-%s-abn-%d", pci_name(hr_dev->pci_dev), j);
6493
6494 for (j = other_num; j < (other_num + aeq_num); j++)
6495 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6496 "hns-%s-aeq-%d", pci_name(hr_dev->pci_dev), j - other_num);
6497
6498 for (j = (other_num + aeq_num); j < irq_num; j++)
6499 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
6500 "hns-%s-ceq-%d", pci_name(hr_dev->pci_dev),
6501 j - other_num - aeq_num);
6502
6503 for (j = 0; j < irq_num; j++) {
6504 if (j < other_num)
6505 ret = request_irq(hr_dev->irq[j],
6506 hns_roce_v2_msix_interrupt_abn,
6507 0, hr_dev->irq_names[j], hr_dev);
6508
6509 else if (j < (other_num + comp_num))
6510 ret = request_irq(eq_table->eq[j - other_num].irq,
6511 hns_roce_v2_msix_interrupt_eq,
6512 0, hr_dev->irq_names[j + aeq_num],
6513 &eq_table->eq[j - other_num]);
6514 else
6515 ret = request_irq(eq_table->eq[j - other_num].irq,
6516 hns_roce_v2_msix_interrupt_eq,
6517 0, hr_dev->irq_names[j - comp_num],
6518 &eq_table->eq[j - other_num]);
6519 if (ret) {
6520 dev_err(hr_dev->dev, "request irq error!\n");
6521 goto err_request_failed;
6522 }
6523 }
6524
6525 return 0;
6526
6527err_request_failed:
6528 for (j -= 1; j >= 0; j--)
6529 if (j < other_num)
6530 free_irq(hr_dev->irq[j], hr_dev);
6531 else
6532 free_irq(eq_table->eq[j - other_num].irq,
6533 &eq_table->eq[j - other_num]);
6534
6535err_kzalloc_failed:
6536 for (i -= 1; i >= 0; i--)
6537 kfree(hr_dev->irq_names[i]);
6538
6539 return ret;
6540}
6541
6542static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
6543{
6544 int irq_num;
6545 int eq_num;
6546 int i;
6547
6548 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6549 irq_num = eq_num + hr_dev->caps.num_other_vectors;
6550
6551 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
6552 free_irq(hr_dev->irq[i], hr_dev);
6553
6554 for (i = 0; i < eq_num; i++)
6555 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
6556
6557 for (i = 0; i < irq_num; i++)
6558 kfree(hr_dev->irq_names[i]);
6559}
6560
6561static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
6562{
6563 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6564 struct device *dev = hr_dev->dev;
6565 struct hns_roce_eq *eq;
6566 int other_num;
6567 int comp_num;
6568 int aeq_num;
6569 int irq_num;
6570 int eq_num;
6571 u8 eq_cmd;
6572 int ret;
6573 int i;
6574
6575 other_num = hr_dev->caps.num_other_vectors;
6576 comp_num = hr_dev->caps.num_comp_vectors;
6577 aeq_num = hr_dev->caps.num_aeq_vectors;
6578
6579 eq_num = comp_num + aeq_num;
6580 irq_num = eq_num + other_num;
6581
6582 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
6583 if (!eq_table->eq)
6584 return -ENOMEM;
6585
6586 /* create eq */
6587 for (i = 0; i < eq_num; i++) {
6588 eq = &eq_table->eq[i];
6589 eq->hr_dev = hr_dev;
6590 eq->eqn = i;
6591 if (i < comp_num) {
6592 /* CEQ */
6593 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
6594 eq->type_flag = HNS_ROCE_CEQ;
6595 eq->entries = hr_dev->caps.ceqe_depth;
6596 eq->eqe_size = hr_dev->caps.ceqe_size;
6597 eq->irq = hr_dev->irq[i + other_num + aeq_num];
6598 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
6599 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
6600 } else {
6601 /* AEQ */
6602 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
6603 eq->type_flag = HNS_ROCE_AEQ;
6604 eq->entries = hr_dev->caps.aeqe_depth;
6605 eq->eqe_size = hr_dev->caps.aeqe_size;
6606 eq->irq = hr_dev->irq[i - comp_num + other_num];
6607 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
6608 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
6609 }
6610
6611 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
6612 if (ret) {
6613 dev_err(dev, "failed to create eq.\n");
6614 goto err_create_eq_fail;
6615 }
6616 }
6617
6618 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work);
6619
6620 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
6621 if (!hr_dev->irq_workq) {
6622 dev_err(dev, "failed to create irq workqueue.\n");
6623 ret = -ENOMEM;
6624 goto err_create_eq_fail;
6625 }
6626
6627 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num,
6628 other_num);
6629 if (ret) {
6630 dev_err(dev, "failed to request irq.\n");
6631 goto err_request_irq_fail;
6632 }
6633
6634 /* enable irq */
6635 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
6636
6637 return 0;
6638
6639err_request_irq_fail:
6640 destroy_workqueue(hr_dev->irq_workq);
6641
6642err_create_eq_fail:
6643 for (i -= 1; i >= 0; i--)
6644 free_eq_buf(hr_dev, &eq_table->eq[i]);
6645 kfree(eq_table->eq);
6646
6647 return ret;
6648}
6649
6650static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
6651{
6652 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
6653 int eq_num;
6654 int i;
6655
6656 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
6657
6658 /* Disable irq */
6659 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
6660
6661 __hns_roce_free_irq(hr_dev);
6662 destroy_workqueue(hr_dev->irq_workq);
6663
6664 for (i = 0; i < eq_num; i++) {
6665 hns_roce_v2_destroy_eqc(hr_dev, i);
6666
6667 free_eq_buf(hr_dev, &eq_table->eq[i]);
6668 }
6669
6670 kfree(eq_table->eq);
6671}
6672
6673static const struct ib_device_ops hns_roce_v2_dev_ops = {
6674 .destroy_qp = hns_roce_v2_destroy_qp,
6675 .modify_cq = hns_roce_v2_modify_cq,
6676 .poll_cq = hns_roce_v2_poll_cq,
6677 .post_recv = hns_roce_v2_post_recv,
6678 .post_send = hns_roce_v2_post_send,
6679 .query_qp = hns_roce_v2_query_qp,
6680 .req_notify_cq = hns_roce_v2_req_notify_cq,
6681};
6682
6683static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6684 .modify_srq = hns_roce_v2_modify_srq,
6685 .post_srq_recv = hns_roce_v2_post_srq_recv,
6686 .query_srq = hns_roce_v2_query_srq,
6687};
6688
6689static const struct hns_roce_hw hns_roce_hw_v2 = {
6690 .cmq_init = hns_roce_v2_cmq_init,
6691 .cmq_exit = hns_roce_v2_cmq_exit,
6692 .hw_profile = hns_roce_v2_profile,
6693 .hw_init = hns_roce_v2_init,
6694 .hw_exit = hns_roce_v2_exit,
6695 .post_mbox = v2_post_mbox,
6696 .poll_mbox_done = v2_poll_mbox_done,
6697 .chk_mbox_avail = v2_chk_mbox_is_avail,
6698 .set_gid = hns_roce_v2_set_gid,
6699 .set_mac = hns_roce_v2_set_mac,
6700 .write_mtpt = hns_roce_v2_write_mtpt,
6701 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
6702 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
6703 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
6704 .write_cqc = hns_roce_v2_write_cqc,
6705 .set_hem = hns_roce_v2_set_hem,
6706 .clear_hem = hns_roce_v2_clear_hem,
6707 .modify_qp = hns_roce_v2_modify_qp,
6708 .dereg_mr = hns_roce_v2_dereg_mr,
6709 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
6710 .init_eq = hns_roce_v2_init_eq_table,
6711 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
6712 .write_srqc = hns_roce_v2_write_srqc,
6713 .query_cqc = hns_roce_v2_query_cqc,
6714 .query_qpc = hns_roce_v2_query_qpc,
6715 .query_mpt = hns_roce_v2_query_mpt,
6716 .query_srqc = hns_roce_v2_query_srqc,
6717 .query_hw_counter = hns_roce_hw_v2_query_counter,
6718 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6719 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
6720};
6721
6722static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6723 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6724 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
6725 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6726 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
6727 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6728 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
6729 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
6730 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
6731 /* required last entry */
6732 {0, }
6733};
6734
6735MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6736
6737static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
6738 struct hnae3_handle *handle)
6739{
6740 struct hns_roce_v2_priv *priv = hr_dev->priv;
6741 const struct pci_device_id *id;
6742 int i;
6743
6744 hr_dev->pci_dev = handle->pdev;
6745 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
6746 hr_dev->is_vf = id->driver_data;
6747 hr_dev->dev = &handle->pdev->dev;
6748 hr_dev->hw = &hns_roce_hw_v2;
6749 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6750 hr_dev->odb_offset = hr_dev->sdb_offset;
6751
6752 /* Get info from NIC driver. */
6753 hr_dev->reg_base = handle->rinfo.roce_io_base;
6754 hr_dev->mem_base = handle->rinfo.roce_mem_base;
6755 hr_dev->caps.num_ports = 1;
6756 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6757 hr_dev->iboe.phy_port[0] = 0;
6758
6759 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6760 hr_dev->iboe.netdevs[0]->dev_addr);
6761
6762 for (i = 0; i < handle->rinfo.num_vectors; i++)
6763 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6764 i + handle->rinfo.base_vector);
6765
6766 /* cmd issue mode: 0 is poll, 1 is event */
6767 hr_dev->cmd_mod = 1;
6768 hr_dev->loop_idc = 0;
6769
6770 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6771 priv->handle = handle;
6772}
6773
6774static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6775{
6776 struct hns_roce_dev *hr_dev;
6777 int ret;
6778
6779 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
6780 if (!hr_dev)
6781 return -ENOMEM;
6782
6783 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6784 if (!hr_dev->priv) {
6785 ret = -ENOMEM;
6786 goto error_failed_kzalloc;
6787 }
6788
6789 hns_roce_hw_v2_get_cfg(hr_dev, handle);
6790
6791 ret = hns_roce_init(hr_dev);
6792 if (ret) {
6793 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6794 goto error_failed_roce_init;
6795 }
6796
6797 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) {
6798 ret = free_mr_init(hr_dev);
6799 if (ret) {
6800 dev_err(hr_dev->dev, "failed to init free mr!\n");
6801 goto error_failed_free_mr_init;
6802 }
6803 }
6804
6805 handle->priv = hr_dev;
6806
6807 return 0;
6808
6809error_failed_free_mr_init:
6810 hns_roce_exit(hr_dev);
6811
6812error_failed_roce_init:
6813 kfree(hr_dev->priv);
6814
6815error_failed_kzalloc:
6816 ib_dealloc_device(&hr_dev->ib_dev);
6817
6818 return ret;
6819}
6820
6821static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6822 bool reset)
6823{
6824 struct hns_roce_dev *hr_dev = handle->priv;
6825
6826 if (!hr_dev)
6827 return;
6828
6829 handle->priv = NULL;
6830
6831 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6832 hns_roce_handle_device_err(hr_dev);
6833
6834 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
6835 free_mr_exit(hr_dev);
6836
6837 hns_roce_exit(hr_dev);
6838 kfree(hr_dev->priv);
6839 ib_dealloc_device(&hr_dev->ib_dev);
6840}
6841
6842static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6843{
6844 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
6845 const struct pci_device_id *id;
6846 struct device *dev = &handle->pdev->dev;
6847 int ret;
6848
6849 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6850
6851 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6852 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6853 goto reset_chk_err;
6854 }
6855
6856 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6857 if (!id)
6858 return 0;
6859
6860 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08)
6861 return 0;
6862
6863 ret = __hns_roce_hw_v2_init_instance(handle);
6864 if (ret) {
6865 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6866 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6867 if (ops->ae_dev_resetting(handle) ||
6868 ops->get_hw_reset_stat(handle))
6869 goto reset_chk_err;
6870 else
6871 return ret;
6872 }
6873
6874 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6875
6876 return 0;
6877
6878reset_chk_err:
6879 dev_err(dev, "Device is busy in resetting state.\n"
6880 "please retry later.\n");
6881
6882 return -EBUSY;
6883}
6884
6885static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6886 bool reset)
6887{
6888 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6889 return;
6890
6891 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6892
6893 __hns_roce_hw_v2_uninit_instance(handle, reset);
6894
6895 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6896}
6897static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6898{
6899 struct hns_roce_dev *hr_dev;
6900
6901 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6902 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6903 return 0;
6904 }
6905
6906 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6907 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6908
6909 hr_dev = handle->priv;
6910 if (!hr_dev)
6911 return 0;
6912
6913 hr_dev->active = false;
6914 hr_dev->dis_db = true;
6915 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
6916
6917 return 0;
6918}
6919
6920static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6921{
6922 struct device *dev = &handle->pdev->dev;
6923 int ret;
6924
6925 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6926 &handle->rinfo.state)) {
6927 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6928 return 0;
6929 }
6930
6931 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6932
6933 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6934 ret = __hns_roce_hw_v2_init_instance(handle);
6935 if (ret) {
6936 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6937 * callback function, RoCE Engine reinitialize. If RoCE reinit
6938 * failed, we should inform NIC driver.
6939 */
6940 handle->priv = NULL;
6941 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6942 } else {
6943 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6944 dev_info(dev, "reset done, RoCE client reinit finished.\n");
6945 }
6946
6947 return ret;
6948}
6949
6950static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6951{
6952 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6953 return 0;
6954
6955 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6956 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
6957 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
6958 __hns_roce_hw_v2_uninit_instance(handle, false);
6959
6960 return 0;
6961}
6962
6963static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6964 enum hnae3_reset_notify_type type)
6965{
6966 int ret = 0;
6967
6968 switch (type) {
6969 case HNAE3_DOWN_CLIENT:
6970 ret = hns_roce_hw_v2_reset_notify_down(handle);
6971 break;
6972 case HNAE3_INIT_CLIENT:
6973 ret = hns_roce_hw_v2_reset_notify_init(handle);
6974 break;
6975 case HNAE3_UNINIT_CLIENT:
6976 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6977 break;
6978 default:
6979 break;
6980 }
6981
6982 return ret;
6983}
6984
6985static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6986 .init_instance = hns_roce_hw_v2_init_instance,
6987 .uninit_instance = hns_roce_hw_v2_uninit_instance,
6988 .reset_notify = hns_roce_hw_v2_reset_notify,
6989};
6990
6991static struct hnae3_client hns_roce_hw_v2_client = {
6992 .name = "hns_roce_hw_v2",
6993 .type = HNAE3_CLIENT_ROCE,
6994 .ops = &hns_roce_hw_v2_ops,
6995};
6996
6997static int __init hns_roce_hw_v2_init(void)
6998{
6999 hns_roce_init_debugfs();
7000 return hnae3_register_client(&hns_roce_hw_v2_client);
7001}
7002
7003static void __exit hns_roce_hw_v2_exit(void)
7004{
7005 hnae3_unregister_client(&hns_roce_hw_v2_client);
7006 hns_roce_cleanup_debugfs();
7007}
7008
7009module_init(hns_roce_hw_v2_init);
7010module_exit(hns_roce_hw_v2_exit);
7011
7012MODULE_LICENSE("Dual BSD/GPL");
7013MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
7014MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
7015MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
7016MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");