1/*
  2 * Copyright (c) 2016 Hisilicon Limited.
  3 *
  4 * This software is available to you under a choice of one of two
  5 * licenses.  You may choose to be licensed under the terms of the GNU
  6 * General Public License (GPL) Version 2, available from the file
  7 * COPYING in the main directory of this source tree, or the
  8 * OpenIB.org BSD license below:
  9 *
 10 *     Redistribution and use in source and binary forms, with or
 11 *     without modification, are permitted provided that the following
 12 *     conditions are met:
 13 *
 14 *      - Redistributions of source code must retain the above
 15 *        copyright notice, this list of conditions and the following
 16 *        disclaimer.
 17 *
 18 *      - Redistributions in binary form must reproduce the above
 19 *        copyright notice, this list of conditions and the following
 20 *        disclaimer in the documentation and/or other materials
 21 *        provided with the distribution.
 22 *
 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 30 * SOFTWARE.
 31 */
 32
 33#ifndef _HNS_ROCE_EQ_H
 34#define _HNS_ROCE_EQ_H
 35
 36#define HNS_ROCE_CEQ			1
 37#define HNS_ROCE_AEQ			2
 38
 39#define HNS_ROCE_CEQ_ENTRY_SIZE		0x4
 40#define HNS_ROCE_AEQ_ENTRY_SIZE		0x10
 41#define HNS_ROCE_CEQC_REG_OFFSET	0x18
 42
 43#define HNS_ROCE_CEQ_DEFAULT_INTERVAL	0x10
 44#define HNS_ROCE_CEQ_DEFAULT_BURST_NUM	0x10
 45
 46#define HNS_ROCE_INT_MASK_DISABLE	0
 47#define HNS_ROCE_INT_MASK_ENABLE	1
 48
 49#define EQ_ENABLE			1
 50#define EQ_DISABLE			0
 51#define CONS_INDEX_MASK			0xffff
 52
 53#define CEQ_REG_OFFSET			0x18
 54
 55enum {
 56	HNS_ROCE_EQ_STAT_INVALID  = 0,
 57	HNS_ROCE_EQ_STAT_VALID    = 2,
 58};
 59
 60struct hns_roce_aeqe {
 61	u32 asyn;
 62	union {
 63		struct {
 64			u32 qp;
 65			u32 rsv0;
 66			u32 rsv1;
 67		} qp_event;
 68
 69		struct {
 70			u32 cq;
 71			u32 rsv0;
 72			u32 rsv1;
 73		} cq_event;
 74
 75		struct {
 76			u32 port;
 77			u32 rsv0;
 78			u32 rsv1;
 79		} port_event;
 80
 81		struct {
 82			u32 ceqe;
 83			u32 rsv0;
 84			u32 rsv1;
 85		} ce_event;
 86
 87		struct {
 88			__le64  out_param;
 89			__le16  token;
 90			u8	status;
 91			u8	rsv0;
 92		} __packed cmd;
 93	 } event;
 94};
 95
 96#define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S 16
 97#define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M   \
 98	(((1UL << 8) - 1) << HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S)
 99
100#define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S 24
101#define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M   \
102	(((1UL << 7) - 1) << HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)
103
104#define HNS_ROCE_AEQE_U32_4_OWNER_S 31
105
106#define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S 0
107#define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M   \
108	(((1UL << 24) - 1) << HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S)
109
110#define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S 25
111#define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M   \
112	(((1UL << 3) - 1) << HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S)
113
114#define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S 0
115#define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M   \
116	(((1UL << 16) - 1) << HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S)
117
118#define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S 0
119#define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M   \
120	(((1UL << 5) - 1) << HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S)
121
122struct hns_roce_ceqe {
123	union {
124		int		comp;
125	} ceqe;
126};
127
128#define HNS_ROCE_CEQE_CEQE_COMP_OWNER_S	0
129
130#define HNS_ROCE_CEQE_CEQE_COMP_CQN_S 16
131#define HNS_ROCE_CEQE_CEQE_COMP_CQN_M   \
132	(((1UL << 16) - 1) << HNS_ROCE_CEQE_CEQE_COMP_CQN_S)
133
134#endif /* _HNS_ROCE_EQ_H */