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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Synopsys DesignWare I2C adapter driver (master only).
4 *
5 * Based on the TI DAVINCI I2C adapter driver.
6 *
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
10 * Copyright (C) 2011, 2015, 2016 Intel Corporation.
11 */
12#include <linux/acpi.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/errno.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/pm_runtime.h>
23#include <linux/power_supply.h>
24#include <linux/sched.h>
25#include <linux/slab.h>
26
27#include "i2c-designware-core.h"
28#include "i2c-ccgx-ucsi.h"
29
30#define DRIVER_NAME "i2c-designware-pci"
31
32enum dw_pci_ctl_id_t {
33 medfield,
34 merrifield,
35 baytrail,
36 cherrytrail,
37 haswell,
38 elkhartlake,
39 navi_amd,
40};
41
42/*
43 * This is a legacy structure to describe the hardware counters
44 * to configure signal timings on the bus. For Device Tree platforms
45 * one should use the respective properties and for ACPI there is
46 * a set of ACPI methods that provide these counters. No new
47 * platform should use this structure.
48 */
49struct dw_scl_sda_cfg {
50 u16 ss_hcnt;
51 u16 fs_hcnt;
52 u16 ss_lcnt;
53 u16 fs_lcnt;
54 u32 sda_hold;
55};
56
57struct dw_pci_controller {
58 u32 bus_num;
59 u32 flags;
60 struct dw_scl_sda_cfg *scl_sda_cfg;
61 int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
62 u32 (*get_clk_rate_khz)(struct dw_i2c_dev *dev);
63};
64
65/* Merrifield HCNT/LCNT/SDA hold time */
66static struct dw_scl_sda_cfg mrfld_config = {
67 .ss_hcnt = 0x2f8,
68 .fs_hcnt = 0x87,
69 .ss_lcnt = 0x37b,
70 .fs_lcnt = 0x10a,
71};
72
73/* BayTrail HCNT/LCNT/SDA hold time */
74static struct dw_scl_sda_cfg byt_config = {
75 .ss_hcnt = 0x200,
76 .fs_hcnt = 0x55,
77 .ss_lcnt = 0x200,
78 .fs_lcnt = 0x99,
79 .sda_hold = 0x6,
80};
81
82/* Haswell HCNT/LCNT/SDA hold time */
83static struct dw_scl_sda_cfg hsw_config = {
84 .ss_hcnt = 0x01b0,
85 .fs_hcnt = 0x48,
86 .ss_lcnt = 0x01fb,
87 .fs_lcnt = 0xa0,
88 .sda_hold = 0x9,
89};
90
91/* NAVI-AMD HCNT/LCNT/SDA hold time */
92static struct dw_scl_sda_cfg navi_amd_config = {
93 .ss_hcnt = 0x1ae,
94 .ss_lcnt = 0x23a,
95 .sda_hold = 0x9,
96};
97
98static u32 mfld_get_clk_rate_khz(struct dw_i2c_dev *dev)
99{
100 return 25000;
101}
102
103static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
104{
105 struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev);
106
107 switch (pdev->device) {
108 case 0x0817:
109 dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
110 fallthrough;
111 case 0x0818:
112 case 0x0819:
113 c->bus_num = pdev->device - 0x817 + 3;
114 return 0;
115 case 0x082C:
116 case 0x082D:
117 case 0x082E:
118 c->bus_num = pdev->device - 0x82C + 0;
119 return 0;
120 }
121 return -ENODEV;
122}
123
124static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
125{
126 /*
127 * On Intel Merrifield the user visible i2c buses are enumerated
128 * [1..7]. So, we add 1 to shift the default range. Besides that the
129 * first PCI slot provides 4 functions, that's why we have to add 0 to
130 * the first slot and 4 to the next one.
131 */
132 switch (PCI_SLOT(pdev->devfn)) {
133 case 8:
134 c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
135 return 0;
136 case 9:
137 c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
138 return 0;
139 }
140 return -ENODEV;
141}
142
143static u32 ehl_get_clk_rate_khz(struct dw_i2c_dev *dev)
144{
145 return 100000;
146}
147
148static u32 navi_amd_get_clk_rate_khz(struct dw_i2c_dev *dev)
149{
150 return 100000;
151}
152
153static int navi_amd_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
154{
155 struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev);
156
157 dev->flags |= MODEL_AMD_NAVI_GPU;
158 dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
159 return 0;
160}
161
162static struct dw_pci_controller dw_pci_controllers[] = {
163 [medfield] = {
164 .bus_num = -1,
165 .setup = mfld_setup,
166 .get_clk_rate_khz = mfld_get_clk_rate_khz,
167 },
168 [merrifield] = {
169 .bus_num = -1,
170 .scl_sda_cfg = &mrfld_config,
171 .setup = mrfld_setup,
172 },
173 [baytrail] = {
174 .bus_num = -1,
175 .scl_sda_cfg = &byt_config,
176 },
177 [haswell] = {
178 .bus_num = -1,
179 .scl_sda_cfg = &hsw_config,
180 },
181 [cherrytrail] = {
182 .bus_num = -1,
183 .scl_sda_cfg = &byt_config,
184 },
185 [elkhartlake] = {
186 .bus_num = -1,
187 .get_clk_rate_khz = ehl_get_clk_rate_khz,
188 },
189 [navi_amd] = {
190 .bus_num = -1,
191 .scl_sda_cfg = &navi_amd_config,
192 .setup = navi_amd_setup,
193 .get_clk_rate_khz = navi_amd_get_clk_rate_khz,
194 },
195};
196
197static int __maybe_unused i2c_dw_pci_runtime_suspend(struct device *dev)
198{
199 struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
200
201 i_dev->disable(i_dev);
202 return 0;
203}
204
205static int __maybe_unused i2c_dw_pci_suspend(struct device *dev)
206{
207 struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
208
209 i2c_mark_adapter_suspended(&i_dev->adapter);
210
211 return i2c_dw_pci_runtime_suspend(dev);
212}
213
214static int __maybe_unused i2c_dw_pci_runtime_resume(struct device *dev)
215{
216 struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
217
218 return i_dev->init(i_dev);
219}
220
221static int __maybe_unused i2c_dw_pci_resume(struct device *dev)
222{
223 struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
224 int ret;
225
226 ret = i2c_dw_pci_runtime_resume(dev);
227
228 i2c_mark_adapter_resumed(&i_dev->adapter);
229
230 return ret;
231}
232
233static const struct dev_pm_ops i2c_dw_pm_ops = {
234 SET_SYSTEM_SLEEP_PM_OPS(i2c_dw_pci_suspend, i2c_dw_pci_resume)
235 SET_RUNTIME_PM_OPS(i2c_dw_pci_runtime_suspend, i2c_dw_pci_runtime_resume, NULL)
236};
237
238static const struct property_entry dgpu_properties[] = {
239 /* USB-C doesn't power the system */
240 PROPERTY_ENTRY_U8("scope", POWER_SUPPLY_SCOPE_DEVICE),
241 {}
242};
243
244static const struct software_node dgpu_node = {
245 .properties = dgpu_properties,
246};
247
248static int i2c_dw_pci_probe(struct pci_dev *pdev,
249 const struct pci_device_id *id)
250{
251 struct dw_i2c_dev *dev;
252 struct i2c_adapter *adap;
253 int r;
254 struct dw_pci_controller *controller;
255 struct dw_scl_sda_cfg *cfg;
256 struct i2c_timings *t;
257
258 if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers))
259 return dev_err_probe(&pdev->dev, -EINVAL,
260 "Invalid driver data %ld\n",
261 id->driver_data);
262
263 controller = &dw_pci_controllers[id->driver_data];
264
265 r = pcim_enable_device(pdev);
266 if (r)
267 return dev_err_probe(&pdev->dev, r,
268 "Failed to enable I2C PCI device\n");
269
270 pci_set_master(pdev);
271
272 r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
273 if (r)
274 return dev_err_probe(&pdev->dev, r,
275 "I/O memory remapping failed\n");
276
277 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
278 if (!dev)
279 return -ENOMEM;
280
281 r = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
282 if (r < 0)
283 return r;
284
285 dev->get_clk_rate_khz = controller->get_clk_rate_khz;
286 dev->base = pcim_iomap_table(pdev)[0];
287 dev->dev = &pdev->dev;
288 dev->irq = pci_irq_vector(pdev, 0);
289 dev->flags |= controller->flags;
290
291 t = &dev->timings;
292 i2c_parse_fw_timings(&pdev->dev, t, false);
293
294 pci_set_drvdata(pdev, dev);
295
296 if (controller->setup) {
297 r = controller->setup(pdev, controller);
298 if (r) {
299 pci_free_irq_vectors(pdev);
300 return r;
301 }
302 }
303
304 i2c_dw_adjust_bus_speed(dev);
305
306 if (has_acpi_companion(&pdev->dev))
307 i2c_dw_acpi_configure(&pdev->dev);
308
309 r = i2c_dw_validate_speed(dev);
310 if (r) {
311 pci_free_irq_vectors(pdev);
312 return r;
313 }
314
315 i2c_dw_configure(dev);
316
317 if (controller->scl_sda_cfg) {
318 cfg = controller->scl_sda_cfg;
319 dev->ss_hcnt = cfg->ss_hcnt;
320 dev->fs_hcnt = cfg->fs_hcnt;
321 dev->ss_lcnt = cfg->ss_lcnt;
322 dev->fs_lcnt = cfg->fs_lcnt;
323 dev->sda_hold_time = cfg->sda_hold;
324 }
325
326 adap = &dev->adapter;
327 adap->owner = THIS_MODULE;
328 adap->class = 0;
329 ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
330 adap->nr = controller->bus_num;
331
332 r = i2c_dw_probe(dev);
333 if (r) {
334 pci_free_irq_vectors(pdev);
335 return r;
336 }
337
338 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) {
339 dev->slave = i2c_new_ccgx_ucsi(&dev->adapter, dev->irq, &dgpu_node);
340 if (IS_ERR(dev->slave))
341 return dev_err_probe(dev->dev, PTR_ERR(dev->slave),
342 "register UCSI failed\n");
343 }
344
345 pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
346 pm_runtime_use_autosuspend(&pdev->dev);
347 pm_runtime_put_autosuspend(&pdev->dev);
348 pm_runtime_allow(&pdev->dev);
349
350 return 0;
351}
352
353static void i2c_dw_pci_remove(struct pci_dev *pdev)
354{
355 struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
356
357 dev->disable(dev);
358 pm_runtime_forbid(&pdev->dev);
359 pm_runtime_get_noresume(&pdev->dev);
360
361 i2c_del_adapter(&dev->adapter);
362 devm_free_irq(&pdev->dev, dev->irq, dev);
363 pci_free_irq_vectors(pdev);
364}
365
366static const struct pci_device_id i2_designware_pci_ids[] = {
367 /* Medfield */
368 { PCI_VDEVICE(INTEL, 0x0817), medfield },
369 { PCI_VDEVICE(INTEL, 0x0818), medfield },
370 { PCI_VDEVICE(INTEL, 0x0819), medfield },
371 { PCI_VDEVICE(INTEL, 0x082C), medfield },
372 { PCI_VDEVICE(INTEL, 0x082D), medfield },
373 { PCI_VDEVICE(INTEL, 0x082E), medfield },
374 /* Merrifield */
375 { PCI_VDEVICE(INTEL, 0x1195), merrifield },
376 { PCI_VDEVICE(INTEL, 0x1196), merrifield },
377 /* Baytrail */
378 { PCI_VDEVICE(INTEL, 0x0F41), baytrail },
379 { PCI_VDEVICE(INTEL, 0x0F42), baytrail },
380 { PCI_VDEVICE(INTEL, 0x0F43), baytrail },
381 { PCI_VDEVICE(INTEL, 0x0F44), baytrail },
382 { PCI_VDEVICE(INTEL, 0x0F45), baytrail },
383 { PCI_VDEVICE(INTEL, 0x0F46), baytrail },
384 { PCI_VDEVICE(INTEL, 0x0F47), baytrail },
385 /* Haswell */
386 { PCI_VDEVICE(INTEL, 0x9c61), haswell },
387 { PCI_VDEVICE(INTEL, 0x9c62), haswell },
388 /* Braswell / Cherrytrail */
389 { PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
390 { PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
391 { PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
392 { PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
393 { PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
394 { PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
395 { PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
396 /* Elkhart Lake (PSE I2C) */
397 { PCI_VDEVICE(INTEL, 0x4bb9), elkhartlake },
398 { PCI_VDEVICE(INTEL, 0x4bba), elkhartlake },
399 { PCI_VDEVICE(INTEL, 0x4bbb), elkhartlake },
400 { PCI_VDEVICE(INTEL, 0x4bbc), elkhartlake },
401 { PCI_VDEVICE(INTEL, 0x4bbd), elkhartlake },
402 { PCI_VDEVICE(INTEL, 0x4bbe), elkhartlake },
403 { PCI_VDEVICE(INTEL, 0x4bbf), elkhartlake },
404 { PCI_VDEVICE(INTEL, 0x4bc0), elkhartlake },
405 /* AMD NAVI */
406 { PCI_VDEVICE(ATI, 0x7314), navi_amd },
407 { PCI_VDEVICE(ATI, 0x73a4), navi_amd },
408 { PCI_VDEVICE(ATI, 0x73e4), navi_amd },
409 { PCI_VDEVICE(ATI, 0x73c4), navi_amd },
410 { PCI_VDEVICE(ATI, 0x7444), navi_amd },
411 { PCI_VDEVICE(ATI, 0x7464), navi_amd },
412 { 0,}
413};
414MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
415
416static struct pci_driver dw_i2c_driver = {
417 .name = DRIVER_NAME,
418 .id_table = i2_designware_pci_ids,
419 .probe = i2c_dw_pci_probe,
420 .remove = i2c_dw_pci_remove,
421 .driver = {
422 .pm = &i2c_dw_pm_ops,
423 },
424};
425module_pci_driver(dw_i2c_driver);
426
427/* Work with hotplug and coldplug */
428MODULE_ALIAS("i2c_designware-pci");
429MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
430MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
431MODULE_LICENSE("GPL");
1/*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 * Copyright (C) 2011, 2015, 2016 Intel Corporation.
10 *
11 * ----------------------------------------------------------------------------
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 * ----------------------------------------------------------------------------
23 *
24 */
25
26#include <linux/acpi.h>
27#include <linux/delay.h>
28#include <linux/err.h>
29#include <linux/errno.h>
30#include <linux/i2c.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/pm_runtime.h>
37#include <linux/sched.h>
38#include <linux/slab.h>
39
40#include "i2c-designware-core.h"
41
42#define DRIVER_NAME "i2c-designware-pci"
43
44enum dw_pci_ctl_id_t {
45 medfield,
46 merrifield,
47 baytrail,
48 haswell,
49};
50
51struct dw_scl_sda_cfg {
52 u32 ss_hcnt;
53 u32 fs_hcnt;
54 u32 ss_lcnt;
55 u32 fs_lcnt;
56 u32 sda_hold;
57};
58
59struct dw_pci_controller {
60 u32 bus_num;
61 u32 bus_cfg;
62 u32 tx_fifo_depth;
63 u32 rx_fifo_depth;
64 u32 clk_khz;
65 u32 functionality;
66 struct dw_scl_sda_cfg *scl_sda_cfg;
67 int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
68};
69
70#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
71 DW_IC_CON_SLAVE_DISABLE | \
72 DW_IC_CON_RESTART_EN)
73
74/* Merrifield HCNT/LCNT/SDA hold time */
75static struct dw_scl_sda_cfg mrfld_config = {
76 .ss_hcnt = 0x2f8,
77 .fs_hcnt = 0x87,
78 .ss_lcnt = 0x37b,
79 .fs_lcnt = 0x10a,
80};
81
82/* BayTrail HCNT/LCNT/SDA hold time */
83static struct dw_scl_sda_cfg byt_config = {
84 .ss_hcnt = 0x200,
85 .fs_hcnt = 0x55,
86 .ss_lcnt = 0x200,
87 .fs_lcnt = 0x99,
88 .sda_hold = 0x6,
89};
90
91/* Haswell HCNT/LCNT/SDA hold time */
92static struct dw_scl_sda_cfg hsw_config = {
93 .ss_hcnt = 0x01b0,
94 .fs_hcnt = 0x48,
95 .ss_lcnt = 0x01fb,
96 .fs_lcnt = 0xa0,
97 .sda_hold = 0x9,
98};
99
100static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
101{
102 switch (pdev->device) {
103 case 0x0817:
104 c->bus_cfg &= ~DW_IC_CON_SPEED_MASK;
105 c->bus_cfg |= DW_IC_CON_SPEED_STD;
106 case 0x0818:
107 case 0x0819:
108 c->bus_num = pdev->device - 0x817 + 3;
109 return 0;
110 case 0x082C:
111 case 0x082D:
112 case 0x082E:
113 c->bus_num = pdev->device - 0x82C + 0;
114 return 0;
115 }
116 return -ENODEV;
117}
118
119static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
120{
121 /*
122 * On Intel Merrifield the user visible i2c busses are enumerated
123 * [1..7]. So, we add 1 to shift the default range. Besides that the
124 * first PCI slot provides 4 functions, that's why we have to add 0 to
125 * the first slot and 4 to the next one.
126 */
127 switch (PCI_SLOT(pdev->devfn)) {
128 case 8:
129 c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
130 return 0;
131 case 9:
132 c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
133 return 0;
134 }
135 return -ENODEV;
136}
137
138static struct dw_pci_controller dw_pci_controllers[] = {
139 [medfield] = {
140 .bus_num = -1,
141 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
142 .tx_fifo_depth = 32,
143 .rx_fifo_depth = 32,
144 .functionality = I2C_FUNC_10BIT_ADDR,
145 .clk_khz = 25000,
146 .setup = mfld_setup,
147 },
148 [merrifield] = {
149 .bus_num = -1,
150 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
151 .tx_fifo_depth = 64,
152 .rx_fifo_depth = 64,
153 .functionality = I2C_FUNC_10BIT_ADDR,
154 .scl_sda_cfg = &mrfld_config,
155 .setup = mrfld_setup,
156 },
157 [baytrail] = {
158 .bus_num = -1,
159 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
160 .tx_fifo_depth = 32,
161 .rx_fifo_depth = 32,
162 .functionality = I2C_FUNC_10BIT_ADDR,
163 .scl_sda_cfg = &byt_config,
164 },
165 [haswell] = {
166 .bus_num = -1,
167 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
168 .tx_fifo_depth = 32,
169 .rx_fifo_depth = 32,
170 .functionality = I2C_FUNC_10BIT_ADDR,
171 .scl_sda_cfg = &hsw_config,
172 },
173};
174
175#ifdef CONFIG_PM
176static int i2c_dw_pci_suspend(struct device *dev)
177{
178 struct pci_dev *pdev = to_pci_dev(dev);
179
180 i2c_dw_disable(pci_get_drvdata(pdev));
181 return 0;
182}
183
184static int i2c_dw_pci_resume(struct device *dev)
185{
186 struct pci_dev *pdev = to_pci_dev(dev);
187
188 return i2c_dw_init(pci_get_drvdata(pdev));
189}
190#endif
191
192static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
193 i2c_dw_pci_resume, NULL);
194
195static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
196{
197 return dev->controller->clk_khz;
198}
199
200static int i2c_dw_pci_probe(struct pci_dev *pdev,
201 const struct pci_device_id *id)
202{
203 struct dw_i2c_dev *dev;
204 struct i2c_adapter *adap;
205 int r;
206 struct dw_pci_controller *controller;
207 struct dw_scl_sda_cfg *cfg;
208
209 if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
210 dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
211 id->driver_data);
212 return -EINVAL;
213 }
214
215 controller = &dw_pci_controllers[id->driver_data];
216
217 r = pcim_enable_device(pdev);
218 if (r) {
219 dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
220 r);
221 return r;
222 }
223
224 r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
225 if (r) {
226 dev_err(&pdev->dev, "I/O memory remapping failed\n");
227 return r;
228 }
229
230 dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
231 if (!dev)
232 return -ENOMEM;
233
234 dev->clk = NULL;
235 dev->controller = controller;
236 dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
237 dev->base = pcim_iomap_table(pdev)[0];
238 dev->dev = &pdev->dev;
239 dev->irq = pdev->irq;
240
241 if (controller->setup) {
242 r = controller->setup(pdev, controller);
243 if (r)
244 return r;
245 }
246
247 dev->functionality = controller->functionality |
248 DW_IC_DEFAULT_FUNCTIONALITY;
249
250 dev->master_cfg = controller->bus_cfg;
251 if (controller->scl_sda_cfg) {
252 cfg = controller->scl_sda_cfg;
253 dev->ss_hcnt = cfg->ss_hcnt;
254 dev->fs_hcnt = cfg->fs_hcnt;
255 dev->ss_lcnt = cfg->ss_lcnt;
256 dev->fs_lcnt = cfg->fs_lcnt;
257 dev->sda_hold_time = cfg->sda_hold;
258 }
259
260 pci_set_drvdata(pdev, dev);
261
262 dev->tx_fifo_depth = controller->tx_fifo_depth;
263 dev->rx_fifo_depth = controller->rx_fifo_depth;
264
265 adap = &dev->adapter;
266 adap->owner = THIS_MODULE;
267 adap->class = 0;
268 ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
269 adap->nr = controller->bus_num;
270
271 r = i2c_dw_probe(dev);
272 if (r)
273 return r;
274
275 pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
276 pm_runtime_use_autosuspend(&pdev->dev);
277 pm_runtime_put_autosuspend(&pdev->dev);
278 pm_runtime_allow(&pdev->dev);
279
280 return 0;
281}
282
283static void i2c_dw_pci_remove(struct pci_dev *pdev)
284{
285 struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
286
287 i2c_dw_disable(dev);
288 pm_runtime_forbid(&pdev->dev);
289 pm_runtime_get_noresume(&pdev->dev);
290
291 i2c_del_adapter(&dev->adapter);
292}
293
294/* work with hotplug and coldplug */
295MODULE_ALIAS("i2c_designware-pci");
296
297static const struct pci_device_id i2_designware_pci_ids[] = {
298 /* Medfield */
299 { PCI_VDEVICE(INTEL, 0x0817), medfield },
300 { PCI_VDEVICE(INTEL, 0x0818), medfield },
301 { PCI_VDEVICE(INTEL, 0x0819), medfield },
302 { PCI_VDEVICE(INTEL, 0x082C), medfield },
303 { PCI_VDEVICE(INTEL, 0x082D), medfield },
304 { PCI_VDEVICE(INTEL, 0x082E), medfield },
305 /* Merrifield */
306 { PCI_VDEVICE(INTEL, 0x1195), merrifield },
307 { PCI_VDEVICE(INTEL, 0x1196), merrifield },
308 /* Baytrail */
309 { PCI_VDEVICE(INTEL, 0x0F41), baytrail },
310 { PCI_VDEVICE(INTEL, 0x0F42), baytrail },
311 { PCI_VDEVICE(INTEL, 0x0F43), baytrail },
312 { PCI_VDEVICE(INTEL, 0x0F44), baytrail },
313 { PCI_VDEVICE(INTEL, 0x0F45), baytrail },
314 { PCI_VDEVICE(INTEL, 0x0F46), baytrail },
315 { PCI_VDEVICE(INTEL, 0x0F47), baytrail },
316 /* Haswell */
317 { PCI_VDEVICE(INTEL, 0x9c61), haswell },
318 { PCI_VDEVICE(INTEL, 0x9c62), haswell },
319 /* Braswell / Cherrytrail */
320 { PCI_VDEVICE(INTEL, 0x22C1), baytrail },
321 { PCI_VDEVICE(INTEL, 0x22C2), baytrail },
322 { PCI_VDEVICE(INTEL, 0x22C3), baytrail },
323 { PCI_VDEVICE(INTEL, 0x22C4), baytrail },
324 { PCI_VDEVICE(INTEL, 0x22C5), baytrail },
325 { PCI_VDEVICE(INTEL, 0x22C6), baytrail },
326 { PCI_VDEVICE(INTEL, 0x22C7), baytrail },
327 { 0,}
328};
329MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
330
331static struct pci_driver dw_i2c_driver = {
332 .name = DRIVER_NAME,
333 .id_table = i2_designware_pci_ids,
334 .probe = i2c_dw_pci_probe,
335 .remove = i2c_dw_pci_remove,
336 .driver = {
337 .pm = &i2c_dw_pm_ops,
338 },
339};
340
341module_pci_driver(dw_i2c_driver);
342
343MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
344MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
345MODULE_LICENSE("GPL");