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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * fam15h_power.c - AMD Family 15h processor power monitoring
4 *
5 * Copyright (c) 2011-2016 Advanced Micro Devices, Inc.
6 * Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
7 */
8
9#include <linux/err.h>
10#include <linux/hwmon.h>
11#include <linux/hwmon-sysfs.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/pci.h>
15#include <linux/bitops.h>
16#include <linux/cpu.h>
17#include <linux/cpumask.h>
18#include <linux/time.h>
19#include <linux/sched.h>
20#include <linux/topology.h>
21#include <asm/processor.h>
22#include <asm/msr.h>
23
24MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
25MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
26MODULE_LICENSE("GPL");
27
28/* D18F3 */
29#define REG_NORTHBRIDGE_CAP 0xe8
30
31/* D18F4 */
32#define REG_PROCESSOR_TDP 0x1b8
33
34/* D18F5 */
35#define REG_TDP_RUNNING_AVERAGE 0xe0
36#define REG_TDP_LIMIT3 0xe8
37
38#define FAM15H_MIN_NUM_ATTRS 2
39#define FAM15H_NUM_GROUPS 2
40#define MAX_CUS 8
41
42/* set maximum interval as 1 second */
43#define MAX_INTERVAL 1000
44
45#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4
46
47struct fam15h_power_data {
48 struct pci_dev *pdev;
49 unsigned int tdp_to_watts;
50 unsigned int base_tdp;
51 unsigned int processor_pwr_watts;
52 unsigned int cpu_pwr_sample_ratio;
53 const struct attribute_group *groups[FAM15H_NUM_GROUPS];
54 struct attribute_group group;
55 /* maximum accumulated power of a compute unit */
56 u64 max_cu_acc_power;
57 /* accumulated power of the compute units */
58 u64 cu_acc_power[MAX_CUS];
59 /* performance timestamp counter */
60 u64 cpu_sw_pwr_ptsc[MAX_CUS];
61 /* online/offline status of current compute unit */
62 int cu_on[MAX_CUS];
63 unsigned long power_period;
64};
65
66static bool is_carrizo_or_later(void)
67{
68 return boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60;
69}
70
71static ssize_t power1_input_show(struct device *dev,
72 struct device_attribute *attr, char *buf)
73{
74 u32 val, tdp_limit, running_avg_range;
75 s32 running_avg_capture;
76 u64 curr_pwr_watts;
77 struct fam15h_power_data *data = dev_get_drvdata(dev);
78 struct pci_dev *f4 = data->pdev;
79
80 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
81 REG_TDP_RUNNING_AVERAGE, &val);
82
83 /*
84 * On Carrizo and later platforms, TdpRunAvgAccCap bit field
85 * is extended to 4:31 from 4:25.
86 */
87 if (is_carrizo_or_later()) {
88 running_avg_capture = val >> 4;
89 running_avg_capture = sign_extend32(running_avg_capture, 27);
90 } else {
91 running_avg_capture = (val >> 4) & 0x3fffff;
92 running_avg_capture = sign_extend32(running_avg_capture, 21);
93 }
94
95 running_avg_range = (val & 0xf) + 1;
96
97 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
98 REG_TDP_LIMIT3, &val);
99
100 /*
101 * On Carrizo and later platforms, ApmTdpLimit bit field
102 * is extended to 16:31 from 16:28.
103 */
104 if (is_carrizo_or_later())
105 tdp_limit = val >> 16;
106 else
107 tdp_limit = (val >> 16) & 0x1fff;
108
109 curr_pwr_watts = ((u64)(tdp_limit +
110 data->base_tdp)) << running_avg_range;
111 curr_pwr_watts -= running_avg_capture;
112 curr_pwr_watts *= data->tdp_to_watts;
113
114 /*
115 * Convert to microWatt
116 *
117 * power is in Watt provided as fixed point integer with
118 * scaling factor 1/(2^16). For conversion we use
119 * (10^6)/(2^16) = 15625/(2^10)
120 */
121 curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range);
122 return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
123}
124static DEVICE_ATTR_RO(power1_input);
125
126static ssize_t power1_crit_show(struct device *dev,
127 struct device_attribute *attr, char *buf)
128{
129 struct fam15h_power_data *data = dev_get_drvdata(dev);
130
131 return sprintf(buf, "%u\n", data->processor_pwr_watts);
132}
133static DEVICE_ATTR_RO(power1_crit);
134
135static void do_read_registers_on_cu(void *_data)
136{
137 struct fam15h_power_data *data = _data;
138 int cu;
139
140 /*
141 * With the new x86 topology modelling, cpu core id actually
142 * is compute unit id.
143 */
144 cu = topology_core_id(smp_processor_id());
145
146 rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]);
147 rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]);
148
149 data->cu_on[cu] = 1;
150}
151
152/*
153 * This function is only able to be called when CPUID
154 * Fn8000_0007:EDX[12] is set.
155 */
156static int read_registers(struct fam15h_power_data *data)
157{
158 int core, this_core;
159 cpumask_var_t mask;
160 int ret, cpu;
161
162 ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
163 if (!ret)
164 return -ENOMEM;
165
166 memset(data->cu_on, 0, sizeof(int) * MAX_CUS);
167
168 cpus_read_lock();
169
170 /*
171 * Choose the first online core of each compute unit, and then
172 * read their MSR value of power and ptsc in a single IPI,
173 * because the MSR value of CPU core represent the compute
174 * unit's.
175 */
176 core = -1;
177
178 for_each_online_cpu(cpu) {
179 this_core = topology_core_id(cpu);
180
181 if (this_core == core)
182 continue;
183
184 core = this_core;
185
186 /* get any CPU on this compute unit */
187 cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask);
188 }
189
190 on_each_cpu_mask(mask, do_read_registers_on_cu, data, true);
191
192 cpus_read_unlock();
193 free_cpumask_var(mask);
194
195 return 0;
196}
197
198static ssize_t power1_average_show(struct device *dev,
199 struct device_attribute *attr, char *buf)
200{
201 struct fam15h_power_data *data = dev_get_drvdata(dev);
202 u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS],
203 jdelta[MAX_CUS];
204 u64 tdelta, avg_acc;
205 int cu, cu_num, ret;
206 signed long leftover;
207
208 /*
209 * With the new x86 topology modelling, x86_max_cores is the
210 * compute unit number.
211 */
212 cu_num = boot_cpu_data.x86_max_cores;
213
214 ret = read_registers(data);
215 if (ret)
216 return 0;
217
218 for (cu = 0; cu < cu_num; cu++) {
219 prev_cu_acc_power[cu] = data->cu_acc_power[cu];
220 prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu];
221 }
222
223 leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period));
224 if (leftover)
225 return 0;
226
227 ret = read_registers(data);
228 if (ret)
229 return 0;
230
231 for (cu = 0, avg_acc = 0; cu < cu_num; cu++) {
232 /* check if current compute unit is online */
233 if (data->cu_on[cu] == 0)
234 continue;
235
236 if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) {
237 jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu];
238 jdelta[cu] -= prev_cu_acc_power[cu];
239 } else {
240 jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu];
241 }
242 tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu];
243 jdelta[cu] *= data->cpu_pwr_sample_ratio * 1000;
244 do_div(jdelta[cu], tdelta);
245
246 /* the unit is microWatt */
247 avg_acc += jdelta[cu];
248 }
249
250 return sprintf(buf, "%llu\n", (unsigned long long)avg_acc);
251}
252static DEVICE_ATTR_RO(power1_average);
253
254static ssize_t power1_average_interval_show(struct device *dev,
255 struct device_attribute *attr,
256 char *buf)
257{
258 struct fam15h_power_data *data = dev_get_drvdata(dev);
259
260 return sprintf(buf, "%lu\n", data->power_period);
261}
262
263static ssize_t power1_average_interval_store(struct device *dev,
264 struct device_attribute *attr,
265 const char *buf, size_t count)
266{
267 struct fam15h_power_data *data = dev_get_drvdata(dev);
268 unsigned long temp;
269 int ret;
270
271 ret = kstrtoul(buf, 10, &temp);
272 if (ret)
273 return ret;
274
275 if (temp > MAX_INTERVAL)
276 return -EINVAL;
277
278 /* the interval value should be greater than 0 */
279 if (temp <= 0)
280 return -EINVAL;
281
282 data->power_period = temp;
283
284 return count;
285}
286static DEVICE_ATTR_RW(power1_average_interval);
287
288static int fam15h_power_init_attrs(struct pci_dev *pdev,
289 struct fam15h_power_data *data)
290{
291 int n = FAM15H_MIN_NUM_ATTRS;
292 struct attribute **fam15h_power_attrs;
293 struct cpuinfo_x86 *c = &boot_cpu_data;
294
295 if (c->x86 == 0x15 &&
296 (c->x86_model <= 0xf ||
297 (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
298 n += 1;
299
300 /* check if processor supports accumulated power */
301 if (boot_cpu_has(X86_FEATURE_ACC_POWER))
302 n += 2;
303
304 fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
305 sizeof(*fam15h_power_attrs),
306 GFP_KERNEL);
307
308 if (!fam15h_power_attrs)
309 return -ENOMEM;
310
311 n = 0;
312 fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr;
313 if (c->x86 == 0x15 &&
314 (c->x86_model <= 0xf ||
315 (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
316 fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;
317
318 if (boot_cpu_has(X86_FEATURE_ACC_POWER)) {
319 fam15h_power_attrs[n++] = &dev_attr_power1_average.attr;
320 fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr;
321 }
322
323 data->group.attrs = fam15h_power_attrs;
324
325 return 0;
326}
327
328static bool should_load_on_this_node(struct pci_dev *f4)
329{
330 u32 val;
331
332 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
333 REG_NORTHBRIDGE_CAP, &val);
334 if ((val & BIT(29)) && ((val >> 30) & 3))
335 return false;
336
337 return true;
338}
339
340/*
341 * Newer BKDG versions have an updated recommendation on how to properly
342 * initialize the running average range (was: 0xE, now: 0x9). This avoids
343 * counter saturations resulting in bogus power readings.
344 * We correct this value ourselves to cope with older BIOSes.
345 */
346static const struct pci_device_id affected_device[] = {
347 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
348 { 0 }
349};
350
351static void tweak_runavg_range(struct pci_dev *pdev)
352{
353 u32 val;
354
355 /*
356 * let this quirk apply only to the current version of the
357 * northbridge, since future versions may change the behavior
358 */
359 if (!pci_match_id(affected_device, pdev))
360 return;
361
362 pci_bus_read_config_dword(pdev->bus,
363 PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
364 REG_TDP_RUNNING_AVERAGE, &val);
365 if ((val & 0xf) != 0xe)
366 return;
367
368 val &= ~0xf;
369 val |= 0x9;
370 pci_bus_write_config_dword(pdev->bus,
371 PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
372 REG_TDP_RUNNING_AVERAGE, val);
373}
374
375#ifdef CONFIG_PM
376static int fam15h_power_resume(struct pci_dev *pdev)
377{
378 tweak_runavg_range(pdev);
379 return 0;
380}
381#else
382#define fam15h_power_resume NULL
383#endif
384
385static int fam15h_power_init_data(struct pci_dev *f4,
386 struct fam15h_power_data *data)
387{
388 u32 val;
389 u64 tmp;
390 int ret;
391
392 pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
393 data->base_tdp = val >> 16;
394 tmp = val & 0xffff;
395
396 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
397 REG_TDP_LIMIT3, &val);
398
399 data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f);
400 tmp *= data->tdp_to_watts;
401
402 /* result not allowed to be >= 256W */
403 if ((tmp >> 16) >= 256)
404 dev_warn(&f4->dev,
405 "Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n",
406 (unsigned int) (tmp >> 16));
407
408 /* convert to microWatt */
409 data->processor_pwr_watts = (tmp * 15625) >> 10;
410
411 ret = fam15h_power_init_attrs(f4, data);
412 if (ret)
413 return ret;
414
415
416 /* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */
417 if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
418 return 0;
419
420 /*
421 * determine the ratio of the compute unit power accumulator
422 * sample period to the PTSC counter period by executing CPUID
423 * Fn8000_0007:ECX
424 */
425 data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);
426
427 if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
428 pr_err("Failed to read max compute unit power accumulator MSR\n");
429 return -ENODEV;
430 }
431
432 data->max_cu_acc_power = tmp;
433
434 /*
435 * Milliseconds are a reasonable interval for the measurement.
436 * But it shouldn't set too long here, because several seconds
437 * would cause the read function to hang. So set default
438 * interval as 10 ms.
439 */
440 data->power_period = 10;
441
442 return read_registers(data);
443}
444
445static int fam15h_power_probe(struct pci_dev *pdev,
446 const struct pci_device_id *id)
447{
448 struct fam15h_power_data *data;
449 struct device *dev = &pdev->dev;
450 struct device *hwmon_dev;
451 int ret;
452
453 /*
454 * though we ignore every other northbridge, we still have to
455 * do the tweaking on _each_ node in MCM processors as the counters
456 * are working hand-in-hand
457 */
458 tweak_runavg_range(pdev);
459
460 if (!should_load_on_this_node(pdev))
461 return -ENODEV;
462
463 data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL);
464 if (!data)
465 return -ENOMEM;
466
467 ret = fam15h_power_init_data(pdev, data);
468 if (ret)
469 return ret;
470
471 data->pdev = pdev;
472
473 data->groups[0] = &data->group;
474
475 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
476 data,
477 &data->groups[0]);
478 return PTR_ERR_OR_ZERO(hwmon_dev);
479}
480
481static const struct pci_device_id fam15h_power_id_table[] = {
482 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
483 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
484 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
485 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
486 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
487 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
488 {}
489};
490MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
491
492static struct pci_driver fam15h_power_driver = {
493 .name = "fam15h_power",
494 .id_table = fam15h_power_id_table,
495 .probe = fam15h_power_probe,
496 .resume = fam15h_power_resume,
497};
498
499module_pci_driver(fam15h_power_driver);
1/*
2 * fam15h_power.c - AMD Family 15h processor power monitoring
3 *
4 * Copyright (c) 2011-2016 Advanced Micro Devices, Inc.
5 * Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
6 *
7 *
8 * This driver is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This driver is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 * See the GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/err.h>
22#include <linux/hwmon.h>
23#include <linux/hwmon-sysfs.h>
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/bitops.h>
28#include <linux/cpu.h>
29#include <linux/cpumask.h>
30#include <linux/time.h>
31#include <linux/sched.h>
32#include <asm/processor.h>
33#include <asm/msr.h>
34
35MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
36MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
37MODULE_LICENSE("GPL");
38
39/* D18F3 */
40#define REG_NORTHBRIDGE_CAP 0xe8
41
42/* D18F4 */
43#define REG_PROCESSOR_TDP 0x1b8
44
45/* D18F5 */
46#define REG_TDP_RUNNING_AVERAGE 0xe0
47#define REG_TDP_LIMIT3 0xe8
48
49#define FAM15H_MIN_NUM_ATTRS 2
50#define FAM15H_NUM_GROUPS 2
51#define MAX_CUS 8
52
53/* set maximum interval as 1 second */
54#define MAX_INTERVAL 1000
55
56#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
57#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
58#define MSR_F15H_PTSC 0xc0010280
59
60#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4
61
62struct fam15h_power_data {
63 struct pci_dev *pdev;
64 unsigned int tdp_to_watts;
65 unsigned int base_tdp;
66 unsigned int processor_pwr_watts;
67 unsigned int cpu_pwr_sample_ratio;
68 const struct attribute_group *groups[FAM15H_NUM_GROUPS];
69 struct attribute_group group;
70 /* maximum accumulated power of a compute unit */
71 u64 max_cu_acc_power;
72 /* accumulated power of the compute units */
73 u64 cu_acc_power[MAX_CUS];
74 /* performance timestamp counter */
75 u64 cpu_sw_pwr_ptsc[MAX_CUS];
76 /* online/offline status of current compute unit */
77 int cu_on[MAX_CUS];
78 unsigned long power_period;
79};
80
81static bool is_carrizo_or_later(void)
82{
83 return boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60;
84}
85
86static ssize_t show_power(struct device *dev,
87 struct device_attribute *attr, char *buf)
88{
89 u32 val, tdp_limit, running_avg_range;
90 s32 running_avg_capture;
91 u64 curr_pwr_watts;
92 struct fam15h_power_data *data = dev_get_drvdata(dev);
93 struct pci_dev *f4 = data->pdev;
94
95 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
96 REG_TDP_RUNNING_AVERAGE, &val);
97
98 /*
99 * On Carrizo and later platforms, TdpRunAvgAccCap bit field
100 * is extended to 4:31 from 4:25.
101 */
102 if (is_carrizo_or_later()) {
103 running_avg_capture = val >> 4;
104 running_avg_capture = sign_extend32(running_avg_capture, 27);
105 } else {
106 running_avg_capture = (val >> 4) & 0x3fffff;
107 running_avg_capture = sign_extend32(running_avg_capture, 21);
108 }
109
110 running_avg_range = (val & 0xf) + 1;
111
112 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
113 REG_TDP_LIMIT3, &val);
114
115 /*
116 * On Carrizo and later platforms, ApmTdpLimit bit field
117 * is extended to 16:31 from 16:28.
118 */
119 if (is_carrizo_or_later())
120 tdp_limit = val >> 16;
121 else
122 tdp_limit = (val >> 16) & 0x1fff;
123
124 curr_pwr_watts = ((u64)(tdp_limit +
125 data->base_tdp)) << running_avg_range;
126 curr_pwr_watts -= running_avg_capture;
127 curr_pwr_watts *= data->tdp_to_watts;
128
129 /*
130 * Convert to microWatt
131 *
132 * power is in Watt provided as fixed point integer with
133 * scaling factor 1/(2^16). For conversion we use
134 * (10^6)/(2^16) = 15625/(2^10)
135 */
136 curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range);
137 return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
138}
139static DEVICE_ATTR(power1_input, S_IRUGO, show_power, NULL);
140
141static ssize_t show_power_crit(struct device *dev,
142 struct device_attribute *attr, char *buf)
143{
144 struct fam15h_power_data *data = dev_get_drvdata(dev);
145
146 return sprintf(buf, "%u\n", data->processor_pwr_watts);
147}
148static DEVICE_ATTR(power1_crit, S_IRUGO, show_power_crit, NULL);
149
150static void do_read_registers_on_cu(void *_data)
151{
152 struct fam15h_power_data *data = _data;
153 int cpu, cu;
154
155 cpu = smp_processor_id();
156
157 /*
158 * With the new x86 topology modelling, cpu core id actually
159 * is compute unit id.
160 */
161 cu = cpu_data(cpu).cpu_core_id;
162
163 rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]);
164 rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]);
165
166 data->cu_on[cu] = 1;
167}
168
169/*
170 * This function is only able to be called when CPUID
171 * Fn8000_0007:EDX[12] is set.
172 */
173static int read_registers(struct fam15h_power_data *data)
174{
175 int core, this_core;
176 cpumask_var_t mask;
177 int ret, cpu;
178
179 ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
180 if (!ret)
181 return -ENOMEM;
182
183 memset(data->cu_on, 0, sizeof(int) * MAX_CUS);
184
185 get_online_cpus();
186
187 /*
188 * Choose the first online core of each compute unit, and then
189 * read their MSR value of power and ptsc in a single IPI,
190 * because the MSR value of CPU core represent the compute
191 * unit's.
192 */
193 core = -1;
194
195 for_each_online_cpu(cpu) {
196 this_core = topology_core_id(cpu);
197
198 if (this_core == core)
199 continue;
200
201 core = this_core;
202
203 /* get any CPU on this compute unit */
204 cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask);
205 }
206
207 on_each_cpu_mask(mask, do_read_registers_on_cu, data, true);
208
209 put_online_cpus();
210 free_cpumask_var(mask);
211
212 return 0;
213}
214
215static ssize_t acc_show_power(struct device *dev,
216 struct device_attribute *attr,
217 char *buf)
218{
219 struct fam15h_power_data *data = dev_get_drvdata(dev);
220 u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS],
221 jdelta[MAX_CUS];
222 u64 tdelta, avg_acc;
223 int cu, cu_num, ret;
224 signed long leftover;
225
226 /*
227 * With the new x86 topology modelling, x86_max_cores is the
228 * compute unit number.
229 */
230 cu_num = boot_cpu_data.x86_max_cores;
231
232 ret = read_registers(data);
233 if (ret)
234 return 0;
235
236 for (cu = 0; cu < cu_num; cu++) {
237 prev_cu_acc_power[cu] = data->cu_acc_power[cu];
238 prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu];
239 }
240
241 leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period));
242 if (leftover)
243 return 0;
244
245 ret = read_registers(data);
246 if (ret)
247 return 0;
248
249 for (cu = 0, avg_acc = 0; cu < cu_num; cu++) {
250 /* check if current compute unit is online */
251 if (data->cu_on[cu] == 0)
252 continue;
253
254 if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) {
255 jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu];
256 jdelta[cu] -= prev_cu_acc_power[cu];
257 } else {
258 jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu];
259 }
260 tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu];
261 jdelta[cu] *= data->cpu_pwr_sample_ratio * 1000;
262 do_div(jdelta[cu], tdelta);
263
264 /* the unit is microWatt */
265 avg_acc += jdelta[cu];
266 }
267
268 return sprintf(buf, "%llu\n", (unsigned long long)avg_acc);
269}
270static DEVICE_ATTR(power1_average, S_IRUGO, acc_show_power, NULL);
271
272static ssize_t acc_show_power_period(struct device *dev,
273 struct device_attribute *attr,
274 char *buf)
275{
276 struct fam15h_power_data *data = dev_get_drvdata(dev);
277
278 return sprintf(buf, "%lu\n", data->power_period);
279}
280
281static ssize_t acc_set_power_period(struct device *dev,
282 struct device_attribute *attr,
283 const char *buf, size_t count)
284{
285 struct fam15h_power_data *data = dev_get_drvdata(dev);
286 unsigned long temp;
287 int ret;
288
289 ret = kstrtoul(buf, 10, &temp);
290 if (ret)
291 return ret;
292
293 if (temp > MAX_INTERVAL)
294 return -EINVAL;
295
296 /* the interval value should be greater than 0 */
297 if (temp <= 0)
298 return -EINVAL;
299
300 data->power_period = temp;
301
302 return count;
303}
304static DEVICE_ATTR(power1_average_interval, S_IRUGO | S_IWUSR,
305 acc_show_power_period, acc_set_power_period);
306
307static int fam15h_power_init_attrs(struct pci_dev *pdev,
308 struct fam15h_power_data *data)
309{
310 int n = FAM15H_MIN_NUM_ATTRS;
311 struct attribute **fam15h_power_attrs;
312 struct cpuinfo_x86 *c = &boot_cpu_data;
313
314 if (c->x86 == 0x15 &&
315 (c->x86_model <= 0xf ||
316 (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
317 n += 1;
318
319 /* check if processor supports accumulated power */
320 if (boot_cpu_has(X86_FEATURE_ACC_POWER))
321 n += 2;
322
323 fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
324 sizeof(*fam15h_power_attrs),
325 GFP_KERNEL);
326
327 if (!fam15h_power_attrs)
328 return -ENOMEM;
329
330 n = 0;
331 fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr;
332 if (c->x86 == 0x15 &&
333 (c->x86_model <= 0xf ||
334 (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
335 fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;
336
337 if (boot_cpu_has(X86_FEATURE_ACC_POWER)) {
338 fam15h_power_attrs[n++] = &dev_attr_power1_average.attr;
339 fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr;
340 }
341
342 data->group.attrs = fam15h_power_attrs;
343
344 return 0;
345}
346
347static bool should_load_on_this_node(struct pci_dev *f4)
348{
349 u32 val;
350
351 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
352 REG_NORTHBRIDGE_CAP, &val);
353 if ((val & BIT(29)) && ((val >> 30) & 3))
354 return false;
355
356 return true;
357}
358
359/*
360 * Newer BKDG versions have an updated recommendation on how to properly
361 * initialize the running average range (was: 0xE, now: 0x9). This avoids
362 * counter saturations resulting in bogus power readings.
363 * We correct this value ourselves to cope with older BIOSes.
364 */
365static const struct pci_device_id affected_device[] = {
366 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
367 { 0 }
368};
369
370static void tweak_runavg_range(struct pci_dev *pdev)
371{
372 u32 val;
373
374 /*
375 * let this quirk apply only to the current version of the
376 * northbridge, since future versions may change the behavior
377 */
378 if (!pci_match_id(affected_device, pdev))
379 return;
380
381 pci_bus_read_config_dword(pdev->bus,
382 PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
383 REG_TDP_RUNNING_AVERAGE, &val);
384 if ((val & 0xf) != 0xe)
385 return;
386
387 val &= ~0xf;
388 val |= 0x9;
389 pci_bus_write_config_dword(pdev->bus,
390 PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
391 REG_TDP_RUNNING_AVERAGE, val);
392}
393
394#ifdef CONFIG_PM
395static int fam15h_power_resume(struct pci_dev *pdev)
396{
397 tweak_runavg_range(pdev);
398 return 0;
399}
400#else
401#define fam15h_power_resume NULL
402#endif
403
404static int fam15h_power_init_data(struct pci_dev *f4,
405 struct fam15h_power_data *data)
406{
407 u32 val;
408 u64 tmp;
409 int ret;
410
411 pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
412 data->base_tdp = val >> 16;
413 tmp = val & 0xffff;
414
415 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
416 REG_TDP_LIMIT3, &val);
417
418 data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f);
419 tmp *= data->tdp_to_watts;
420
421 /* result not allowed to be >= 256W */
422 if ((tmp >> 16) >= 256)
423 dev_warn(&f4->dev,
424 "Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n",
425 (unsigned int) (tmp >> 16));
426
427 /* convert to microWatt */
428 data->processor_pwr_watts = (tmp * 15625) >> 10;
429
430 ret = fam15h_power_init_attrs(f4, data);
431 if (ret)
432 return ret;
433
434
435 /* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */
436 if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
437 return 0;
438
439 /*
440 * determine the ratio of the compute unit power accumulator
441 * sample period to the PTSC counter period by executing CPUID
442 * Fn8000_0007:ECX
443 */
444 data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);
445
446 if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
447 pr_err("Failed to read max compute unit power accumulator MSR\n");
448 return -ENODEV;
449 }
450
451 data->max_cu_acc_power = tmp;
452
453 /*
454 * Milliseconds are a reasonable interval for the measurement.
455 * But it shouldn't set too long here, because several seconds
456 * would cause the read function to hang. So set default
457 * interval as 10 ms.
458 */
459 data->power_period = 10;
460
461 return read_registers(data);
462}
463
464static int fam15h_power_probe(struct pci_dev *pdev,
465 const struct pci_device_id *id)
466{
467 struct fam15h_power_data *data;
468 struct device *dev = &pdev->dev;
469 struct device *hwmon_dev;
470 int ret;
471
472 /*
473 * though we ignore every other northbridge, we still have to
474 * do the tweaking on _each_ node in MCM processors as the counters
475 * are working hand-in-hand
476 */
477 tweak_runavg_range(pdev);
478
479 if (!should_load_on_this_node(pdev))
480 return -ENODEV;
481
482 data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL);
483 if (!data)
484 return -ENOMEM;
485
486 ret = fam15h_power_init_data(pdev, data);
487 if (ret)
488 return ret;
489
490 data->pdev = pdev;
491
492 data->groups[0] = &data->group;
493
494 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
495 data,
496 &data->groups[0]);
497 return PTR_ERR_OR_ZERO(hwmon_dev);
498}
499
500static const struct pci_device_id fam15h_power_id_table[] = {
501 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
502 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
503 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
504 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
505 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
506 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
507 {}
508};
509MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
510
511static struct pci_driver fam15h_power_driver = {
512 .name = "fam15h_power",
513 .id_table = fam15h_power_id_table,
514 .probe = fam15h_power_probe,
515 .resume = fam15h_power_resume,
516};
517
518module_pci_driver(fam15h_power_driver);