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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#ifndef __MSM_DRV_H__
9#define __MSM_DRV_H__
10
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/cpufreq.h>
14#include <linux/devfreq.h>
15#include <linux/module.h>
16#include <linux/component.h>
17#include <linux/platform_device.h>
18#include <linux/pm.h>
19#include <linux/pm_runtime.h>
20#include <linux/slab.h>
21#include <linux/list.h>
22#include <linux/iommu.h>
23#include <linux/types.h>
24#include <linux/of_graph.h>
25#include <linux/of_device.h>
26#include <linux/sizes.h>
27#include <linux/kthread.h>
28
29#include <drm/drm_atomic.h>
30#include <drm/drm_atomic_helper.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/display/drm_dsc.h>
33#include <drm/msm_drm.h>
34#include <drm/drm_gem.h>
35
36#ifdef CONFIG_FAULT_INJECTION
37extern struct fault_attr fail_gem_alloc;
38extern struct fault_attr fail_gem_iova;
39#else
40# define should_fail(attr, size) 0
41#endif
42
43struct msm_kms;
44struct msm_gpu;
45struct msm_mmu;
46struct msm_mdss;
47struct msm_rd_state;
48struct msm_perf_state;
49struct msm_gem_submit;
50struct msm_fence_context;
51struct msm_gem_address_space;
52struct msm_gem_vma;
53struct msm_disp_state;
54
55#define MAX_CRTCS 8
56#define MAX_BRIDGES 8
57
58#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
59
60enum msm_dp_controller {
61 MSM_DP_CONTROLLER_0,
62 MSM_DP_CONTROLLER_1,
63 MSM_DP_CONTROLLER_2,
64 MSM_DP_CONTROLLER_3,
65 MSM_DP_CONTROLLER_COUNT,
66};
67
68enum msm_dsi_controller {
69 MSM_DSI_CONTROLLER_0,
70 MSM_DSI_CONTROLLER_1,
71 MSM_DSI_CONTROLLER_COUNT,
72};
73
74#define MSM_GPU_MAX_RINGS 4
75#define MAX_H_TILES_PER_DISPLAY 2
76
77/**
78 * enum msm_event_wait - type of HW events to wait for
79 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
80 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
81 */
82enum msm_event_wait {
83 MSM_ENC_COMMIT_DONE = 0,
84 MSM_ENC_TX_COMPLETE,
85};
86
87/**
88 * struct msm_display_topology - defines a display topology pipeline
89 * @num_lm: number of layer mixers used
90 * @num_intf: number of interfaces the panel is mounted on
91 * @num_dspp: number of dspp blocks used
92 * @num_dsc: number of Display Stream Compression (DSC) blocks used
93 * @needs_cdm: indicates whether cdm block is needed for this display topology
94 */
95struct msm_display_topology {
96 u32 num_lm;
97 u32 num_intf;
98 u32 num_dspp;
99 u32 num_dsc;
100 bool needs_cdm;
101};
102
103/* Commit/Event thread specific structure */
104struct msm_drm_thread {
105 struct drm_device *dev;
106 struct kthread_worker *worker;
107};
108
109struct msm_drm_private {
110
111 struct drm_device *dev;
112
113 struct msm_kms *kms;
114 int (*kms_init)(struct drm_device *dev);
115
116 /* subordinate devices, if present: */
117 struct platform_device *gpu_pdev;
118
119 /* possibly this should be in the kms component, but it is
120 * shared by both mdp4 and mdp5..
121 */
122 struct hdmi *hdmi;
123
124 /* DSI is shared by mdp4 and mdp5 */
125 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT];
126
127 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT];
128
129 /* when we have more than one 'msm_gpu' these need to be an array: */
130 struct msm_gpu *gpu;
131
132 /* gpu is only set on open(), but we need this info earlier */
133 bool is_a2xx;
134 bool has_cached_coherent;
135
136 struct msm_rd_state *rd; /* debugfs to dump all submits */
137 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
138 struct msm_perf_state *perf;
139
140 /**
141 * List of all GEM objects (mainly for debugfs, protected by obj_lock
142 * (acquire before per GEM object lock)
143 */
144 struct list_head objects;
145 struct mutex obj_lock;
146
147 /**
148 * lru:
149 *
150 * The various LRU's that a GEM object is in at various stages of
151 * it's lifetime. Objects start out in the unbacked LRU. When
152 * pinned (for scannout or permanently mapped GPU buffers, like
153 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When
154 * unpinned, it moves into willneed or dontneed LRU depending on
155 * madvise state. When backing pages are evicted (willneed) or
156 * purged (dontneed) it moves back into the unbacked LRU.
157 *
158 * The dontneed LRU is considered by the shrinker for objects
159 * that are candidate for purging, and the willneed LRU is
160 * considered for objects that could be evicted.
161 */
162 struct {
163 /**
164 * unbacked:
165 *
166 * The LRU for GEM objects without backing pages allocated.
167 * This mostly exists so that objects are always is one
168 * LRU.
169 */
170 struct drm_gem_lru unbacked;
171
172 /**
173 * pinned:
174 *
175 * The LRU for pinned GEM objects
176 */
177 struct drm_gem_lru pinned;
178
179 /**
180 * willneed:
181 *
182 * The LRU for unpinned GEM objects which are in madvise
183 * WILLNEED state (ie. can be evicted)
184 */
185 struct drm_gem_lru willneed;
186
187 /**
188 * dontneed:
189 *
190 * The LRU for unpinned GEM objects which are in madvise
191 * DONTNEED state (ie. can be purged)
192 */
193 struct drm_gem_lru dontneed;
194
195 /**
196 * lock:
197 *
198 * Protects manipulation of all of the LRUs.
199 */
200 struct mutex lock;
201 } lru;
202
203 struct workqueue_struct *wq;
204
205 unsigned int num_crtcs;
206
207 struct msm_drm_thread event_thread[MAX_CRTCS];
208
209 /* VRAM carveout, used when no IOMMU: */
210 struct {
211 unsigned long size;
212 dma_addr_t paddr;
213 /* NOTE: mm managed at the page level, size is in # of pages
214 * and position mm_node->start is in # of pages:
215 */
216 struct drm_mm mm;
217 spinlock_t lock; /* Protects drm_mm node allocation/removal */
218 } vram;
219
220 struct notifier_block vmap_notifier;
221 struct shrinker *shrinker;
222
223 struct drm_atomic_state *pm_state;
224
225 /**
226 * hangcheck_period: For hang detection, in ms
227 *
228 * Note that in practice, a submit/job will get at least two hangcheck
229 * periods, due to checking for progress being implemented as simply
230 * "have the CP position registers changed since last time?"
231 */
232 unsigned int hangcheck_period;
233
234 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */
235 struct devfreq_simple_ondemand_data gpu_devfreq_config;
236
237 /**
238 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive
239 */
240 bool gpu_clamp_to_idle;
241
242 /**
243 * disable_err_irq:
244 *
245 * Disable handling of GPU hw error interrupts, to force fallback to
246 * sw hangcheck timer. Written (via debugfs) by igt tests to test
247 * the sw hangcheck mechanism.
248 */
249 bool disable_err_irq;
250};
251
252struct msm_format {
253 uint32_t pixel_format;
254};
255
256struct msm_pending_timer;
257
258int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
259 struct msm_kms *kms, int crtc_idx);
260void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
261void msm_atomic_commit_tail(struct drm_atomic_state *state);
262int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
263struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
264void msm_atomic_state_clear(struct drm_atomic_state *state);
265void msm_atomic_state_free(struct drm_atomic_state *state);
266
267int msm_crtc_enable_vblank(struct drm_crtc *crtc);
268void msm_crtc_disable_vblank(struct drm_crtc *crtc);
269
270int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
271void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
272
273struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev);
274bool msm_use_mmu(struct drm_device *dev);
275
276int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
277 struct drm_file *file);
278
279#ifdef CONFIG_DEBUG_FS
280unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
281#endif
282
283int msm_gem_shrinker_init(struct drm_device *dev);
284void msm_gem_shrinker_cleanup(struct drm_device *dev);
285
286struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
287int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
288void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
289struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
290 struct dma_buf_attachment *attach, struct sg_table *sg);
291int msm_gem_prime_pin(struct drm_gem_object *obj);
292void msm_gem_prime_unpin(struct drm_gem_object *obj);
293
294int msm_framebuffer_prepare(struct drm_framebuffer *fb,
295 struct msm_gem_address_space *aspace, bool needs_dirtyfb);
296void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
297 struct msm_gem_address_space *aspace, bool needed_dirtyfb);
298uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
299 struct msm_gem_address_space *aspace, int plane);
300struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
301const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
302struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
303 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
304struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
305 int w, int h, int p, uint32_t format);
306
307#ifdef CONFIG_DRM_FBDEV_EMULATION
308void msm_fbdev_setup(struct drm_device *dev);
309#else
310static inline void msm_fbdev_setup(struct drm_device *dev)
311{
312}
313#endif
314
315struct hdmi;
316#ifdef CONFIG_DRM_MSM_HDMI
317int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
318 struct drm_encoder *encoder);
319void __init msm_hdmi_register(void);
320void __exit msm_hdmi_unregister(void);
321#else
322static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
323 struct drm_encoder *encoder)
324{
325 return -EINVAL;
326}
327static inline void __init msm_hdmi_register(void) {}
328static inline void __exit msm_hdmi_unregister(void) {}
329#endif
330
331struct msm_dsi;
332#ifdef CONFIG_DRM_MSM_DSI
333int dsi_dev_attach(struct platform_device *pdev);
334void dsi_dev_detach(struct platform_device *pdev);
335void __init msm_dsi_register(void);
336void __exit msm_dsi_unregister(void);
337int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
338 struct drm_encoder *encoder);
339void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
340bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
341bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
342bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
343bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi);
344struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
345#else
346static inline void __init msm_dsi_register(void)
347{
348}
349static inline void __exit msm_dsi_unregister(void)
350{
351}
352static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
353 struct drm_device *dev,
354 struct drm_encoder *encoder)
355{
356 return -EINVAL;
357}
358static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
359{
360}
361static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
362{
363 return false;
364}
365static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi)
366{
367 return false;
368}
369static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
370{
371 return false;
372}
373static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi)
374{
375 return false;
376}
377
378static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
379{
380 return NULL;
381}
382#endif
383
384#ifdef CONFIG_DRM_MSM_DP
385int __init msm_dp_register(void);
386void __exit msm_dp_unregister(void);
387int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
388 struct drm_encoder *encoder);
389void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
390
391bool msm_dp_wide_bus_available(const struct msm_dp *dp_display);
392
393#else
394static inline int __init msm_dp_register(void)
395{
396 return -EINVAL;
397}
398static inline void __exit msm_dp_unregister(void)
399{
400}
401static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
402 struct drm_device *dev,
403 struct drm_encoder *encoder)
404{
405 return -EINVAL;
406}
407
408static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
409{
410}
411
412static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)
413{
414 return false;
415}
416
417#endif
418
419#ifdef CONFIG_DRM_MSM_MDP4
420void msm_mdp4_register(void);
421void msm_mdp4_unregister(void);
422#else
423static inline void msm_mdp4_register(void) {}
424static inline void msm_mdp4_unregister(void) {}
425#endif
426
427#ifdef CONFIG_DRM_MSM_MDP5
428void msm_mdp_register(void);
429void msm_mdp_unregister(void);
430#else
431static inline void msm_mdp_register(void) {}
432static inline void msm_mdp_unregister(void) {}
433#endif
434
435#ifdef CONFIG_DRM_MSM_DPU
436void msm_dpu_register(void);
437void msm_dpu_unregister(void);
438#else
439static inline void msm_dpu_register(void) {}
440static inline void msm_dpu_unregister(void) {}
441#endif
442
443#ifdef CONFIG_DRM_MSM_MDSS
444void msm_mdss_register(void);
445void msm_mdss_unregister(void);
446#else
447static inline void msm_mdss_register(void) {}
448static inline void msm_mdss_unregister(void) {}
449#endif
450
451#ifdef CONFIG_DEBUG_FS
452void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
453int msm_debugfs_late_init(struct drm_device *dev);
454int msm_rd_debugfs_init(struct drm_minor *minor);
455void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
456__printf(3, 4)
457void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
458 const char *fmt, ...);
459int msm_perf_debugfs_init(struct drm_minor *minor);
460void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
461#else
462static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
463__printf(3, 4)
464static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
465 struct msm_gem_submit *submit,
466 const char *fmt, ...) {}
467static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
468static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
469#endif
470
471struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
472
473struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
474 const char *name);
475void __iomem *msm_ioremap(struct platform_device *pdev, const char *name);
476void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
477 phys_addr_t *size);
478void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name);
479
480struct icc_path *msm_icc_get(struct device *dev, const char *name);
481
482#define msm_writel(data, addr) writel((data), (addr))
483#define msm_readl(addr) readl((addr))
484
485static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or)
486{
487 u32 val = msm_readl(addr);
488
489 val &= ~mask;
490 msm_writel(val | or, addr);
491}
492
493/**
494 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work
495 *
496 * @timer: hrtimer to control when the kthread work is triggered
497 * @work: the kthread work
498 * @worker: the kthread worker the work will be scheduled on
499 */
500struct msm_hrtimer_work {
501 struct hrtimer timer;
502 struct kthread_work work;
503 struct kthread_worker *worker;
504};
505
506void msm_hrtimer_queue_work(struct msm_hrtimer_work *work,
507 ktime_t wakeup_time,
508 enum hrtimer_mode mode);
509void msm_hrtimer_work_init(struct msm_hrtimer_work *work,
510 struct kthread_worker *worker,
511 kthread_work_func_t fn,
512 clockid_t clock_id,
513 enum hrtimer_mode mode);
514
515#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
516#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
517
518static inline int align_pitch(int width, int bpp)
519{
520 int bytespp = (bpp + 7) / 8;
521 /* adreno needs pitch aligned to 32 pixels: */
522 return bytespp * ALIGN(width, 32);
523}
524
525/* for the generated headers: */
526#define INVALID_IDX(idx) ({BUG(); 0;})
527#define fui(x) ({BUG(); 0;})
528#define _mesa_float_to_half(x) ({BUG(); 0;})
529
530
531#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
532
533/* for conditionally setting boolean flag(s): */
534#define COND(bool, val) ((bool) ? (val) : 0)
535
536static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
537{
538 ktime_t now = ktime_get();
539 s64 remaining_jiffies;
540
541 if (ktime_compare(*timeout, now) < 0) {
542 remaining_jiffies = 0;
543 } else {
544 ktime_t rem = ktime_sub(*timeout, now);
545 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
546 }
547
548 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX);
549}
550
551/* Driver helpers */
552
553extern const struct component_master_ops msm_drm_ops;
554
555int msm_kms_pm_prepare(struct device *dev);
556void msm_kms_pm_complete(struct device *dev);
557
558int msm_drv_probe(struct device *dev,
559 int (*kms_init)(struct drm_device *dev),
560 struct msm_kms *kms);
561void msm_kms_shutdown(struct platform_device *pdev);
562
563
564#endif /* __MSM_DRV_H__ */
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_DRV_H__
19#define __MSM_DRV_H__
20
21#include <linux/kernel.h>
22#include <linux/clk.h>
23#include <linux/cpufreq.h>
24#include <linux/module.h>
25#include <linux/component.h>
26#include <linux/platform_device.h>
27#include <linux/pm.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/list.h>
31#include <linux/iommu.h>
32#include <linux/types.h>
33#include <linux/of_graph.h>
34#include <linux/of_device.h>
35#include <asm/sizes.h>
36
37#include <drm/drmP.h>
38#include <drm/drm_atomic.h>
39#include <drm/drm_atomic_helper.h>
40#include <drm/drm_crtc_helper.h>
41#include <drm/drm_plane_helper.h>
42#include <drm/drm_fb_helper.h>
43#include <drm/msm_drm.h>
44#include <drm/drm_gem.h>
45
46struct msm_kms;
47struct msm_gpu;
48struct msm_mmu;
49struct msm_mdss;
50struct msm_rd_state;
51struct msm_perf_state;
52struct msm_gem_submit;
53struct msm_fence_context;
54struct msm_fence_cb;
55struct msm_gem_address_space;
56struct msm_gem_vma;
57
58#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
59
60struct msm_file_private {
61 /* currently we don't do anything useful with this.. but when
62 * per-context address spaces are supported we'd keep track of
63 * the context's page-tables here.
64 */
65 int dummy;
66};
67
68enum msm_mdp_plane_property {
69 PLANE_PROP_ZPOS,
70 PLANE_PROP_ALPHA,
71 PLANE_PROP_PREMULTIPLIED,
72 PLANE_PROP_MAX_NUM
73};
74
75struct msm_vblank_ctrl {
76 struct work_struct work;
77 struct list_head event_list;
78 spinlock_t lock;
79};
80
81struct msm_drm_private {
82
83 struct drm_device *dev;
84
85 struct msm_kms *kms;
86
87 /* subordinate devices, if present: */
88 struct platform_device *gpu_pdev;
89
90 /* top level MDSS wrapper device (for MDP5 only) */
91 struct msm_mdss *mdss;
92
93 /* possibly this should be in the kms component, but it is
94 * shared by both mdp4 and mdp5..
95 */
96 struct hdmi *hdmi;
97
98 /* eDP is for mdp5 only, but kms has not been created
99 * when edp_bind() and edp_init() are called. Here is the only
100 * place to keep the edp instance.
101 */
102 struct msm_edp *edp;
103
104 /* DSI is shared by mdp4 and mdp5 */
105 struct msm_dsi *dsi[2];
106
107 /* when we have more than one 'msm_gpu' these need to be an array: */
108 struct msm_gpu *gpu;
109 struct msm_file_private *lastctx;
110
111 struct drm_fb_helper *fbdev;
112
113 struct msm_rd_state *rd;
114 struct msm_perf_state *perf;
115
116 /* list of GEM objects: */
117 struct list_head inactive_list;
118
119 struct workqueue_struct *wq;
120 struct workqueue_struct *atomic_wq;
121
122 /* crtcs pending async atomic updates: */
123 uint32_t pending_crtcs;
124 wait_queue_head_t pending_crtcs_event;
125
126 /* Registered address spaces.. currently this is fixed per # of
127 * iommu's. Ie. one for display block and one for gpu block.
128 * Eventually, to do per-process gpu pagetables, we'll want one
129 * of these per-process.
130 */
131 unsigned int num_aspaces;
132 struct msm_gem_address_space *aspace[NUM_DOMAINS];
133
134 unsigned int num_planes;
135 struct drm_plane *planes[16];
136
137 unsigned int num_crtcs;
138 struct drm_crtc *crtcs[8];
139
140 unsigned int num_encoders;
141 struct drm_encoder *encoders[8];
142
143 unsigned int num_bridges;
144 struct drm_bridge *bridges[8];
145
146 unsigned int num_connectors;
147 struct drm_connector *connectors[8];
148
149 /* Properties */
150 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
151
152 /* VRAM carveout, used when no IOMMU: */
153 struct {
154 unsigned long size;
155 dma_addr_t paddr;
156 /* NOTE: mm managed at the page level, size is in # of pages
157 * and position mm_node->start is in # of pages:
158 */
159 struct drm_mm mm;
160 } vram;
161
162 struct notifier_block vmap_notifier;
163 struct shrinker shrinker;
164
165 struct msm_vblank_ctrl vblank_ctrl;
166
167 /* task holding struct_mutex.. currently only used in submit path
168 * to detect and reject faults from copy_from_user() for submit
169 * ioctl.
170 */
171 struct task_struct *struct_mutex_task;
172};
173
174struct msm_format {
175 uint32_t pixel_format;
176};
177
178int msm_atomic_check(struct drm_device *dev,
179 struct drm_atomic_state *state);
180int msm_atomic_commit(struct drm_device *dev,
181 struct drm_atomic_state *state, bool nonblock);
182struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
183void msm_atomic_state_clear(struct drm_atomic_state *state);
184void msm_atomic_state_free(struct drm_atomic_state *state);
185
186int msm_register_address_space(struct drm_device *dev,
187 struct msm_gem_address_space *aspace);
188
189void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
190 struct msm_gem_vma *vma, struct sg_table *sgt);
191int msm_gem_map_vma(struct msm_gem_address_space *aspace,
192 struct msm_gem_vma *vma, struct sg_table *sgt, int npages);
193
194void msm_gem_address_space_destroy(struct msm_gem_address_space *aspace);
195struct msm_gem_address_space *
196msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
197 const char *name);
198
199void msm_gem_submit_free(struct msm_gem_submit *submit);
200int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
201 struct drm_file *file);
202
203void msm_gem_shrinker_init(struct drm_device *dev);
204void msm_gem_shrinker_cleanup(struct drm_device *dev);
205
206int msm_gem_mmap_obj(struct drm_gem_object *obj,
207 struct vm_area_struct *vma);
208int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
209int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
210uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
211int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
212 uint64_t *iova);
213int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint64_t *iova);
214uint64_t msm_gem_iova(struct drm_gem_object *obj, int id);
215struct page **msm_gem_get_pages(struct drm_gem_object *obj);
216void msm_gem_put_pages(struct drm_gem_object *obj);
217void msm_gem_put_iova(struct drm_gem_object *obj, int id);
218int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
219 struct drm_mode_create_dumb *args);
220int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
221 uint32_t handle, uint64_t *offset);
222struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
223void *msm_gem_prime_vmap(struct drm_gem_object *obj);
224void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
225int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
226struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
227 struct dma_buf_attachment *attach, struct sg_table *sg);
228int msm_gem_prime_pin(struct drm_gem_object *obj);
229void msm_gem_prime_unpin(struct drm_gem_object *obj);
230void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj);
231void *msm_gem_get_vaddr(struct drm_gem_object *obj);
232void msm_gem_put_vaddr_locked(struct drm_gem_object *obj);
233void msm_gem_put_vaddr(struct drm_gem_object *obj);
234int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
235void msm_gem_purge(struct drm_gem_object *obj);
236void msm_gem_vunmap(struct drm_gem_object *obj);
237int msm_gem_sync_object(struct drm_gem_object *obj,
238 struct msm_fence_context *fctx, bool exclusive);
239void msm_gem_move_to_active(struct drm_gem_object *obj,
240 struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence);
241void msm_gem_move_to_inactive(struct drm_gem_object *obj);
242int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
243int msm_gem_cpu_fini(struct drm_gem_object *obj);
244void msm_gem_free_object(struct drm_gem_object *obj);
245int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
246 uint32_t size, uint32_t flags, uint32_t *handle);
247struct drm_gem_object *msm_gem_new(struct drm_device *dev,
248 uint32_t size, uint32_t flags);
249struct drm_gem_object *msm_gem_import(struct drm_device *dev,
250 struct dma_buf *dmabuf, struct sg_table *sgt);
251
252int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
253void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
254uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
255struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
256const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
257struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
258 const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
259struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
260 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
261
262struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
263void msm_fbdev_free(struct drm_device *dev);
264
265struct hdmi;
266int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
267 struct drm_encoder *encoder);
268void __init msm_hdmi_register(void);
269void __exit msm_hdmi_unregister(void);
270
271struct msm_edp;
272void __init msm_edp_register(void);
273void __exit msm_edp_unregister(void);
274int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
275 struct drm_encoder *encoder);
276
277struct msm_dsi;
278enum msm_dsi_encoder_id {
279 MSM_DSI_VIDEO_ENCODER_ID = 0,
280 MSM_DSI_CMD_ENCODER_ID = 1,
281 MSM_DSI_ENCODER_NUM = 2
282};
283#ifdef CONFIG_DRM_MSM_DSI
284void __init msm_dsi_register(void);
285void __exit msm_dsi_unregister(void);
286int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
287 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]);
288#else
289static inline void __init msm_dsi_register(void)
290{
291}
292static inline void __exit msm_dsi_unregister(void)
293{
294}
295static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
296 struct drm_device *dev,
297 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM])
298{
299 return -EINVAL;
300}
301#endif
302
303void __init msm_mdp_register(void);
304void __exit msm_mdp_unregister(void);
305
306#ifdef CONFIG_DEBUG_FS
307void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
308void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
309void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
310int msm_debugfs_late_init(struct drm_device *dev);
311int msm_rd_debugfs_init(struct drm_minor *minor);
312void msm_rd_debugfs_cleanup(struct drm_minor *minor);
313void msm_rd_dump_submit(struct msm_gem_submit *submit);
314int msm_perf_debugfs_init(struct drm_minor *minor);
315void msm_perf_debugfs_cleanup(struct drm_minor *minor);
316#else
317static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
318static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
319#endif
320
321void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
322 const char *dbgname);
323void msm_writel(u32 data, void __iomem *addr);
324u32 msm_readl(const void __iomem *addr);
325
326#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
327#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
328
329static inline int align_pitch(int width, int bpp)
330{
331 int bytespp = (bpp + 7) / 8;
332 /* adreno needs pitch aligned to 32 pixels: */
333 return bytespp * ALIGN(width, 32);
334}
335
336/* for the generated headers: */
337#define INVALID_IDX(idx) ({BUG(); 0;})
338#define fui(x) ({BUG(); 0;})
339#define util_float_to_half(x) ({BUG(); 0;})
340
341
342#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
343
344/* for conditionally setting boolean flag(s): */
345#define COND(bool, val) ((bool) ? (val) : 0)
346
347static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
348{
349 ktime_t now = ktime_get();
350 unsigned long remaining_jiffies;
351
352 if (ktime_compare(*timeout, now) < 0) {
353 remaining_jiffies = 0;
354 } else {
355 ktime_t rem = ktime_sub(*timeout, now);
356 struct timespec ts = ktime_to_timespec(rem);
357 remaining_jiffies = timespec_to_jiffies(&ts);
358 }
359
360 return remaining_jiffies;
361}
362
363#endif /* __MSM_DRV_H__ */