Loading...
1/*
2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
7 * for more details.
8 *
9 * ARM HDLCD Driver
10 */
11
12#include <linux/module.h>
13#include <linux/spinlock.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/console.h>
17#include <linux/dma-mapping.h>
18#include <linux/list.h>
19#include <linux/of_graph.h>
20#include <linux/of_reserved_mem.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23
24#include <drm/drm_aperture.h>
25#include <drm/drm_atomic_helper.h>
26#include <drm/drm_crtc.h>
27#include <drm/drm_debugfs.h>
28#include <drm/drm_drv.h>
29#include <drm/drm_fbdev_dma.h>
30#include <drm/drm_gem_dma_helper.h>
31#include <drm/drm_gem_framebuffer_helper.h>
32#include <drm/drm_modeset_helper.h>
33#include <drm/drm_module.h>
34#include <drm/drm_of.h>
35#include <drm/drm_probe_helper.h>
36#include <drm/drm_vblank.h>
37
38#include "hdlcd_drv.h"
39#include "hdlcd_regs.h"
40
41static irqreturn_t hdlcd_irq(int irq, void *arg)
42{
43 struct hdlcd_drm_private *hdlcd = arg;
44 unsigned long irq_status;
45
46 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
47
48#ifdef CONFIG_DEBUG_FS
49 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
50 atomic_inc(&hdlcd->buffer_underrun_count);
51
52 if (irq_status & HDLCD_INTERRUPT_DMA_END)
53 atomic_inc(&hdlcd->dma_end_count);
54
55 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
56 atomic_inc(&hdlcd->bus_error_count);
57
58 if (irq_status & HDLCD_INTERRUPT_VSYNC)
59 atomic_inc(&hdlcd->vsync_count);
60
61#endif
62 if (irq_status & HDLCD_INTERRUPT_VSYNC)
63 drm_crtc_handle_vblank(&hdlcd->crtc);
64
65 /* acknowledge interrupt(s) */
66 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
67
68 return IRQ_HANDLED;
69}
70
71static int hdlcd_irq_install(struct hdlcd_drm_private *hdlcd)
72{
73 int ret;
74
75 /* Ensure interrupts are disabled */
76 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
77 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
78
79 ret = request_irq(hdlcd->irq, hdlcd_irq, 0, "hdlcd", hdlcd);
80 if (ret)
81 return ret;
82
83#ifdef CONFIG_DEBUG_FS
84 /* enable debug interrupts */
85 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, HDLCD_DEBUG_INT_MASK);
86#endif
87
88 return 0;
89}
90
91static void hdlcd_irq_uninstall(struct hdlcd_drm_private *hdlcd)
92{
93 /* disable all the interrupts that we might have enabled */
94 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
95
96 free_irq(hdlcd->irq, hdlcd);
97}
98
99static int hdlcd_load(struct drm_device *drm, unsigned long flags)
100{
101 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
102 struct platform_device *pdev = to_platform_device(drm->dev);
103 u32 version;
104 int ret;
105
106 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
107 if (IS_ERR(hdlcd->clk))
108 return PTR_ERR(hdlcd->clk);
109
110#ifdef CONFIG_DEBUG_FS
111 atomic_set(&hdlcd->buffer_underrun_count, 0);
112 atomic_set(&hdlcd->bus_error_count, 0);
113 atomic_set(&hdlcd->vsync_count, 0);
114 atomic_set(&hdlcd->dma_end_count, 0);
115#endif
116
117 hdlcd->mmio = devm_platform_ioremap_resource(pdev, 0);
118 if (IS_ERR(hdlcd->mmio)) {
119 DRM_ERROR("failed to map control registers area\n");
120 ret = PTR_ERR(hdlcd->mmio);
121 hdlcd->mmio = NULL;
122 return ret;
123 }
124
125 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
126 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
127 DRM_ERROR("unknown product id: 0x%x\n", version);
128 return -EINVAL;
129 }
130 DRM_INFO("found ARM HDLCD version r%dp%d\n",
131 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
132 version & HDLCD_VERSION_MINOR_MASK);
133
134 /* Get the optional framebuffer memory resource */
135 ret = of_reserved_mem_device_init(drm->dev);
136 if (ret && ret != -ENODEV)
137 return ret;
138
139 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
140 if (ret)
141 goto setup_fail;
142
143 ret = hdlcd_setup_crtc(drm);
144 if (ret < 0) {
145 DRM_ERROR("failed to create crtc\n");
146 goto setup_fail;
147 }
148
149 ret = platform_get_irq(pdev, 0);
150 if (ret < 0)
151 goto irq_fail;
152 hdlcd->irq = ret;
153
154 ret = hdlcd_irq_install(hdlcd);
155 if (ret < 0) {
156 DRM_ERROR("failed to install IRQ handler\n");
157 goto irq_fail;
158 }
159
160 return 0;
161
162irq_fail:
163 drm_crtc_cleanup(&hdlcd->crtc);
164setup_fail:
165 of_reserved_mem_device_release(drm->dev);
166
167 return ret;
168}
169
170static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
171 .fb_create = drm_gem_fb_create,
172 .atomic_check = drm_atomic_helper_check,
173 .atomic_commit = drm_atomic_helper_commit,
174};
175
176static int hdlcd_setup_mode_config(struct drm_device *drm)
177{
178 int ret;
179
180 ret = drmm_mode_config_init(drm);
181 if (ret)
182 return ret;
183
184 drm->mode_config.min_width = 0;
185 drm->mode_config.min_height = 0;
186 drm->mode_config.max_width = HDLCD_MAX_XRES;
187 drm->mode_config.max_height = HDLCD_MAX_YRES;
188 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
189
190 return 0;
191}
192
193#ifdef CONFIG_DEBUG_FS
194static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
195{
196 struct drm_debugfs_entry *entry = m->private;
197 struct drm_device *drm = entry->dev;
198 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
199
200 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
201 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
202 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
203 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
204 return 0;
205}
206
207static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
208{
209 struct drm_debugfs_entry *entry = m->private;
210 struct drm_device *drm = entry->dev;
211 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
212 unsigned long clkrate = clk_get_rate(hdlcd->clk);
213 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
214
215 seq_printf(m, "hw : %lu\n", clkrate);
216 seq_printf(m, "mode: %lu\n", mode_clock);
217 return 0;
218}
219
220static struct drm_debugfs_info hdlcd_debugfs_list[] = {
221 { "interrupt_count", hdlcd_show_underrun_count, 0 },
222 { "clocks", hdlcd_show_pxlclock, 0 },
223};
224#endif
225
226DEFINE_DRM_GEM_DMA_FOPS(fops);
227
228static const struct drm_driver hdlcd_driver = {
229 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
230 DRM_GEM_DMA_DRIVER_OPS,
231 .fops = &fops,
232 .name = "hdlcd",
233 .desc = "ARM HDLCD Controller DRM",
234 .date = "20151021",
235 .major = 1,
236 .minor = 0,
237};
238
239static int hdlcd_drm_bind(struct device *dev)
240{
241 struct drm_device *drm;
242 struct hdlcd_drm_private *hdlcd;
243 int ret;
244
245 hdlcd = devm_drm_dev_alloc(dev, &hdlcd_driver, typeof(*hdlcd), base);
246 if (IS_ERR(hdlcd))
247 return PTR_ERR(hdlcd);
248
249 drm = &hdlcd->base;
250
251 dev_set_drvdata(dev, drm);
252
253 ret = hdlcd_setup_mode_config(drm);
254 if (ret)
255 goto err_free;
256
257 ret = hdlcd_load(drm, 0);
258 if (ret)
259 goto err_free;
260
261 /* Set the CRTC's port so that the encoder component can find it */
262 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
263
264 ret = component_bind_all(dev, drm);
265 if (ret) {
266 DRM_ERROR("Failed to bind all components\n");
267 goto err_unload;
268 }
269
270 ret = pm_runtime_set_active(dev);
271 if (ret)
272 goto err_pm_active;
273
274 pm_runtime_enable(dev);
275
276 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
277 if (ret < 0) {
278 DRM_ERROR("failed to initialise vblank\n");
279 goto err_vblank;
280 }
281
282 /*
283 * If EFI left us running, take over from simple framebuffer
284 * drivers. Read HDLCD_REG_COMMAND to see if we are enabled.
285 */
286 if (hdlcd_read(hdlcd, HDLCD_REG_COMMAND)) {
287 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
288 drm_aperture_remove_framebuffers(&hdlcd_driver);
289 }
290
291 drm_mode_config_reset(drm);
292 drm_kms_helper_poll_init(drm);
293
294#ifdef CONFIG_DEBUG_FS
295 drm_debugfs_add_files(drm, hdlcd_debugfs_list, ARRAY_SIZE(hdlcd_debugfs_list));
296#endif
297
298 ret = drm_dev_register(drm, 0);
299 if (ret)
300 goto err_register;
301
302 drm_fbdev_dma_setup(drm, 32);
303
304 return 0;
305
306err_register:
307 drm_kms_helper_poll_fini(drm);
308err_vblank:
309 pm_runtime_disable(drm->dev);
310err_pm_active:
311 drm_atomic_helper_shutdown(drm);
312 component_unbind_all(dev, drm);
313err_unload:
314 of_node_put(hdlcd->crtc.port);
315 hdlcd->crtc.port = NULL;
316 hdlcd_irq_uninstall(hdlcd);
317 of_reserved_mem_device_release(drm->dev);
318err_free:
319 dev_set_drvdata(dev, NULL);
320 return ret;
321}
322
323static void hdlcd_drm_unbind(struct device *dev)
324{
325 struct drm_device *drm = dev_get_drvdata(dev);
326 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
327
328 drm_dev_unregister(drm);
329 drm_kms_helper_poll_fini(drm);
330 component_unbind_all(dev, drm);
331 of_node_put(hdlcd->crtc.port);
332 hdlcd->crtc.port = NULL;
333 pm_runtime_get_sync(dev);
334 drm_atomic_helper_shutdown(drm);
335 hdlcd_irq_uninstall(hdlcd);
336 pm_runtime_put(dev);
337 if (pm_runtime_enabled(dev))
338 pm_runtime_disable(dev);
339 of_reserved_mem_device_release(dev);
340 dev_set_drvdata(dev, NULL);
341}
342
343static const struct component_master_ops hdlcd_master_ops = {
344 .bind = hdlcd_drm_bind,
345 .unbind = hdlcd_drm_unbind,
346};
347
348static int compare_dev(struct device *dev, void *data)
349{
350 return dev->of_node == data;
351}
352
353static int hdlcd_probe(struct platform_device *pdev)
354{
355 struct device_node *port;
356 struct component_match *match = NULL;
357
358 /* there is only one output port inside each device, find it */
359 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
360 if (!port)
361 return -ENODEV;
362
363 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
364 of_node_put(port);
365
366 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
367 match);
368}
369
370static void hdlcd_remove(struct platform_device *pdev)
371{
372 component_master_del(&pdev->dev, &hdlcd_master_ops);
373}
374
375static void hdlcd_shutdown(struct platform_device *pdev)
376{
377 drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
378}
379
380static const struct of_device_id hdlcd_of_match[] = {
381 { .compatible = "arm,hdlcd" },
382 {},
383};
384MODULE_DEVICE_TABLE(of, hdlcd_of_match);
385
386static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
387{
388 struct drm_device *drm = dev_get_drvdata(dev);
389
390 return drm_mode_config_helper_suspend(drm);
391}
392
393static int __maybe_unused hdlcd_pm_resume(struct device *dev)
394{
395 struct drm_device *drm = dev_get_drvdata(dev);
396
397 drm_mode_config_helper_resume(drm);
398
399 return 0;
400}
401
402static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
403
404static struct platform_driver hdlcd_platform_driver = {
405 .probe = hdlcd_probe,
406 .remove_new = hdlcd_remove,
407 .shutdown = hdlcd_shutdown,
408 .driver = {
409 .name = "hdlcd",
410 .pm = &hdlcd_pm_ops,
411 .of_match_table = hdlcd_of_match,
412 },
413};
414
415drm_module_platform_driver(hdlcd_platform_driver);
416
417MODULE_AUTHOR("Liviu Dudau");
418MODULE_DESCRIPTION("ARM HDLCD DRM driver");
419MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
7 * for more details.
8 *
9 * ARM HDLCD Driver
10 */
11
12#include <linux/module.h>
13#include <linux/spinlock.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/list.h>
17#include <linux/of_graph.h>
18#include <linux/of_reserved_mem.h>
19#include <linux/pm_runtime.h>
20
21#include <drm/drmP.h>
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_crtc.h>
24#include <drm/drm_crtc_helper.h>
25#include <drm/drm_fb_helper.h>
26#include <drm/drm_fb_cma_helper.h>
27#include <drm/drm_gem_cma_helper.h>
28#include <drm/drm_of.h>
29
30#include "hdlcd_drv.h"
31#include "hdlcd_regs.h"
32
33static int hdlcd_load(struct drm_device *drm, unsigned long flags)
34{
35 struct hdlcd_drm_private *hdlcd = drm->dev_private;
36 struct platform_device *pdev = to_platform_device(drm->dev);
37 struct resource *res;
38 u32 version;
39 int ret;
40
41 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
42 if (IS_ERR(hdlcd->clk))
43 return PTR_ERR(hdlcd->clk);
44
45#ifdef CONFIG_DEBUG_FS
46 atomic_set(&hdlcd->buffer_underrun_count, 0);
47 atomic_set(&hdlcd->bus_error_count, 0);
48 atomic_set(&hdlcd->vsync_count, 0);
49 atomic_set(&hdlcd->dma_end_count, 0);
50#endif
51
52 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
53 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
54 if (IS_ERR(hdlcd->mmio)) {
55 DRM_ERROR("failed to map control registers area\n");
56 ret = PTR_ERR(hdlcd->mmio);
57 hdlcd->mmio = NULL;
58 return ret;
59 }
60
61 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
62 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
63 DRM_ERROR("unknown product id: 0x%x\n", version);
64 return -EINVAL;
65 }
66 DRM_INFO("found ARM HDLCD version r%dp%d\n",
67 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
68 version & HDLCD_VERSION_MINOR_MASK);
69
70 /* Get the optional framebuffer memory resource */
71 ret = of_reserved_mem_device_init(drm->dev);
72 if (ret && ret != -ENODEV)
73 return ret;
74
75 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
76 if (ret)
77 goto setup_fail;
78
79 ret = hdlcd_setup_crtc(drm);
80 if (ret < 0) {
81 DRM_ERROR("failed to create crtc\n");
82 goto setup_fail;
83 }
84
85 ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
86 if (ret < 0) {
87 DRM_ERROR("failed to install IRQ handler\n");
88 goto irq_fail;
89 }
90
91 return 0;
92
93irq_fail:
94 drm_crtc_cleanup(&hdlcd->crtc);
95setup_fail:
96 of_reserved_mem_device_release(drm->dev);
97
98 return ret;
99}
100
101static void hdlcd_fb_output_poll_changed(struct drm_device *drm)
102{
103 struct hdlcd_drm_private *hdlcd = drm->dev_private;
104
105 drm_fbdev_cma_hotplug_event(hdlcd->fbdev);
106}
107
108static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
109 .fb_create = drm_fb_cma_create,
110 .output_poll_changed = hdlcd_fb_output_poll_changed,
111 .atomic_check = drm_atomic_helper_check,
112 .atomic_commit = drm_atomic_helper_commit,
113};
114
115static void hdlcd_setup_mode_config(struct drm_device *drm)
116{
117 drm_mode_config_init(drm);
118 drm->mode_config.min_width = 0;
119 drm->mode_config.min_height = 0;
120 drm->mode_config.max_width = HDLCD_MAX_XRES;
121 drm->mode_config.max_height = HDLCD_MAX_YRES;
122 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
123}
124
125static void hdlcd_lastclose(struct drm_device *drm)
126{
127 struct hdlcd_drm_private *hdlcd = drm->dev_private;
128
129 drm_fbdev_cma_restore_mode(hdlcd->fbdev);
130}
131
132static irqreturn_t hdlcd_irq(int irq, void *arg)
133{
134 struct drm_device *drm = arg;
135 struct hdlcd_drm_private *hdlcd = drm->dev_private;
136 unsigned long irq_status;
137
138 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
139
140#ifdef CONFIG_DEBUG_FS
141 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
142 atomic_inc(&hdlcd->buffer_underrun_count);
143
144 if (irq_status & HDLCD_INTERRUPT_DMA_END)
145 atomic_inc(&hdlcd->dma_end_count);
146
147 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
148 atomic_inc(&hdlcd->bus_error_count);
149
150 if (irq_status & HDLCD_INTERRUPT_VSYNC)
151 atomic_inc(&hdlcd->vsync_count);
152
153#endif
154 if (irq_status & HDLCD_INTERRUPT_VSYNC)
155 drm_crtc_handle_vblank(&hdlcd->crtc);
156
157 /* acknowledge interrupt(s) */
158 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
159
160 return IRQ_HANDLED;
161}
162
163static void hdlcd_irq_preinstall(struct drm_device *drm)
164{
165 struct hdlcd_drm_private *hdlcd = drm->dev_private;
166 /* Ensure interrupts are disabled */
167 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
168 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
169}
170
171static int hdlcd_irq_postinstall(struct drm_device *drm)
172{
173#ifdef CONFIG_DEBUG_FS
174 struct hdlcd_drm_private *hdlcd = drm->dev_private;
175 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
176
177 /* enable debug interrupts */
178 irq_mask |= HDLCD_DEBUG_INT_MASK;
179
180 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
181#endif
182 return 0;
183}
184
185static void hdlcd_irq_uninstall(struct drm_device *drm)
186{
187 struct hdlcd_drm_private *hdlcd = drm->dev_private;
188 /* disable all the interrupts that we might have enabled */
189 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
190
191#ifdef CONFIG_DEBUG_FS
192 /* disable debug interrupts */
193 irq_mask &= ~HDLCD_DEBUG_INT_MASK;
194#endif
195
196 /* disable vsync interrupts */
197 irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
198
199 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
200}
201
202static int hdlcd_enable_vblank(struct drm_device *drm, unsigned int crtc)
203{
204 struct hdlcd_drm_private *hdlcd = drm->dev_private;
205 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
206
207 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
208
209 return 0;
210}
211
212static void hdlcd_disable_vblank(struct drm_device *drm, unsigned int crtc)
213{
214 struct hdlcd_drm_private *hdlcd = drm->dev_private;
215 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
216
217 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
218}
219
220#ifdef CONFIG_DEBUG_FS
221static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
222{
223 struct drm_info_node *node = (struct drm_info_node *)m->private;
224 struct drm_device *drm = node->minor->dev;
225 struct hdlcd_drm_private *hdlcd = drm->dev_private;
226
227 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
228 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
229 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
230 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
231 return 0;
232}
233
234static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
235{
236 struct drm_info_node *node = (struct drm_info_node *)m->private;
237 struct drm_device *drm = node->minor->dev;
238 struct hdlcd_drm_private *hdlcd = drm->dev_private;
239 unsigned long clkrate = clk_get_rate(hdlcd->clk);
240 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
241
242 seq_printf(m, "hw : %lu\n", clkrate);
243 seq_printf(m, "mode: %lu\n", mode_clock);
244 return 0;
245}
246
247static struct drm_info_list hdlcd_debugfs_list[] = {
248 { "interrupt_count", hdlcd_show_underrun_count, 0 },
249 { "clocks", hdlcd_show_pxlclock, 0 },
250 { "fb", drm_fb_cma_debugfs_show, 0 },
251};
252
253static int hdlcd_debugfs_init(struct drm_minor *minor)
254{
255 return drm_debugfs_create_files(hdlcd_debugfs_list,
256 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
257}
258
259static void hdlcd_debugfs_cleanup(struct drm_minor *minor)
260{
261 drm_debugfs_remove_files(hdlcd_debugfs_list,
262 ARRAY_SIZE(hdlcd_debugfs_list), minor);
263}
264#endif
265
266static const struct file_operations fops = {
267 .owner = THIS_MODULE,
268 .open = drm_open,
269 .release = drm_release,
270 .unlocked_ioctl = drm_ioctl,
271 .compat_ioctl = drm_compat_ioctl,
272 .poll = drm_poll,
273 .read = drm_read,
274 .llseek = noop_llseek,
275 .mmap = drm_gem_cma_mmap,
276};
277
278static struct drm_driver hdlcd_driver = {
279 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
280 DRIVER_MODESET | DRIVER_PRIME |
281 DRIVER_ATOMIC,
282 .lastclose = hdlcd_lastclose,
283 .irq_handler = hdlcd_irq,
284 .irq_preinstall = hdlcd_irq_preinstall,
285 .irq_postinstall = hdlcd_irq_postinstall,
286 .irq_uninstall = hdlcd_irq_uninstall,
287 .get_vblank_counter = drm_vblank_no_hw_counter,
288 .enable_vblank = hdlcd_enable_vblank,
289 .disable_vblank = hdlcd_disable_vblank,
290 .gem_free_object_unlocked = drm_gem_cma_free_object,
291 .gem_vm_ops = &drm_gem_cma_vm_ops,
292 .dumb_create = drm_gem_cma_dumb_create,
293 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
294 .dumb_destroy = drm_gem_dumb_destroy,
295 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
296 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
297 .gem_prime_export = drm_gem_prime_export,
298 .gem_prime_import = drm_gem_prime_import,
299 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
300 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
301 .gem_prime_vmap = drm_gem_cma_prime_vmap,
302 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
303 .gem_prime_mmap = drm_gem_cma_prime_mmap,
304#ifdef CONFIG_DEBUG_FS
305 .debugfs_init = hdlcd_debugfs_init,
306 .debugfs_cleanup = hdlcd_debugfs_cleanup,
307#endif
308 .fops = &fops,
309 .name = "hdlcd",
310 .desc = "ARM HDLCD Controller DRM",
311 .date = "20151021",
312 .major = 1,
313 .minor = 0,
314};
315
316static int hdlcd_drm_bind(struct device *dev)
317{
318 struct drm_device *drm;
319 struct hdlcd_drm_private *hdlcd;
320 int ret;
321
322 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
323 if (!hdlcd)
324 return -ENOMEM;
325
326 drm = drm_dev_alloc(&hdlcd_driver, dev);
327 if (IS_ERR(drm))
328 return PTR_ERR(drm);
329
330 drm->dev_private = hdlcd;
331 dev_set_drvdata(dev, drm);
332
333 hdlcd_setup_mode_config(drm);
334 ret = hdlcd_load(drm, 0);
335 if (ret)
336 goto err_free;
337
338 ret = component_bind_all(dev, drm);
339 if (ret) {
340 DRM_ERROR("Failed to bind all components\n");
341 goto err_unload;
342 }
343
344 ret = pm_runtime_set_active(dev);
345 if (ret)
346 goto err_pm_active;
347
348 pm_runtime_enable(dev);
349
350 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
351 if (ret < 0) {
352 DRM_ERROR("failed to initialise vblank\n");
353 goto err_vblank;
354 }
355
356 drm_mode_config_reset(drm);
357 drm_kms_helper_poll_init(drm);
358
359 hdlcd->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
360 drm->mode_config.num_connector);
361
362 if (IS_ERR(hdlcd->fbdev)) {
363 ret = PTR_ERR(hdlcd->fbdev);
364 hdlcd->fbdev = NULL;
365 goto err_fbdev;
366 }
367
368 ret = drm_dev_register(drm, 0);
369 if (ret)
370 goto err_register;
371
372 return 0;
373
374err_register:
375 if (hdlcd->fbdev) {
376 drm_fbdev_cma_fini(hdlcd->fbdev);
377 hdlcd->fbdev = NULL;
378 }
379err_fbdev:
380 drm_kms_helper_poll_fini(drm);
381 drm_vblank_cleanup(drm);
382err_vblank:
383 pm_runtime_disable(drm->dev);
384err_pm_active:
385 component_unbind_all(dev, drm);
386err_unload:
387 drm_irq_uninstall(drm);
388 of_reserved_mem_device_release(drm->dev);
389err_free:
390 drm_mode_config_cleanup(drm);
391 dev_set_drvdata(dev, NULL);
392 drm_dev_unref(drm);
393
394 return ret;
395}
396
397static void hdlcd_drm_unbind(struct device *dev)
398{
399 struct drm_device *drm = dev_get_drvdata(dev);
400 struct hdlcd_drm_private *hdlcd = drm->dev_private;
401
402 drm_dev_unregister(drm);
403 if (hdlcd->fbdev) {
404 drm_fbdev_cma_fini(hdlcd->fbdev);
405 hdlcd->fbdev = NULL;
406 }
407 drm_kms_helper_poll_fini(drm);
408 component_unbind_all(dev, drm);
409 drm_vblank_cleanup(drm);
410 pm_runtime_get_sync(drm->dev);
411 drm_irq_uninstall(drm);
412 pm_runtime_put_sync(drm->dev);
413 pm_runtime_disable(drm->dev);
414 of_reserved_mem_device_release(drm->dev);
415 drm_mode_config_cleanup(drm);
416 drm_dev_unref(drm);
417 drm->dev_private = NULL;
418 dev_set_drvdata(dev, NULL);
419}
420
421static const struct component_master_ops hdlcd_master_ops = {
422 .bind = hdlcd_drm_bind,
423 .unbind = hdlcd_drm_unbind,
424};
425
426static int compare_dev(struct device *dev, void *data)
427{
428 return dev->of_node == data;
429}
430
431static int hdlcd_probe(struct platform_device *pdev)
432{
433 struct device_node *port, *ep;
434 struct component_match *match = NULL;
435
436 if (!pdev->dev.of_node)
437 return -ENODEV;
438
439 /* there is only one output port inside each device, find it */
440 ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
441 if (!ep)
442 return -ENODEV;
443
444 if (!of_device_is_available(ep)) {
445 of_node_put(ep);
446 return -ENODEV;
447 }
448
449 /* add the remote encoder port as component */
450 port = of_graph_get_remote_port_parent(ep);
451 of_node_put(ep);
452 if (!port || !of_device_is_available(port)) {
453 of_node_put(port);
454 return -EAGAIN;
455 }
456
457 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
458 of_node_put(port);
459
460 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
461 match);
462}
463
464static int hdlcd_remove(struct platform_device *pdev)
465{
466 component_master_del(&pdev->dev, &hdlcd_master_ops);
467 return 0;
468}
469
470static const struct of_device_id hdlcd_of_match[] = {
471 { .compatible = "arm,hdlcd" },
472 {},
473};
474MODULE_DEVICE_TABLE(of, hdlcd_of_match);
475
476static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
477{
478 struct drm_device *drm = dev_get_drvdata(dev);
479 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
480
481 if (!hdlcd)
482 return 0;
483
484 drm_kms_helper_poll_disable(drm);
485
486 hdlcd->state = drm_atomic_helper_suspend(drm);
487 if (IS_ERR(hdlcd->state)) {
488 drm_kms_helper_poll_enable(drm);
489 return PTR_ERR(hdlcd->state);
490 }
491
492 return 0;
493}
494
495static int __maybe_unused hdlcd_pm_resume(struct device *dev)
496{
497 struct drm_device *drm = dev_get_drvdata(dev);
498 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
499
500 if (!hdlcd)
501 return 0;
502
503 drm_atomic_helper_resume(drm, hdlcd->state);
504 drm_kms_helper_poll_enable(drm);
505 pm_runtime_set_active(dev);
506
507 return 0;
508}
509
510static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
511
512static struct platform_driver hdlcd_platform_driver = {
513 .probe = hdlcd_probe,
514 .remove = hdlcd_remove,
515 .driver = {
516 .name = "hdlcd",
517 .pm = &hdlcd_pm_ops,
518 .of_match_table = hdlcd_of_match,
519 },
520};
521
522module_platform_driver(hdlcd_platform_driver);
523
524MODULE_AUTHOR("Liviu Dudau");
525MODULE_DESCRIPTION("ARM HDLCD DRM driver");
526MODULE_LICENSE("GPL v2");