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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
4 */
5#ifndef IOATDMA_H
6#define IOATDMA_H
7
8#include <linux/dmaengine.h>
9#include <linux/init.h>
10#include <linux/dmapool.h>
11#include <linux/cache.h>
12#include <linux/pci_ids.h>
13#include <linux/circ_buf.h>
14#include <linux/interrupt.h>
15#include "registers.h"
16#include "hw.h"
17
18#define IOAT_DMA_VERSION "5.00"
19
20#define IOAT_DMA_DCA_ANY_CPU ~0
21
22#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, dma_dev)
23#define to_dev(ioat_chan) (&(ioat_chan)->ioat_dma->pdev->dev)
24#define to_pdev(ioat_chan) ((ioat_chan)->ioat_dma->pdev)
25
26#define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80)
27
28/* ioat hardware assumes at least two sources for raid operations */
29#define src_cnt_to_sw(x) ((x) + 2)
30#define src_cnt_to_hw(x) ((x) - 2)
31#define ndest_to_sw(x) ((x) + 1)
32#define ndest_to_hw(x) ((x) - 1)
33#define src16_cnt_to_sw(x) ((x) + 9)
34#define src16_cnt_to_hw(x) ((x) - 9)
35
36/*
37 * workaround for IOAT ver.3.0 null descriptor issue
38 * (channel returns error when size is 0)
39 */
40#define NULL_DESC_BUFFER_SIZE 1
41
42enum ioat_irq_mode {
43 IOAT_NOIRQ = 0,
44 IOAT_MSIX,
45 IOAT_MSI,
46 IOAT_INTX
47};
48
49/**
50 * struct ioatdma_device - internal representation of a IOAT device
51 * @pdev: PCI-Express device
52 * @reg_base: MMIO register space base address
53 * @completion_pool: DMA buffers for completion ops
54 * @sed_hw_pool: DMA super descriptor pools
55 * @dma_dev: embedded struct dma_device
56 * @version: version of ioatdma device
57 * @msix_entries: irq handlers
58 * @idx: per channel data
59 * @dca: direct cache access context
60 * @irq_mode: interrupt mode (INTX, MSI, MSIX)
61 * @cap: read DMA capabilities register
62 */
63struct ioatdma_device {
64 struct pci_dev *pdev;
65 void __iomem *reg_base;
66 struct dma_pool *completion_pool;
67#define MAX_SED_POOLS 5
68 struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
69 struct dma_device dma_dev;
70 u8 version;
71#define IOAT_MAX_CHANS 4
72 struct msix_entry msix_entries[IOAT_MAX_CHANS];
73 struct ioatdma_chan *idx[IOAT_MAX_CHANS];
74 struct dca_provider *dca;
75 enum ioat_irq_mode irq_mode;
76 u32 cap;
77 int chancnt;
78
79 /* shadow version for CB3.3 chan reset errata workaround */
80 u64 msixtba0;
81 u64 msixdata0;
82 u32 msixpba;
83};
84
85#define IOAT_MAX_ORDER 16
86#define IOAT_MAX_DESCS (1 << IOAT_MAX_ORDER)
87#define IOAT_CHUNK_SIZE (SZ_512K)
88#define IOAT_DESCS_PER_CHUNK (IOAT_CHUNK_SIZE / IOAT_DESC_SZ)
89
90struct ioat_descs {
91 void *virt;
92 dma_addr_t hw;
93};
94
95struct ioatdma_chan {
96 struct dma_chan dma_chan;
97 void __iomem *reg_base;
98 dma_addr_t last_completion;
99 spinlock_t cleanup_lock;
100 unsigned long state;
101 #define IOAT_CHAN_DOWN 0
102 #define IOAT_COMPLETION_ACK 1
103 #define IOAT_RESET_PENDING 2
104 #define IOAT_KOBJ_INIT_FAIL 3
105 #define IOAT_RUN 5
106 #define IOAT_CHAN_ACTIVE 6
107 struct timer_list timer;
108 #define RESET_DELAY msecs_to_jiffies(100)
109 struct ioatdma_device *ioat_dma;
110 dma_addr_t completion_dma;
111 u64 *completion;
112 struct tasklet_struct cleanup_task;
113 struct kobject kobj;
114
115/* ioat v2 / v3 channel attributes
116 * @xfercap_log; log2 of channel max transfer length (for fast division)
117 * @head: allocated index
118 * @issued: hardware notification point
119 * @tail: cleanup index
120 * @dmacount: identical to 'head' except for occasionally resetting to zero
121 * @alloc_order: log2 of the number of allocated descriptors
122 * @produce: number of descriptors to produce at submit time
123 * @ring: software ring buffer implementation of hardware ring
124 * @prep_lock: serializes descriptor preparation (producers)
125 */
126 size_t xfercap_log;
127 u16 head;
128 u16 issued;
129 u16 tail;
130 u16 dmacount;
131 u16 alloc_order;
132 u16 produce;
133 struct ioat_ring_ent **ring;
134 spinlock_t prep_lock;
135 struct ioat_descs descs[IOAT_MAX_DESCS / IOAT_DESCS_PER_CHUNK];
136 int desc_chunks;
137 int intr_coalesce;
138 int prev_intr_coalesce;
139};
140
141struct ioat_sysfs_entry {
142 struct attribute attr;
143 ssize_t (*show)(struct dma_chan *, char *);
144 ssize_t (*store)(struct dma_chan *, const char *, size_t);
145};
146
147/**
148 * struct ioat_sed_ent - wrapper around super extended hardware descriptor
149 * @hw: hardware SED
150 * @dma: dma address for the SED
151 * @parent: point to the dma descriptor that's the parent
152 * @hw_pool: descriptor pool index
153 */
154struct ioat_sed_ent {
155 struct ioat_sed_raw_descriptor *hw;
156 dma_addr_t dma;
157 struct ioat_ring_ent *parent;
158 unsigned int hw_pool;
159};
160
161/**
162 * struct ioat_ring_ent - wrapper around hardware descriptor
163 * @hw: hardware DMA descriptor (for memcpy)
164 * @xor: hardware xor descriptor
165 * @xor_ex: hardware xor extension descriptor
166 * @pq: hardware pq descriptor
167 * @pq_ex: hardware pq extension descriptor
168 * @pqu: hardware pq update descriptor
169 * @raw: hardware raw (un-typed) descriptor
170 * @txd: the generic software descriptor for all engines
171 * @len: total transaction length for unmap
172 * @result: asynchronous result of validate operations
173 * @id: identifier for debug
174 * @sed: pointer to super extended descriptor sw desc
175 */
176
177struct ioat_ring_ent {
178 union {
179 struct ioat_dma_descriptor *hw;
180 struct ioat_xor_descriptor *xor;
181 struct ioat_xor_ext_descriptor *xor_ex;
182 struct ioat_pq_descriptor *pq;
183 struct ioat_pq_ext_descriptor *pq_ex;
184 struct ioat_pq_update_descriptor *pqu;
185 struct ioat_raw_descriptor *raw;
186 };
187 size_t len;
188 struct dma_async_tx_descriptor txd;
189 enum sum_check_flags *result;
190 #ifdef DEBUG
191 int id;
192 #endif
193 struct ioat_sed_ent *sed;
194};
195
196extern const struct sysfs_ops ioat_sysfs_ops;
197extern struct ioat_sysfs_entry ioat_version_attr;
198extern struct ioat_sysfs_entry ioat_cap_attr;
199extern int ioat_pending_level;
200extern struct kobj_type ioat_ktype;
201extern struct kmem_cache *ioat_cache;
202extern struct kmem_cache *ioat_sed_cache;
203
204static inline struct ioatdma_chan *to_ioat_chan(struct dma_chan *c)
205{
206 return container_of(c, struct ioatdma_chan, dma_chan);
207}
208
209/* wrapper around hardware descriptor format + additional software fields */
210#ifdef DEBUG
211#define set_desc_id(desc, i) ((desc)->id = (i))
212#define desc_id(desc) ((desc)->id)
213#else
214#define set_desc_id(desc, i)
215#define desc_id(desc) (0)
216#endif
217
218static inline void
219__dump_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_dma_descriptor *hw,
220 struct dma_async_tx_descriptor *tx, int id)
221{
222 struct device *dev = to_dev(ioat_chan);
223
224 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
225 " ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
226 (unsigned long long) tx->phys,
227 (unsigned long long) hw->next, tx->cookie, tx->flags,
228 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
229}
230
231#define dump_desc_dbg(c, d) \
232 ({ if (d) __dump_desc_dbg(c, d->hw, &d->txd, desc_id(d)); 0; })
233
234static inline struct ioatdma_chan *
235ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index)
236{
237 return ioat_dma->idx[index];
238}
239
240static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan)
241{
242 return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET);
243}
244
245static inline u64 ioat_chansts_to_addr(u64 status)
246{
247 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
248}
249
250static inline u32 ioat_chanerr(struct ioatdma_chan *ioat_chan)
251{
252 return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
253}
254
255static inline void ioat_suspend(struct ioatdma_chan *ioat_chan)
256{
257 u8 ver = ioat_chan->ioat_dma->version;
258
259 writeb(IOAT_CHANCMD_SUSPEND,
260 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
261}
262
263static inline void ioat_reset(struct ioatdma_chan *ioat_chan)
264{
265 u8 ver = ioat_chan->ioat_dma->version;
266
267 writeb(IOAT_CHANCMD_RESET,
268 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
269}
270
271static inline bool ioat_reset_pending(struct ioatdma_chan *ioat_chan)
272{
273 u8 ver = ioat_chan->ioat_dma->version;
274 u8 cmd;
275
276 cmd = readb(ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
277 return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
278}
279
280static inline bool is_ioat_active(unsigned long status)
281{
282 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
283}
284
285static inline bool is_ioat_idle(unsigned long status)
286{
287 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
288}
289
290static inline bool is_ioat_halted(unsigned long status)
291{
292 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
293}
294
295static inline bool is_ioat_suspended(unsigned long status)
296{
297 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
298}
299
300/* channel was fatally programmed */
301static inline bool is_ioat_bug(unsigned long err)
302{
303 return !!err;
304}
305
306
307static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan)
308{
309 return 1 << ioat_chan->alloc_order;
310}
311
312/* count of descriptors in flight with the engine */
313static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan)
314{
315 return CIRC_CNT(ioat_chan->head, ioat_chan->tail,
316 ioat_ring_size(ioat_chan));
317}
318
319/* count of descriptors pending submission to hardware */
320static inline u16 ioat_ring_pending(struct ioatdma_chan *ioat_chan)
321{
322 return CIRC_CNT(ioat_chan->head, ioat_chan->issued,
323 ioat_ring_size(ioat_chan));
324}
325
326static inline u32 ioat_ring_space(struct ioatdma_chan *ioat_chan)
327{
328 return ioat_ring_size(ioat_chan) - ioat_ring_active(ioat_chan);
329}
330
331static inline u16
332ioat_xferlen_to_descs(struct ioatdma_chan *ioat_chan, size_t len)
333{
334 u16 num_descs = len >> ioat_chan->xfercap_log;
335
336 num_descs += !!(len & ((1 << ioat_chan->xfercap_log) - 1));
337 return num_descs;
338}
339
340static inline struct ioat_ring_ent *
341ioat_get_ring_ent(struct ioatdma_chan *ioat_chan, u16 idx)
342{
343 return ioat_chan->ring[idx & (ioat_ring_size(ioat_chan) - 1)];
344}
345
346static inline void
347ioat_set_chainaddr(struct ioatdma_chan *ioat_chan, u64 addr)
348{
349 writel(addr & 0x00000000FFFFFFFF,
350 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
351 writel(addr >> 32,
352 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
353}
354
355/* IOAT Prep functions */
356struct dma_async_tx_descriptor *
357ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
358 dma_addr_t dma_src, size_t len, unsigned long flags);
359struct dma_async_tx_descriptor *
360ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags);
361struct dma_async_tx_descriptor *
362ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
363 unsigned int src_cnt, size_t len, unsigned long flags);
364struct dma_async_tx_descriptor *
365ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
366 unsigned int src_cnt, size_t len,
367 enum sum_check_flags *result, unsigned long flags);
368struct dma_async_tx_descriptor *
369ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
370 unsigned int src_cnt, const unsigned char *scf, size_t len,
371 unsigned long flags);
372struct dma_async_tx_descriptor *
373ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
374 unsigned int src_cnt, const unsigned char *scf, size_t len,
375 enum sum_check_flags *pqres, unsigned long flags);
376struct dma_async_tx_descriptor *
377ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
378 unsigned int src_cnt, size_t len, unsigned long flags);
379struct dma_async_tx_descriptor *
380ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
381 unsigned int src_cnt, size_t len,
382 enum sum_check_flags *result, unsigned long flags);
383
384/* IOAT Operation functions */
385irqreturn_t ioat_dma_do_interrupt(int irq, void *data);
386irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data);
387struct ioat_ring_ent **
388ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags);
389void ioat_start_null_desc(struct ioatdma_chan *ioat_chan);
390void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan);
391int ioat_reset_hw(struct ioatdma_chan *ioat_chan);
392enum dma_status
393ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
394 struct dma_tx_state *txstate);
395void ioat_cleanup_event(struct tasklet_struct *t);
396void ioat_timer_event(struct timer_list *t);
397int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs);
398void ioat_issue_pending(struct dma_chan *chan);
399
400/* IOAT Init functions */
401bool is_bwd_ioat(struct pci_dev *pdev);
402struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
403void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type);
404void ioat_kobject_del(struct ioatdma_device *ioat_dma);
405int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma);
406void ioat_stop(struct ioatdma_chan *ioat_chan);
407#endif /* IOATDMA_H */
1/*
2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called COPYING.
16 */
17#ifndef IOATDMA_H
18#define IOATDMA_H
19
20#include <linux/dmaengine.h>
21#include <linux/init.h>
22#include <linux/dmapool.h>
23#include <linux/cache.h>
24#include <linux/pci_ids.h>
25#include <linux/circ_buf.h>
26#include <linux/interrupt.h>
27#include "registers.h"
28#include "hw.h"
29
30#define IOAT_DMA_VERSION "4.00"
31
32#define IOAT_DMA_DCA_ANY_CPU ~0
33
34#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, dma_dev)
35#define to_dev(ioat_chan) (&(ioat_chan)->ioat_dma->pdev->dev)
36#define to_pdev(ioat_chan) ((ioat_chan)->ioat_dma->pdev)
37
38#define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80)
39
40/* ioat hardware assumes at least two sources for raid operations */
41#define src_cnt_to_sw(x) ((x) + 2)
42#define src_cnt_to_hw(x) ((x) - 2)
43#define ndest_to_sw(x) ((x) + 1)
44#define ndest_to_hw(x) ((x) - 1)
45#define src16_cnt_to_sw(x) ((x) + 9)
46#define src16_cnt_to_hw(x) ((x) - 9)
47
48/*
49 * workaround for IOAT ver.3.0 null descriptor issue
50 * (channel returns error when size is 0)
51 */
52#define NULL_DESC_BUFFER_SIZE 1
53
54enum ioat_irq_mode {
55 IOAT_NOIRQ = 0,
56 IOAT_MSIX,
57 IOAT_MSI,
58 IOAT_INTX
59};
60
61/**
62 * struct ioatdma_device - internal representation of a IOAT device
63 * @pdev: PCI-Express device
64 * @reg_base: MMIO register space base address
65 * @completion_pool: DMA buffers for completion ops
66 * @sed_hw_pool: DMA super descriptor pools
67 * @dma_dev: embedded struct dma_device
68 * @version: version of ioatdma device
69 * @msix_entries: irq handlers
70 * @idx: per channel data
71 * @dca: direct cache access context
72 * @irq_mode: interrupt mode (INTX, MSI, MSIX)
73 * @cap: read DMA capabilities register
74 */
75struct ioatdma_device {
76 struct pci_dev *pdev;
77 void __iomem *reg_base;
78 struct dma_pool *completion_pool;
79#define MAX_SED_POOLS 5
80 struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
81 struct dma_device dma_dev;
82 u8 version;
83#define IOAT_MAX_CHANS 4
84 struct msix_entry msix_entries[IOAT_MAX_CHANS];
85 struct ioatdma_chan *idx[IOAT_MAX_CHANS];
86 struct dca_provider *dca;
87 enum ioat_irq_mode irq_mode;
88 u32 cap;
89
90 /* shadow version for CB3.3 chan reset errata workaround */
91 u64 msixtba0;
92 u64 msixdata0;
93 u32 msixpba;
94};
95
96struct ioat_descs {
97 void *virt;
98 dma_addr_t hw;
99};
100
101struct ioatdma_chan {
102 struct dma_chan dma_chan;
103 void __iomem *reg_base;
104 dma_addr_t last_completion;
105 spinlock_t cleanup_lock;
106 unsigned long state;
107 #define IOAT_CHAN_DOWN 0
108 #define IOAT_COMPLETION_ACK 1
109 #define IOAT_RESET_PENDING 2
110 #define IOAT_KOBJ_INIT_FAIL 3
111 #define IOAT_RUN 5
112 #define IOAT_CHAN_ACTIVE 6
113 struct timer_list timer;
114 #define COMPLETION_TIMEOUT msecs_to_jiffies(100)
115 #define IDLE_TIMEOUT msecs_to_jiffies(2000)
116 #define RESET_DELAY msecs_to_jiffies(100)
117 struct ioatdma_device *ioat_dma;
118 dma_addr_t completion_dma;
119 u64 *completion;
120 struct tasklet_struct cleanup_task;
121 struct kobject kobj;
122
123/* ioat v2 / v3 channel attributes
124 * @xfercap_log; log2 of channel max transfer length (for fast division)
125 * @head: allocated index
126 * @issued: hardware notification point
127 * @tail: cleanup index
128 * @dmacount: identical to 'head' except for occasionally resetting to zero
129 * @alloc_order: log2 of the number of allocated descriptors
130 * @produce: number of descriptors to produce at submit time
131 * @ring: software ring buffer implementation of hardware ring
132 * @prep_lock: serializes descriptor preparation (producers)
133 */
134 size_t xfercap_log;
135 u16 head;
136 u16 issued;
137 u16 tail;
138 u16 dmacount;
139 u16 alloc_order;
140 u16 produce;
141 struct ioat_ring_ent **ring;
142 spinlock_t prep_lock;
143 struct ioat_descs descs[2];
144 int desc_chunks;
145};
146
147struct ioat_sysfs_entry {
148 struct attribute attr;
149 ssize_t (*show)(struct dma_chan *, char *);
150};
151
152/**
153 * struct ioat_sed_ent - wrapper around super extended hardware descriptor
154 * @hw: hardware SED
155 * @dma: dma address for the SED
156 * @parent: point to the dma descriptor that's the parent
157 * @hw_pool: descriptor pool index
158 */
159struct ioat_sed_ent {
160 struct ioat_sed_raw_descriptor *hw;
161 dma_addr_t dma;
162 struct ioat_ring_ent *parent;
163 unsigned int hw_pool;
164};
165
166/**
167 * struct ioat_ring_ent - wrapper around hardware descriptor
168 * @hw: hardware DMA descriptor (for memcpy)
169 * @xor: hardware xor descriptor
170 * @xor_ex: hardware xor extension descriptor
171 * @pq: hardware pq descriptor
172 * @pq_ex: hardware pq extension descriptor
173 * @pqu: hardware pq update descriptor
174 * @raw: hardware raw (un-typed) descriptor
175 * @txd: the generic software descriptor for all engines
176 * @len: total transaction length for unmap
177 * @result: asynchronous result of validate operations
178 * @id: identifier for debug
179 * @sed: pointer to super extended descriptor sw desc
180 */
181
182struct ioat_ring_ent {
183 union {
184 struct ioat_dma_descriptor *hw;
185 struct ioat_xor_descriptor *xor;
186 struct ioat_xor_ext_descriptor *xor_ex;
187 struct ioat_pq_descriptor *pq;
188 struct ioat_pq_ext_descriptor *pq_ex;
189 struct ioat_pq_update_descriptor *pqu;
190 struct ioat_raw_descriptor *raw;
191 };
192 size_t len;
193 struct dma_async_tx_descriptor txd;
194 enum sum_check_flags *result;
195 #ifdef DEBUG
196 int id;
197 #endif
198 struct ioat_sed_ent *sed;
199};
200
201extern const struct sysfs_ops ioat_sysfs_ops;
202extern struct ioat_sysfs_entry ioat_version_attr;
203extern struct ioat_sysfs_entry ioat_cap_attr;
204extern int ioat_pending_level;
205extern int ioat_ring_alloc_order;
206extern struct kobj_type ioat_ktype;
207extern struct kmem_cache *ioat_cache;
208extern int ioat_ring_max_alloc_order;
209extern struct kmem_cache *ioat_sed_cache;
210
211static inline struct ioatdma_chan *to_ioat_chan(struct dma_chan *c)
212{
213 return container_of(c, struct ioatdma_chan, dma_chan);
214}
215
216/* wrapper around hardware descriptor format + additional software fields */
217#ifdef DEBUG
218#define set_desc_id(desc, i) ((desc)->id = (i))
219#define desc_id(desc) ((desc)->id)
220#else
221#define set_desc_id(desc, i)
222#define desc_id(desc) (0)
223#endif
224
225static inline void
226__dump_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_dma_descriptor *hw,
227 struct dma_async_tx_descriptor *tx, int id)
228{
229 struct device *dev = to_dev(ioat_chan);
230
231 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
232 " ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
233 (unsigned long long) tx->phys,
234 (unsigned long long) hw->next, tx->cookie, tx->flags,
235 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
236}
237
238#define dump_desc_dbg(c, d) \
239 ({ if (d) __dump_desc_dbg(c, d->hw, &d->txd, desc_id(d)); 0; })
240
241static inline struct ioatdma_chan *
242ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index)
243{
244 return ioat_dma->idx[index];
245}
246
247static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan)
248{
249 return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET);
250}
251
252static inline u64 ioat_chansts_to_addr(u64 status)
253{
254 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
255}
256
257static inline u32 ioat_chanerr(struct ioatdma_chan *ioat_chan)
258{
259 return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
260}
261
262static inline void ioat_suspend(struct ioatdma_chan *ioat_chan)
263{
264 u8 ver = ioat_chan->ioat_dma->version;
265
266 writeb(IOAT_CHANCMD_SUSPEND,
267 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
268}
269
270static inline void ioat_reset(struct ioatdma_chan *ioat_chan)
271{
272 u8 ver = ioat_chan->ioat_dma->version;
273
274 writeb(IOAT_CHANCMD_RESET,
275 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
276}
277
278static inline bool ioat_reset_pending(struct ioatdma_chan *ioat_chan)
279{
280 u8 ver = ioat_chan->ioat_dma->version;
281 u8 cmd;
282
283 cmd = readb(ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
284 return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
285}
286
287static inline bool is_ioat_active(unsigned long status)
288{
289 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
290}
291
292static inline bool is_ioat_idle(unsigned long status)
293{
294 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
295}
296
297static inline bool is_ioat_halted(unsigned long status)
298{
299 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
300}
301
302static inline bool is_ioat_suspended(unsigned long status)
303{
304 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
305}
306
307/* channel was fatally programmed */
308static inline bool is_ioat_bug(unsigned long err)
309{
310 return !!err;
311}
312
313#define IOAT_MAX_ORDER 16
314#define IOAT_MAX_DESCS 65536
315#define IOAT_DESCS_PER_2M 32768
316
317static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan)
318{
319 return 1 << ioat_chan->alloc_order;
320}
321
322/* count of descriptors in flight with the engine */
323static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan)
324{
325 return CIRC_CNT(ioat_chan->head, ioat_chan->tail,
326 ioat_ring_size(ioat_chan));
327}
328
329/* count of descriptors pending submission to hardware */
330static inline u16 ioat_ring_pending(struct ioatdma_chan *ioat_chan)
331{
332 return CIRC_CNT(ioat_chan->head, ioat_chan->issued,
333 ioat_ring_size(ioat_chan));
334}
335
336static inline u32 ioat_ring_space(struct ioatdma_chan *ioat_chan)
337{
338 return ioat_ring_size(ioat_chan) - ioat_ring_active(ioat_chan);
339}
340
341static inline u16
342ioat_xferlen_to_descs(struct ioatdma_chan *ioat_chan, size_t len)
343{
344 u16 num_descs = len >> ioat_chan->xfercap_log;
345
346 num_descs += !!(len & ((1 << ioat_chan->xfercap_log) - 1));
347 return num_descs;
348}
349
350static inline struct ioat_ring_ent *
351ioat_get_ring_ent(struct ioatdma_chan *ioat_chan, u16 idx)
352{
353 return ioat_chan->ring[idx & (ioat_ring_size(ioat_chan) - 1)];
354}
355
356static inline void
357ioat_set_chainaddr(struct ioatdma_chan *ioat_chan, u64 addr)
358{
359 writel(addr & 0x00000000FFFFFFFF,
360 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
361 writel(addr >> 32,
362 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
363}
364
365/* IOAT Prep functions */
366struct dma_async_tx_descriptor *
367ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
368 dma_addr_t dma_src, size_t len, unsigned long flags);
369struct dma_async_tx_descriptor *
370ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags);
371struct dma_async_tx_descriptor *
372ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
373 unsigned int src_cnt, size_t len, unsigned long flags);
374struct dma_async_tx_descriptor *
375ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
376 unsigned int src_cnt, size_t len,
377 enum sum_check_flags *result, unsigned long flags);
378struct dma_async_tx_descriptor *
379ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
380 unsigned int src_cnt, const unsigned char *scf, size_t len,
381 unsigned long flags);
382struct dma_async_tx_descriptor *
383ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
384 unsigned int src_cnt, const unsigned char *scf, size_t len,
385 enum sum_check_flags *pqres, unsigned long flags);
386struct dma_async_tx_descriptor *
387ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
388 unsigned int src_cnt, size_t len, unsigned long flags);
389struct dma_async_tx_descriptor *
390ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
391 unsigned int src_cnt, size_t len,
392 enum sum_check_flags *result, unsigned long flags);
393
394/* IOAT Operation functions */
395irqreturn_t ioat_dma_do_interrupt(int irq, void *data);
396irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data);
397struct ioat_ring_ent **
398ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags);
399void ioat_start_null_desc(struct ioatdma_chan *ioat_chan);
400void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan);
401int ioat_reset_hw(struct ioatdma_chan *ioat_chan);
402enum dma_status
403ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
404 struct dma_tx_state *txstate);
405void ioat_cleanup_event(unsigned long data);
406void ioat_timer_event(unsigned long data);
407int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs);
408void ioat_issue_pending(struct dma_chan *chan);
409void ioat_timer_event(unsigned long data);
410
411/* IOAT Init functions */
412bool is_bwd_ioat(struct pci_dev *pdev);
413struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
414void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type);
415void ioat_kobject_del(struct ioatdma_device *ioat_dma);
416int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma);
417void ioat_stop(struct ioatdma_chan *ioat_chan);
418#endif /* IOATDMA_H */