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1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright(c) 2020 Intel Corporation. */
3
4#ifndef __CXL_H__
5#define __CXL_H__
6
7#include <linux/libnvdimm.h>
8#include <linux/bitfield.h>
9#include <linux/bitops.h>
10#include <linux/log2.h>
11#include <linux/node.h>
12#include <linux/io.h>
13
14/**
15 * DOC: cxl objects
16 *
17 * The CXL core objects like ports, decoders, and regions are shared
18 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
19 * (port-driver, region-driver, nvdimm object-drivers... etc).
20 */
21
22/* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */
23#define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K
24
25/* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
26#define CXL_CM_OFFSET 0x1000
27#define CXL_CM_CAP_HDR_OFFSET 0x0
28#define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
29#define CM_CAP_HDR_CAP_ID 1
30#define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
31#define CM_CAP_HDR_CAP_VERSION 1
32#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)
33#define CM_CAP_HDR_CACHE_MEM_VERSION 1
34#define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)
35#define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)
36
37#define CXL_CM_CAP_CAP_ID_RAS 0x2
38#define CXL_CM_CAP_CAP_ID_HDM 0x5
39#define CXL_CM_CAP_CAP_HDM_VERSION 1
40
41/* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
42#define CXL_HDM_DECODER_CAP_OFFSET 0x0
43#define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
44#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
45#define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)
46#define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)
47#define CXL_HDM_DECODER_CTRL_OFFSET 0x4
48#define CXL_HDM_DECODER_ENABLE BIT(1)
49#define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)
50#define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14)
51#define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18)
52#define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c)
53#define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20)
54#define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0)
55#define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4)
56#define CXL_HDM_DECODER0_CTRL_LOCK BIT(8)
57#define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9)
58#define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10)
59#define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11)
60#define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12)
61#define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24)
62#define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28)
63#define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i)
64#define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i)
65
66/* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */
67#define CXL_DECODER_MIN_GRANULARITY 256
68#define CXL_DECODER_MAX_ENCODED_IG 6
69
70static inline int cxl_hdm_decoder_count(u32 cap_hdr)
71{
72 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
73
74 return val ? val * 2 : 1;
75}
76
77/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
78static inline int eig_to_granularity(u16 eig, unsigned int *granularity)
79{
80 if (eig > CXL_DECODER_MAX_ENCODED_IG)
81 return -EINVAL;
82 *granularity = CXL_DECODER_MIN_GRANULARITY << eig;
83 return 0;
84}
85
86/* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
87static inline int eiw_to_ways(u8 eiw, unsigned int *ways)
88{
89 switch (eiw) {
90 case 0 ... 4:
91 *ways = 1 << eiw;
92 break;
93 case 8 ... 10:
94 *ways = 3 << (eiw - 8);
95 break;
96 default:
97 return -EINVAL;
98 }
99
100 return 0;
101}
102
103static inline int granularity_to_eig(int granularity, u16 *eig)
104{
105 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY ||
106 !is_power_of_2(granularity))
107 return -EINVAL;
108 *eig = ilog2(granularity) - 8;
109 return 0;
110}
111
112static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
113{
114 if (ways > 16)
115 return -EINVAL;
116 if (is_power_of_2(ways)) {
117 *eiw = ilog2(ways);
118 return 0;
119 }
120 if (ways % 3)
121 return -EINVAL;
122 ways /= 3;
123 if (!is_power_of_2(ways))
124 return -EINVAL;
125 *eiw = ilog2(ways) + 8;
126 return 0;
127}
128
129/* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */
130#define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0
131#define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0))
132#define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4
133#define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0))
134#define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8)
135#define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8
136#define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0))
137#define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC
138#define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0)
139#define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10
140#define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0)
141#define CXL_RAS_CAP_CONTROL_OFFSET 0x14
142#define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0)
143#define CXL_RAS_HEADER_LOG_OFFSET 0x18
144#define CXL_RAS_CAPABILITY_LENGTH 0x58
145#define CXL_HEADERLOG_SIZE SZ_512
146#define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32)
147
148/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
149#define CXLDEV_CAP_ARRAY_OFFSET 0x0
150#define CXLDEV_CAP_ARRAY_CAP_ID 0
151#define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
152#define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
153/* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */
154#define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)
155/* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */
156#define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1
157#define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2
158#define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3
159#define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000
160
161/* CXL 3.0 8.2.8.3.1 Event Status Register */
162#define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00
163#define CXLDEV_EVENT_STATUS_INFO BIT(0)
164#define CXLDEV_EVENT_STATUS_WARN BIT(1)
165#define CXLDEV_EVENT_STATUS_FAIL BIT(2)
166#define CXLDEV_EVENT_STATUS_FATAL BIT(3)
167
168#define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \
169 CXLDEV_EVENT_STATUS_WARN | \
170 CXLDEV_EVENT_STATUS_FAIL | \
171 CXLDEV_EVENT_STATUS_FATAL)
172
173/* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */
174#define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0)
175#define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4)
176
177/* CXL 2.0 8.2.8.4 Mailbox Registers */
178#define CXLDEV_MBOX_CAPS_OFFSET 0x00
179#define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)
180#define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6)
181#define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7)
182#define CXLDEV_MBOX_CTRL_OFFSET 0x04
183#define CXLDEV_MBOX_CTRL_DOORBELL BIT(0)
184#define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2)
185#define CXLDEV_MBOX_CMD_OFFSET 0x08
186#define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
187#define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
188#define CXLDEV_MBOX_STATUS_OFFSET 0x10
189#define CXLDEV_MBOX_STATUS_BG_CMD BIT(0)
190#define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
191#define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18
192#define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
193#define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16)
194#define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32)
195#define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48)
196#define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
197
198/*
199 * Using struct_group() allows for per register-block-type helper routines,
200 * without requiring block-type agnostic code to include the prefix.
201 */
202struct cxl_regs {
203 /*
204 * Common set of CXL Component register block base pointers
205 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
206 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure
207 */
208 struct_group_tagged(cxl_component_regs, component,
209 void __iomem *hdm_decoder;
210 void __iomem *ras;
211 );
212 /*
213 * Common set of CXL Device register block base pointers
214 * @status: CXL 2.0 8.2.8.3 Device Status Registers
215 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
216 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
217 */
218 struct_group_tagged(cxl_device_regs, device_regs,
219 void __iomem *status, *mbox, *memdev;
220 );
221
222 struct_group_tagged(cxl_pmu_regs, pmu_regs,
223 void __iomem *pmu;
224 );
225
226 /*
227 * RCH downstream port specific RAS register
228 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB
229 */
230 struct_group_tagged(cxl_rch_regs, rch_regs,
231 void __iomem *dport_aer;
232 );
233};
234
235struct cxl_reg_map {
236 bool valid;
237 int id;
238 unsigned long offset;
239 unsigned long size;
240};
241
242struct cxl_component_reg_map {
243 struct cxl_reg_map hdm_decoder;
244 struct cxl_reg_map ras;
245};
246
247struct cxl_device_reg_map {
248 struct cxl_reg_map status;
249 struct cxl_reg_map mbox;
250 struct cxl_reg_map memdev;
251};
252
253struct cxl_pmu_reg_map {
254 struct cxl_reg_map pmu;
255};
256
257/**
258 * struct cxl_register_map - DVSEC harvested register block mapping parameters
259 * @host: device for devm operations and logging
260 * @base: virtual base of the register-block-BAR + @block_offset
261 * @resource: physical resource base of the register block
262 * @max_size: maximum mapping size to perform register search
263 * @reg_type: see enum cxl_regloc_type
264 * @component_map: cxl_reg_map for component registers
265 * @device_map: cxl_reg_maps for device registers
266 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units
267 */
268struct cxl_register_map {
269 struct device *host;
270 void __iomem *base;
271 resource_size_t resource;
272 resource_size_t max_size;
273 u8 reg_type;
274 union {
275 struct cxl_component_reg_map component_map;
276 struct cxl_device_reg_map device_map;
277 struct cxl_pmu_reg_map pmu_map;
278 };
279};
280
281void cxl_probe_component_regs(struct device *dev, void __iomem *base,
282 struct cxl_component_reg_map *map);
283void cxl_probe_device_regs(struct device *dev, void __iomem *base,
284 struct cxl_device_reg_map *map);
285int cxl_map_component_regs(const struct cxl_register_map *map,
286 struct cxl_component_regs *regs,
287 unsigned long map_mask);
288int cxl_map_device_regs(const struct cxl_register_map *map,
289 struct cxl_device_regs *regs);
290int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs);
291
292enum cxl_regloc_type;
293int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
294int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type,
295 struct cxl_register_map *map, int index);
296int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
297 struct cxl_register_map *map);
298int cxl_setup_regs(struct cxl_register_map *map);
299struct cxl_dport;
300resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
301 struct cxl_dport *dport);
302
303#define CXL_RESOURCE_NONE ((resource_size_t) -1)
304#define CXL_TARGET_STRLEN 20
305
306/*
307 * cxl_decoder flags that define the type of memory / devices this
308 * decoder supports as well as configuration lock status See "CXL 2.0
309 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details.
310 * Additionally indicate whether decoder settings were autodetected,
311 * user customized.
312 */
313#define CXL_DECODER_F_RAM BIT(0)
314#define CXL_DECODER_F_PMEM BIT(1)
315#define CXL_DECODER_F_TYPE2 BIT(2)
316#define CXL_DECODER_F_TYPE3 BIT(3)
317#define CXL_DECODER_F_LOCK BIT(4)
318#define CXL_DECODER_F_ENABLE BIT(5)
319#define CXL_DECODER_F_MASK GENMASK(5, 0)
320
321enum cxl_decoder_type {
322 CXL_DECODER_DEVMEM = 2,
323 CXL_DECODER_HOSTONLYMEM = 3,
324};
325
326/*
327 * Current specification goes up to 8, double that seems a reasonable
328 * software max for the foreseeable future
329 */
330#define CXL_DECODER_MAX_INTERLEAVE 16
331
332#define CXL_QOS_CLASS_INVALID -1
333
334/**
335 * struct cxl_decoder - Common CXL HDM Decoder Attributes
336 * @dev: this decoder's device
337 * @id: kernel device name id
338 * @hpa_range: Host physical address range mapped by this decoder
339 * @interleave_ways: number of cxl_dports in this decode
340 * @interleave_granularity: data stride per dport
341 * @target_type: accelerator vs expander (type2 vs type3) selector
342 * @region: currently assigned region for this decoder
343 * @flags: memory type capabilities and locking
344 * @commit: device/decoder-type specific callback to commit settings to hw
345 * @reset: device/decoder-type specific callback to reset hw settings
346*/
347struct cxl_decoder {
348 struct device dev;
349 int id;
350 struct range hpa_range;
351 int interleave_ways;
352 int interleave_granularity;
353 enum cxl_decoder_type target_type;
354 struct cxl_region *region;
355 unsigned long flags;
356 int (*commit)(struct cxl_decoder *cxld);
357 int (*reset)(struct cxl_decoder *cxld);
358};
359
360/*
361 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions
362 * while cxld_unregister() is running
363 */
364enum cxl_decoder_mode {
365 CXL_DECODER_NONE,
366 CXL_DECODER_RAM,
367 CXL_DECODER_PMEM,
368 CXL_DECODER_MIXED,
369 CXL_DECODER_DEAD,
370};
371
372static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode)
373{
374 static const char * const names[] = {
375 [CXL_DECODER_NONE] = "none",
376 [CXL_DECODER_RAM] = "ram",
377 [CXL_DECODER_PMEM] = "pmem",
378 [CXL_DECODER_MIXED] = "mixed",
379 };
380
381 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED)
382 return names[mode];
383 return "mixed";
384}
385
386/*
387 * Track whether this decoder is reserved for region autodiscovery, or
388 * free for userspace provisioning.
389 */
390enum cxl_decoder_state {
391 CXL_DECODER_STATE_MANUAL,
392 CXL_DECODER_STATE_AUTO,
393};
394
395/**
396 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder
397 * @cxld: base cxl_decoder_object
398 * @dpa_res: actively claimed DPA span of this decoder
399 * @skip: offset into @dpa_res where @cxld.hpa_range maps
400 * @mode: which memory type / access-mode-partition this decoder targets
401 * @state: autodiscovery state
402 * @pos: interleave position in @cxld.region
403 */
404struct cxl_endpoint_decoder {
405 struct cxl_decoder cxld;
406 struct resource *dpa_res;
407 resource_size_t skip;
408 enum cxl_decoder_mode mode;
409 enum cxl_decoder_state state;
410 int pos;
411};
412
413/**
414 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder
415 * @cxld: base cxl_decoder object
416 * @nr_targets: number of elements in @target
417 * @target: active ordered target list in current decoder configuration
418 *
419 * The 'switch' decoder type represents the decoder instances of cxl_port's that
420 * route from the root of a CXL memory decode topology to the endpoints. They
421 * come in two flavors, root-level decoders, statically defined by platform
422 * firmware, and mid-level decoders, where interleave-granularity,
423 * interleave-width, and the target list are mutable.
424 */
425struct cxl_switch_decoder {
426 struct cxl_decoder cxld;
427 int nr_targets;
428 struct cxl_dport *target[];
429};
430
431struct cxl_root_decoder;
432typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd,
433 int pos);
434
435/**
436 * struct cxl_root_decoder - Static platform CXL address decoder
437 * @res: host / parent resource for region allocations
438 * @region_id: region id for next region provisioning event
439 * @calc_hb: which host bridge covers the n'th position by granularity
440 * @platform_data: platform specific configuration data
441 * @range_lock: sync region autodiscovery by address range
442 * @qos_class: QoS performance class cookie
443 * @cxlsd: base cxl switch decoder
444 */
445struct cxl_root_decoder {
446 struct resource *res;
447 atomic_t region_id;
448 cxl_calc_hb_fn calc_hb;
449 void *platform_data;
450 struct mutex range_lock;
451 int qos_class;
452 struct cxl_switch_decoder cxlsd;
453};
454
455/*
456 * enum cxl_config_state - State machine for region configuration
457 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely
458 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more
459 * changes to interleave_ways or interleave_granularity
460 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now
461 * active
462 * @CXL_CONFIG_RESET_PENDING: see commit_store()
463 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware
464 */
465enum cxl_config_state {
466 CXL_CONFIG_IDLE,
467 CXL_CONFIG_INTERLEAVE_ACTIVE,
468 CXL_CONFIG_ACTIVE,
469 CXL_CONFIG_RESET_PENDING,
470 CXL_CONFIG_COMMIT,
471};
472
473/**
474 * struct cxl_region_params - region settings
475 * @state: allow the driver to lockdown further parameter changes
476 * @uuid: unique id for persistent regions
477 * @interleave_ways: number of endpoints in the region
478 * @interleave_granularity: capacity each endpoint contributes to a stripe
479 * @res: allocated iomem capacity for this region
480 * @targets: active ordered targets in current decoder configuration
481 * @nr_targets: number of targets
482 *
483 * State transitions are protected by the cxl_region_rwsem
484 */
485struct cxl_region_params {
486 enum cxl_config_state state;
487 uuid_t uuid;
488 int interleave_ways;
489 int interleave_granularity;
490 struct resource *res;
491 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE];
492 int nr_targets;
493};
494
495/*
496 * Indicate whether this region has been assembled by autodetection or
497 * userspace assembly. Prevent endpoint decoders outside of automatic
498 * detection from being added to the region.
499 */
500#define CXL_REGION_F_AUTO 0
501
502/*
503 * Require that a committed region successfully complete a teardown once
504 * any of its associated decoders have been torn down. This maintains
505 * the commit state for the region since there are committed decoders,
506 * but blocks cxl_region_probe().
507 */
508#define CXL_REGION_F_NEEDS_RESET 1
509
510/**
511 * struct cxl_region - CXL region
512 * @dev: This region's device
513 * @id: This region's id. Id is globally unique across all regions
514 * @mode: Endpoint decoder allocation / access mode
515 * @type: Endpoint decoder target type
516 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown
517 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge
518 * @flags: Region state flags
519 * @params: active + config params for the region
520 */
521struct cxl_region {
522 struct device dev;
523 int id;
524 enum cxl_decoder_mode mode;
525 enum cxl_decoder_type type;
526 struct cxl_nvdimm_bridge *cxl_nvb;
527 struct cxl_pmem_region *cxlr_pmem;
528 unsigned long flags;
529 struct cxl_region_params params;
530};
531
532struct cxl_nvdimm_bridge {
533 int id;
534 struct device dev;
535 struct cxl_port *port;
536 struct nvdimm_bus *nvdimm_bus;
537 struct nvdimm_bus_descriptor nd_desc;
538};
539
540#define CXL_DEV_ID_LEN 19
541
542struct cxl_nvdimm {
543 struct device dev;
544 struct cxl_memdev *cxlmd;
545 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */
546};
547
548struct cxl_pmem_region_mapping {
549 struct cxl_memdev *cxlmd;
550 struct cxl_nvdimm *cxl_nvd;
551 u64 start;
552 u64 size;
553 int position;
554};
555
556struct cxl_pmem_region {
557 struct device dev;
558 struct cxl_region *cxlr;
559 struct nd_region *nd_region;
560 struct range hpa_range;
561 int nr_mappings;
562 struct cxl_pmem_region_mapping mapping[];
563};
564
565struct cxl_dax_region {
566 struct device dev;
567 struct cxl_region *cxlr;
568 struct range hpa_range;
569};
570
571/**
572 * struct cxl_port - logical collection of upstream port devices and
573 * downstream port devices to construct a CXL memory
574 * decode hierarchy.
575 * @dev: this port's device
576 * @uport_dev: PCI or platform device implementing the upstream port capability
577 * @host_bridge: Shortcut to the platform attach point for this port
578 * @id: id for port device-name
579 * @dports: cxl_dport instances referenced by decoders
580 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port
581 * @regions: cxl_region_ref instances, regions mapped by this port
582 * @parent_dport: dport that points to this port in the parent
583 * @decoder_ida: allocator for decoder ids
584 * @reg_map: component and ras register mapping parameters
585 * @nr_dports: number of entries in @dports
586 * @hdm_end: track last allocated HDM decoder instance for allocation ordering
587 * @commit_end: cursor to track highest committed decoder for commit ordering
588 * @dead: last ep has been removed, force port re-creation
589 * @depth: How deep this port is relative to the root. depth 0 is the root.
590 * @cdat: Cached CDAT data
591 * @cdat_available: Should a CDAT attribute be available in sysfs
592 * @pci_latency: Upstream latency in picoseconds
593 */
594struct cxl_port {
595 struct device dev;
596 struct device *uport_dev;
597 struct device *host_bridge;
598 int id;
599 struct xarray dports;
600 struct xarray endpoints;
601 struct xarray regions;
602 struct cxl_dport *parent_dport;
603 struct ida decoder_ida;
604 struct cxl_register_map reg_map;
605 int nr_dports;
606 int hdm_end;
607 int commit_end;
608 bool dead;
609 unsigned int depth;
610 struct cxl_cdat {
611 void *table;
612 size_t length;
613 } cdat;
614 bool cdat_available;
615 long pci_latency;
616};
617
618/**
619 * struct cxl_root - logical collection of root cxl_port items
620 *
621 * @port: cxl_port member
622 * @ops: cxl root operations
623 */
624struct cxl_root {
625 struct cxl_port port;
626 const struct cxl_root_ops *ops;
627};
628
629static inline struct cxl_root *
630to_cxl_root(const struct cxl_port *port)
631{
632 return container_of(port, struct cxl_root, port);
633}
634
635struct cxl_root_ops {
636 int (*qos_class)(struct cxl_root *cxl_root,
637 struct access_coordinate *coord, int entries,
638 int *qos_class);
639};
640
641static inline struct cxl_dport *
642cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
643{
644 return xa_load(&port->dports, (unsigned long)dport_dev);
645}
646
647struct cxl_rcrb_info {
648 resource_size_t base;
649 u16 aer_cap;
650};
651
652/**
653 * struct cxl_dport - CXL downstream port
654 * @dport_dev: PCI bridge or firmware device representing the downstream link
655 * @reg_map: component and ras register mapping parameters
656 * @port_id: unique hardware identifier for dport in decoder target list
657 * @rcrb: Data about the Root Complex Register Block layout
658 * @rch: Indicate whether this dport was enumerated in RCH or VH mode
659 * @port: reference to cxl_port that contains this downstream port
660 * @regs: Dport parsed register blocks
661 * @sw_coord: access coordinates (performance) for switch from CDAT
662 * @hb_coord: access coordinates (performance) from ACPI generic port (host bridge)
663 * @link_latency: calculated PCIe downstream latency
664 */
665struct cxl_dport {
666 struct device *dport_dev;
667 struct cxl_register_map reg_map;
668 int port_id;
669 struct cxl_rcrb_info rcrb;
670 bool rch;
671 struct cxl_port *port;
672 struct cxl_regs regs;
673 struct access_coordinate sw_coord;
674 struct access_coordinate hb_coord;
675 long link_latency;
676};
677
678/**
679 * struct cxl_ep - track an endpoint's interest in a port
680 * @ep: device that hosts a generic CXL endpoint (expander or accelerator)
681 * @dport: which dport routes to this endpoint on @port
682 * @next: cxl switch port across the link attached to @dport NULL if
683 * attached to an endpoint
684 */
685struct cxl_ep {
686 struct device *ep;
687 struct cxl_dport *dport;
688 struct cxl_port *next;
689};
690
691/**
692 * struct cxl_region_ref - track a region's interest in a port
693 * @port: point in topology to install this reference
694 * @decoder: decoder assigned for @region in @port
695 * @region: region for this reference
696 * @endpoints: cxl_ep references for region members beneath @port
697 * @nr_targets_set: track how many targets have been programmed during setup
698 * @nr_eps: number of endpoints beneath @port
699 * @nr_targets: number of distinct targets needed to reach @nr_eps
700 */
701struct cxl_region_ref {
702 struct cxl_port *port;
703 struct cxl_decoder *decoder;
704 struct cxl_region *region;
705 struct xarray endpoints;
706 int nr_targets_set;
707 int nr_eps;
708 int nr_targets;
709};
710
711/*
712 * The platform firmware device hosting the root is also the top of the
713 * CXL port topology. All other CXL ports have another CXL port as their
714 * parent and their ->uport_dev / host device is out-of-line of the port
715 * ancestry.
716 */
717static inline bool is_cxl_root(struct cxl_port *port)
718{
719 return port->uport_dev == port->dev.parent;
720}
721
722int cxl_num_decoders_committed(struct cxl_port *port);
723bool is_cxl_port(const struct device *dev);
724struct cxl_port *to_cxl_port(const struct device *dev);
725struct pci_bus;
726int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev,
727 struct pci_bus *bus);
728struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
729struct cxl_port *devm_cxl_add_port(struct device *host,
730 struct device *uport_dev,
731 resource_size_t component_reg_phys,
732 struct cxl_dport *parent_dport);
733struct cxl_root *devm_cxl_add_root(struct device *host,
734 const struct cxl_root_ops *ops);
735struct cxl_root *find_cxl_root(struct cxl_port *port);
736void put_cxl_root(struct cxl_root *cxl_root);
737DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T))
738
739int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
740void cxl_bus_rescan(void);
741void cxl_bus_drain(void);
742struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev,
743 struct cxl_dport **dport);
744struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
745 struct cxl_dport **dport);
746bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd);
747
748struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
749 struct device *dport, int port_id,
750 resource_size_t component_reg_phys);
751struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
752 struct device *dport_dev, int port_id,
753 resource_size_t rcrb);
754
755#ifdef CONFIG_PCIEAER_CXL
756void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport);
757#else
758static inline void cxl_setup_parent_dport(struct device *host,
759 struct cxl_dport *dport) { }
760#endif
761
762struct cxl_decoder *to_cxl_decoder(struct device *dev);
763struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
764struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
765struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev);
766bool is_root_decoder(struct device *dev);
767bool is_switch_decoder(struct device *dev);
768bool is_endpoint_decoder(struct device *dev);
769struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
770 unsigned int nr_targets,
771 cxl_calc_hb_fn calc_hb);
772struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos);
773struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
774 unsigned int nr_targets);
775int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
776struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
777int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
778int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
779int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint);
780
781/**
782 * struct cxl_endpoint_dvsec_info - Cached DVSEC info
783 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time
784 * @ranges: Number of active HDM ranges this device uses.
785 * @port: endpoint port associated with this info instance
786 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
787 */
788struct cxl_endpoint_dvsec_info {
789 bool mem_enabled;
790 int ranges;
791 struct cxl_port *port;
792 struct range dvsec_range[2];
793};
794
795struct cxl_hdm;
796struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
797 struct cxl_endpoint_dvsec_info *info);
798int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm,
799 struct cxl_endpoint_dvsec_info *info);
800int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
801int cxl_dvsec_rr_decode(struct device *dev, int dvsec,
802 struct cxl_endpoint_dvsec_info *info);
803
804bool is_cxl_region(struct device *dev);
805
806extern struct bus_type cxl_bus_type;
807
808struct cxl_driver {
809 const char *name;
810 int (*probe)(struct device *dev);
811 void (*remove)(struct device *dev);
812 struct device_driver drv;
813 int id;
814};
815
816static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv)
817{
818 return container_of(drv, struct cxl_driver, drv);
819}
820
821int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner,
822 const char *modname);
823#define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME)
824void cxl_driver_unregister(struct cxl_driver *cxl_drv);
825
826#define module_cxl_driver(__cxl_driver) \
827 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister)
828
829#define CXL_DEVICE_NVDIMM_BRIDGE 1
830#define CXL_DEVICE_NVDIMM 2
831#define CXL_DEVICE_PORT 3
832#define CXL_DEVICE_ROOT 4
833#define CXL_DEVICE_MEMORY_EXPANDER 5
834#define CXL_DEVICE_REGION 6
835#define CXL_DEVICE_PMEM_REGION 7
836#define CXL_DEVICE_DAX_REGION 8
837#define CXL_DEVICE_PMU 9
838
839#define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
840#define CXL_MODALIAS_FMT "cxl:t%d"
841
842struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev);
843struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
844 struct cxl_port *port);
845struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
846bool is_cxl_nvdimm(struct device *dev);
847bool is_cxl_nvdimm_bridge(struct device *dev);
848int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd);
849struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd);
850
851#ifdef CONFIG_CXL_REGION
852bool is_cxl_pmem_region(struct device *dev);
853struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
854int cxl_add_to_region(struct cxl_port *root,
855 struct cxl_endpoint_decoder *cxled);
856struct cxl_dax_region *to_cxl_dax_region(struct device *dev);
857#else
858static inline bool is_cxl_pmem_region(struct device *dev)
859{
860 return false;
861}
862static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
863{
864 return NULL;
865}
866static inline int cxl_add_to_region(struct cxl_port *root,
867 struct cxl_endpoint_decoder *cxled)
868{
869 return 0;
870}
871static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev)
872{
873 return NULL;
874}
875#endif
876
877void cxl_endpoint_parse_cdat(struct cxl_port *port);
878void cxl_switch_parse_cdat(struct cxl_port *port);
879
880int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
881 struct access_coordinate *coord);
882
883void cxl_memdev_update_perf(struct cxl_memdev *cxlmd);
884
885/*
886 * Unit test builds overrides this to __weak, find the 'strong' version
887 * of these symbols in tools/testing/cxl/.
888 */
889#ifndef __mock
890#define __mock static
891#endif
892
893#endif /* __CXL_H__ */