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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SHA-256 routines supporting the Power 7+ Nest Accelerators driver
4 *
5 * Copyright (C) 2011-2012 International Business Machines Inc.
6 *
7 * Author: Kent Yoder <yoder1@us.ibm.com>
8 */
9
10#include <crypto/internal/hash.h>
11#include <crypto/sha2.h>
12#include <linux/module.h>
13#include <asm/vio.h>
14#include <asm/byteorder.h>
15
16#include "nx_csbcpb.h"
17#include "nx.h"
18
19struct sha256_state_be {
20 __be32 state[SHA256_DIGEST_SIZE / 4];
21 u64 count;
22 u8 buf[SHA256_BLOCK_SIZE];
23};
24
25static int nx_crypto_ctx_sha256_init(struct crypto_tfm *tfm)
26{
27 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
28 int err;
29
30 err = nx_crypto_ctx_sha_init(tfm);
31 if (err)
32 return err;
33
34 nx_ctx_init(nx_ctx, HCOP_FC_SHA);
35
36 nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA256];
37
38 NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA256);
39
40 return 0;
41}
42
43static int nx_sha256_init(struct shash_desc *desc) {
44 struct sha256_state_be *sctx = shash_desc_ctx(desc);
45
46 memset(sctx, 0, sizeof *sctx);
47
48 sctx->state[0] = __cpu_to_be32(SHA256_H0);
49 sctx->state[1] = __cpu_to_be32(SHA256_H1);
50 sctx->state[2] = __cpu_to_be32(SHA256_H2);
51 sctx->state[3] = __cpu_to_be32(SHA256_H3);
52 sctx->state[4] = __cpu_to_be32(SHA256_H4);
53 sctx->state[5] = __cpu_to_be32(SHA256_H5);
54 sctx->state[6] = __cpu_to_be32(SHA256_H6);
55 sctx->state[7] = __cpu_to_be32(SHA256_H7);
56 sctx->count = 0;
57
58 return 0;
59}
60
61static int nx_sha256_update(struct shash_desc *desc, const u8 *data,
62 unsigned int len)
63{
64 struct sha256_state_be *sctx = shash_desc_ctx(desc);
65 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
66 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
67 struct nx_sg *out_sg;
68 u64 to_process = 0, leftover, total;
69 unsigned long irq_flags;
70 int rc = 0;
71 int data_len;
72 u32 max_sg_len;
73 u64 buf_len = (sctx->count % SHA256_BLOCK_SIZE);
74
75 spin_lock_irqsave(&nx_ctx->lock, irq_flags);
76
77 /* 2 cases for total data len:
78 * 1: < SHA256_BLOCK_SIZE: copy into state, return 0
79 * 2: >= SHA256_BLOCK_SIZE: process X blocks, copy in leftover
80 */
81 total = (sctx->count % SHA256_BLOCK_SIZE) + len;
82 if (total < SHA256_BLOCK_SIZE) {
83 memcpy(sctx->buf + buf_len, data, len);
84 sctx->count += len;
85 goto out;
86 }
87
88 memcpy(csbcpb->cpb.sha256.message_digest, sctx->state, SHA256_DIGEST_SIZE);
89 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
90 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
91
92 max_sg_len = min_t(u64, nx_ctx->ap->sglen,
93 nx_driver.of.max_sg_len/sizeof(struct nx_sg));
94 max_sg_len = min_t(u64, max_sg_len,
95 nx_ctx->ap->databytelen/NX_PAGE_SIZE);
96
97 data_len = SHA256_DIGEST_SIZE;
98 out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
99 &data_len, max_sg_len);
100 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
101
102 if (data_len != SHA256_DIGEST_SIZE) {
103 rc = -EINVAL;
104 goto out;
105 }
106
107 do {
108 int used_sgs = 0;
109 struct nx_sg *in_sg = nx_ctx->in_sg;
110
111 if (buf_len) {
112 data_len = buf_len;
113 in_sg = nx_build_sg_list(in_sg,
114 (u8 *) sctx->buf,
115 &data_len,
116 max_sg_len);
117
118 if (data_len != buf_len) {
119 rc = -EINVAL;
120 goto out;
121 }
122 used_sgs = in_sg - nx_ctx->in_sg;
123 }
124
125 /* to_process: SHA256_BLOCK_SIZE aligned chunk to be
126 * processed in this iteration. This value is restricted
127 * by sg list limits and number of sgs we already used
128 * for leftover data. (see above)
129 * In ideal case, we could allow NX_PAGE_SIZE * max_sg_len,
130 * but because data may not be aligned, we need to account
131 * for that too. */
132 to_process = min_t(u64, total,
133 (max_sg_len - 1 - used_sgs) * NX_PAGE_SIZE);
134 to_process = to_process & ~(SHA256_BLOCK_SIZE - 1);
135
136 data_len = to_process - buf_len;
137 in_sg = nx_build_sg_list(in_sg, (u8 *) data,
138 &data_len, max_sg_len);
139
140 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
141
142 to_process = data_len + buf_len;
143 leftover = total - to_process;
144
145 /*
146 * we've hit the nx chip previously and we're updating
147 * again, so copy over the partial digest.
148 */
149 memcpy(csbcpb->cpb.sha256.input_partial_digest,
150 csbcpb->cpb.sha256.message_digest,
151 SHA256_DIGEST_SIZE);
152
153 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
154 rc = -EINVAL;
155 goto out;
156 }
157
158 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0);
159 if (rc)
160 goto out;
161
162 atomic_inc(&(nx_ctx->stats->sha256_ops));
163
164 total -= to_process;
165 data += to_process - buf_len;
166 buf_len = 0;
167
168 } while (leftover >= SHA256_BLOCK_SIZE);
169
170 /* copy the leftover back into the state struct */
171 if (leftover)
172 memcpy(sctx->buf, data, leftover);
173
174 sctx->count += len;
175 memcpy(sctx->state, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
176out:
177 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
178 return rc;
179}
180
181static int nx_sha256_final(struct shash_desc *desc, u8 *out)
182{
183 struct sha256_state_be *sctx = shash_desc_ctx(desc);
184 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
185 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
186 struct nx_sg *in_sg, *out_sg;
187 unsigned long irq_flags;
188 u32 max_sg_len;
189 int rc = 0;
190 int len;
191
192 spin_lock_irqsave(&nx_ctx->lock, irq_flags);
193
194 max_sg_len = min_t(u64, nx_ctx->ap->sglen,
195 nx_driver.of.max_sg_len/sizeof(struct nx_sg));
196 max_sg_len = min_t(u64, max_sg_len,
197 nx_ctx->ap->databytelen/NX_PAGE_SIZE);
198
199 /* final is represented by continuing the operation and indicating that
200 * this is not an intermediate operation */
201 if (sctx->count >= SHA256_BLOCK_SIZE) {
202 /* we've hit the nx chip previously, now we're finalizing,
203 * so copy over the partial digest */
204 memcpy(csbcpb->cpb.sha256.input_partial_digest, sctx->state, SHA256_DIGEST_SIZE);
205 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
206 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
207 } else {
208 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
209 NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
210 }
211
212 csbcpb->cpb.sha256.message_bit_length = (u64) (sctx->count * 8);
213
214 len = sctx->count & (SHA256_BLOCK_SIZE - 1);
215 in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *) sctx->buf,
216 &len, max_sg_len);
217
218 if (len != (sctx->count & (SHA256_BLOCK_SIZE - 1))) {
219 rc = -EINVAL;
220 goto out;
221 }
222
223 len = SHA256_DIGEST_SIZE;
224 out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len, max_sg_len);
225
226 if (len != SHA256_DIGEST_SIZE) {
227 rc = -EINVAL;
228 goto out;
229 }
230
231 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
232 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
233 if (!nx_ctx->op.outlen) {
234 rc = -EINVAL;
235 goto out;
236 }
237
238 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0);
239 if (rc)
240 goto out;
241
242 atomic_inc(&(nx_ctx->stats->sha256_ops));
243
244 atomic64_add(sctx->count, &(nx_ctx->stats->sha256_bytes));
245 memcpy(out, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
246out:
247 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
248 return rc;
249}
250
251static int nx_sha256_export(struct shash_desc *desc, void *out)
252{
253 struct sha256_state_be *sctx = shash_desc_ctx(desc);
254
255 memcpy(out, sctx, sizeof(*sctx));
256
257 return 0;
258}
259
260static int nx_sha256_import(struct shash_desc *desc, const void *in)
261{
262 struct sha256_state_be *sctx = shash_desc_ctx(desc);
263
264 memcpy(sctx, in, sizeof(*sctx));
265
266 return 0;
267}
268
269struct shash_alg nx_shash_sha256_alg = {
270 .digestsize = SHA256_DIGEST_SIZE,
271 .init = nx_sha256_init,
272 .update = nx_sha256_update,
273 .final = nx_sha256_final,
274 .export = nx_sha256_export,
275 .import = nx_sha256_import,
276 .descsize = sizeof(struct sha256_state_be),
277 .statesize = sizeof(struct sha256_state_be),
278 .base = {
279 .cra_name = "sha256",
280 .cra_driver_name = "sha256-nx",
281 .cra_priority = 300,
282 .cra_blocksize = SHA256_BLOCK_SIZE,
283 .cra_module = THIS_MODULE,
284 .cra_ctxsize = sizeof(struct nx_crypto_ctx),
285 .cra_init = nx_crypto_ctx_sha256_init,
286 .cra_exit = nx_crypto_ctx_exit,
287 }
288};
1/**
2 * SHA-256 routines supporting the Power 7+ Nest Accelerators driver
3 *
4 * Copyright (C) 2011-2012 International Business Machines Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 only.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Author: Kent Yoder <yoder1@us.ibm.com>
20 */
21
22#include <crypto/internal/hash.h>
23#include <crypto/sha.h>
24#include <linux/module.h>
25#include <asm/vio.h>
26#include <asm/byteorder.h>
27
28#include "nx_csbcpb.h"
29#include "nx.h"
30
31
32static int nx_crypto_ctx_sha256_init(struct crypto_tfm *tfm)
33{
34 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
35 int err;
36
37 err = nx_crypto_ctx_sha_init(tfm);
38 if (err)
39 return err;
40
41 nx_ctx_init(nx_ctx, HCOP_FC_SHA);
42
43 nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA256];
44
45 NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA256);
46
47 return 0;
48}
49
50static int nx_sha256_init(struct shash_desc *desc) {
51 struct sha256_state *sctx = shash_desc_ctx(desc);
52
53 memset(sctx, 0, sizeof *sctx);
54
55 sctx->state[0] = __cpu_to_be32(SHA256_H0);
56 sctx->state[1] = __cpu_to_be32(SHA256_H1);
57 sctx->state[2] = __cpu_to_be32(SHA256_H2);
58 sctx->state[3] = __cpu_to_be32(SHA256_H3);
59 sctx->state[4] = __cpu_to_be32(SHA256_H4);
60 sctx->state[5] = __cpu_to_be32(SHA256_H5);
61 sctx->state[6] = __cpu_to_be32(SHA256_H6);
62 sctx->state[7] = __cpu_to_be32(SHA256_H7);
63 sctx->count = 0;
64
65 return 0;
66}
67
68static int nx_sha256_update(struct shash_desc *desc, const u8 *data,
69 unsigned int len)
70{
71 struct sha256_state *sctx = shash_desc_ctx(desc);
72 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
73 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
74 struct nx_sg *out_sg;
75 u64 to_process = 0, leftover, total;
76 unsigned long irq_flags;
77 int rc = 0;
78 int data_len;
79 u32 max_sg_len;
80 u64 buf_len = (sctx->count % SHA256_BLOCK_SIZE);
81
82 spin_lock_irqsave(&nx_ctx->lock, irq_flags);
83
84 /* 2 cases for total data len:
85 * 1: < SHA256_BLOCK_SIZE: copy into state, return 0
86 * 2: >= SHA256_BLOCK_SIZE: process X blocks, copy in leftover
87 */
88 total = (sctx->count % SHA256_BLOCK_SIZE) + len;
89 if (total < SHA256_BLOCK_SIZE) {
90 memcpy(sctx->buf + buf_len, data, len);
91 sctx->count += len;
92 goto out;
93 }
94
95 memcpy(csbcpb->cpb.sha256.message_digest, sctx->state, SHA256_DIGEST_SIZE);
96 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
97 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
98
99 max_sg_len = min_t(u64, nx_ctx->ap->sglen,
100 nx_driver.of.max_sg_len/sizeof(struct nx_sg));
101 max_sg_len = min_t(u64, max_sg_len,
102 nx_ctx->ap->databytelen/NX_PAGE_SIZE);
103
104 data_len = SHA256_DIGEST_SIZE;
105 out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
106 &data_len, max_sg_len);
107 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
108
109 if (data_len != SHA256_DIGEST_SIZE) {
110 rc = -EINVAL;
111 goto out;
112 }
113
114 do {
115 int used_sgs = 0;
116 struct nx_sg *in_sg = nx_ctx->in_sg;
117
118 if (buf_len) {
119 data_len = buf_len;
120 in_sg = nx_build_sg_list(in_sg,
121 (u8 *) sctx->buf,
122 &data_len,
123 max_sg_len);
124
125 if (data_len != buf_len) {
126 rc = -EINVAL;
127 goto out;
128 }
129 used_sgs = in_sg - nx_ctx->in_sg;
130 }
131
132 /* to_process: SHA256_BLOCK_SIZE aligned chunk to be
133 * processed in this iteration. This value is restricted
134 * by sg list limits and number of sgs we already used
135 * for leftover data. (see above)
136 * In ideal case, we could allow NX_PAGE_SIZE * max_sg_len,
137 * but because data may not be aligned, we need to account
138 * for that too. */
139 to_process = min_t(u64, total,
140 (max_sg_len - 1 - used_sgs) * NX_PAGE_SIZE);
141 to_process = to_process & ~(SHA256_BLOCK_SIZE - 1);
142
143 data_len = to_process - buf_len;
144 in_sg = nx_build_sg_list(in_sg, (u8 *) data,
145 &data_len, max_sg_len);
146
147 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
148
149 to_process = data_len + buf_len;
150 leftover = total - to_process;
151
152 /*
153 * we've hit the nx chip previously and we're updating
154 * again, so copy over the partial digest.
155 */
156 memcpy(csbcpb->cpb.sha256.input_partial_digest,
157 csbcpb->cpb.sha256.message_digest,
158 SHA256_DIGEST_SIZE);
159
160 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
161 rc = -EINVAL;
162 goto out;
163 }
164
165 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
166 desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
167 if (rc)
168 goto out;
169
170 atomic_inc(&(nx_ctx->stats->sha256_ops));
171
172 total -= to_process;
173 data += to_process - buf_len;
174 buf_len = 0;
175
176 } while (leftover >= SHA256_BLOCK_SIZE);
177
178 /* copy the leftover back into the state struct */
179 if (leftover)
180 memcpy(sctx->buf, data, leftover);
181
182 sctx->count += len;
183 memcpy(sctx->state, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
184out:
185 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
186 return rc;
187}
188
189static int nx_sha256_final(struct shash_desc *desc, u8 *out)
190{
191 struct sha256_state *sctx = shash_desc_ctx(desc);
192 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
193 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
194 struct nx_sg *in_sg, *out_sg;
195 unsigned long irq_flags;
196 u32 max_sg_len;
197 int rc = 0;
198 int len;
199
200 spin_lock_irqsave(&nx_ctx->lock, irq_flags);
201
202 max_sg_len = min_t(u64, nx_ctx->ap->sglen,
203 nx_driver.of.max_sg_len/sizeof(struct nx_sg));
204 max_sg_len = min_t(u64, max_sg_len,
205 nx_ctx->ap->databytelen/NX_PAGE_SIZE);
206
207 /* final is represented by continuing the operation and indicating that
208 * this is not an intermediate operation */
209 if (sctx->count >= SHA256_BLOCK_SIZE) {
210 /* we've hit the nx chip previously, now we're finalizing,
211 * so copy over the partial digest */
212 memcpy(csbcpb->cpb.sha256.input_partial_digest, sctx->state, SHA256_DIGEST_SIZE);
213 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
214 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
215 } else {
216 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
217 NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
218 }
219
220 csbcpb->cpb.sha256.message_bit_length = (u64) (sctx->count * 8);
221
222 len = sctx->count & (SHA256_BLOCK_SIZE - 1);
223 in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *) sctx->buf,
224 &len, max_sg_len);
225
226 if (len != (sctx->count & (SHA256_BLOCK_SIZE - 1))) {
227 rc = -EINVAL;
228 goto out;
229 }
230
231 len = SHA256_DIGEST_SIZE;
232 out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len, max_sg_len);
233
234 if (len != SHA256_DIGEST_SIZE) {
235 rc = -EINVAL;
236 goto out;
237 }
238
239 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
240 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
241 if (!nx_ctx->op.outlen) {
242 rc = -EINVAL;
243 goto out;
244 }
245
246 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
247 desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
248 if (rc)
249 goto out;
250
251 atomic_inc(&(nx_ctx->stats->sha256_ops));
252
253 atomic64_add(sctx->count, &(nx_ctx->stats->sha256_bytes));
254 memcpy(out, csbcpb->cpb.sha256.message_digest, SHA256_DIGEST_SIZE);
255out:
256 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
257 return rc;
258}
259
260static int nx_sha256_export(struct shash_desc *desc, void *out)
261{
262 struct sha256_state *sctx = shash_desc_ctx(desc);
263
264 memcpy(out, sctx, sizeof(*sctx));
265
266 return 0;
267}
268
269static int nx_sha256_import(struct shash_desc *desc, const void *in)
270{
271 struct sha256_state *sctx = shash_desc_ctx(desc);
272
273 memcpy(sctx, in, sizeof(*sctx));
274
275 return 0;
276}
277
278struct shash_alg nx_shash_sha256_alg = {
279 .digestsize = SHA256_DIGEST_SIZE,
280 .init = nx_sha256_init,
281 .update = nx_sha256_update,
282 .final = nx_sha256_final,
283 .export = nx_sha256_export,
284 .import = nx_sha256_import,
285 .descsize = sizeof(struct sha256_state),
286 .statesize = sizeof(struct sha256_state),
287 .base = {
288 .cra_name = "sha256",
289 .cra_driver_name = "sha256-nx",
290 .cra_priority = 300,
291 .cra_flags = CRYPTO_ALG_TYPE_SHASH,
292 .cra_blocksize = SHA256_BLOCK_SIZE,
293 .cra_module = THIS_MODULE,
294 .cra_ctxsize = sizeof(struct nx_crypto_ctx),
295 .cra_init = nx_crypto_ctx_sha256_init,
296 .cra_exit = nx_crypto_ctx_exit,
297 }
298};