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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * include/asm/processor.h
4 *
5 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#ifndef __ASM_SPARC64_PROCESSOR_H
9#define __ASM_SPARC64_PROCESSOR_H
10
11#include <asm/asi.h>
12#include <asm/pstate.h>
13#include <asm/ptrace.h>
14#include <asm/page.h>
15
16/*
17 * User lives in his very own context, and cannot reference us. Note
18 * that TASK_SIZE is a misnomer, it really gives maximum user virtual
19 * address that the kernel will allocate out.
20 *
21 * XXX No longer using virtual page tables, kill this upper limit...
22 */
23#define VA_BITS 44
24#ifndef __ASSEMBLY__
25#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
26#else
27#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
28#endif
29
30#define TASK_SIZE_OF(tsk) \
31 (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
32 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
33#define TASK_SIZE \
34 (test_thread_flag(TIF_32BIT) ? \
35 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
36#ifdef __KERNEL__
37
38#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
39#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
40
41#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
42 STACK_TOP32 : STACK_TOP64)
43
44#define STACK_TOP_MAX STACK_TOP64
45
46#endif
47
48#ifndef __ASSEMBLY__
49
50/* The Sparc processor specific thread struct. */
51/* XXX This should die, everything can go into thread_info now. */
52struct thread_struct {
53#ifdef CONFIG_DEBUG_SPINLOCK
54 /* How many spinlocks held by this thread.
55 * Used with spin lock debugging to catch tasks
56 * sleeping illegally with locks held.
57 */
58 int smp_lock_count;
59 unsigned int smp_lock_pc;
60#else
61 int dummy; /* f'in gcc bug... */
62#endif
63};
64
65#endif /* !(__ASSEMBLY__) */
66
67#ifndef CONFIG_DEBUG_SPINLOCK
68#define INIT_THREAD { \
69 0, \
70}
71#else /* CONFIG_DEBUG_SPINLOCK */
72#define INIT_THREAD { \
73/* smp_lock_count, smp_lock_pc, */ \
74 0, 0, \
75}
76#endif /* !(CONFIG_DEBUG_SPINLOCK) */
77
78#ifndef __ASSEMBLY__
79
80#include <linux/types.h>
81#include <asm/fpumacro.h>
82
83struct task_struct;
84
85/* On Uniprocessor, even in RMO processes see TSO semantics */
86#ifdef CONFIG_SMP
87#define TSTATE_INITIAL_MM TSTATE_TSO
88#else
89#define TSTATE_INITIAL_MM TSTATE_RMO
90#endif
91
92/* Do necessary setup to start up a newly executed thread. */
93#define start_thread(regs, pc, sp) \
94do { \
95 unsigned long __asi = ASI_PNF; \
96 regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
97 regs->tpc = ((pc & (~3)) - 4); \
98 regs->tnpc = regs->tpc + 4; \
99 regs->y = 0; \
100 set_thread_wstate(1 << 3); \
101 if (current_thread_info()->utraps) { \
102 if (*(current_thread_info()->utraps) < 2) \
103 kfree(current_thread_info()->utraps); \
104 else \
105 (*(current_thread_info()->utraps))--; \
106 current_thread_info()->utraps = NULL; \
107 } \
108 __asm__ __volatile__( \
109 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
110 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
111 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
112 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
113 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
114 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
115 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
116 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
117 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
118 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
119 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
120 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
121 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
122 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
123 "stx %1, [%0 + %2 + 0x70]\n\t" \
124 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
125 "wrpr %%g0, (1 << 3), %%wstate\n\t" \
126 : \
127 : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
128 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
129 fprs_write(0); \
130 current_thread_info()->xfsr[0] = 0; \
131 current_thread_info()->fpsaved[0] = 0; \
132 regs->tstate &= ~TSTATE_PEF; \
133} while (0)
134
135#define start_thread32(regs, pc, sp) \
136do { \
137 unsigned long __asi = ASI_PNF; \
138 pc &= 0x00000000ffffffffUL; \
139 sp &= 0x00000000ffffffffUL; \
140 regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
141 regs->tpc = ((pc & (~3)) - 4); \
142 regs->tnpc = regs->tpc + 4; \
143 regs->y = 0; \
144 set_thread_wstate(2 << 3); \
145 if (current_thread_info()->utraps) { \
146 if (*(current_thread_info()->utraps) < 2) \
147 kfree(current_thread_info()->utraps); \
148 else \
149 (*(current_thread_info()->utraps))--; \
150 current_thread_info()->utraps = NULL; \
151 } \
152 __asm__ __volatile__( \
153 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
154 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
155 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
156 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
157 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
158 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
159 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
160 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
161 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
162 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
163 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
164 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
165 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
166 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
167 "stx %1, [%0 + %2 + 0x70]\n\t" \
168 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
169 "wrpr %%g0, (2 << 3), %%wstate\n\t" \
170 : \
171 : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
172 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
173 fprs_write(0); \
174 current_thread_info()->xfsr[0] = 0; \
175 current_thread_info()->fpsaved[0] = 0; \
176 regs->tstate &= ~TSTATE_PEF; \
177} while (0)
178
179unsigned long __get_wchan(struct task_struct *task);
180
181#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
182#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
183#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
184
185/* Please see the commentary in asm/backoff.h for a description of
186 * what these instructions are doing and how they have been chosen.
187 * To make a long story short, we are trying to yield the current cpu
188 * strand during busy loops.
189 */
190#ifdef BUILD_VDSO
191#define cpu_relax() asm volatile("\n99:\n\t" \
192 "rd %%ccr, %%g0\n\t" \
193 "rd %%ccr, %%g0\n\t" \
194 "rd %%ccr, %%g0\n\t" \
195 ::: "memory")
196#else /* ! BUILD_VDSO */
197#define cpu_relax() asm volatile("\n99:\n\t" \
198 "rd %%ccr, %%g0\n\t" \
199 "rd %%ccr, %%g0\n\t" \
200 "rd %%ccr, %%g0\n\t" \
201 ".section .pause_3insn_patch,\"ax\"\n\t"\
202 ".word 99b\n\t" \
203 "wr %%g0, 128, %%asr27\n\t" \
204 "nop\n\t" \
205 "nop\n\t" \
206 ".previous" \
207 ::: "memory")
208#endif
209
210/* Prefetch support. This is tuned for UltraSPARC-III and later.
211 * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
212 * a shallower prefetch queue than later chips.
213 */
214#define ARCH_HAS_PREFETCH
215#define ARCH_HAS_PREFETCHW
216
217static inline void prefetch(const void *x)
218{
219 /* We do not use the read prefetch mnemonic because that
220 * prefetches into the prefetch-cache which only is accessible
221 * by floating point operations in UltraSPARC-III and later.
222 * By contrast, "#one_write" prefetches into the L2 cache
223 * in shared state.
224 */
225 __asm__ __volatile__("prefetch [%0], #one_write"
226 : /* no outputs */
227 : "r" (x));
228}
229
230static inline void prefetchw(const void *x)
231{
232 /* The most optimal prefetch to use for writes is
233 * "#n_writes". This brings the cacheline into the
234 * L2 cache in "owned" state.
235 */
236 __asm__ __volatile__("prefetch [%0], #n_writes"
237 : /* no outputs */
238 : "r" (x));
239}
240
241#define HAVE_ARCH_PICK_MMAP_LAYOUT
242
243int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap);
244
245#endif /* !(__ASSEMBLY__) */
246
247#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
1/*
2 * include/asm/processor.h
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef __ASM_SPARC64_PROCESSOR_H
8#define __ASM_SPARC64_PROCESSOR_H
9
10/*
11 * Sparc64 implementation of macro that returns current
12 * instruction pointer ("program counter").
13 */
14#define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
15
16#include <asm/asi.h>
17#include <asm/pstate.h>
18#include <asm/ptrace.h>
19#include <asm/page.h>
20
21/* The sparc has no problems with write protection */
22#define wp_works_ok 1
23#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
24
25/*
26 * User lives in his very own context, and cannot reference us. Note
27 * that TASK_SIZE is a misnomer, it really gives maximum user virtual
28 * address that the kernel will allocate out.
29 *
30 * XXX No longer using virtual page tables, kill this upper limit...
31 */
32#define VA_BITS 44
33#ifndef __ASSEMBLY__
34#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
35#else
36#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
37#endif
38
39#define TASK_SIZE_OF(tsk) \
40 (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
41 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
42#define TASK_SIZE \
43 (test_thread_flag(TIF_32BIT) ? \
44 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
45#ifdef __KERNEL__
46
47#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
48#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
49
50#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
51 STACK_TOP32 : STACK_TOP64)
52
53#define STACK_TOP_MAX STACK_TOP64
54
55#endif
56
57#ifndef __ASSEMBLY__
58
59typedef struct {
60 unsigned char seg;
61} mm_segment_t;
62
63/* The Sparc processor specific thread struct. */
64/* XXX This should die, everything can go into thread_info now. */
65struct thread_struct {
66#ifdef CONFIG_DEBUG_SPINLOCK
67 /* How many spinlocks held by this thread.
68 * Used with spin lock debugging to catch tasks
69 * sleeping illegally with locks held.
70 */
71 int smp_lock_count;
72 unsigned int smp_lock_pc;
73#else
74 int dummy; /* f'in gcc bug... */
75#endif
76};
77
78#endif /* !(__ASSEMBLY__) */
79
80#ifndef CONFIG_DEBUG_SPINLOCK
81#define INIT_THREAD { \
82 0, \
83}
84#else /* CONFIG_DEBUG_SPINLOCK */
85#define INIT_THREAD { \
86/* smp_lock_count, smp_lock_pc, */ \
87 0, 0, \
88}
89#endif /* !(CONFIG_DEBUG_SPINLOCK) */
90
91#ifndef __ASSEMBLY__
92
93#include <linux/types.h>
94#include <asm/fpumacro.h>
95
96/* Return saved PC of a blocked thread. */
97struct task_struct;
98unsigned long thread_saved_pc(struct task_struct *);
99
100/* On Uniprocessor, even in RMO processes see TSO semantics */
101#ifdef CONFIG_SMP
102#define TSTATE_INITIAL_MM TSTATE_TSO
103#else
104#define TSTATE_INITIAL_MM TSTATE_RMO
105#endif
106
107/* Do necessary setup to start up a newly executed thread. */
108#define start_thread(regs, pc, sp) \
109do { \
110 unsigned long __asi = ASI_PNF; \
111 regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
112 regs->tpc = ((pc & (~3)) - 4); \
113 regs->tnpc = regs->tpc + 4; \
114 regs->y = 0; \
115 set_thread_wstate(1 << 3); \
116 if (current_thread_info()->utraps) { \
117 if (*(current_thread_info()->utraps) < 2) \
118 kfree(current_thread_info()->utraps); \
119 else \
120 (*(current_thread_info()->utraps))--; \
121 current_thread_info()->utraps = NULL; \
122 } \
123 __asm__ __volatile__( \
124 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
125 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
126 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
127 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
128 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
129 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
130 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
131 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
132 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
133 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
134 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
135 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
136 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
137 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
138 "stx %1, [%0 + %2 + 0x70]\n\t" \
139 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
140 "wrpr %%g0, (1 << 3), %%wstate\n\t" \
141 : \
142 : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
143 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
144 fprs_write(0); \
145 current_thread_info()->xfsr[0] = 0; \
146 current_thread_info()->fpsaved[0] = 0; \
147 regs->tstate &= ~TSTATE_PEF; \
148} while (0)
149
150#define start_thread32(regs, pc, sp) \
151do { \
152 unsigned long __asi = ASI_PNF; \
153 pc &= 0x00000000ffffffffUL; \
154 sp &= 0x00000000ffffffffUL; \
155 regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
156 regs->tpc = ((pc & (~3)) - 4); \
157 regs->tnpc = regs->tpc + 4; \
158 regs->y = 0; \
159 set_thread_wstate(2 << 3); \
160 if (current_thread_info()->utraps) { \
161 if (*(current_thread_info()->utraps) < 2) \
162 kfree(current_thread_info()->utraps); \
163 else \
164 (*(current_thread_info()->utraps))--; \
165 current_thread_info()->utraps = NULL; \
166 } \
167 __asm__ __volatile__( \
168 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
169 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
170 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
171 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
172 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
173 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
174 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
175 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
176 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
177 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
178 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
179 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
180 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
181 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
182 "stx %1, [%0 + %2 + 0x70]\n\t" \
183 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
184 "wrpr %%g0, (2 << 3), %%wstate\n\t" \
185 : \
186 : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
187 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
188 fprs_write(0); \
189 current_thread_info()->xfsr[0] = 0; \
190 current_thread_info()->fpsaved[0] = 0; \
191 regs->tstate &= ~TSTATE_PEF; \
192} while (0)
193
194/* Free all resources held by a thread. */
195#define release_thread(tsk) do { } while (0)
196
197unsigned long get_wchan(struct task_struct *task);
198
199#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
200#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
201#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
202
203/* Please see the commentary in asm/backoff.h for a description of
204 * what these instructions are doing and how they have been chosen.
205 * To make a long story short, we are trying to yield the current cpu
206 * strand during busy loops.
207 */
208#define cpu_relax() asm volatile("\n99:\n\t" \
209 "rd %%ccr, %%g0\n\t" \
210 "rd %%ccr, %%g0\n\t" \
211 "rd %%ccr, %%g0\n\t" \
212 ".section .pause_3insn_patch,\"ax\"\n\t"\
213 ".word 99b\n\t" \
214 "wr %%g0, 128, %%asr27\n\t" \
215 "nop\n\t" \
216 "nop\n\t" \
217 ".previous" \
218 ::: "memory")
219
220/* Prefetch support. This is tuned for UltraSPARC-III and later.
221 * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
222 * a shallower prefetch queue than later chips.
223 */
224#define ARCH_HAS_PREFETCH
225#define ARCH_HAS_PREFETCHW
226#define ARCH_HAS_SPINLOCK_PREFETCH
227
228static inline void prefetch(const void *x)
229{
230 /* We do not use the read prefetch mnemonic because that
231 * prefetches into the prefetch-cache which only is accessible
232 * by floating point operations in UltraSPARC-III and later.
233 * By contrast, "#one_write" prefetches into the L2 cache
234 * in shared state.
235 */
236 __asm__ __volatile__("prefetch [%0], #one_write"
237 : /* no outputs */
238 : "r" (x));
239}
240
241static inline void prefetchw(const void *x)
242{
243 /* The most optimal prefetch to use for writes is
244 * "#n_writes". This brings the cacheline into the
245 * L2 cache in "owned" state.
246 */
247 __asm__ __volatile__("prefetch [%0], #n_writes"
248 : /* no outputs */
249 : "r" (x));
250}
251
252#define spin_lock_prefetch(x) prefetchw(x)
253
254#define HAVE_ARCH_PICK_MMAP_LAYOUT
255
256int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap);
257
258#endif /* !(__ASSEMBLY__) */
259
260#endif /* !(__ASM_SPARC64_PROCESSOR_H) */