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1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated
3 *
4 * Hwmod present only in AM43x and those that differ other than register
5 * offsets as compared to AM335x.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/platform_data/gpio-omap.h>
18#include <linux/platform_data/spi-omap2-mcspi.h>
19#include "omap_hwmod.h"
20#include "omap_hwmod_33xx_43xx_common_data.h"
21#include "prcm43xx.h"
22#include "omap_hwmod_common_data.h"
23#include "hdq1w.h"
24
25
26/* IP blocks */
27static struct omap_hwmod am43xx_emif_hwmod = {
28 .name = "emif",
29 .class = &am33xx_emif_hwmod_class,
30 .clkdm_name = "emif_clkdm",
31 .flags = HWMOD_INIT_NO_IDLE,
32 .main_clk = "dpll_ddr_m2_ck",
33 .prcm = {
34 .omap4 = {
35 .clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
36 .modulemode = MODULEMODE_SWCTRL,
37 },
38 },
39};
40
41static struct omap_hwmod am43xx_l4_hs_hwmod = {
42 .name = "l4_hs",
43 .class = &am33xx_l4_hwmod_class,
44 .clkdm_name = "l3_clkdm",
45 .flags = HWMOD_INIT_NO_IDLE,
46 .main_clk = "l4hs_gclk",
47 .prcm = {
48 .omap4 = {
49 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
50 .modulemode = MODULEMODE_SWCTRL,
51 },
52 },
53};
54
55static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
56 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
57};
58
59static struct omap_hwmod am43xx_wkup_m3_hwmod = {
60 .name = "wkup_m3",
61 .class = &am33xx_wkup_m3_hwmod_class,
62 .clkdm_name = "l4_wkup_aon_clkdm",
63 /* Keep hardreset asserted */
64 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
65 .main_clk = "sys_clkin_ck",
66 .prcm = {
67 .omap4 = {
68 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
69 .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
70 .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
71 .modulemode = MODULEMODE_SWCTRL,
72 },
73 },
74 .rst_lines = am33xx_wkup_m3_resets,
75 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
76};
77
78static struct omap_hwmod am43xx_control_hwmod = {
79 .name = "control",
80 .class = &am33xx_control_hwmod_class,
81 .clkdm_name = "l4_wkup_clkdm",
82 .flags = HWMOD_INIT_NO_IDLE,
83 .main_clk = "sys_clkin_ck",
84 .prcm = {
85 .omap4 = {
86 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
87 .modulemode = MODULEMODE_SWCTRL,
88 },
89 },
90};
91
92static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
93 { .role = "dbclk", .clk = "gpio0_dbclk" },
94};
95
96static struct omap_hwmod am43xx_gpio0_hwmod = {
97 .name = "gpio1",
98 .class = &am33xx_gpio_hwmod_class,
99 .clkdm_name = "l4_wkup_clkdm",
100 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
101 .main_clk = "sys_clkin_ck",
102 .prcm = {
103 .omap4 = {
104 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
105 .modulemode = MODULEMODE_SWCTRL,
106 },
107 },
108 .opt_clks = gpio0_opt_clks,
109 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
110 .dev_attr = &gpio_dev_attr,
111};
112
113static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
114 .rev_offs = 0x0,
115 .sysc_offs = 0x4,
116 .sysc_flags = SYSC_HAS_SIDLEMODE,
117 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
118 .sysc_fields = &omap_hwmod_sysc_type1,
119};
120
121static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
122 .name = "synctimer",
123 .sysc = &am43xx_synctimer_sysc,
124};
125
126static struct omap_hwmod am43xx_synctimer_hwmod = {
127 .name = "counter_32k",
128 .class = &am43xx_synctimer_hwmod_class,
129 .clkdm_name = "l4_wkup_aon_clkdm",
130 .flags = HWMOD_SWSUP_SIDLE,
131 .main_clk = "synctimer_32kclk",
132 .prcm = {
133 .omap4 = {
134 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
135 .modulemode = MODULEMODE_SWCTRL,
136 },
137 },
138};
139
140static struct omap_hwmod am43xx_timer8_hwmod = {
141 .name = "timer8",
142 .class = &am33xx_timer_hwmod_class,
143 .clkdm_name = "l4ls_clkdm",
144 .main_clk = "timer8_fck",
145 .prcm = {
146 .omap4 = {
147 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
148 .modulemode = MODULEMODE_SWCTRL,
149 },
150 },
151};
152
153static struct omap_hwmod am43xx_timer9_hwmod = {
154 .name = "timer9",
155 .class = &am33xx_timer_hwmod_class,
156 .clkdm_name = "l4ls_clkdm",
157 .main_clk = "timer9_fck",
158 .prcm = {
159 .omap4 = {
160 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
161 .modulemode = MODULEMODE_SWCTRL,
162 },
163 },
164};
165
166static struct omap_hwmod am43xx_timer10_hwmod = {
167 .name = "timer10",
168 .class = &am33xx_timer_hwmod_class,
169 .clkdm_name = "l4ls_clkdm",
170 .main_clk = "timer10_fck",
171 .prcm = {
172 .omap4 = {
173 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
174 .modulemode = MODULEMODE_SWCTRL,
175 },
176 },
177};
178
179static struct omap_hwmod am43xx_timer11_hwmod = {
180 .name = "timer11",
181 .class = &am33xx_timer_hwmod_class,
182 .clkdm_name = "l4ls_clkdm",
183 .main_clk = "timer11_fck",
184 .prcm = {
185 .omap4 = {
186 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
187 .modulemode = MODULEMODE_SWCTRL,
188 },
189 },
190};
191
192static struct omap_hwmod am43xx_epwmss3_hwmod = {
193 .name = "epwmss3",
194 .class = &am33xx_epwmss_hwmod_class,
195 .clkdm_name = "l4ls_clkdm",
196 .main_clk = "l4ls_gclk",
197 .prcm = {
198 .omap4 = {
199 .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
200 .modulemode = MODULEMODE_SWCTRL,
201 },
202 },
203};
204
205static struct omap_hwmod am43xx_epwmss4_hwmod = {
206 .name = "epwmss4",
207 .class = &am33xx_epwmss_hwmod_class,
208 .clkdm_name = "l4ls_clkdm",
209 .main_clk = "l4ls_gclk",
210 .prcm = {
211 .omap4 = {
212 .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
214 },
215 },
216};
217
218static struct omap_hwmod am43xx_epwmss5_hwmod = {
219 .name = "epwmss5",
220 .class = &am33xx_epwmss_hwmod_class,
221 .clkdm_name = "l4ls_clkdm",
222 .main_clk = "l4ls_gclk",
223 .prcm = {
224 .omap4 = {
225 .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
226 .modulemode = MODULEMODE_SWCTRL,
227 },
228 },
229};
230
231static struct omap_hwmod am43xx_spi2_hwmod = {
232 .name = "spi2",
233 .class = &am33xx_spi_hwmod_class,
234 .clkdm_name = "l4ls_clkdm",
235 .main_clk = "dpll_per_m2_div4_ck",
236 .prcm = {
237 .omap4 = {
238 .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
239 .modulemode = MODULEMODE_SWCTRL,
240 },
241 },
242 .dev_attr = &mcspi_attrib,
243};
244
245static struct omap_hwmod am43xx_spi3_hwmod = {
246 .name = "spi3",
247 .class = &am33xx_spi_hwmod_class,
248 .clkdm_name = "l4ls_clkdm",
249 .main_clk = "dpll_per_m2_div4_ck",
250 .prcm = {
251 .omap4 = {
252 .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
253 .modulemode = MODULEMODE_SWCTRL,
254 },
255 },
256 .dev_attr = &mcspi_attrib,
257};
258
259static struct omap_hwmod am43xx_spi4_hwmod = {
260 .name = "spi4",
261 .class = &am33xx_spi_hwmod_class,
262 .clkdm_name = "l4ls_clkdm",
263 .main_clk = "dpll_per_m2_div4_ck",
264 .prcm = {
265 .omap4 = {
266 .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
267 .modulemode = MODULEMODE_SWCTRL,
268 },
269 },
270 .dev_attr = &mcspi_attrib,
271};
272
273static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
274 { .role = "dbclk", .clk = "gpio4_dbclk" },
275};
276
277static struct omap_hwmod am43xx_gpio4_hwmod = {
278 .name = "gpio5",
279 .class = &am33xx_gpio_hwmod_class,
280 .clkdm_name = "l4ls_clkdm",
281 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
282 .main_clk = "l4ls_gclk",
283 .prcm = {
284 .omap4 = {
285 .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
286 .modulemode = MODULEMODE_SWCTRL,
287 },
288 },
289 .opt_clks = gpio4_opt_clks,
290 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
291 .dev_attr = &gpio_dev_attr,
292};
293
294static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
295 { .role = "dbclk", .clk = "gpio5_dbclk" },
296};
297
298static struct omap_hwmod am43xx_gpio5_hwmod = {
299 .name = "gpio6",
300 .class = &am33xx_gpio_hwmod_class,
301 .clkdm_name = "l4ls_clkdm",
302 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
303 .main_clk = "l4ls_gclk",
304 .prcm = {
305 .omap4 = {
306 .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
307 .modulemode = MODULEMODE_SWCTRL,
308 },
309 },
310 .opt_clks = gpio5_opt_clks,
311 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
312 .dev_attr = &gpio_dev_attr,
313};
314
315static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
316 .name = "ocp2scp",
317};
318
319static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
320 .name = "ocp2scp0",
321 .class = &am43xx_ocp2scp_hwmod_class,
322 .clkdm_name = "l4ls_clkdm",
323 .main_clk = "l4ls_gclk",
324 .prcm = {
325 .omap4 = {
326 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
327 .modulemode = MODULEMODE_SWCTRL,
328 },
329 },
330};
331
332static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
333 .name = "ocp2scp1",
334 .class = &am43xx_ocp2scp_hwmod_class,
335 .clkdm_name = "l4ls_clkdm",
336 .main_clk = "l4ls_gclk",
337 .prcm = {
338 .omap4 = {
339 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
340 .modulemode = MODULEMODE_SWCTRL,
341 },
342 },
343};
344
345static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
346 .rev_offs = 0x0000,
347 .sysc_offs = 0x0010,
348 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
349 SYSC_HAS_SIDLEMODE),
350 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
351 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
352 MSTANDBY_NO | MSTANDBY_SMART |
353 MSTANDBY_SMART_WKUP),
354 .sysc_fields = &omap_hwmod_sysc_type2,
355};
356
357static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
358 .name = "usb_otg_ss",
359 .sysc = &am43xx_usb_otg_ss_sysc,
360};
361
362static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
363 .name = "usb_otg_ss0",
364 .class = &am43xx_usb_otg_ss_hwmod_class,
365 .clkdm_name = "l3s_clkdm",
366 .main_clk = "l3s_gclk",
367 .prcm = {
368 .omap4 = {
369 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
370 .modulemode = MODULEMODE_SWCTRL,
371 },
372 },
373};
374
375static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
376 .name = "usb_otg_ss1",
377 .class = &am43xx_usb_otg_ss_hwmod_class,
378 .clkdm_name = "l3s_clkdm",
379 .main_clk = "l3s_gclk",
380 .prcm = {
381 .omap4 = {
382 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
383 .modulemode = MODULEMODE_SWCTRL,
384 },
385 },
386};
387
388static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
389 .sysc_offs = 0x0010,
390 .sysc_flags = SYSC_HAS_SIDLEMODE,
391 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
392 SIDLE_SMART_WKUP),
393 .sysc_fields = &omap_hwmod_sysc_type2,
394};
395
396static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
397 .name = "qspi",
398 .sysc = &am43xx_qspi_sysc,
399};
400
401static struct omap_hwmod am43xx_qspi_hwmod = {
402 .name = "qspi",
403 .class = &am43xx_qspi_hwmod_class,
404 .clkdm_name = "l3s_clkdm",
405 .main_clk = "l3s_gclk",
406 .prcm = {
407 .omap4 = {
408 .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
409 .modulemode = MODULEMODE_SWCTRL,
410 },
411 },
412};
413
414/*
415 * 'adc/tsc' class
416 * TouchScreen Controller (Analog-To-Digital Converter)
417 */
418static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
419 .rev_offs = 0x00,
420 .sysc_offs = 0x10,
421 .sysc_flags = SYSC_HAS_SIDLEMODE,
422 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
423 SIDLE_SMART_WKUP),
424 .sysc_fields = &omap_hwmod_sysc_type2,
425};
426
427static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
428 .name = "adc_tsc",
429 .sysc = &am43xx_adc_tsc_sysc,
430};
431
432static struct omap_hwmod am43xx_adc_tsc_hwmod = {
433 .name = "adc_tsc",
434 .class = &am43xx_adc_tsc_hwmod_class,
435 .clkdm_name = "l3s_tsc_clkdm",
436 .main_clk = "adc_tsc_fck",
437 .prcm = {
438 .omap4 = {
439 .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
440 .modulemode = MODULEMODE_SWCTRL,
441 },
442 },
443};
444
445static struct omap_hwmod_class_sysconfig am43xx_des_sysc = {
446 .rev_offs = 0x30,
447 .sysc_offs = 0x34,
448 .syss_offs = 0x38,
449 .sysc_flags = SYSS_HAS_RESET_STATUS,
450};
451
452static struct omap_hwmod_class am43xx_des_hwmod_class = {
453 .name = "des",
454 .sysc = &am43xx_des_sysc,
455};
456
457static struct omap_hwmod am43xx_des_hwmod = {
458 .name = "des",
459 .class = &am43xx_des_hwmod_class,
460 .clkdm_name = "l3_clkdm",
461 .main_clk = "l3_gclk",
462 .prcm = {
463 .omap4 = {
464 .clkctrl_offs = AM43XX_CM_PER_DES_CLKCTRL_OFFSET,
465 .modulemode = MODULEMODE_SWCTRL,
466 },
467 },
468};
469
470/* dss */
471
472static struct omap_hwmod am43xx_dss_core_hwmod = {
473 .name = "dss_core",
474 .class = &omap2_dss_hwmod_class,
475 .clkdm_name = "dss_clkdm",
476 .main_clk = "disp_clk",
477 .prcm = {
478 .omap4 = {
479 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
480 .modulemode = MODULEMODE_SWCTRL,
481 },
482 },
483};
484
485/* dispc */
486
487static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
488 .manager_count = 1,
489 .has_framedonetv_irq = 0
490};
491
492static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
493 .rev_offs = 0x0000,
494 .sysc_offs = 0x0010,
495 .syss_offs = 0x0014,
496 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
497 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
498 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
499 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
500 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
501 .sysc_fields = &omap_hwmod_sysc_type1,
502};
503
504static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
505 .name = "dispc",
506 .sysc = &am43xx_dispc_sysc,
507};
508
509static struct omap_hwmod am43xx_dss_dispc_hwmod = {
510 .name = "dss_dispc",
511 .class = &am43xx_dispc_hwmod_class,
512 .clkdm_name = "dss_clkdm",
513 .main_clk = "disp_clk",
514 .prcm = {
515 .omap4 = {
516 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
517 },
518 },
519 .dev_attr = &am43xx_dss_dispc_dev_attr,
520 .parent_hwmod = &am43xx_dss_core_hwmod,
521};
522
523/* rfbi */
524
525static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
526 .name = "dss_rfbi",
527 .class = &omap2_rfbi_hwmod_class,
528 .clkdm_name = "dss_clkdm",
529 .main_clk = "disp_clk",
530 .prcm = {
531 .omap4 = {
532 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
533 },
534 },
535 .parent_hwmod = &am43xx_dss_core_hwmod,
536};
537
538/* HDQ1W */
539static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
540 .rev_offs = 0x0000,
541 .sysc_offs = 0x0014,
542 .syss_offs = 0x0018,
543 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
544 .sysc_fields = &omap_hwmod_sysc_type1,
545};
546
547static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
548 .name = "hdq1w",
549 .sysc = &am43xx_hdq1w_sysc,
550 .reset = &omap_hdq1w_reset,
551};
552
553static struct omap_hwmod am43xx_hdq1w_hwmod = {
554 .name = "hdq1w",
555 .class = &am43xx_hdq1w_hwmod_class,
556 .clkdm_name = "l4ls_clkdm",
557 .prcm = {
558 .omap4 = {
559 .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
560 .modulemode = MODULEMODE_SWCTRL,
561 },
562 },
563};
564
565static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
566 .rev_offs = 0x0,
567 .sysc_offs = 0x104,
568 .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
569 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
570 MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
571 .sysc_fields = &omap_hwmod_sysc_type2,
572};
573
574static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
575 .name = "vpfe",
576 .sysc = &am43xx_vpfe_sysc,
577};
578
579static struct omap_hwmod am43xx_vpfe0_hwmod = {
580 .name = "vpfe0",
581 .class = &am43xx_vpfe_hwmod_class,
582 .clkdm_name = "l3s_clkdm",
583 .prcm = {
584 .omap4 = {
585 .modulemode = MODULEMODE_SWCTRL,
586 .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
587 },
588 },
589};
590
591static struct omap_hwmod am43xx_vpfe1_hwmod = {
592 .name = "vpfe1",
593 .class = &am43xx_vpfe_hwmod_class,
594 .clkdm_name = "l3s_clkdm",
595 .prcm = {
596 .omap4 = {
597 .modulemode = MODULEMODE_SWCTRL,
598 .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
599 },
600 },
601};
602
603/* Interfaces */
604static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
605 .master = &am33xx_l3_main_hwmod,
606 .slave = &am43xx_emif_hwmod,
607 .clk = "dpll_core_m4_ck",
608 .user = OCP_USER_MPU | OCP_USER_SDMA,
609};
610
611static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
612 .master = &am33xx_l3_main_hwmod,
613 .slave = &am43xx_l4_hs_hwmod,
614 .clk = "l3s_gclk",
615 .user = OCP_USER_MPU | OCP_USER_SDMA,
616};
617
618static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
619 .master = &am43xx_wkup_m3_hwmod,
620 .slave = &am33xx_l4_wkup_hwmod,
621 .clk = "sys_clkin_ck",
622 .user = OCP_USER_MPU | OCP_USER_SDMA,
623};
624
625static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
626 .master = &am33xx_l4_wkup_hwmod,
627 .slave = &am43xx_wkup_m3_hwmod,
628 .clk = "sys_clkin_ck",
629 .user = OCP_USER_MPU | OCP_USER_SDMA,
630};
631
632static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
633 .master = &am33xx_l3_main_hwmod,
634 .slave = &am33xx_pruss_hwmod,
635 .clk = "dpll_core_m4_ck",
636 .user = OCP_USER_MPU,
637};
638
639static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
640 .master = &am33xx_l4_wkup_hwmod,
641 .slave = &am33xx_smartreflex0_hwmod,
642 .clk = "sys_clkin_ck",
643 .user = OCP_USER_MPU,
644};
645
646static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
647 .master = &am33xx_l4_wkup_hwmod,
648 .slave = &am33xx_smartreflex1_hwmod,
649 .clk = "sys_clkin_ck",
650 .user = OCP_USER_MPU,
651};
652
653static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
654 .master = &am33xx_l4_wkup_hwmod,
655 .slave = &am43xx_control_hwmod,
656 .clk = "sys_clkin_ck",
657 .user = OCP_USER_MPU,
658};
659
660static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
661 .master = &am33xx_l4_wkup_hwmod,
662 .slave = &am33xx_i2c1_hwmod,
663 .clk = "sys_clkin_ck",
664 .user = OCP_USER_MPU,
665};
666
667static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
668 .master = &am33xx_l4_wkup_hwmod,
669 .slave = &am43xx_gpio0_hwmod,
670 .clk = "sys_clkin_ck",
671 .user = OCP_USER_MPU | OCP_USER_SDMA,
672};
673
674static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
675 .master = &am33xx_l4_wkup_hwmod,
676 .slave = &am43xx_adc_tsc_hwmod,
677 .clk = "dpll_core_m4_div2_ck",
678 .user = OCP_USER_MPU,
679};
680
681static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
682 .master = &am43xx_l4_hs_hwmod,
683 .slave = &am33xx_cpgmac0_hwmod,
684 .clk = "cpsw_125mhz_gclk",
685 .user = OCP_USER_MPU,
686};
687
688static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
689 .master = &am33xx_l4_wkup_hwmod,
690 .slave = &am33xx_timer1_hwmod,
691 .clk = "sys_clkin_ck",
692 .user = OCP_USER_MPU,
693};
694
695static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
696 .master = &am33xx_l4_wkup_hwmod,
697 .slave = &am33xx_uart1_hwmod,
698 .clk = "sys_clkin_ck",
699 .user = OCP_USER_MPU,
700};
701
702static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
703 .master = &am33xx_l4_wkup_hwmod,
704 .slave = &am33xx_wd_timer1_hwmod,
705 .clk = "sys_clkin_ck",
706 .user = OCP_USER_MPU,
707};
708
709static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
710 .master = &am33xx_l4_wkup_hwmod,
711 .slave = &am43xx_synctimer_hwmod,
712 .clk = "sys_clkin_ck",
713 .user = OCP_USER_MPU,
714};
715
716static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
717 .master = &am33xx_l4_ls_hwmod,
718 .slave = &am43xx_timer8_hwmod,
719 .clk = "l4ls_gclk",
720 .user = OCP_USER_MPU,
721};
722
723static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
724 .master = &am33xx_l4_ls_hwmod,
725 .slave = &am43xx_timer9_hwmod,
726 .clk = "l4ls_gclk",
727 .user = OCP_USER_MPU,
728};
729
730static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
731 .master = &am33xx_l4_ls_hwmod,
732 .slave = &am43xx_timer10_hwmod,
733 .clk = "l4ls_gclk",
734 .user = OCP_USER_MPU,
735};
736
737static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
738 .master = &am33xx_l4_ls_hwmod,
739 .slave = &am43xx_timer11_hwmod,
740 .clk = "l4ls_gclk",
741 .user = OCP_USER_MPU,
742};
743
744static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
745 .master = &am33xx_l4_ls_hwmod,
746 .slave = &am43xx_epwmss3_hwmod,
747 .clk = "l4ls_gclk",
748 .user = OCP_USER_MPU,
749};
750
751static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
752 .master = &am33xx_l4_ls_hwmod,
753 .slave = &am43xx_epwmss4_hwmod,
754 .clk = "l4ls_gclk",
755 .user = OCP_USER_MPU,
756};
757
758static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
759 .master = &am33xx_l4_ls_hwmod,
760 .slave = &am43xx_epwmss5_hwmod,
761 .clk = "l4ls_gclk",
762 .user = OCP_USER_MPU,
763};
764
765static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
766 .master = &am33xx_l4_ls_hwmod,
767 .slave = &am43xx_spi2_hwmod,
768 .clk = "l4ls_gclk",
769 .user = OCP_USER_MPU,
770};
771
772static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
773 .master = &am33xx_l4_ls_hwmod,
774 .slave = &am43xx_spi3_hwmod,
775 .clk = "l4ls_gclk",
776 .user = OCP_USER_MPU,
777};
778
779static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
780 .master = &am33xx_l4_ls_hwmod,
781 .slave = &am43xx_spi4_hwmod,
782 .clk = "l4ls_gclk",
783 .user = OCP_USER_MPU,
784};
785
786static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
787 .master = &am33xx_l4_ls_hwmod,
788 .slave = &am43xx_gpio4_hwmod,
789 .clk = "l4ls_gclk",
790 .user = OCP_USER_MPU | OCP_USER_SDMA,
791};
792
793static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
794 .master = &am33xx_l4_ls_hwmod,
795 .slave = &am43xx_gpio5_hwmod,
796 .clk = "l4ls_gclk",
797 .user = OCP_USER_MPU | OCP_USER_SDMA,
798};
799
800static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
801 .master = &am33xx_l4_ls_hwmod,
802 .slave = &am43xx_ocp2scp0_hwmod,
803 .clk = "l4ls_gclk",
804 .user = OCP_USER_MPU,
805};
806
807static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
808 .master = &am33xx_l4_ls_hwmod,
809 .slave = &am43xx_ocp2scp1_hwmod,
810 .clk = "l4ls_gclk",
811 .user = OCP_USER_MPU,
812};
813
814static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
815 .master = &am33xx_l3_s_hwmod,
816 .slave = &am43xx_usb_otg_ss0_hwmod,
817 .clk = "l3s_gclk",
818 .user = OCP_USER_MPU | OCP_USER_SDMA,
819};
820
821static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
822 .master = &am33xx_l3_s_hwmod,
823 .slave = &am43xx_usb_otg_ss1_hwmod,
824 .clk = "l3s_gclk",
825 .user = OCP_USER_MPU | OCP_USER_SDMA,
826};
827
828static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
829 .master = &am33xx_l3_s_hwmod,
830 .slave = &am43xx_qspi_hwmod,
831 .clk = "l3s_gclk",
832 .user = OCP_USER_MPU | OCP_USER_SDMA,
833};
834
835static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
836 .master = &am43xx_dss_core_hwmod,
837 .slave = &am33xx_l3_main_hwmod,
838 .clk = "l3_gclk",
839 .user = OCP_USER_MPU | OCP_USER_SDMA,
840};
841
842static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
843 .master = &am33xx_l4_ls_hwmod,
844 .slave = &am43xx_dss_core_hwmod,
845 .clk = "l4ls_gclk",
846 .user = OCP_USER_MPU | OCP_USER_SDMA,
847};
848
849static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
850 .master = &am33xx_l4_ls_hwmod,
851 .slave = &am43xx_dss_dispc_hwmod,
852 .clk = "l4ls_gclk",
853 .user = OCP_USER_MPU | OCP_USER_SDMA,
854};
855
856static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
857 .master = &am33xx_l4_ls_hwmod,
858 .slave = &am43xx_dss_rfbi_hwmod,
859 .clk = "l4ls_gclk",
860 .user = OCP_USER_MPU | OCP_USER_SDMA,
861};
862
863static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
864 .master = &am33xx_l4_ls_hwmod,
865 .slave = &am43xx_hdq1w_hwmod,
866 .clk = "l4ls_gclk",
867 .user = OCP_USER_MPU | OCP_USER_SDMA,
868};
869
870static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
871 .master = &am43xx_vpfe0_hwmod,
872 .slave = &am33xx_l3_main_hwmod,
873 .clk = "l3_gclk",
874 .user = OCP_USER_MPU | OCP_USER_SDMA,
875};
876
877static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
878 .master = &am43xx_vpfe1_hwmod,
879 .slave = &am33xx_l3_main_hwmod,
880 .clk = "l3_gclk",
881 .user = OCP_USER_MPU | OCP_USER_SDMA,
882};
883
884static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
885 .master = &am33xx_l4_ls_hwmod,
886 .slave = &am43xx_vpfe0_hwmod,
887 .clk = "l4ls_gclk",
888 .user = OCP_USER_MPU | OCP_USER_SDMA,
889};
890
891static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
892 .master = &am33xx_l4_ls_hwmod,
893 .slave = &am43xx_vpfe1_hwmod,
894 .clk = "l4ls_gclk",
895 .user = OCP_USER_MPU | OCP_USER_SDMA,
896};
897
898static struct omap_hwmod_ocp_if am43xx_l3_main__des = {
899 .master = &am33xx_l3_main_hwmod,
900 .slave = &am43xx_des_hwmod,
901 .clk = "l3_gclk",
902 .user = OCP_USER_MPU,
903};
904
905static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
906 &am33xx_l4_wkup__synctimer,
907 &am43xx_l4_ls__timer8,
908 &am43xx_l4_ls__timer9,
909 &am43xx_l4_ls__timer10,
910 &am43xx_l4_ls__timer11,
911 &am43xx_l4_ls__epwmss3,
912 &am43xx_l4_ls__epwmss4,
913 &am43xx_l4_ls__epwmss5,
914 &am43xx_l4_ls__mcspi2,
915 &am43xx_l4_ls__mcspi3,
916 &am43xx_l4_ls__mcspi4,
917 &am43xx_l4_ls__gpio4,
918 &am43xx_l4_ls__gpio5,
919 &am43xx_l3_main__pruss,
920 &am33xx_mpu__l3_main,
921 &am33xx_mpu__prcm,
922 &am33xx_l3_s__l4_ls,
923 &am33xx_l3_s__l4_wkup,
924 &am43xx_l3_main__l4_hs,
925 &am33xx_l3_main__l3_s,
926 &am33xx_l3_main__l3_instr,
927 &am33xx_l3_main__gfx,
928 &am33xx_l3_s__l3_main,
929 &am43xx_l3_main__emif,
930 &am33xx_pruss__l3_main,
931 &am43xx_wkup_m3__l4_wkup,
932 &am33xx_gfx__l3_main,
933 &am43xx_l4_wkup__wkup_m3,
934 &am43xx_l4_wkup__control,
935 &am43xx_l4_wkup__smartreflex0,
936 &am43xx_l4_wkup__smartreflex1,
937 &am43xx_l4_wkup__uart1,
938 &am43xx_l4_wkup__timer1,
939 &am43xx_l4_wkup__i2c1,
940 &am43xx_l4_wkup__gpio0,
941 &am43xx_l4_wkup__wd_timer1,
942 &am43xx_l4_wkup__adc_tsc,
943 &am43xx_l3_s__qspi,
944 &am33xx_l4_per__dcan0,
945 &am33xx_l4_per__dcan1,
946 &am33xx_l4_per__gpio1,
947 &am33xx_l4_per__gpio2,
948 &am33xx_l4_per__gpio3,
949 &am33xx_l4_per__i2c2,
950 &am33xx_l4_per__i2c3,
951 &am33xx_l4_per__mailbox,
952 &am33xx_l4_per__rng,
953 &am33xx_l4_ls__mcasp0,
954 &am33xx_l4_ls__mcasp1,
955 &am33xx_l4_ls__mmc0,
956 &am33xx_l4_ls__mmc1,
957 &am33xx_l3_s__mmc2,
958 &am33xx_l4_ls__timer2,
959 &am33xx_l4_ls__timer3,
960 &am33xx_l4_ls__timer4,
961 &am33xx_l4_ls__timer5,
962 &am33xx_l4_ls__timer6,
963 &am33xx_l4_ls__timer7,
964 &am33xx_l3_main__tpcc,
965 &am33xx_l4_ls__uart2,
966 &am33xx_l4_ls__uart3,
967 &am33xx_l4_ls__uart4,
968 &am33xx_l4_ls__uart5,
969 &am33xx_l4_ls__uart6,
970 &am33xx_l4_ls__spinlock,
971 &am33xx_l4_ls__elm,
972 &am33xx_l4_ls__epwmss0,
973 &am33xx_l4_ls__epwmss1,
974 &am33xx_l4_ls__epwmss2,
975 &am33xx_l3_s__gpmc,
976 &am33xx_l4_ls__mcspi0,
977 &am33xx_l4_ls__mcspi1,
978 &am33xx_l3_main__tptc0,
979 &am33xx_l3_main__tptc1,
980 &am33xx_l3_main__tptc2,
981 &am33xx_l3_main__ocmc,
982 &am43xx_l4_hs__cpgmac0,
983 &am33xx_cpgmac0__mdio,
984 &am33xx_l3_main__sha0,
985 &am33xx_l3_main__aes0,
986 &am43xx_l3_main__des,
987 &am43xx_l4_ls__ocp2scp0,
988 &am43xx_l4_ls__ocp2scp1,
989 &am43xx_l3_s__usbotgss0,
990 &am43xx_l3_s__usbotgss1,
991 &am43xx_dss__l3_main,
992 &am43xx_l4_ls__dss,
993 &am43xx_l4_ls__dss_dispc,
994 &am43xx_l4_ls__dss_rfbi,
995 &am43xx_l4_ls__hdq1w,
996 &am43xx_l3__vpfe0,
997 &am43xx_l3__vpfe1,
998 &am43xx_l4_ls__vpfe0,
999 &am43xx_l4_ls__vpfe1,
1000 NULL,
1001};
1002
1003static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
1004 &am33xx_l4_wkup__rtc,
1005 NULL,
1006};
1007
1008int __init am43xx_hwmod_init(void)
1009{
1010 int ret;
1011
1012 omap_hwmod_am43xx_reg();
1013 omap_hwmod_init();
1014 ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
1015
1016 if (!ret && of_machine_is_compatible("ti,am4372"))
1017 ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
1018
1019 return ret;
1020}