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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * mtu3_core.c - hardware access layer and gadget init/exit of
4 * MediaTek usb3 Dual-Role Controller Driver
5 *
6 * Copyright (C) 2016 MediaTek Inc.
7 *
8 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
9 */
10
11#include <linux/dma-mapping.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <linux/platform_device.h>
17
18#include "mtu3.h"
19#include "mtu3_dr.h"
20#include "mtu3_debug.h"
21#include "mtu3_trace.h"
22
23static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
24{
25 struct mtu3_fifo_info *fifo = mep->fifo;
26 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
27 u32 start_bit;
28
29 /* ensure that @mep->fifo_seg_size is power of two */
30 num_bits = roundup_pow_of_two(num_bits);
31 if (num_bits > fifo->limit)
32 return -EINVAL;
33
34 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
35 num_bits = num_bits * (mep->slot + 1);
36 start_bit = bitmap_find_next_zero_area(fifo->bitmap,
37 fifo->limit, 0, num_bits, 0);
38 if (start_bit >= fifo->limit)
39 return -EOVERFLOW;
40
41 bitmap_set(fifo->bitmap, start_bit, num_bits);
42 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
43 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
44
45 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
46 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
47
48 return mep->fifo_addr;
49}
50
51static void ep_fifo_free(struct mtu3_ep *mep)
52{
53 struct mtu3_fifo_info *fifo = mep->fifo;
54 u32 addr = mep->fifo_addr;
55 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
56 u32 start_bit;
57
58 if (unlikely(addr < fifo->base || bits > fifo->limit))
59 return;
60
61 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
62 bitmap_clear(fifo->bitmap, start_bit, bits);
63 mep->fifo_size = 0;
64 mep->fifo_seg_size = 0;
65
66 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
67 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
68}
69
70/* enable/disable U3D SS function */
71static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
72{
73 /* If usb3_en==0, LTSSM will go to SS.Disable state */
74 if (enable)
75 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
76 else
77 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
78
79 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
80}
81
82/* set/clear U3D HS device soft connect */
83static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
84{
85 if (enable) {
86 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
87 SOFT_CONN | SUSPENDM_ENABLE);
88 } else {
89 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
90 SOFT_CONN | SUSPENDM_ENABLE);
91 }
92 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
93}
94
95/* only port0 of U2/U3 supports device mode */
96static int mtu3_device_enable(struct mtu3 *mtu)
97{
98 void __iomem *ibase = mtu->ippc_base;
99 u32 check_clk = 0;
100
101 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
102
103 if (mtu->u3_capable) {
104 check_clk = SSUSB_U3_MAC_RST_B_STS;
105 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
106 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
107 SSUSB_U3_PORT_HOST_SEL));
108 }
109 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
110 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
111 SSUSB_U2_PORT_HOST_SEL));
112
113 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
114 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
115 if (mtu->u3_capable)
116 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
117 SSUSB_U3_PORT_DUAL_MODE);
118 }
119
120 return ssusb_check_clocks(mtu->ssusb, check_clk);
121}
122
123static void mtu3_device_disable(struct mtu3 *mtu)
124{
125 void __iomem *ibase = mtu->ippc_base;
126
127 if (mtu->u3_capable)
128 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
129 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
130
131 mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
132 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
133
134 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
135 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
136 if (mtu->u3_capable)
137 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
138 SSUSB_U3_PORT_DUAL_MODE);
139 }
140
141 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
142}
143
144static void mtu3_dev_power_on(struct mtu3 *mtu)
145{
146 void __iomem *ibase = mtu->ippc_base;
147
148 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
149 if (mtu->u3_capable)
150 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN);
151
152 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN);
153}
154
155static void mtu3_dev_power_down(struct mtu3 *mtu)
156{
157 void __iomem *ibase = mtu->ippc_base;
158
159 if (mtu->u3_capable)
160 mtu3_setbits(ibase, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN);
161
162 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN);
163 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
164}
165
166/* reset U3D's device module. */
167static void mtu3_device_reset(struct mtu3 *mtu)
168{
169 void __iomem *ibase = mtu->ippc_base;
170
171 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
172 udelay(1);
173 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
174}
175
176static void mtu3_intr_status_clear(struct mtu3 *mtu)
177{
178 void __iomem *mbase = mtu->mac_base;
179
180 /* Clear EP0 and Tx/Rx EPn interrupts status */
181 mtu3_writel(mbase, U3D_EPISR, ~0x0);
182 /* Clear U2 USB common interrupts status */
183 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
184 /* Clear U3 LTSSM interrupts status */
185 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
186 /* Clear speed change interrupt status */
187 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
188 /* Clear QMU interrupt status */
189 mtu3_writel(mbase, U3D_QISAR0, ~0x0);
190}
191
192/* disable all interrupts */
193static void mtu3_intr_disable(struct mtu3 *mtu)
194{
195 /* Disable level 1 interrupts */
196 mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0);
197 /* Disable endpoint interrupts */
198 mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0);
199 mtu3_intr_status_clear(mtu);
200}
201
202/* enable system global interrupt */
203static void mtu3_intr_enable(struct mtu3 *mtu)
204{
205 void __iomem *mbase = mtu->mac_base;
206 u32 value;
207
208 /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
209 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
210 mtu3_writel(mbase, U3D_LV1IESR, value);
211
212 /* Enable U2 common USB interrupts */
213 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
214 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
215
216 if (mtu->u3_capable) {
217 /* Enable U3 LTSSM interrupts */
218 value = HOT_RST_INTR | WARM_RST_INTR |
219 ENTER_U3_INTR | EXIT_U3_INTR;
220 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
221 }
222
223 /* Enable QMU interrupts. */
224 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
225 RXQ_LENERR_INT | RXQ_ZLPERR_INT;
226 mtu3_writel(mbase, U3D_QIESR1, value);
227
228 /* Enable speed change interrupt */
229 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
230}
231
232static void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed)
233{
234 void __iomem *mbase = mtu->mac_base;
235
236 if (speed > mtu->max_speed)
237 speed = mtu->max_speed;
238
239 switch (speed) {
240 case USB_SPEED_FULL:
241 /* disable U3 SS function */
242 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
243 /* disable HS function */
244 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
245 break;
246 case USB_SPEED_HIGH:
247 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
248 /* HS/FS detected by HW */
249 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
250 break;
251 case USB_SPEED_SUPER:
252 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
253 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
254 SSUSB_U3_PORT_SSP_SPEED);
255 break;
256 case USB_SPEED_SUPER_PLUS:
257 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
258 mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
259 SSUSB_U3_PORT_SSP_SPEED);
260 break;
261 default:
262 dev_err(mtu->dev, "invalid speed: %s\n",
263 usb_speed_string(speed));
264 return;
265 }
266
267 mtu->speed = speed;
268 dev_dbg(mtu->dev, "set speed: %s\n", usb_speed_string(speed));
269}
270
271/* CSR registers will be reset to default value if port is disabled */
272static void mtu3_csr_init(struct mtu3 *mtu)
273{
274 void __iomem *mbase = mtu->mac_base;
275
276 if (mtu->u3_capable) {
277 /* disable LGO_U1/U2 by default */
278 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
279 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
280 /* enable accept LGO_U1/U2 link command from host */
281 mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
282 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
283 /* device responses to u3_exit from host automatically */
284 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
285 /* automatically build U2 link when U3 detect fail */
286 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
287 /* auto clear SOFT_CONN when clear USB3_EN if work as HS */
288 mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
289 }
290
291 /* delay about 0.1us from detecting reset to send chirp-K */
292 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
293 /* enable automatical HWRW from L1 */
294 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
295}
296
297/* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
298static void mtu3_ep_reset(struct mtu3_ep *mep)
299{
300 struct mtu3 *mtu = mep->mtu;
301 u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
302
303 mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
304 mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
305}
306
307/* set/clear the stall and toggle bits for non-ep0 */
308void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
309{
310 struct mtu3 *mtu = mep->mtu;
311 void __iomem *mbase = mtu->mac_base;
312 u8 epnum = mep->epnum;
313 u32 csr;
314
315 if (mep->is_in) { /* TX */
316 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
317 if (set)
318 csr |= TX_SENDSTALL;
319 else
320 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
321 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
322 } else { /* RX */
323 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
324 if (set)
325 csr |= RX_SENDSTALL;
326 else
327 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
328 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
329 }
330
331 if (!set) {
332 mtu3_ep_reset(mep);
333 mep->flags &= ~MTU3_EP_STALL;
334 } else {
335 mep->flags |= MTU3_EP_STALL;
336 }
337
338 dev_dbg(mtu->dev, "%s: %s\n", mep->name,
339 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
340}
341
342void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
343{
344 if (mtu->u3_capable && mtu->speed >= USB_SPEED_SUPER)
345 mtu3_ss_func_set(mtu, is_on);
346 else
347 mtu3_hs_softconn_set(mtu, is_on);
348
349 dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
350 usb_speed_string(mtu->speed), is_on ? "+" : "-");
351}
352
353void mtu3_start(struct mtu3 *mtu)
354{
355 void __iomem *mbase = mtu->mac_base;
356
357 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
358 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
359
360 mtu3_dev_power_on(mtu);
361 mtu3_csr_init(mtu);
362 mtu3_set_speed(mtu, mtu->speed);
363
364 /* Initialize the default interrupts */
365 mtu3_intr_enable(mtu);
366 mtu->is_active = 1;
367
368 if (mtu->softconnect)
369 mtu3_dev_on_off(mtu, 1);
370}
371
372void mtu3_stop(struct mtu3 *mtu)
373{
374 dev_dbg(mtu->dev, "%s\n", __func__);
375
376 mtu3_intr_disable(mtu);
377
378 if (mtu->softconnect)
379 mtu3_dev_on_off(mtu, 0);
380
381 mtu->is_active = 0;
382 mtu3_dev_power_down(mtu);
383}
384
385static void mtu3_dev_suspend(struct mtu3 *mtu)
386{
387 if (!mtu->is_active)
388 return;
389
390 mtu3_intr_disable(mtu);
391 mtu3_dev_power_down(mtu);
392}
393
394static void mtu3_dev_resume(struct mtu3 *mtu)
395{
396 if (!mtu->is_active)
397 return;
398
399 mtu3_dev_power_on(mtu);
400 mtu3_intr_enable(mtu);
401}
402
403/* for non-ep0 */
404int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
405 int interval, int burst, int mult)
406{
407 void __iomem *mbase = mtu->mac_base;
408 bool gen2cp = mtu->gen2cp;
409 int epnum = mep->epnum;
410 u32 csr0, csr1, csr2;
411 int fifo_sgsz, fifo_addr;
412 int num_pkts;
413
414 fifo_addr = ep_fifo_alloc(mep, mep->maxp);
415 if (fifo_addr < 0) {
416 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
417 return -ENOMEM;
418 }
419 fifo_sgsz = ilog2(mep->fifo_seg_size);
420 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
421 mep->fifo_seg_size, mep->fifo_size);
422
423 if (mep->is_in) {
424 csr0 = TX_TXMAXPKTSZ(mep->maxp);
425 csr0 |= TX_DMAREQEN;
426
427 num_pkts = (burst + 1) * (mult + 1) - 1;
428 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
429 csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
430
431 csr2 = TX_FIFOADDR(fifo_addr >> 4);
432 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
433
434 switch (mep->type) {
435 case USB_ENDPOINT_XFER_BULK:
436 csr1 |= TX_TYPE(TYPE_BULK);
437 break;
438 case USB_ENDPOINT_XFER_ISOC:
439 csr1 |= TX_TYPE(TYPE_ISO);
440 csr2 |= TX_BINTERVAL(interval);
441 break;
442 case USB_ENDPOINT_XFER_INT:
443 csr1 |= TX_TYPE(TYPE_INT);
444 csr2 |= TX_BINTERVAL(interval);
445 break;
446 }
447
448 /* Enable QMU Done interrupt */
449 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
450
451 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
452 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
453 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
454
455 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
456 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
457 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
458 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
459 } else {
460 csr0 = RX_RXMAXPKTSZ(mep->maxp);
461 csr0 |= RX_DMAREQEN;
462
463 num_pkts = (burst + 1) * (mult + 1) - 1;
464 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
465 csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
466
467 csr2 = RX_FIFOADDR(fifo_addr >> 4);
468 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
469
470 switch (mep->type) {
471 case USB_ENDPOINT_XFER_BULK:
472 csr1 |= RX_TYPE(TYPE_BULK);
473 break;
474 case USB_ENDPOINT_XFER_ISOC:
475 csr1 |= RX_TYPE(TYPE_ISO);
476 csr2 |= RX_BINTERVAL(interval);
477 break;
478 case USB_ENDPOINT_XFER_INT:
479 csr1 |= RX_TYPE(TYPE_INT);
480 csr2 |= RX_BINTERVAL(interval);
481 break;
482 }
483
484 /*Enable QMU Done interrupt */
485 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
486
487 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
488 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
489 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
490
491 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
492 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
493 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
494 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
495 }
496
497 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
498 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
499 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
500 fifo_sgsz, mep->fifo_seg_size);
501
502 return 0;
503}
504
505/* for non-ep0 */
506void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
507{
508 void __iomem *mbase = mtu->mac_base;
509 int epnum = mep->epnum;
510
511 if (mep->is_in) {
512 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
513 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
514 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
515 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
516 } else {
517 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
518 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
519 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
520 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
521 }
522
523 mtu3_ep_reset(mep);
524 ep_fifo_free(mep);
525
526 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
527}
528
529/*
530 * Two scenarios:
531 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
532 * are separated;
533 * 2. when supports only HS, the fifo is shared for all EPs, and
534 * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
535 * the total fifo size of non-ep0, and ep0's is fixed to 64B,
536 * so the total fifo size is 64B + @EPNTXFFSZ;
537 * Due to the first 64B should be reserved for EP0, non-ep0's fifo
538 * starts from offset 64 and are divided into two equal parts for
539 * TX or RX EPs for simplification.
540 */
541static void get_ep_fifo_config(struct mtu3 *mtu)
542{
543 struct mtu3_fifo_info *tx_fifo;
544 struct mtu3_fifo_info *rx_fifo;
545 u32 fifosize;
546
547 if (mtu->separate_fifo) {
548 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
549 tx_fifo = &mtu->tx_fifo;
550 tx_fifo->base = 0;
551 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
552 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
553
554 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
555 rx_fifo = &mtu->rx_fifo;
556 rx_fifo->base = 0;
557 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
558 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
559 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
560 } else {
561 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
562 tx_fifo = &mtu->tx_fifo;
563 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
564 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
565 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
566
567 rx_fifo = &mtu->rx_fifo;
568 rx_fifo->base =
569 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
570 rx_fifo->limit = tx_fifo->limit;
571 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
572 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
573 }
574
575 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
576 __func__, tx_fifo->base, tx_fifo->limit,
577 rx_fifo->base, rx_fifo->limit);
578}
579
580static void mtu3_ep0_setup(struct mtu3 *mtu)
581{
582 u32 maxpacket = mtu->g.ep0->maxpacket;
583 u32 csr;
584
585 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
586
587 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
588 csr &= ~EP0_MAXPKTSZ_MSK;
589 csr |= EP0_MAXPKTSZ(maxpacket);
590 csr &= EP0_W1C_BITS;
591 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
592
593 /* Enable EP0 interrupt */
594 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
595}
596
597static int mtu3_mem_alloc(struct mtu3 *mtu)
598{
599 void __iomem *mbase = mtu->mac_base;
600 struct mtu3_ep *ep_array;
601 int in_ep_num, out_ep_num;
602 u32 cap_epinfo;
603 int ret;
604 int i;
605
606 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
607 in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
608 out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
609
610 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
611 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
612 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
613
614 /* one for ep0, another is reserved */
615 mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
616 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
617 if (ep_array == NULL)
618 return -ENOMEM;
619
620 mtu->ep_array = ep_array;
621 mtu->in_eps = ep_array;
622 mtu->out_eps = &ep_array[mtu->num_eps];
623 /* ep0 uses in_eps[0], out_eps[0] is reserved */
624 mtu->ep0 = mtu->in_eps;
625 mtu->ep0->mtu = mtu;
626 mtu->ep0->epnum = 0;
627
628 for (i = 1; i < mtu->num_eps; i++) {
629 struct mtu3_ep *mep = mtu->in_eps + i;
630
631 mep->fifo = &mtu->tx_fifo;
632 mep = mtu->out_eps + i;
633 mep->fifo = &mtu->rx_fifo;
634 }
635
636 get_ep_fifo_config(mtu);
637
638 ret = mtu3_qmu_init(mtu);
639 if (ret)
640 kfree(mtu->ep_array);
641
642 return ret;
643}
644
645static void mtu3_mem_free(struct mtu3 *mtu)
646{
647 mtu3_qmu_exit(mtu);
648 kfree(mtu->ep_array);
649}
650
651static void mtu3_regs_init(struct mtu3 *mtu)
652{
653 void __iomem *mbase = mtu->mac_base;
654
655 /* be sure interrupts are disabled before registration of ISR */
656 mtu3_intr_disable(mtu);
657
658 mtu3_csr_init(mtu);
659
660 /* U2/U3 detected by HW */
661 mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
662 /* vbus detected by HW */
663 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
664 /* use new QMU format when HW version >= 0x1003 */
665 if (mtu->gen2cp)
666 mtu3_writel(mbase, U3D_QFCR, ~0x0);
667}
668
669static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
670{
671 void __iomem *mbase = mtu->mac_base;
672 enum usb_device_speed udev_speed;
673 u32 maxpkt = 64;
674 u32 link;
675 u32 speed;
676
677 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
678 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
679 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
680 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
681
682 if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
683 return IRQ_NONE;
684
685 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
686
687 switch (speed) {
688 case MTU3_SPEED_FULL:
689 udev_speed = USB_SPEED_FULL;
690 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
691 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
692 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
693 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
694 LPM_BESL_STALL | LPM_BESLD_STALL);
695 break;
696 case MTU3_SPEED_HIGH:
697 udev_speed = USB_SPEED_HIGH;
698 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
699 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
700 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
701 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
702 LPM_BESL_STALL | LPM_BESLD_STALL);
703 break;
704 case MTU3_SPEED_SUPER:
705 udev_speed = USB_SPEED_SUPER;
706 maxpkt = 512;
707 break;
708 case MTU3_SPEED_SUPER_PLUS:
709 udev_speed = USB_SPEED_SUPER_PLUS;
710 maxpkt = 512;
711 break;
712 default:
713 udev_speed = USB_SPEED_UNKNOWN;
714 break;
715 }
716 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
717 mtu3_dbg_trace(mtu->dev, "link speed %s",
718 usb_speed_string(udev_speed));
719
720 mtu->g.speed = udev_speed;
721 mtu->g.ep0->maxpacket = maxpkt;
722 mtu->ep0_state = MU3D_EP0_STATE_SETUP;
723 mtu->connected = !!(udev_speed != USB_SPEED_UNKNOWN);
724
725 if (udev_speed == USB_SPEED_UNKNOWN) {
726 mtu3_gadget_disconnect(mtu);
727 pm_runtime_put(mtu->dev);
728 } else {
729 pm_runtime_get(mtu->dev);
730 mtu3_ep0_setup(mtu);
731 }
732
733 return IRQ_HANDLED;
734}
735
736static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
737{
738 void __iomem *mbase = mtu->mac_base;
739 u32 ltssm;
740
741 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
742 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
743 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
744 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
745 trace_mtu3_u3_ltssm_isr(ltssm);
746
747 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
748 mtu3_gadget_reset(mtu);
749
750 if (ltssm & VBUS_FALL_INTR) {
751 mtu3_ss_func_set(mtu, false);
752 mtu3_gadget_reset(mtu);
753 }
754
755 if (ltssm & VBUS_RISE_INTR)
756 mtu3_ss_func_set(mtu, true);
757
758 if (ltssm & EXIT_U3_INTR)
759 mtu3_gadget_resume(mtu);
760
761 if (ltssm & ENTER_U3_INTR)
762 mtu3_gadget_suspend(mtu);
763
764 return IRQ_HANDLED;
765}
766
767static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
768{
769 void __iomem *mbase = mtu->mac_base;
770 u32 u2comm;
771
772 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
773 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
774 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
775 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
776 trace_mtu3_u2_common_isr(u2comm);
777
778 if (u2comm & SUSPEND_INTR)
779 mtu3_gadget_suspend(mtu);
780
781 if (u2comm & RESUME_INTR)
782 mtu3_gadget_resume(mtu);
783
784 if (u2comm & RESET_INTR)
785 mtu3_gadget_reset(mtu);
786
787 return IRQ_HANDLED;
788}
789
790static irqreturn_t mtu3_irq(int irq, void *data)
791{
792 struct mtu3 *mtu = (struct mtu3 *)data;
793 unsigned long flags;
794 u32 level1;
795
796 spin_lock_irqsave(&mtu->lock, flags);
797
798 /* U3D_LV1ISR is RU */
799 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
800 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
801
802 if (level1 & EP_CTRL_INTR)
803 mtu3_link_isr(mtu);
804
805 if (level1 & MAC2_INTR)
806 mtu3_u2_common_isr(mtu);
807
808 if (level1 & MAC3_INTR)
809 mtu3_u3_ltssm_isr(mtu);
810
811 if (level1 & BMU_INTR)
812 mtu3_ep0_isr(mtu);
813
814 if (level1 & QMU_INTR)
815 mtu3_qmu_isr(mtu);
816
817 spin_unlock_irqrestore(&mtu->lock, flags);
818
819 return IRQ_HANDLED;
820}
821
822static void mtu3_check_params(struct mtu3 *mtu)
823{
824 /* device's u3 port (port0) is disabled */
825 if (mtu->u3_capable && (mtu->ssusb->u3p_dis_msk & BIT(0)))
826 mtu->u3_capable = 0;
827
828 /* check the max_speed parameter */
829 switch (mtu->max_speed) {
830 case USB_SPEED_FULL:
831 case USB_SPEED_HIGH:
832 case USB_SPEED_SUPER:
833 case USB_SPEED_SUPER_PLUS:
834 break;
835 default:
836 dev_err(mtu->dev, "invalid max_speed: %s\n",
837 usb_speed_string(mtu->max_speed));
838 fallthrough;
839 case USB_SPEED_UNKNOWN:
840 /* default as SSP */
841 mtu->max_speed = USB_SPEED_SUPER_PLUS;
842 break;
843 }
844
845 if (!mtu->u3_capable && (mtu->max_speed > USB_SPEED_HIGH))
846 mtu->max_speed = USB_SPEED_HIGH;
847
848 mtu->speed = mtu->max_speed;
849
850 dev_info(mtu->dev, "max_speed: %s\n",
851 usb_speed_string(mtu->max_speed));
852}
853
854static int mtu3_hw_init(struct mtu3 *mtu)
855{
856 u32 value;
857 int ret;
858
859 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
860 mtu->hw_version = IP_TRUNK_VERS(value);
861 mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
862
863 value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
864 mtu->u3_capable = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
865 /* usb3 ip uses separate fifo */
866 mtu->separate_fifo = mtu->u3_capable;
867
868 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
869 mtu->u3_capable ? "U3" : "U2");
870
871 mtu3_check_params(mtu);
872
873 mtu3_device_reset(mtu);
874
875 ret = mtu3_device_enable(mtu);
876 if (ret) {
877 dev_err(mtu->dev, "device enable failed %d\n", ret);
878 return ret;
879 }
880
881 ret = mtu3_mem_alloc(mtu);
882 if (ret)
883 return -ENOMEM;
884
885 mtu3_regs_init(mtu);
886
887 return 0;
888}
889
890static void mtu3_hw_exit(struct mtu3 *mtu)
891{
892 mtu3_device_disable(mtu);
893 mtu3_mem_free(mtu);
894}
895
896/*
897 * we set 32-bit DMA mask by default, here check whether the controller
898 * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
899 */
900static int mtu3_set_dma_mask(struct mtu3 *mtu)
901{
902 struct device *dev = mtu->dev;
903 bool is_36bit = false;
904 int ret = 0;
905 u32 value;
906
907 value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
908 if (value & DMA_ADDR_36BIT) {
909 is_36bit = true;
910 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
911 /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
912 if (ret) {
913 is_36bit = false;
914 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
915 }
916 }
917 dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
918
919 return ret;
920}
921
922int ssusb_gadget_init(struct ssusb_mtk *ssusb)
923{
924 struct device *dev = ssusb->dev;
925 struct platform_device *pdev = to_platform_device(dev);
926 struct mtu3 *mtu = NULL;
927 int ret = -ENOMEM;
928
929 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
930 if (mtu == NULL)
931 return -ENOMEM;
932
933 mtu->irq = platform_get_irq_byname_optional(pdev, "device");
934 if (mtu->irq < 0) {
935 if (mtu->irq == -EPROBE_DEFER)
936 return mtu->irq;
937
938 /* for backward compatibility */
939 mtu->irq = platform_get_irq(pdev, 0);
940 if (mtu->irq < 0)
941 return mtu->irq;
942 }
943 dev_info(dev, "irq %d\n", mtu->irq);
944
945 mtu->mac_base = devm_platform_ioremap_resource_byname(pdev, "mac");
946 if (IS_ERR(mtu->mac_base)) {
947 dev_err(dev, "error mapping memory for dev mac\n");
948 return PTR_ERR(mtu->mac_base);
949 }
950
951 spin_lock_init(&mtu->lock);
952 mtu->dev = dev;
953 mtu->ippc_base = ssusb->ippc_base;
954 ssusb->mac_base = mtu->mac_base;
955 ssusb->u3d = mtu;
956 mtu->ssusb = ssusb;
957 mtu->max_speed = usb_get_maximum_speed(dev);
958
959 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
960 mtu->mac_base, mtu->ippc_base);
961
962 ret = mtu3_hw_init(mtu);
963 if (ret) {
964 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
965 return ret;
966 }
967
968 ret = mtu3_set_dma_mask(mtu);
969 if (ret) {
970 dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
971 goto dma_mask_err;
972 }
973
974 ret = devm_request_threaded_irq(dev, mtu->irq, NULL, mtu3_irq,
975 IRQF_ONESHOT, dev_name(dev), mtu);
976 if (ret) {
977 dev_err(dev, "request irq %d failed!\n", mtu->irq);
978 goto irq_err;
979 }
980
981 /* power down device IP for power saving by default */
982 mtu3_stop(mtu);
983
984 ret = mtu3_gadget_setup(mtu);
985 if (ret) {
986 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
987 goto gadget_err;
988 }
989
990 ssusb_dev_debugfs_init(ssusb);
991
992 dev_dbg(dev, " %s() done...\n", __func__);
993
994 return 0;
995
996gadget_err:
997 device_init_wakeup(dev, false);
998
999dma_mask_err:
1000irq_err:
1001 mtu3_hw_exit(mtu);
1002 ssusb->u3d = NULL;
1003 dev_err(dev, " %s() fail...\n", __func__);
1004
1005 return ret;
1006}
1007
1008void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
1009{
1010 struct mtu3 *mtu = ssusb->u3d;
1011
1012 mtu3_gadget_cleanup(mtu);
1013 device_init_wakeup(ssusb->dev, false);
1014 mtu3_hw_exit(mtu);
1015}
1016
1017bool ssusb_gadget_ip_sleep_check(struct ssusb_mtk *ssusb)
1018{
1019 struct mtu3 *mtu = ssusb->u3d;
1020
1021 /* host only, should wait for ip sleep */
1022 if (!mtu)
1023 return true;
1024
1025 /* device is started and pullup D+, ip can sleep */
1026 if (mtu->is_active && mtu->softconnect)
1027 return true;
1028
1029 /* ip can't sleep if not pullup D+ when support device mode */
1030 return false;
1031}
1032
1033int ssusb_gadget_suspend(struct ssusb_mtk *ssusb, pm_message_t msg)
1034{
1035 struct mtu3 *mtu = ssusb->u3d;
1036
1037 if (!mtu->gadget_driver)
1038 return 0;
1039
1040 if (mtu->connected)
1041 return -EBUSY;
1042
1043 mtu3_dev_suspend(mtu);
1044 synchronize_irq(mtu->irq);
1045
1046 return 0;
1047}
1048
1049int ssusb_gadget_resume(struct ssusb_mtk *ssusb, pm_message_t msg)
1050{
1051 struct mtu3 *mtu = ssusb->u3d;
1052
1053 if (!mtu->gadget_driver)
1054 return 0;
1055
1056 mtu3_dev_resume(mtu);
1057
1058 return 0;
1059}
1/*
2 * mtu3_core.c - hardware access layer and gadget init/exit of
3 * MediaTek usb3 Dual-Role Controller Driver
4 *
5 * Copyright (C) 2016 MediaTek Inc.
6 *
7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24#include <linux/platform_device.h>
25
26#include "mtu3.h"
27
28static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
29{
30 struct mtu3_fifo_info *fifo = mep->fifo;
31 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
32 u32 start_bit;
33
34 /* ensure that @mep->fifo_seg_size is power of two */
35 num_bits = roundup_pow_of_two(num_bits);
36 if (num_bits > fifo->limit)
37 return -EINVAL;
38
39 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
40 num_bits = num_bits * (mep->slot + 1);
41 start_bit = bitmap_find_next_zero_area(fifo->bitmap,
42 fifo->limit, 0, num_bits, 0);
43 if (start_bit >= fifo->limit)
44 return -EOVERFLOW;
45
46 bitmap_set(fifo->bitmap, start_bit, num_bits);
47 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
48 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
49
50 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
51 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
52
53 return mep->fifo_addr;
54}
55
56static void ep_fifo_free(struct mtu3_ep *mep)
57{
58 struct mtu3_fifo_info *fifo = mep->fifo;
59 u32 addr = mep->fifo_addr;
60 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
61 u32 start_bit;
62
63 if (unlikely(addr < fifo->base || bits > fifo->limit))
64 return;
65
66 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
67 bitmap_clear(fifo->bitmap, start_bit, bits);
68 mep->fifo_size = 0;
69 mep->fifo_seg_size = 0;
70
71 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
72 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
73}
74
75/* enable/disable U3D SS function */
76static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
77{
78 /* If usb3_en==0, LTSSM will go to SS.Disable state */
79 if (enable)
80 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
81 else
82 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
83
84 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
85}
86
87/* set/clear U3D HS device soft connect */
88static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
89{
90 if (enable) {
91 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
92 SOFT_CONN | SUSPENDM_ENABLE);
93 } else {
94 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
95 SOFT_CONN | SUSPENDM_ENABLE);
96 }
97 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
98}
99
100/* only port0 of U2/U3 supports device mode */
101static int mtu3_device_enable(struct mtu3 *mtu)
102{
103 void __iomem *ibase = mtu->ippc_base;
104 u32 check_clk = 0;
105
106 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
107
108 if (mtu->is_u3_ip) {
109 check_clk = SSUSB_U3_MAC_RST_B_STS;
110 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
111 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
112 SSUSB_U3_PORT_HOST_SEL));
113 }
114 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
115 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
116 SSUSB_U2_PORT_HOST_SEL));
117 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
118
119 return ssusb_check_clocks(mtu->ssusb, check_clk);
120}
121
122static void mtu3_device_disable(struct mtu3 *mtu)
123{
124 void __iomem *ibase = mtu->ippc_base;
125
126 if (mtu->is_u3_ip)
127 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
128 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
129
130 mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
131 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
132 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
133 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
134}
135
136/* reset U3D's device module. */
137static void mtu3_device_reset(struct mtu3 *mtu)
138{
139 void __iomem *ibase = mtu->ippc_base;
140
141 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
142 udelay(1);
143 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
144}
145
146/* disable all interrupts */
147static void mtu3_intr_disable(struct mtu3 *mtu)
148{
149 void __iomem *mbase = mtu->mac_base;
150
151 /* Disable level 1 interrupts */
152 mtu3_writel(mbase, U3D_LV1IECR, ~0x0);
153 /* Disable endpoint interrupts */
154 mtu3_writel(mbase, U3D_EPIECR, ~0x0);
155}
156
157static void mtu3_intr_status_clear(struct mtu3 *mtu)
158{
159 void __iomem *mbase = mtu->mac_base;
160
161 /* Clear EP0 and Tx/Rx EPn interrupts status */
162 mtu3_writel(mbase, U3D_EPISR, ~0x0);
163 /* Clear U2 USB common interrupts status */
164 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
165 /* Clear U3 LTSSM interrupts status */
166 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
167 /* Clear speed change interrupt status */
168 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
169}
170
171/* enable system global interrupt */
172static void mtu3_intr_enable(struct mtu3 *mtu)
173{
174 void __iomem *mbase = mtu->mac_base;
175 u32 value;
176
177 /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
178 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
179 mtu3_writel(mbase, U3D_LV1IESR, value);
180
181 /* Enable U2 common USB interrupts */
182 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
183 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
184
185 if (mtu->is_u3_ip) {
186 /* Enable U3 LTSSM interrupts */
187 value = HOT_RST_INTR | WARM_RST_INTR | VBUS_RISE_INTR |
188 VBUS_FALL_INTR | ENTER_U3_INTR | EXIT_U3_INTR;
189 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
190 }
191
192 /* Enable QMU interrupts. */
193 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
194 RXQ_LENERR_INT | RXQ_ZLPERR_INT;
195 mtu3_writel(mbase, U3D_QIESR1, value);
196
197 /* Enable speed change interrupt */
198 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
199}
200
201/* set/clear the stall and toggle bits for non-ep0 */
202void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
203{
204 struct mtu3 *mtu = mep->mtu;
205 void __iomem *mbase = mtu->mac_base;
206 u8 epnum = mep->epnum;
207 u32 csr;
208
209 if (mep->is_in) { /* TX */
210 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
211 if (set)
212 csr |= TX_SENDSTALL;
213 else
214 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
215 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
216 } else { /* RX */
217 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
218 if (set)
219 csr |= RX_SENDSTALL;
220 else
221 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
222 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
223 }
224
225 if (!set) {
226 mtu3_setbits(mbase, U3D_EP_RST, EP_RST(mep->is_in, epnum));
227 mtu3_clrbits(mbase, U3D_EP_RST, EP_RST(mep->is_in, epnum));
228 mep->flags &= ~MTU3_EP_STALL;
229 } else {
230 mep->flags |= MTU3_EP_STALL;
231 }
232
233 dev_dbg(mtu->dev, "%s: %s\n", mep->name,
234 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
235}
236
237void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
238{
239 if (mtu->is_u3_ip && (mtu->max_speed == USB_SPEED_SUPER))
240 mtu3_ss_func_set(mtu, is_on);
241 else
242 mtu3_hs_softconn_set(mtu, is_on);
243
244 dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
245 usb_speed_string(mtu->max_speed), is_on ? "+" : "-");
246}
247
248void mtu3_start(struct mtu3 *mtu)
249{
250 void __iomem *mbase = mtu->mac_base;
251
252 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
253 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
254
255 mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
256
257 /*
258 * When disable U2 port, USB2_CSR's register will be reset to
259 * default value after re-enable it again(HS is enabled by default).
260 * So if force mac to work as FS, disable HS function.
261 */
262 if (mtu->max_speed == USB_SPEED_FULL)
263 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
264
265 /* Initialize the default interrupts */
266 mtu3_intr_enable(mtu);
267 mtu->is_active = 1;
268
269 if (mtu->softconnect)
270 mtu3_dev_on_off(mtu, 1);
271}
272
273void mtu3_stop(struct mtu3 *mtu)
274{
275 dev_dbg(mtu->dev, "%s\n", __func__);
276
277 mtu3_intr_disable(mtu);
278 mtu3_intr_status_clear(mtu);
279
280 if (mtu->softconnect)
281 mtu3_dev_on_off(mtu, 0);
282
283 mtu->is_active = 0;
284 mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
285}
286
287/* for non-ep0 */
288int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
289 int interval, int burst, int mult)
290{
291 void __iomem *mbase = mtu->mac_base;
292 int epnum = mep->epnum;
293 u32 csr0, csr1, csr2;
294 int fifo_sgsz, fifo_addr;
295 int num_pkts;
296
297 fifo_addr = ep_fifo_alloc(mep, mep->maxp);
298 if (fifo_addr < 0) {
299 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
300 return -ENOMEM;
301 }
302 fifo_sgsz = ilog2(mep->fifo_seg_size);
303 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
304 mep->fifo_seg_size, mep->fifo_size);
305
306 if (mep->is_in) {
307 csr0 = TX_TXMAXPKTSZ(mep->maxp);
308 csr0 |= TX_DMAREQEN;
309
310 num_pkts = (burst + 1) * (mult + 1) - 1;
311 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
312 csr1 |= TX_MAX_PKT(num_pkts) | TX_MULT(mult);
313
314 csr2 = TX_FIFOADDR(fifo_addr >> 4);
315 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
316
317 switch (mep->type) {
318 case USB_ENDPOINT_XFER_BULK:
319 csr1 |= TX_TYPE(TYPE_BULK);
320 break;
321 case USB_ENDPOINT_XFER_ISOC:
322 csr1 |= TX_TYPE(TYPE_ISO);
323 csr2 |= TX_BINTERVAL(interval);
324 break;
325 case USB_ENDPOINT_XFER_INT:
326 csr1 |= TX_TYPE(TYPE_INT);
327 csr2 |= TX_BINTERVAL(interval);
328 break;
329 }
330
331 /* Enable QMU Done interrupt */
332 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
333
334 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
335 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
336 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
337
338 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
339 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
340 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
341 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
342 } else {
343 csr0 = RX_RXMAXPKTSZ(mep->maxp);
344 csr0 |= RX_DMAREQEN;
345
346 num_pkts = (burst + 1) * (mult + 1) - 1;
347 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
348 csr1 |= RX_MAX_PKT(num_pkts) | RX_MULT(mult);
349
350 csr2 = RX_FIFOADDR(fifo_addr >> 4);
351 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
352
353 switch (mep->type) {
354 case USB_ENDPOINT_XFER_BULK:
355 csr1 |= RX_TYPE(TYPE_BULK);
356 break;
357 case USB_ENDPOINT_XFER_ISOC:
358 csr1 |= RX_TYPE(TYPE_ISO);
359 csr2 |= RX_BINTERVAL(interval);
360 break;
361 case USB_ENDPOINT_XFER_INT:
362 csr1 |= RX_TYPE(TYPE_INT);
363 csr2 |= RX_BINTERVAL(interval);
364 break;
365 }
366
367 /*Enable QMU Done interrupt */
368 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
369
370 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
371 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
372 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
373
374 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
375 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
376 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
377 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
378 }
379
380 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
381 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
382 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
383 fifo_sgsz, mep->fifo_seg_size);
384
385 return 0;
386}
387
388/* for non-ep0 */
389void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
390{
391 void __iomem *mbase = mtu->mac_base;
392 int epnum = mep->epnum;
393
394 if (mep->is_in) {
395 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
396 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
397 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
398 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
399 } else {
400 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
401 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
402 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
403 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
404 }
405
406 ep_fifo_free(mep);
407
408 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
409}
410
411/*
412 * Two scenarios:
413 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
414 * are separated;
415 * 2. when supports only HS, the fifo is shared for all EPs, and
416 * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
417 * the total fifo size of non-ep0, and ep0's is fixed to 64B,
418 * so the total fifo size is 64B + @EPNTXFFSZ;
419 * Due to the first 64B should be reserved for EP0, non-ep0's fifo
420 * starts from offset 64 and are divided into two equal parts for
421 * TX or RX EPs for simplification.
422 */
423static void get_ep_fifo_config(struct mtu3 *mtu)
424{
425 struct mtu3_fifo_info *tx_fifo;
426 struct mtu3_fifo_info *rx_fifo;
427 u32 fifosize;
428
429 if (mtu->is_u3_ip) {
430 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
431 tx_fifo = &mtu->tx_fifo;
432 tx_fifo->base = 0;
433 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
434 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
435
436 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
437 rx_fifo = &mtu->rx_fifo;
438 rx_fifo->base = 0;
439 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
440 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
441 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
442 } else {
443 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
444 tx_fifo = &mtu->tx_fifo;
445 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
446 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
447 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
448
449 rx_fifo = &mtu->rx_fifo;
450 rx_fifo->base =
451 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
452 rx_fifo->limit = tx_fifo->limit;
453 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
454 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
455 }
456
457 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
458 __func__, tx_fifo->base, tx_fifo->limit,
459 rx_fifo->base, rx_fifo->limit);
460}
461
462void mtu3_ep0_setup(struct mtu3 *mtu)
463{
464 u32 maxpacket = mtu->g.ep0->maxpacket;
465 u32 csr;
466
467 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
468
469 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
470 csr &= ~EP0_MAXPKTSZ_MSK;
471 csr |= EP0_MAXPKTSZ(maxpacket);
472 csr &= EP0_W1C_BITS;
473 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
474
475 /* Enable EP0 interrupt */
476 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR);
477}
478
479static int mtu3_mem_alloc(struct mtu3 *mtu)
480{
481 void __iomem *mbase = mtu->mac_base;
482 struct mtu3_ep *ep_array;
483 int in_ep_num, out_ep_num;
484 u32 cap_epinfo;
485 int ret;
486 int i;
487
488 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
489 in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
490 out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
491
492 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
493 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
494 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
495
496 /* one for ep0, another is reserved */
497 mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
498 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
499 if (ep_array == NULL)
500 return -ENOMEM;
501
502 mtu->ep_array = ep_array;
503 mtu->in_eps = ep_array;
504 mtu->out_eps = &ep_array[mtu->num_eps];
505 /* ep0 uses in_eps[0], out_eps[0] is reserved */
506 mtu->ep0 = mtu->in_eps;
507 mtu->ep0->mtu = mtu;
508 mtu->ep0->epnum = 0;
509
510 for (i = 1; i < mtu->num_eps; i++) {
511 struct mtu3_ep *mep = mtu->in_eps + i;
512
513 mep->fifo = &mtu->tx_fifo;
514 mep = mtu->out_eps + i;
515 mep->fifo = &mtu->rx_fifo;
516 }
517
518 get_ep_fifo_config(mtu);
519
520 ret = mtu3_qmu_init(mtu);
521 if (ret)
522 kfree(mtu->ep_array);
523
524 return ret;
525}
526
527static void mtu3_mem_free(struct mtu3 *mtu)
528{
529 mtu3_qmu_exit(mtu);
530 kfree(mtu->ep_array);
531}
532
533static void mtu3_set_speed(struct mtu3 *mtu)
534{
535 void __iomem *mbase = mtu->mac_base;
536
537 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
538 mtu->max_speed = USB_SPEED_HIGH;
539
540 if (mtu->max_speed == USB_SPEED_FULL) {
541 /* disable U3 SS function */
542 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
543 /* disable HS function */
544 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
545 } else if (mtu->max_speed == USB_SPEED_HIGH) {
546 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
547 /* HS/FS detected by HW */
548 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
549 }
550
551 dev_info(mtu->dev, "max_speed: %s\n",
552 usb_speed_string(mtu->max_speed));
553}
554
555static void mtu3_regs_init(struct mtu3 *mtu)
556{
557
558 void __iomem *mbase = mtu->mac_base;
559
560 /* be sure interrupts are disabled before registration of ISR */
561 mtu3_intr_disable(mtu);
562 mtu3_intr_status_clear(mtu);
563
564 if (mtu->is_u3_ip) {
565 /* disable LGO_U1/U2 by default */
566 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
567 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE |
568 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
569 /* device responses to u3_exit from host automatically */
570 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
571 /* automatically build U2 link when U3 detect fail */
572 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
573 }
574
575 mtu3_set_speed(mtu);
576
577 /* delay about 0.1us from detecting reset to send chirp-K */
578 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
579 /* U2/U3 detected by HW */
580 mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
581 /* enable QMU 16B checksum */
582 mtu3_setbits(mbase, U3D_QCR0, QMU_CS16B_EN);
583 /* vbus detected by HW */
584 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
585}
586
587static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
588{
589 void __iomem *mbase = mtu->mac_base;
590 enum usb_device_speed udev_speed;
591 u32 maxpkt = 64;
592 u32 link;
593 u32 speed;
594
595 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
596 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
597 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
598 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
599
600 if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
601 return IRQ_NONE;
602
603 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
604
605 switch (speed) {
606 case MTU3_SPEED_FULL:
607 udev_speed = USB_SPEED_FULL;
608 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
609 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
610 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
611 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
612 LPM_BESL_STALL | LPM_BESLD_STALL);
613 break;
614 case MTU3_SPEED_HIGH:
615 udev_speed = USB_SPEED_HIGH;
616 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
617 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
618 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
619 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
620 LPM_BESL_STALL | LPM_BESLD_STALL);
621 break;
622 case MTU3_SPEED_SUPER:
623 udev_speed = USB_SPEED_SUPER;
624 maxpkt = 512;
625 break;
626 default:
627 udev_speed = USB_SPEED_UNKNOWN;
628 break;
629 }
630 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
631
632 mtu->g.speed = udev_speed;
633 mtu->g.ep0->maxpacket = maxpkt;
634 mtu->ep0_state = MU3D_EP0_STATE_SETUP;
635
636 if (udev_speed == USB_SPEED_UNKNOWN)
637 mtu3_gadget_disconnect(mtu);
638 else
639 mtu3_ep0_setup(mtu);
640
641 return IRQ_HANDLED;
642}
643
644static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
645{
646 void __iomem *mbase = mtu->mac_base;
647 u32 ltssm;
648
649 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
650 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
651 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
652 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
653
654 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
655 mtu3_gadget_reset(mtu);
656
657 if (ltssm & VBUS_FALL_INTR)
658 mtu3_ss_func_set(mtu, false);
659
660 if (ltssm & VBUS_RISE_INTR)
661 mtu3_ss_func_set(mtu, true);
662
663 if (ltssm & EXIT_U3_INTR)
664 mtu3_gadget_resume(mtu);
665
666 if (ltssm & ENTER_U3_INTR)
667 mtu3_gadget_suspend(mtu);
668
669 return IRQ_HANDLED;
670}
671
672static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
673{
674 void __iomem *mbase = mtu->mac_base;
675 u32 u2comm;
676
677 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
678 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
679 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
680 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
681
682 if (u2comm & SUSPEND_INTR)
683 mtu3_gadget_suspend(mtu);
684
685 if (u2comm & RESUME_INTR)
686 mtu3_gadget_resume(mtu);
687
688 if (u2comm & RESET_INTR)
689 mtu3_gadget_reset(mtu);
690
691 return IRQ_HANDLED;
692}
693
694static irqreturn_t mtu3_irq(int irq, void *data)
695{
696 struct mtu3 *mtu = (struct mtu3 *)data;
697 unsigned long flags;
698 u32 level1;
699
700 spin_lock_irqsave(&mtu->lock, flags);
701
702 /* U3D_LV1ISR is RU */
703 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
704 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
705
706 if (level1 & EP_CTRL_INTR)
707 mtu3_link_isr(mtu);
708
709 if (level1 & MAC2_INTR)
710 mtu3_u2_common_isr(mtu);
711
712 if (level1 & MAC3_INTR)
713 mtu3_u3_ltssm_isr(mtu);
714
715 if (level1 & BMU_INTR)
716 mtu3_ep0_isr(mtu);
717
718 if (level1 & QMU_INTR)
719 mtu3_qmu_isr(mtu);
720
721 spin_unlock_irqrestore(&mtu->lock, flags);
722
723 return IRQ_HANDLED;
724}
725
726static int mtu3_hw_init(struct mtu3 *mtu)
727{
728 u32 cap_dev;
729 int ret;
730
731 mtu->hw_version = mtu3_readl(mtu->ippc_base, U3D_SSUSB_HW_ID);
732
733 cap_dev = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
734 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(cap_dev);
735
736 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
737 mtu->is_u3_ip ? "U3" : "U2");
738
739 mtu3_device_reset(mtu);
740
741 ret = mtu3_device_enable(mtu);
742 if (ret) {
743 dev_err(mtu->dev, "device enable failed %d\n", ret);
744 return ret;
745 }
746
747 ret = mtu3_mem_alloc(mtu);
748 if (ret)
749 return -ENOMEM;
750
751 mtu3_regs_init(mtu);
752
753 return 0;
754}
755
756static void mtu3_hw_exit(struct mtu3 *mtu)
757{
758 mtu3_device_disable(mtu);
759 mtu3_mem_free(mtu);
760}
761
762/*-------------------------------------------------------------------------*/
763
764int ssusb_gadget_init(struct ssusb_mtk *ssusb)
765{
766 struct device *dev = ssusb->dev;
767 struct platform_device *pdev = to_platform_device(dev);
768 struct mtu3 *mtu = NULL;
769 struct resource *res;
770 int ret = -ENOMEM;
771
772 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
773 if (mtu == NULL)
774 return -ENOMEM;
775
776 mtu->irq = platform_get_irq(pdev, 0);
777 if (mtu->irq <= 0) {
778 dev_err(dev, "fail to get irq number\n");
779 return -ENODEV;
780 }
781 dev_info(dev, "irq %d\n", mtu->irq);
782
783 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
784 mtu->mac_base = devm_ioremap_resource(dev, res);
785 if (IS_ERR(mtu->mac_base)) {
786 dev_err(dev, "error mapping memory for dev mac\n");
787 return PTR_ERR(mtu->mac_base);
788 }
789
790 spin_lock_init(&mtu->lock);
791 mtu->dev = dev;
792 mtu->ippc_base = ssusb->ippc_base;
793 ssusb->mac_base = mtu->mac_base;
794 ssusb->u3d = mtu;
795 mtu->ssusb = ssusb;
796 mtu->max_speed = usb_get_maximum_speed(dev);
797
798 /* check the max_speed parameter */
799 switch (mtu->max_speed) {
800 case USB_SPEED_FULL:
801 case USB_SPEED_HIGH:
802 case USB_SPEED_SUPER:
803 break;
804 default:
805 dev_err(dev, "invalid max_speed: %s\n",
806 usb_speed_string(mtu->max_speed));
807 /* fall through */
808 case USB_SPEED_UNKNOWN:
809 /* default as SS */
810 mtu->max_speed = USB_SPEED_SUPER;
811 break;
812 }
813
814 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
815 mtu->mac_base, mtu->ippc_base);
816
817 ret = mtu3_hw_init(mtu);
818 if (ret) {
819 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
820 return ret;
821 }
822
823 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
824 if (ret) {
825 dev_err(dev, "request irq %d failed!\n", mtu->irq);
826 goto irq_err;
827 }
828
829 device_init_wakeup(dev, true);
830
831 ret = mtu3_gadget_setup(mtu);
832 if (ret) {
833 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
834 goto gadget_err;
835 }
836
837 /* init as host mode, power down device IP for power saving */
838 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
839 mtu3_stop(mtu);
840
841 dev_dbg(dev, " %s() done...\n", __func__);
842
843 return 0;
844
845gadget_err:
846 device_init_wakeup(dev, false);
847
848irq_err:
849 mtu3_hw_exit(mtu);
850 ssusb->u3d = NULL;
851 dev_err(dev, " %s() fail...\n", __func__);
852
853 return ret;
854}
855
856void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
857{
858 struct mtu3 *mtu = ssusb->u3d;
859
860 mtu3_gadget_cleanup(mtu);
861 device_init_wakeup(ssusb->dev, false);
862 mtu3_hw_exit(mtu);
863}