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1#ifndef MOXA_H_FILE
2#define MOXA_H_FILE
3
4#define MOXA 0x400
5#define MOXA_GET_IQUEUE (MOXA + 1) /* get input buffered count */
6#define MOXA_GET_OQUEUE (MOXA + 2) /* get output buffered count */
7#define MOXA_GETDATACOUNT (MOXA + 23)
8#define MOXA_GET_IOQUEUE (MOXA + 27)
9#define MOXA_FLUSH_QUEUE (MOXA + 28)
10#define MOXA_GETMSTATUS (MOXA + 65)
11
12/*
13 * System Configuration
14 */
15
16#define Magic_code 0x404
17
18/*
19 * for C218 BIOS initialization
20 */
21#define C218_ConfBase 0x800
22#define C218_status (C218_ConfBase + 0) /* BIOS running status */
23#define C218_diag (C218_ConfBase + 2) /* diagnostic status */
24#define C218_key (C218_ConfBase + 4) /* WORD (0x218 for C218) */
25#define C218DLoad_len (C218_ConfBase + 6) /* WORD */
26#define C218check_sum (C218_ConfBase + 8) /* BYTE */
27#define C218chksum_ok (C218_ConfBase + 0x0a) /* BYTE (1:ok) */
28#define C218_TestRx (C218_ConfBase + 0x10) /* 8 bytes for 8 ports */
29#define C218_TestTx (C218_ConfBase + 0x18) /* 8 bytes for 8 ports */
30#define C218_RXerr (C218_ConfBase + 0x20) /* 8 bytes for 8 ports */
31#define C218_ErrFlag (C218_ConfBase + 0x28) /* 8 bytes for 8 ports */
32
33#define C218_LoadBuf 0x0F00
34#define C218_KeyCode 0x218
35#define CP204J_KeyCode 0x204
36
37/*
38 * for C320 BIOS initialization
39 */
40#define C320_ConfBase 0x800
41#define C320_LoadBuf 0x0f00
42#define STS_init 0x05 /* for C320_status */
43
44#define C320_status C320_ConfBase + 0 /* BIOS running status */
45#define C320_diag C320_ConfBase + 2 /* diagnostic status */
46#define C320_key C320_ConfBase + 4 /* WORD (0320H for C320) */
47#define C320DLoad_len C320_ConfBase + 6 /* WORD */
48#define C320check_sum C320_ConfBase + 8 /* WORD */
49#define C320chksum_ok C320_ConfBase + 0x0a /* WORD (1:ok) */
50#define C320bapi_len C320_ConfBase + 0x0c /* WORD */
51#define C320UART_no C320_ConfBase + 0x0e /* WORD */
52
53#define C320_KeyCode 0x320
54
55#define FixPage_addr 0x0000 /* starting addr of static page */
56#define DynPage_addr 0x2000 /* starting addr of dynamic page */
57#define C218_start 0x3000 /* starting addr of C218 BIOS prg */
58#define Control_reg 0x1ff0 /* select page and reset control */
59#define HW_reset 0x80
60
61/*
62 * Function Codes
63 */
64#define FC_CardReset 0x80
65#define FC_ChannelReset 1 /* C320 firmware not supported */
66#define FC_EnableCH 2
67#define FC_DisableCH 3
68#define FC_SetParam 4
69#define FC_SetMode 5
70#define FC_SetRate 6
71#define FC_LineControl 7
72#define FC_LineStatus 8
73#define FC_XmitControl 9
74#define FC_FlushQueue 10
75#define FC_SendBreak 11
76#define FC_StopBreak 12
77#define FC_LoopbackON 13
78#define FC_LoopbackOFF 14
79#define FC_ClrIrqTable 15
80#define FC_SendXon 16
81#define FC_SetTermIrq 17 /* C320 firmware not supported */
82#define FC_SetCntIrq 18 /* C320 firmware not supported */
83#define FC_SetBreakIrq 19
84#define FC_SetLineIrq 20
85#define FC_SetFlowCtl 21
86#define FC_GenIrq 22
87#define FC_InCD180 23
88#define FC_OutCD180 24
89#define FC_InUARTreg 23
90#define FC_OutUARTreg 24
91#define FC_SetXonXoff 25
92#define FC_OutCD180CCR 26
93#define FC_ExtIQueue 27
94#define FC_ExtOQueue 28
95#define FC_ClrLineIrq 29
96#define FC_HWFlowCtl 30
97#define FC_GetClockRate 35
98#define FC_SetBaud 36
99#define FC_SetDataMode 41
100#define FC_GetCCSR 43
101#define FC_GetDataError 45
102#define FC_RxControl 50
103#define FC_ImmSend 51
104#define FC_SetXonState 52
105#define FC_SetXoffState 53
106#define FC_SetRxFIFOTrig 54
107#define FC_SetTxFIFOCnt 55
108#define FC_UnixRate 56
109#define FC_UnixResetTimer 57
110
111#define RxFIFOTrig1 0
112#define RxFIFOTrig4 1
113#define RxFIFOTrig8 2
114#define RxFIFOTrig14 3
115
116/*
117 * Dual-Ported RAM
118 */
119#define DRAM_global 0
120#define INT_data (DRAM_global + 0)
121#define Config_base (DRAM_global + 0x108)
122
123#define IRQindex (INT_data + 0)
124#define IRQpending (INT_data + 4)
125#define IRQtable (INT_data + 8)
126
127/*
128 * Interrupt Status
129 */
130#define IntrRx 0x01 /* receiver data O.K. */
131#define IntrTx 0x02 /* transmit buffer empty */
132#define IntrFunc 0x04 /* function complete */
133#define IntrBreak 0x08 /* received break */
134#define IntrLine 0x10 /* line status change
135 for transmitter */
136#define IntrIntr 0x20 /* received INTR code */
137#define IntrQuit 0x40 /* received QUIT code */
138#define IntrEOF 0x80 /* received EOF code */
139
140#define IntrRxTrigger 0x100 /* rx data count reach tigger value */
141#define IntrTxTrigger 0x200 /* tx data count below trigger value */
142
143#define Magic_no (Config_base + 0)
144#define Card_model_no (Config_base + 2)
145#define Total_ports (Config_base + 4)
146#define Module_cnt (Config_base + 8)
147#define Module_no (Config_base + 10)
148#define Timer_10ms (Config_base + 14)
149#define Disable_IRQ (Config_base + 20)
150#define TMS320_PORT1 (Config_base + 22)
151#define TMS320_PORT2 (Config_base + 24)
152#define TMS320_CLOCK (Config_base + 26)
153
154/*
155 * DATA BUFFER in DRAM
156 */
157#define Extern_table 0x400 /* Base address of the external table
158 (24 words * 64) total 3K bytes
159 (24 words * 128) total 6K bytes */
160#define Extern_size 0x60 /* 96 bytes */
161#define RXrptr 0x00 /* read pointer for RX buffer */
162#define RXwptr 0x02 /* write pointer for RX buffer */
163#define TXrptr 0x04 /* read pointer for TX buffer */
164#define TXwptr 0x06 /* write pointer for TX buffer */
165#define HostStat 0x08 /* IRQ flag and general flag */
166#define FlagStat 0x0A
167#define FlowControl 0x0C /* B7 B6 B5 B4 B3 B2 B1 B0 */
168 /* x x x x | | | | */
169 /* | | | + CTS flow */
170 /* | | +--- RTS flow */
171 /* | +------ TX Xon/Xoff */
172 /* +--------- RX Xon/Xoff */
173#define Break_cnt 0x0E /* received break count */
174#define CD180TXirq 0x10 /* if non-0: enable TX irq */
175#define RX_mask 0x12
176#define TX_mask 0x14
177#define Ofs_rxb 0x16
178#define Ofs_txb 0x18
179#define Page_rxb 0x1A
180#define Page_txb 0x1C
181#define EndPage_rxb 0x1E
182#define EndPage_txb 0x20
183#define Data_error 0x22
184#define RxTrigger 0x28
185#define TxTrigger 0x2a
186
187#define rRXwptr 0x34
188#define Low_water 0x36
189
190#define FuncCode 0x40
191#define FuncArg 0x42
192#define FuncArg1 0x44
193
194#define C218rx_size 0x2000 /* 8K bytes */
195#define C218tx_size 0x8000 /* 32K bytes */
196
197#define C218rx_mask (C218rx_size - 1)
198#define C218tx_mask (C218tx_size - 1)
199
200#define C320p8rx_size 0x2000
201#define C320p8tx_size 0x8000
202#define C320p8rx_mask (C320p8rx_size - 1)
203#define C320p8tx_mask (C320p8tx_size - 1)
204
205#define C320p16rx_size 0x2000
206#define C320p16tx_size 0x4000
207#define C320p16rx_mask (C320p16rx_size - 1)
208#define C320p16tx_mask (C320p16tx_size - 1)
209
210#define C320p24rx_size 0x2000
211#define C320p24tx_size 0x2000
212#define C320p24rx_mask (C320p24rx_size - 1)
213#define C320p24tx_mask (C320p24tx_size - 1)
214
215#define C320p32rx_size 0x1000
216#define C320p32tx_size 0x1000
217#define C320p32rx_mask (C320p32rx_size - 1)
218#define C320p32tx_mask (C320p32tx_size - 1)
219
220#define Page_size 0x2000U
221#define Page_mask (Page_size - 1)
222#define C218rx_spage 3
223#define C218tx_spage 4
224#define C218rx_pageno 1
225#define C218tx_pageno 4
226#define C218buf_pageno 5
227
228#define C320p8rx_spage 3
229#define C320p8tx_spage 4
230#define C320p8rx_pgno 1
231#define C320p8tx_pgno 4
232#define C320p8buf_pgno 5
233
234#define C320p16rx_spage 3
235#define C320p16tx_spage 4
236#define C320p16rx_pgno 1
237#define C320p16tx_pgno 2
238#define C320p16buf_pgno 3
239
240#define C320p24rx_spage 3
241#define C320p24tx_spage 4
242#define C320p24rx_pgno 1
243#define C320p24tx_pgno 1
244#define C320p24buf_pgno 2
245
246#define C320p32rx_spage 3
247#define C320p32tx_ofs C320p32rx_size
248#define C320p32tx_spage 3
249#define C320p32buf_pgno 1
250
251/*
252 * Host Status
253 */
254#define WakeupRx 0x01
255#define WakeupTx 0x02
256#define WakeupBreak 0x08
257#define WakeupLine 0x10
258#define WakeupIntr 0x20
259#define WakeupQuit 0x40
260#define WakeupEOF 0x80 /* used in VTIME control */
261#define WakeupRxTrigger 0x100
262#define WakeupTxTrigger 0x200
263/*
264 * Flag status
265 */
266#define Rx_over 0x01
267#define Xoff_state 0x02
268#define Tx_flowOff 0x04
269#define Tx_enable 0x08
270#define CTS_state 0x10
271#define DSR_state 0x20
272#define DCD_state 0x80
273/*
274 * FlowControl
275 */
276#define CTS_FlowCtl 1
277#define RTS_FlowCtl 2
278#define Tx_FlowCtl 4
279#define Rx_FlowCtl 8
280#define IXM_IXANY 0x10
281
282#define LowWater 128
283
284#define DTR_ON 1
285#define RTS_ON 2
286#define CTS_ON 1
287#define DSR_ON 2
288#define DCD_ON 8
289
290/* mode definition */
291#define MX_CS8 0x03
292#define MX_CS7 0x02
293#define MX_CS6 0x01
294#define MX_CS5 0x00
295
296#define MX_STOP1 0x00
297#define MX_STOP15 0x04
298#define MX_STOP2 0x08
299
300#define MX_PARNONE 0x00
301#define MX_PAREVEN 0x40
302#define MX_PARODD 0xC0
303
304#endif