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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SH SPI bus driver
4 *
5 * Copyright (C) 2011 Renesas Solutions Corp.
6 *
7 * Based on pxa2xx_spi.c:
8 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/errno.h>
15#include <linux/timer.h>
16#include <linux/delay.h>
17#include <linux/list.h>
18#include <linux/workqueue.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/spi/spi.h>
23
24#define SPI_SH_TBR 0x00
25#define SPI_SH_RBR 0x00
26#define SPI_SH_CR1 0x08
27#define SPI_SH_CR2 0x10
28#define SPI_SH_CR3 0x18
29#define SPI_SH_CR4 0x20
30#define SPI_SH_CR5 0x28
31
32/* CR1 */
33#define SPI_SH_TBE 0x80
34#define SPI_SH_TBF 0x40
35#define SPI_SH_RBE 0x20
36#define SPI_SH_RBF 0x10
37#define SPI_SH_PFONRD 0x08
38#define SPI_SH_SSDB 0x04
39#define SPI_SH_SSD 0x02
40#define SPI_SH_SSA 0x01
41
42/* CR2 */
43#define SPI_SH_RSTF 0x80
44#define SPI_SH_LOOPBK 0x40
45#define SPI_SH_CPOL 0x20
46#define SPI_SH_CPHA 0x10
47#define SPI_SH_L1M0 0x08
48
49/* CR3 */
50#define SPI_SH_MAX_BYTE 0xFF
51
52/* CR4 */
53#define SPI_SH_TBEI 0x80
54#define SPI_SH_TBFI 0x40
55#define SPI_SH_RBEI 0x20
56#define SPI_SH_RBFI 0x10
57#define SPI_SH_WPABRT 0x04
58#define SPI_SH_SSS 0x01
59
60/* CR8 */
61#define SPI_SH_P1L0 0x80
62#define SPI_SH_PP1L0 0x40
63#define SPI_SH_MUXI 0x20
64#define SPI_SH_MUXIRQ 0x10
65
66#define SPI_SH_FIFO_SIZE 32
67#define SPI_SH_SEND_TIMEOUT (3 * HZ)
68#define SPI_SH_RECEIVE_TIMEOUT (HZ >> 3)
69
70#undef DEBUG
71
72struct spi_sh_data {
73 void __iomem *addr;
74 int irq;
75 struct spi_controller *host;
76 unsigned long cr1;
77 wait_queue_head_t wait;
78 int width;
79};
80
81static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
82 unsigned long offset)
83{
84 if (ss->width == 8)
85 iowrite8(data, ss->addr + (offset >> 2));
86 else if (ss->width == 32)
87 iowrite32(data, ss->addr + offset);
88}
89
90static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
91{
92 if (ss->width == 8)
93 return ioread8(ss->addr + (offset >> 2));
94 else if (ss->width == 32)
95 return ioread32(ss->addr + offset);
96 else
97 return 0;
98}
99
100static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
101 unsigned long offset)
102{
103 unsigned long tmp;
104
105 tmp = spi_sh_read(ss, offset);
106 tmp |= val;
107 spi_sh_write(ss, tmp, offset);
108}
109
110static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
111 unsigned long offset)
112{
113 unsigned long tmp;
114
115 tmp = spi_sh_read(ss, offset);
116 tmp &= ~val;
117 spi_sh_write(ss, tmp, offset);
118}
119
120static void clear_fifo(struct spi_sh_data *ss)
121{
122 spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
123 spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
124}
125
126static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
127{
128 int timeout = 100000;
129
130 while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
131 udelay(10);
132 if (timeout-- < 0)
133 return -ETIMEDOUT;
134 }
135 return 0;
136}
137
138static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
139{
140 int timeout = 100000;
141
142 while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
143 udelay(10);
144 if (timeout-- < 0)
145 return -ETIMEDOUT;
146 }
147 return 0;
148}
149
150static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
151 struct spi_transfer *t)
152{
153 int i, retval = 0;
154 int remain = t->len;
155 int cur_len;
156 unsigned char *data;
157 long ret;
158
159 if (t->len)
160 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
161
162 data = (unsigned char *)t->tx_buf;
163 while (remain > 0) {
164 cur_len = min(SPI_SH_FIFO_SIZE, remain);
165 for (i = 0; i < cur_len &&
166 !(spi_sh_read(ss, SPI_SH_CR4) &
167 SPI_SH_WPABRT) &&
168 !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
169 i++)
170 spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
171
172 if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
173 /* Abort SPI operation */
174 spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
175 retval = -EIO;
176 break;
177 }
178
179 cur_len = i;
180
181 remain -= cur_len;
182 data += cur_len;
183
184 if (remain > 0) {
185 ss->cr1 &= ~SPI_SH_TBE;
186 spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
187 ret = wait_event_interruptible_timeout(ss->wait,
188 ss->cr1 & SPI_SH_TBE,
189 SPI_SH_SEND_TIMEOUT);
190 if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
191 printk(KERN_ERR "%s: timeout\n", __func__);
192 return -ETIMEDOUT;
193 }
194 }
195 }
196
197 if (list_is_last(&t->transfer_list, &mesg->transfers)) {
198 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
199 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
200
201 ss->cr1 &= ~SPI_SH_TBE;
202 spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
203 ret = wait_event_interruptible_timeout(ss->wait,
204 ss->cr1 & SPI_SH_TBE,
205 SPI_SH_SEND_TIMEOUT);
206 if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
207 printk(KERN_ERR "%s: timeout\n", __func__);
208 return -ETIMEDOUT;
209 }
210 }
211
212 return retval;
213}
214
215static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
216 struct spi_transfer *t)
217{
218 int i;
219 int remain = t->len;
220 int cur_len;
221 unsigned char *data;
222 long ret;
223
224 if (t->len > SPI_SH_MAX_BYTE)
225 spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
226 else
227 spi_sh_write(ss, t->len, SPI_SH_CR3);
228
229 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
230 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
231
232 spi_sh_wait_write_buffer_empty(ss);
233
234 data = (unsigned char *)t->rx_buf;
235 while (remain > 0) {
236 if (remain >= SPI_SH_FIFO_SIZE) {
237 ss->cr1 &= ~SPI_SH_RBF;
238 spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
239 ret = wait_event_interruptible_timeout(ss->wait,
240 ss->cr1 & SPI_SH_RBF,
241 SPI_SH_RECEIVE_TIMEOUT);
242 if (ret == 0 &&
243 spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
244 printk(KERN_ERR "%s: timeout\n", __func__);
245 return -ETIMEDOUT;
246 }
247 }
248
249 cur_len = min(SPI_SH_FIFO_SIZE, remain);
250 for (i = 0; i < cur_len; i++) {
251 if (spi_sh_wait_receive_buffer(ss))
252 break;
253 data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
254 }
255
256 remain -= cur_len;
257 data += cur_len;
258 }
259
260 /* deassert CS when SPI is receiving. */
261 if (t->len > SPI_SH_MAX_BYTE) {
262 clear_fifo(ss);
263 spi_sh_write(ss, 1, SPI_SH_CR3);
264 } else {
265 spi_sh_write(ss, 0, SPI_SH_CR3);
266 }
267
268 return 0;
269}
270
271static int spi_sh_transfer_one_message(struct spi_controller *ctlr,
272 struct spi_message *mesg)
273{
274 struct spi_sh_data *ss = spi_controller_get_devdata(ctlr);
275 struct spi_transfer *t;
276 int ret;
277
278 pr_debug("%s: enter\n", __func__);
279
280 spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
281
282 list_for_each_entry(t, &mesg->transfers, transfer_list) {
283 pr_debug("tx_buf = %p, rx_buf = %p\n",
284 t->tx_buf, t->rx_buf);
285 pr_debug("len = %d, delay.value = %d\n",
286 t->len, t->delay.value);
287
288 if (t->tx_buf) {
289 ret = spi_sh_send(ss, mesg, t);
290 if (ret < 0)
291 goto error;
292 }
293 if (t->rx_buf) {
294 ret = spi_sh_receive(ss, mesg, t);
295 if (ret < 0)
296 goto error;
297 }
298 mesg->actual_length += t->len;
299 }
300
301 mesg->status = 0;
302 spi_finalize_current_message(ctlr);
303
304 clear_fifo(ss);
305 spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
306 udelay(100);
307
308 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
309 SPI_SH_CR1);
310
311 clear_fifo(ss);
312
313 return 0;
314
315 error:
316 mesg->status = ret;
317 spi_finalize_current_message(ctlr);
318 if (mesg->complete)
319 mesg->complete(mesg->context);
320
321 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
322 SPI_SH_CR1);
323 clear_fifo(ss);
324
325 return ret;
326}
327
328static int spi_sh_setup(struct spi_device *spi)
329{
330 struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);
331
332 pr_debug("%s: enter\n", __func__);
333
334 spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
335 spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */
336 spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */
337
338 clear_fifo(ss);
339
340 /* 1/8 clock */
341 spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
342 udelay(10);
343
344 return 0;
345}
346
347static void spi_sh_cleanup(struct spi_device *spi)
348{
349 struct spi_sh_data *ss = spi_controller_get_devdata(spi->controller);
350
351 pr_debug("%s: enter\n", __func__);
352
353 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
354 SPI_SH_CR1);
355}
356
357static irqreturn_t spi_sh_irq(int irq, void *_ss)
358{
359 struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
360 unsigned long cr1;
361
362 cr1 = spi_sh_read(ss, SPI_SH_CR1);
363 if (cr1 & SPI_SH_TBE)
364 ss->cr1 |= SPI_SH_TBE;
365 if (cr1 & SPI_SH_TBF)
366 ss->cr1 |= SPI_SH_TBF;
367 if (cr1 & SPI_SH_RBE)
368 ss->cr1 |= SPI_SH_RBE;
369 if (cr1 & SPI_SH_RBF)
370 ss->cr1 |= SPI_SH_RBF;
371
372 if (ss->cr1) {
373 spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
374 wake_up(&ss->wait);
375 }
376
377 return IRQ_HANDLED;
378}
379
380static void spi_sh_remove(struct platform_device *pdev)
381{
382 struct spi_sh_data *ss = platform_get_drvdata(pdev);
383
384 spi_unregister_controller(ss->host);
385 free_irq(ss->irq, ss);
386}
387
388static int spi_sh_probe(struct platform_device *pdev)
389{
390 struct resource *res;
391 struct spi_controller *host;
392 struct spi_sh_data *ss;
393 int ret, irq;
394
395 /* get base addr */
396 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
397 if (unlikely(res == NULL)) {
398 dev_err(&pdev->dev, "invalid resource\n");
399 return -EINVAL;
400 }
401
402 irq = platform_get_irq(pdev, 0);
403 if (irq < 0)
404 return irq;
405
406 host = devm_spi_alloc_host(&pdev->dev, sizeof(struct spi_sh_data));
407 if (host == NULL) {
408 dev_err(&pdev->dev, "devm_spi_alloc_host error.\n");
409 return -ENOMEM;
410 }
411
412 ss = spi_controller_get_devdata(host);
413 platform_set_drvdata(pdev, ss);
414
415 switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
416 case IORESOURCE_MEM_8BIT:
417 ss->width = 8;
418 break;
419 case IORESOURCE_MEM_32BIT:
420 ss->width = 32;
421 break;
422 default:
423 dev_err(&pdev->dev, "No support width\n");
424 return -ENODEV;
425 }
426 ss->irq = irq;
427 ss->host = host;
428 ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
429 if (ss->addr == NULL) {
430 dev_err(&pdev->dev, "ioremap error.\n");
431 return -ENOMEM;
432 }
433 init_waitqueue_head(&ss->wait);
434
435 ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
436 if (ret < 0) {
437 dev_err(&pdev->dev, "request_irq error\n");
438 return ret;
439 }
440
441 host->num_chipselect = 2;
442 host->bus_num = pdev->id;
443 host->setup = spi_sh_setup;
444 host->transfer_one_message = spi_sh_transfer_one_message;
445 host->cleanup = spi_sh_cleanup;
446
447 ret = spi_register_controller(host);
448 if (ret < 0) {
449 printk(KERN_ERR "spi_register_controller error.\n");
450 goto error3;
451 }
452
453 return 0;
454
455 error3:
456 free_irq(irq, ss);
457 return ret;
458}
459
460static struct platform_driver spi_sh_driver = {
461 .probe = spi_sh_probe,
462 .remove_new = spi_sh_remove,
463 .driver = {
464 .name = "sh_spi",
465 },
466};
467module_platform_driver(spi_sh_driver);
468
469MODULE_DESCRIPTION("SH SPI bus driver");
470MODULE_LICENSE("GPL v2");
471MODULE_AUTHOR("Yoshihiro Shimoda");
472MODULE_ALIAS("platform:sh_spi");
1/*
2 * SH SPI bus driver
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 *
6 * Based on pxa2xx_spi.c:
7 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/errno.h>
23#include <linux/timer.h>
24#include <linux/delay.h>
25#include <linux/list.h>
26#include <linux/workqueue.h>
27#include <linux/interrupt.h>
28#include <linux/platform_device.h>
29#include <linux/io.h>
30#include <linux/spi/spi.h>
31
32#define SPI_SH_TBR 0x00
33#define SPI_SH_RBR 0x00
34#define SPI_SH_CR1 0x08
35#define SPI_SH_CR2 0x10
36#define SPI_SH_CR3 0x18
37#define SPI_SH_CR4 0x20
38#define SPI_SH_CR5 0x28
39
40/* CR1 */
41#define SPI_SH_TBE 0x80
42#define SPI_SH_TBF 0x40
43#define SPI_SH_RBE 0x20
44#define SPI_SH_RBF 0x10
45#define SPI_SH_PFONRD 0x08
46#define SPI_SH_SSDB 0x04
47#define SPI_SH_SSD 0x02
48#define SPI_SH_SSA 0x01
49
50/* CR2 */
51#define SPI_SH_RSTF 0x80
52#define SPI_SH_LOOPBK 0x40
53#define SPI_SH_CPOL 0x20
54#define SPI_SH_CPHA 0x10
55#define SPI_SH_L1M0 0x08
56
57/* CR3 */
58#define SPI_SH_MAX_BYTE 0xFF
59
60/* CR4 */
61#define SPI_SH_TBEI 0x80
62#define SPI_SH_TBFI 0x40
63#define SPI_SH_RBEI 0x20
64#define SPI_SH_RBFI 0x10
65#define SPI_SH_WPABRT 0x04
66#define SPI_SH_SSS 0x01
67
68/* CR8 */
69#define SPI_SH_P1L0 0x80
70#define SPI_SH_PP1L0 0x40
71#define SPI_SH_MUXI 0x20
72#define SPI_SH_MUXIRQ 0x10
73
74#define SPI_SH_FIFO_SIZE 32
75#define SPI_SH_SEND_TIMEOUT (3 * HZ)
76#define SPI_SH_RECEIVE_TIMEOUT (HZ >> 3)
77
78#undef DEBUG
79
80struct spi_sh_data {
81 void __iomem *addr;
82 int irq;
83 struct spi_master *master;
84 struct list_head queue;
85 struct work_struct ws;
86 unsigned long cr1;
87 wait_queue_head_t wait;
88 spinlock_t lock;
89 int width;
90};
91
92static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
93 unsigned long offset)
94{
95 if (ss->width == 8)
96 iowrite8(data, ss->addr + (offset >> 2));
97 else if (ss->width == 32)
98 iowrite32(data, ss->addr + offset);
99}
100
101static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
102{
103 if (ss->width == 8)
104 return ioread8(ss->addr + (offset >> 2));
105 else if (ss->width == 32)
106 return ioread32(ss->addr + offset);
107 else
108 return 0;
109}
110
111static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
112 unsigned long offset)
113{
114 unsigned long tmp;
115
116 tmp = spi_sh_read(ss, offset);
117 tmp |= val;
118 spi_sh_write(ss, tmp, offset);
119}
120
121static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
122 unsigned long offset)
123{
124 unsigned long tmp;
125
126 tmp = spi_sh_read(ss, offset);
127 tmp &= ~val;
128 spi_sh_write(ss, tmp, offset);
129}
130
131static void clear_fifo(struct spi_sh_data *ss)
132{
133 spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
134 spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
135}
136
137static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
138{
139 int timeout = 100000;
140
141 while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
142 udelay(10);
143 if (timeout-- < 0)
144 return -ETIMEDOUT;
145 }
146 return 0;
147}
148
149static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
150{
151 int timeout = 100000;
152
153 while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
154 udelay(10);
155 if (timeout-- < 0)
156 return -ETIMEDOUT;
157 }
158 return 0;
159}
160
161static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
162 struct spi_transfer *t)
163{
164 int i, retval = 0;
165 int remain = t->len;
166 int cur_len;
167 unsigned char *data;
168 long ret;
169
170 if (t->len)
171 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
172
173 data = (unsigned char *)t->tx_buf;
174 while (remain > 0) {
175 cur_len = min(SPI_SH_FIFO_SIZE, remain);
176 for (i = 0; i < cur_len &&
177 !(spi_sh_read(ss, SPI_SH_CR4) &
178 SPI_SH_WPABRT) &&
179 !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
180 i++)
181 spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
182
183 if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
184 /* Abort SPI operation */
185 spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
186 retval = -EIO;
187 break;
188 }
189
190 cur_len = i;
191
192 remain -= cur_len;
193 data += cur_len;
194
195 if (remain > 0) {
196 ss->cr1 &= ~SPI_SH_TBE;
197 spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
198 ret = wait_event_interruptible_timeout(ss->wait,
199 ss->cr1 & SPI_SH_TBE,
200 SPI_SH_SEND_TIMEOUT);
201 if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
202 printk(KERN_ERR "%s: timeout\n", __func__);
203 return -ETIMEDOUT;
204 }
205 }
206 }
207
208 if (list_is_last(&t->transfer_list, &mesg->transfers)) {
209 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
210 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
211
212 ss->cr1 &= ~SPI_SH_TBE;
213 spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
214 ret = wait_event_interruptible_timeout(ss->wait,
215 ss->cr1 & SPI_SH_TBE,
216 SPI_SH_SEND_TIMEOUT);
217 if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
218 printk(KERN_ERR "%s: timeout\n", __func__);
219 return -ETIMEDOUT;
220 }
221 }
222
223 return retval;
224}
225
226static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
227 struct spi_transfer *t)
228{
229 int i;
230 int remain = t->len;
231 int cur_len;
232 unsigned char *data;
233 long ret;
234
235 if (t->len > SPI_SH_MAX_BYTE)
236 spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
237 else
238 spi_sh_write(ss, t->len, SPI_SH_CR3);
239
240 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
241 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
242
243 spi_sh_wait_write_buffer_empty(ss);
244
245 data = (unsigned char *)t->rx_buf;
246 while (remain > 0) {
247 if (remain >= SPI_SH_FIFO_SIZE) {
248 ss->cr1 &= ~SPI_SH_RBF;
249 spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
250 ret = wait_event_interruptible_timeout(ss->wait,
251 ss->cr1 & SPI_SH_RBF,
252 SPI_SH_RECEIVE_TIMEOUT);
253 if (ret == 0 &&
254 spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
255 printk(KERN_ERR "%s: timeout\n", __func__);
256 return -ETIMEDOUT;
257 }
258 }
259
260 cur_len = min(SPI_SH_FIFO_SIZE, remain);
261 for (i = 0; i < cur_len; i++) {
262 if (spi_sh_wait_receive_buffer(ss))
263 break;
264 data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
265 }
266
267 remain -= cur_len;
268 data += cur_len;
269 }
270
271 /* deassert CS when SPI is receiving. */
272 if (t->len > SPI_SH_MAX_BYTE) {
273 clear_fifo(ss);
274 spi_sh_write(ss, 1, SPI_SH_CR3);
275 } else {
276 spi_sh_write(ss, 0, SPI_SH_CR3);
277 }
278
279 return 0;
280}
281
282static void spi_sh_work(struct work_struct *work)
283{
284 struct spi_sh_data *ss = container_of(work, struct spi_sh_data, ws);
285 struct spi_message *mesg;
286 struct spi_transfer *t;
287 unsigned long flags;
288 int ret;
289
290 pr_debug("%s: enter\n", __func__);
291
292 spin_lock_irqsave(&ss->lock, flags);
293 while (!list_empty(&ss->queue)) {
294 mesg = list_entry(ss->queue.next, struct spi_message, queue);
295 list_del_init(&mesg->queue);
296
297 spin_unlock_irqrestore(&ss->lock, flags);
298 list_for_each_entry(t, &mesg->transfers, transfer_list) {
299 pr_debug("tx_buf = %p, rx_buf = %p\n",
300 t->tx_buf, t->rx_buf);
301 pr_debug("len = %d, delay_usecs = %d\n",
302 t->len, t->delay_usecs);
303
304 if (t->tx_buf) {
305 ret = spi_sh_send(ss, mesg, t);
306 if (ret < 0)
307 goto error;
308 }
309 if (t->rx_buf) {
310 ret = spi_sh_receive(ss, mesg, t);
311 if (ret < 0)
312 goto error;
313 }
314 mesg->actual_length += t->len;
315 }
316 spin_lock_irqsave(&ss->lock, flags);
317
318 mesg->status = 0;
319 if (mesg->complete)
320 mesg->complete(mesg->context);
321 }
322
323 clear_fifo(ss);
324 spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
325 udelay(100);
326
327 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
328 SPI_SH_CR1);
329
330 clear_fifo(ss);
331
332 spin_unlock_irqrestore(&ss->lock, flags);
333
334 return;
335
336 error:
337 mesg->status = ret;
338 if (mesg->complete)
339 mesg->complete(mesg->context);
340
341 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
342 SPI_SH_CR1);
343 clear_fifo(ss);
344
345}
346
347static int spi_sh_setup(struct spi_device *spi)
348{
349 struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
350
351 pr_debug("%s: enter\n", __func__);
352
353 spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
354 spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */
355 spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */
356
357 clear_fifo(ss);
358
359 /* 1/8 clock */
360 spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
361 udelay(10);
362
363 return 0;
364}
365
366static int spi_sh_transfer(struct spi_device *spi, struct spi_message *mesg)
367{
368 struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
369 unsigned long flags;
370
371 pr_debug("%s: enter\n", __func__);
372 pr_debug("\tmode = %02x\n", spi->mode);
373
374 spin_lock_irqsave(&ss->lock, flags);
375
376 mesg->actual_length = 0;
377 mesg->status = -EINPROGRESS;
378
379 spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
380
381 list_add_tail(&mesg->queue, &ss->queue);
382 schedule_work(&ss->ws);
383
384 spin_unlock_irqrestore(&ss->lock, flags);
385
386 return 0;
387}
388
389static void spi_sh_cleanup(struct spi_device *spi)
390{
391 struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
392
393 pr_debug("%s: enter\n", __func__);
394
395 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
396 SPI_SH_CR1);
397}
398
399static irqreturn_t spi_sh_irq(int irq, void *_ss)
400{
401 struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
402 unsigned long cr1;
403
404 cr1 = spi_sh_read(ss, SPI_SH_CR1);
405 if (cr1 & SPI_SH_TBE)
406 ss->cr1 |= SPI_SH_TBE;
407 if (cr1 & SPI_SH_TBF)
408 ss->cr1 |= SPI_SH_TBF;
409 if (cr1 & SPI_SH_RBE)
410 ss->cr1 |= SPI_SH_RBE;
411 if (cr1 & SPI_SH_RBF)
412 ss->cr1 |= SPI_SH_RBF;
413
414 if (ss->cr1) {
415 spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
416 wake_up(&ss->wait);
417 }
418
419 return IRQ_HANDLED;
420}
421
422static int spi_sh_remove(struct platform_device *pdev)
423{
424 struct spi_sh_data *ss = platform_get_drvdata(pdev);
425
426 spi_unregister_master(ss->master);
427 flush_work(&ss->ws);
428 free_irq(ss->irq, ss);
429
430 return 0;
431}
432
433static int spi_sh_probe(struct platform_device *pdev)
434{
435 struct resource *res;
436 struct spi_master *master;
437 struct spi_sh_data *ss;
438 int ret, irq;
439
440 /* get base addr */
441 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
442 if (unlikely(res == NULL)) {
443 dev_err(&pdev->dev, "invalid resource\n");
444 return -EINVAL;
445 }
446
447 irq = platform_get_irq(pdev, 0);
448 if (irq < 0) {
449 dev_err(&pdev->dev, "platform_get_irq error\n");
450 return -ENODEV;
451 }
452
453 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
454 if (master == NULL) {
455 dev_err(&pdev->dev, "spi_alloc_master error.\n");
456 return -ENOMEM;
457 }
458
459 ss = spi_master_get_devdata(master);
460 platform_set_drvdata(pdev, ss);
461
462 switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
463 case IORESOURCE_MEM_8BIT:
464 ss->width = 8;
465 break;
466 case IORESOURCE_MEM_32BIT:
467 ss->width = 32;
468 break;
469 default:
470 dev_err(&pdev->dev, "No support width\n");
471 ret = -ENODEV;
472 goto error1;
473 }
474 ss->irq = irq;
475 ss->master = master;
476 ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
477 if (ss->addr == NULL) {
478 dev_err(&pdev->dev, "ioremap error.\n");
479 ret = -ENOMEM;
480 goto error1;
481 }
482 INIT_LIST_HEAD(&ss->queue);
483 spin_lock_init(&ss->lock);
484 INIT_WORK(&ss->ws, spi_sh_work);
485 init_waitqueue_head(&ss->wait);
486
487 ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
488 if (ret < 0) {
489 dev_err(&pdev->dev, "request_irq error\n");
490 goto error1;
491 }
492
493 master->num_chipselect = 2;
494 master->bus_num = pdev->id;
495 master->setup = spi_sh_setup;
496 master->transfer = spi_sh_transfer;
497 master->cleanup = spi_sh_cleanup;
498
499 ret = spi_register_master(master);
500 if (ret < 0) {
501 printk(KERN_ERR "spi_register_master error.\n");
502 goto error3;
503 }
504
505 return 0;
506
507 error3:
508 free_irq(irq, ss);
509 error1:
510 spi_master_put(master);
511
512 return ret;
513}
514
515static struct platform_driver spi_sh_driver = {
516 .probe = spi_sh_probe,
517 .remove = spi_sh_remove,
518 .driver = {
519 .name = "sh_spi",
520 },
521};
522module_platform_driver(spi_sh_driver);
523
524MODULE_DESCRIPTION("SH SPI bus driver");
525MODULE_LICENSE("GPL");
526MODULE_AUTHOR("Yoshihiro Shimoda");
527MODULE_ALIAS("platform:sh_spi");