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1/*******************************************************************************
2*
3* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
4*
5* This software is available to you under a choice of one of two
6* licenses. You may choose to be licensed under the terms of the GNU
7* General Public License (GPL) Version 2, available from the file
8* COPYING in the main directory of this source tree, or the
9* OpenFabrics.org BSD license below:
10*
11* Redistribution and use in source and binary forms, with or
12* without modification, are permitted provided that the following
13* conditions are met:
14*
15* - Redistributions of source code must retain the above
16* copyright notice, this list of conditions and the following
17* disclaimer.
18*
19* - Redistributions in binary form must reproduce the above
20* copyright notice, this list of conditions and the following
21* disclaimer in the documentation and/or other materials
22* provided with the distribution.
23*
24* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31* SOFTWARE.
32*
33*******************************************************************************/
34
35#ifndef I40IW_USER_H
36#define I40IW_USER_H
37
38enum i40iw_device_capabilities_const {
39 I40IW_WQE_SIZE = 4,
40 I40IW_CQP_WQE_SIZE = 8,
41 I40IW_CQE_SIZE = 4,
42 I40IW_EXTENDED_CQE_SIZE = 8,
43 I40IW_AEQE_SIZE = 2,
44 I40IW_CEQE_SIZE = 1,
45 I40IW_CQP_CTX_SIZE = 8,
46 I40IW_SHADOW_AREA_SIZE = 8,
47 I40IW_CEQ_MAX_COUNT = 256,
48 I40IW_QUERY_FPM_BUF_SIZE = 128,
49 I40IW_COMMIT_FPM_BUF_SIZE = 128,
50 I40IW_MIN_IW_QP_ID = 1,
51 I40IW_MAX_IW_QP_ID = 262143,
52 I40IW_MIN_CEQID = 0,
53 I40IW_MAX_CEQID = 256,
54 I40IW_MIN_CQID = 0,
55 I40IW_MAX_CQID = 131071,
56 I40IW_MIN_AEQ_ENTRIES = 1,
57 I40IW_MAX_AEQ_ENTRIES = 524287,
58 I40IW_MIN_CEQ_ENTRIES = 1,
59 I40IW_MAX_CEQ_ENTRIES = 131071,
60 I40IW_MIN_CQ_SIZE = 1,
61 I40IW_MAX_CQ_SIZE = 1048575,
62 I40IW_MAX_AEQ_ALLOCATE_COUNT = 255,
63 I40IW_DB_ID_ZERO = 0,
64 I40IW_MAX_WQ_FRAGMENT_COUNT = 3,
65 I40IW_MAX_SGE_RD = 1,
66 I40IW_MAX_OUTBOUND_MESSAGE_SIZE = 2147483647,
67 I40IW_MAX_INBOUND_MESSAGE_SIZE = 2147483647,
68 I40IW_MAX_PUSH_PAGE_COUNT = 4096,
69 I40IW_MAX_PE_ENABLED_VF_COUNT = 32,
70 I40IW_MAX_VF_FPM_ID = 47,
71 I40IW_MAX_VF_PER_PF = 127,
72 I40IW_MAX_SQ_PAYLOAD_SIZE = 2145386496,
73 I40IW_MAX_INLINE_DATA_SIZE = 48,
74 I40IW_MAX_PUSHMODE_INLINE_DATA_SIZE = 48,
75 I40IW_MAX_IRD_SIZE = 63,
76 I40IW_MAX_ORD_SIZE = 127,
77 I40IW_MAX_WQ_ENTRIES = 2048,
78 I40IW_Q2_BUFFER_SIZE = (248 + 100),
79 I40IW_MAX_WQE_SIZE_RQ = 128,
80 I40IW_QP_CTX_SIZE = 248,
81 I40IW_MAX_PDS = 32768
82};
83
84#define i40iw_handle void *
85#define i40iw_adapter_handle i40iw_handle
86#define i40iw_qp_handle i40iw_handle
87#define i40iw_cq_handle i40iw_handle
88#define i40iw_srq_handle i40iw_handle
89#define i40iw_pd_id i40iw_handle
90#define i40iw_stag_handle i40iw_handle
91#define i40iw_stag_index u32
92#define i40iw_stag u32
93#define i40iw_stag_key u8
94
95#define i40iw_tagged_offset u64
96#define i40iw_access_privileges u32
97#define i40iw_physical_fragment u64
98#define i40iw_address_list u64 *
99
100#define I40IW_MAX_MR_SIZE 0x10000000000L
101#define I40IW_MAX_RQ_WQE_SHIFT 2
102
103struct i40iw_qp_uk;
104struct i40iw_cq_uk;
105struct i40iw_srq_uk;
106struct i40iw_qp_uk_init_info;
107struct i40iw_cq_uk_init_info;
108struct i40iw_srq_uk_init_info;
109
110struct i40iw_sge {
111 i40iw_tagged_offset tag_off;
112 u32 len;
113 i40iw_stag stag;
114};
115
116#define i40iw_sgl struct i40iw_sge *
117
118struct i40iw_ring {
119 u32 head;
120 u32 tail;
121 u32 size;
122};
123
124struct i40iw_cqe {
125 u64 buf[I40IW_CQE_SIZE];
126};
127
128struct i40iw_extended_cqe {
129 u64 buf[I40IW_EXTENDED_CQE_SIZE];
130};
131
132struct i40iw_wqe {
133 u64 buf[I40IW_WQE_SIZE];
134};
135
136struct i40iw_qp_uk_ops;
137
138enum i40iw_addressing_type {
139 I40IW_ADDR_TYPE_ZERO_BASED = 0,
140 I40IW_ADDR_TYPE_VA_BASED = 1,
141};
142
143#define I40IW_ACCESS_FLAGS_LOCALREAD 0x01
144#define I40IW_ACCESS_FLAGS_LOCALWRITE 0x02
145#define I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY 0x04
146#define I40IW_ACCESS_FLAGS_REMOTEREAD 0x05
147#define I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY 0x08
148#define I40IW_ACCESS_FLAGS_REMOTEWRITE 0x0a
149#define I40IW_ACCESS_FLAGS_BIND_WINDOW 0x10
150#define I40IW_ACCESS_FLAGS_ALL 0x1F
151
152#define I40IW_OP_TYPE_RDMA_WRITE 0
153#define I40IW_OP_TYPE_RDMA_READ 1
154#define I40IW_OP_TYPE_SEND 3
155#define I40IW_OP_TYPE_SEND_INV 4
156#define I40IW_OP_TYPE_SEND_SOL 5
157#define I40IW_OP_TYPE_SEND_SOL_INV 6
158#define I40IW_OP_TYPE_REC 7
159#define I40IW_OP_TYPE_BIND_MW 8
160#define I40IW_OP_TYPE_FAST_REG_NSMR 9
161#define I40IW_OP_TYPE_INV_STAG 10
162#define I40IW_OP_TYPE_RDMA_READ_INV_STAG 11
163#define I40IW_OP_TYPE_NOP 12
164
165enum i40iw_completion_status {
166 I40IW_COMPL_STATUS_SUCCESS = 0,
167 I40IW_COMPL_STATUS_FLUSHED,
168 I40IW_COMPL_STATUS_INVALID_WQE,
169 I40IW_COMPL_STATUS_QP_CATASTROPHIC,
170 I40IW_COMPL_STATUS_REMOTE_TERMINATION,
171 I40IW_COMPL_STATUS_INVALID_STAG,
172 I40IW_COMPL_STATUS_BASE_BOUND_VIOLATION,
173 I40IW_COMPL_STATUS_ACCESS_VIOLATION,
174 I40IW_COMPL_STATUS_INVALID_PD_ID,
175 I40IW_COMPL_STATUS_WRAP_ERROR,
176 I40IW_COMPL_STATUS_STAG_INVALID_PDID,
177 I40IW_COMPL_STATUS_RDMA_READ_ZERO_ORD,
178 I40IW_COMPL_STATUS_QP_NOT_PRIVLEDGED,
179 I40IW_COMPL_STATUS_STAG_NOT_INVALID,
180 I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_SIZE,
181 I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_ENTRY,
182 I40IW_COMPL_STATUS_INVALID_FBO,
183 I40IW_COMPL_STATUS_INVALID_LENGTH,
184 I40IW_COMPL_STATUS_INVALID_ACCESS,
185 I40IW_COMPL_STATUS_PHYS_BUFFER_LIST_TOO_LONG,
186 I40IW_COMPL_STATUS_INVALID_VIRT_ADDRESS,
187 I40IW_COMPL_STATUS_INVALID_REGION,
188 I40IW_COMPL_STATUS_INVALID_WINDOW,
189 I40IW_COMPL_STATUS_INVALID_TOTAL_LENGTH
190};
191
192enum i40iw_completion_notify {
193 IW_CQ_COMPL_EVENT = 0,
194 IW_CQ_COMPL_SOLICITED = 1
195};
196
197struct i40iw_post_send {
198 i40iw_sgl sg_list;
199 u32 num_sges;
200};
201
202struct i40iw_post_inline_send {
203 void *data;
204 u32 len;
205};
206
207struct i40iw_post_send_w_inv {
208 i40iw_sgl sg_list;
209 u32 num_sges;
210 i40iw_stag remote_stag_to_inv;
211};
212
213struct i40iw_post_inline_send_w_inv {
214 void *data;
215 u32 len;
216 i40iw_stag remote_stag_to_inv;
217};
218
219struct i40iw_rdma_write {
220 i40iw_sgl lo_sg_list;
221 u32 num_lo_sges;
222 struct i40iw_sge rem_addr;
223};
224
225struct i40iw_inline_rdma_write {
226 void *data;
227 u32 len;
228 struct i40iw_sge rem_addr;
229};
230
231struct i40iw_rdma_read {
232 struct i40iw_sge lo_addr;
233 struct i40iw_sge rem_addr;
234};
235
236struct i40iw_bind_window {
237 i40iw_stag mr_stag;
238 u64 bind_length;
239 void *va;
240 enum i40iw_addressing_type addressing_type;
241 bool enable_reads;
242 bool enable_writes;
243 i40iw_stag mw_stag;
244};
245
246struct i40iw_inv_local_stag {
247 i40iw_stag target_stag;
248};
249
250struct i40iw_post_sq_info {
251 u64 wr_id;
252 u8 op_type;
253 bool signaled;
254 bool read_fence;
255 bool local_fence;
256 bool inline_data;
257 bool defer_flag;
258 union {
259 struct i40iw_post_send send;
260 struct i40iw_post_send send_w_sol;
261 struct i40iw_post_send_w_inv send_w_inv;
262 struct i40iw_post_send_w_inv send_w_sol_inv;
263 struct i40iw_rdma_write rdma_write;
264 struct i40iw_rdma_read rdma_read;
265 struct i40iw_rdma_read rdma_read_inv;
266 struct i40iw_bind_window bind_window;
267 struct i40iw_inv_local_stag inv_local_stag;
268 struct i40iw_inline_rdma_write inline_rdma_write;
269 struct i40iw_post_inline_send inline_send;
270 struct i40iw_post_inline_send inline_send_w_sol;
271 struct i40iw_post_inline_send_w_inv inline_send_w_inv;
272 struct i40iw_post_inline_send_w_inv inline_send_w_sol_inv;
273 } op;
274};
275
276struct i40iw_post_rq_info {
277 u64 wr_id;
278 i40iw_sgl sg_list;
279 u32 num_sges;
280};
281
282struct i40iw_cq_poll_info {
283 u64 wr_id;
284 i40iw_qp_handle qp_handle;
285 u32 bytes_xfered;
286 u32 tcp_seq_num;
287 u32 qp_id;
288 i40iw_stag inv_stag;
289 enum i40iw_completion_status comp_status;
290 u16 major_err;
291 u16 minor_err;
292 u8 op_type;
293 bool stag_invalid_set;
294 bool push_dropped;
295 bool error;
296 bool is_srq;
297 bool solicited_event;
298};
299
300struct i40iw_qp_uk_ops {
301 void (*iw_qp_post_wr)(struct i40iw_qp_uk *);
302 void (*iw_qp_ring_push_db)(struct i40iw_qp_uk *, u32);
303 enum i40iw_status_code (*iw_rdma_write)(struct i40iw_qp_uk *,
304 struct i40iw_post_sq_info *, bool);
305 enum i40iw_status_code (*iw_rdma_read)(struct i40iw_qp_uk *,
306 struct i40iw_post_sq_info *, bool, bool);
307 enum i40iw_status_code (*iw_send)(struct i40iw_qp_uk *,
308 struct i40iw_post_sq_info *, u32, bool);
309 enum i40iw_status_code (*iw_inline_rdma_write)(struct i40iw_qp_uk *,
310 struct i40iw_post_sq_info *, bool);
311 enum i40iw_status_code (*iw_inline_send)(struct i40iw_qp_uk *,
312 struct i40iw_post_sq_info *, u32, bool);
313 enum i40iw_status_code (*iw_stag_local_invalidate)(struct i40iw_qp_uk *,
314 struct i40iw_post_sq_info *, bool);
315 enum i40iw_status_code (*iw_mw_bind)(struct i40iw_qp_uk *,
316 struct i40iw_post_sq_info *, bool);
317 enum i40iw_status_code (*iw_post_receive)(struct i40iw_qp_uk *,
318 struct i40iw_post_rq_info *);
319 enum i40iw_status_code (*iw_post_nop)(struct i40iw_qp_uk *, u64, bool, bool);
320};
321
322struct i40iw_cq_ops {
323 void (*iw_cq_request_notification)(struct i40iw_cq_uk *,
324 enum i40iw_completion_notify);
325 enum i40iw_status_code (*iw_cq_poll_completion)(struct i40iw_cq_uk *,
326 struct i40iw_cq_poll_info *);
327 enum i40iw_status_code (*iw_cq_post_entries)(struct i40iw_cq_uk *, u8 count);
328 void (*iw_cq_clean)(void *, struct i40iw_cq_uk *);
329};
330
331struct i40iw_dev_uk;
332
333struct i40iw_device_uk_ops {
334 enum i40iw_status_code (*iwarp_cq_uk_init)(struct i40iw_cq_uk *,
335 struct i40iw_cq_uk_init_info *);
336 enum i40iw_status_code (*iwarp_qp_uk_init)(struct i40iw_qp_uk *,
337 struct i40iw_qp_uk_init_info *);
338};
339
340struct i40iw_dev_uk {
341 struct i40iw_device_uk_ops ops_uk;
342};
343
344struct i40iw_sq_uk_wr_trk_info {
345 u64 wrid;
346 u32 wr_len;
347 u8 wqe_size;
348 u8 reserved[3];
349};
350
351struct i40iw_qp_quanta {
352 u64 elem[I40IW_WQE_SIZE];
353};
354
355struct i40iw_qp_uk {
356 struct i40iw_qp_quanta *sq_base;
357 struct i40iw_qp_quanta *rq_base;
358 u32 __iomem *wqe_alloc_reg;
359 struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
360 u64 *rq_wrid_array;
361 u64 *shadow_area;
362 u32 *push_db;
363 u64 *push_wqe;
364 struct i40iw_ring sq_ring;
365 struct i40iw_ring rq_ring;
366 struct i40iw_ring initial_ring;
367 u32 qp_id;
368 u32 sq_size;
369 u32 rq_size;
370 u32 max_sq_frag_cnt;
371 u32 max_rq_frag_cnt;
372 struct i40iw_qp_uk_ops ops;
373 bool use_srq;
374 u8 swqe_polarity;
375 u8 swqe_polarity_deferred;
376 u8 rwqe_polarity;
377 u8 rq_wqe_size;
378 u8 rq_wqe_size_multiplier;
379 bool deferred_flag;
380};
381
382struct i40iw_cq_uk {
383 struct i40iw_cqe *cq_base;
384 u32 __iomem *cqe_alloc_reg;
385 u64 *shadow_area;
386 u32 cq_id;
387 u32 cq_size;
388 struct i40iw_ring cq_ring;
389 u8 polarity;
390 bool avoid_mem_cflct;
391
392 struct i40iw_cq_ops ops;
393};
394
395struct i40iw_qp_uk_init_info {
396 struct i40iw_qp_quanta *sq;
397 struct i40iw_qp_quanta *rq;
398 u32 __iomem *wqe_alloc_reg;
399 u64 *shadow_area;
400 struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
401 u64 *rq_wrid_array;
402 u32 *push_db;
403 u64 *push_wqe;
404 u32 qp_id;
405 u32 sq_size;
406 u32 rq_size;
407 u32 max_sq_frag_cnt;
408 u32 max_rq_frag_cnt;
409 u32 max_inline_data;
410 int abi_ver;
411};
412
413struct i40iw_cq_uk_init_info {
414 u32 __iomem *cqe_alloc_reg;
415 struct i40iw_cqe *cq_base;
416 u64 *shadow_area;
417 u32 cq_size;
418 u32 cq_id;
419 bool avoid_mem_cflct;
420};
421
422void i40iw_device_init_uk(struct i40iw_dev_uk *dev);
423
424void i40iw_qp_post_wr(struct i40iw_qp_uk *qp);
425u64 *i40iw_qp_get_next_send_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx,
426 u8 wqe_size,
427 u32 total_size,
428 u64 wr_id
429 );
430u64 *i40iw_qp_get_next_recv_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx);
431u64 *i40iw_qp_get_next_srq_wqe(struct i40iw_srq_uk *srq, u32 *wqe_idx);
432
433enum i40iw_status_code i40iw_cq_uk_init(struct i40iw_cq_uk *cq,
434 struct i40iw_cq_uk_init_info *info);
435enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
436 struct i40iw_qp_uk_init_info *info);
437
438void i40iw_clean_cq(void *queue, struct i40iw_cq_uk *cq);
439enum i40iw_status_code i40iw_nop(struct i40iw_qp_uk *qp, u64 wr_id,
440 bool signaled, bool post_sq);
441enum i40iw_status_code i40iw_fragcnt_to_wqesize_sq(u32 frag_cnt, u8 *wqe_size);
442enum i40iw_status_code i40iw_fragcnt_to_wqesize_rq(u32 frag_cnt, u8 *wqe_size);
443enum i40iw_status_code i40iw_inline_data_size_to_wqesize(u32 data_size,
444 u8 *wqe_size);
445enum i40iw_status_code i40iw_get_wqe_shift(u32 wqdepth, u32 sge, u32 inline_data, u8 *shift);
446#endif