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1/*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef _HNS_ROCE_HW_V1_H
34#define _HNS_ROCE_HW_V1_H
35
36#define CQ_STATE_VALID 2
37
38#define HNS_ROCE_V1_MAX_PD_NUM 0x8000
39#define HNS_ROCE_V1_MAX_CQ_NUM 0x10000
40#define HNS_ROCE_V1_MAX_CQE_NUM 0x8000
41
42#define HNS_ROCE_V1_MAX_QP_NUM 0x40000
43#define HNS_ROCE_V1_MAX_WQE_NUM 0x4000
44
45#define HNS_ROCE_V1_MAX_MTPT_NUM 0x80000
46
47#define HNS_ROCE_V1_MAX_MTT_SEGS 0x100000
48
49#define HNS_ROCE_V1_MAX_QP_INIT_RDMA 128
50#define HNS_ROCE_V1_MAX_QP_DEST_RDMA 128
51
52#define HNS_ROCE_V1_MAX_SQ_DESC_SZ 64
53#define HNS_ROCE_V1_MAX_RQ_DESC_SZ 64
54#define HNS_ROCE_V1_SG_NUM 2
55#define HNS_ROCE_V1_INLINE_SIZE 32
56
57#define HNS_ROCE_V1_UAR_NUM 256
58#define HNS_ROCE_V1_PHY_UAR_NUM 8
59
60#define HNS_ROCE_V1_GID_NUM 16
61#define HNS_ROCE_V1_RESV_QP 8
62
63#define HNS_ROCE_V1_NUM_COMP_EQE 0x8000
64#define HNS_ROCE_V1_NUM_ASYNC_EQE 0x400
65
66#define HNS_ROCE_V1_QPC_ENTRY_SIZE 256
67#define HNS_ROCE_V1_IRRL_ENTRY_SIZE 8
68#define HNS_ROCE_V1_CQC_ENTRY_SIZE 64
69#define HNS_ROCE_V1_MTPT_ENTRY_SIZE 64
70#define HNS_ROCE_V1_MTT_ENTRY_SIZE 64
71
72#define HNS_ROCE_V1_CQE_ENTRY_SIZE 32
73#define HNS_ROCE_V1_PAGE_SIZE_SUPPORT 0xFFFFF000
74
75#define HNS_ROCE_V1_EXT_RAQ_WF 8
76#define HNS_ROCE_V1_RAQ_ENTRY 64
77#define HNS_ROCE_V1_RAQ_DEPTH 32768
78#define HNS_ROCE_V1_RAQ_SIZE (HNS_ROCE_V1_RAQ_ENTRY * HNS_ROCE_V1_RAQ_DEPTH)
79
80#define HNS_ROCE_V1_SDB_DEPTH 0x400
81#define HNS_ROCE_V1_ODB_DEPTH 0x400
82
83#define HNS_ROCE_V1_DB_RSVD 0x80
84
85#define HNS_ROCE_V1_SDB_ALEPT HNS_ROCE_V1_DB_RSVD
86#define HNS_ROCE_V1_SDB_ALFUL (HNS_ROCE_V1_SDB_DEPTH - HNS_ROCE_V1_DB_RSVD)
87#define HNS_ROCE_V1_ODB_ALEPT HNS_ROCE_V1_DB_RSVD
88#define HNS_ROCE_V1_ODB_ALFUL (HNS_ROCE_V1_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD)
89
90#define HNS_ROCE_V1_EXT_SDB_DEPTH 0x4000
91#define HNS_ROCE_V1_EXT_ODB_DEPTH 0x4000
92#define HNS_ROCE_V1_EXT_SDB_ENTRY 16
93#define HNS_ROCE_V1_EXT_ODB_ENTRY 16
94#define HNS_ROCE_V1_EXT_SDB_SIZE \
95 (HNS_ROCE_V1_EXT_SDB_DEPTH * HNS_ROCE_V1_EXT_SDB_ENTRY)
96#define HNS_ROCE_V1_EXT_ODB_SIZE \
97 (HNS_ROCE_V1_EXT_ODB_DEPTH * HNS_ROCE_V1_EXT_ODB_ENTRY)
98
99#define HNS_ROCE_V1_EXT_SDB_ALEPT HNS_ROCE_V1_DB_RSVD
100#define HNS_ROCE_V1_EXT_SDB_ALFUL \
101 (HNS_ROCE_V1_EXT_SDB_DEPTH - HNS_ROCE_V1_DB_RSVD)
102#define HNS_ROCE_V1_EXT_ODB_ALEPT HNS_ROCE_V1_DB_RSVD
103#define HNS_ROCE_V1_EXT_ODB_ALFUL \
104 (HNS_ROCE_V1_EXT_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD)
105
106#define HNS_ROCE_V1_DB_WAIT_OK 0
107#define HNS_ROCE_V1_DB_STAGE1 1
108#define HNS_ROCE_V1_DB_STAGE2 2
109#define HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS 10000
110#define HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS 20
111#define HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS 50000
112#define HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS 10000
113#define HNS_ROCE_V1_FREE_MR_WAIT_VALUE 5
114#define HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE 20
115
116#define HNS_ROCE_BT_RSV_BUF_SIZE (1 << 17)
117
118#define HNS_ROCE_V1_TPTR_ENTRY_SIZE 2
119#define HNS_ROCE_V1_TPTR_BUF_SIZE \
120 (HNS_ROCE_V1_TPTR_ENTRY_SIZE * HNS_ROCE_V1_MAX_CQ_NUM)
121
122#define HNS_ROCE_ODB_POLL_MODE 0
123
124#define HNS_ROCE_SDB_NORMAL_MODE 0
125#define HNS_ROCE_SDB_EXTEND_MODE 1
126
127#define HNS_ROCE_ODB_EXTEND_MODE 1
128
129#define KEY_VALID 0x02
130
131#define HNS_ROCE_CQE_QPN_MASK 0x3ffff
132#define HNS_ROCE_CQE_STATUS_MASK 0x1f
133#define HNS_ROCE_CQE_OPCODE_MASK 0xf
134
135#define HNS_ROCE_CQE_SUCCESS 0x00
136#define HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR 0x01
137#define HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR 0x02
138#define HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR 0x03
139#define HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR 0x04
140#define HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR 0x05
141#define HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR 0x06
142#define HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR 0x07
143#define HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR 0x08
144#define HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR 0x09
145#define HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR 0x0a
146#define HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR 0x0b
147#define HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR 0x0c
148
149#define QP1C_CFGN_OFFSET 0x28
150#define PHY_PORT_OFFSET 0x8
151#define MTPT_IDX_SHIFT 16
152#define ALL_PORT_VAL_OPEN 0x3f
153#define POL_TIME_INTERVAL_VAL 0x80
154#define SLEEP_TIME_INTERVAL 20
155#define SQ_PSN_SHIFT 8
156#define QKEY_VAL 0x80010000
157#define SDB_INV_CNT_OFFSET 8
158#define SDB_ST_CMP_VAL 8
159
160struct hns_roce_cq_context {
161 u32 cqc_byte_4;
162 u32 cq_bt_l;
163 u32 cqc_byte_12;
164 u32 cur_cqe_ba0_l;
165 u32 cqc_byte_20;
166 u32 cqe_tptr_addr_l;
167 u32 cur_cqe_ba1_l;
168 u32 cqc_byte_32;
169};
170
171#define CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S 0
172#define CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M \
173 (((1UL << 2) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S)
174
175#define CQ_CONTEXT_CQC_BYTE_4_CQN_S 16
176#define CQ_CONTEXT_CQC_BYTE_4_CQN_M \
177 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_4_CQN_S)
178
179#define CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S 0
180#define CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M \
181 (((1UL << 17) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S)
182
183#define CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S 20
184#define CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M \
185 (((1UL << 4) - 1) << CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S)
186
187#define CQ_CONTEXT_CQC_BYTE_12_CEQN_S 24
188#define CQ_CONTEXT_CQC_BYTE_12_CEQN_M \
189 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_12_CEQN_S)
190
191#define CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S 0
192#define CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M \
193 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S)
194
195#define CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S 16
196#define CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M \
197 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S)
198
199#define CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S 8
200#define CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M \
201 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S)
202
203#define CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S 0
204#define CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M \
205 (((1UL << 5) - 1) << CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S)
206
207#define CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S 9
208
209#define CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S 8
210#define CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S 14
211#define CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S 15
212
213#define CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S 16
214#define CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M \
215 (((1UL << 16) - 1) << CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S)
216
217struct hns_roce_cqe {
218 u32 cqe_byte_4;
219 union {
220 u32 r_key;
221 u32 immediate_data;
222 };
223 u32 byte_cnt;
224 u32 cqe_byte_16;
225 u32 cqe_byte_20;
226 u32 s_mac_l;
227 u32 cqe_byte_28;
228 u32 reserved;
229};
230
231#define CQE_BYTE_4_OWNER_S 7
232#define CQE_BYTE_4_SQ_RQ_FLAG_S 14
233
234#define CQE_BYTE_4_STATUS_OF_THE_OPERATION_S 8
235#define CQE_BYTE_4_STATUS_OF_THE_OPERATION_M \
236 (((1UL << 5) - 1) << CQE_BYTE_4_STATUS_OF_THE_OPERATION_S)
237
238#define CQE_BYTE_4_WQE_INDEX_S 16
239#define CQE_BYTE_4_WQE_INDEX_M (((1UL << 14) - 1) << CQE_BYTE_4_WQE_INDEX_S)
240
241#define CQE_BYTE_4_OPERATION_TYPE_S 0
242#define CQE_BYTE_4_OPERATION_TYPE_M \
243 (((1UL << 4) - 1) << CQE_BYTE_4_OPERATION_TYPE_S)
244
245#define CQE_BYTE_4_IMM_INDICATOR_S 15
246
247#define CQE_BYTE_16_LOCAL_QPN_S 0
248#define CQE_BYTE_16_LOCAL_QPN_M (((1UL << 24) - 1) << CQE_BYTE_16_LOCAL_QPN_S)
249
250#define CQE_BYTE_20_PORT_NUM_S 26
251#define CQE_BYTE_20_PORT_NUM_M (((1UL << 3) - 1) << CQE_BYTE_20_PORT_NUM_S)
252
253#define CQE_BYTE_20_SL_S 24
254#define CQE_BYTE_20_SL_M (((1UL << 2) - 1) << CQE_BYTE_20_SL_S)
255
256#define CQE_BYTE_20_REMOTE_QPN_S 0
257#define CQE_BYTE_20_REMOTE_QPN_M \
258 (((1UL << 24) - 1) << CQE_BYTE_20_REMOTE_QPN_S)
259
260#define CQE_BYTE_20_GRH_PRESENT_S 29
261
262#define CQE_BYTE_28_P_KEY_IDX_S 16
263#define CQE_BYTE_28_P_KEY_IDX_M (((1UL << 16) - 1) << CQE_BYTE_28_P_KEY_IDX_S)
264
265#define CQ_DB_REQ_NOT_SOL 0
266#define CQ_DB_REQ_NOT (1 << 16)
267
268struct hns_roce_v1_mpt_entry {
269 u32 mpt_byte_4;
270 u32 pbl_addr_l;
271 u32 mpt_byte_12;
272 u32 virt_addr_l;
273 u32 virt_addr_h;
274 u32 length;
275 u32 mpt_byte_28;
276 u32 pa0_l;
277 u32 mpt_byte_36;
278 u32 mpt_byte_40;
279 u32 mpt_byte_44;
280 u32 mpt_byte_48;
281 u32 pa4_l;
282 u32 mpt_byte_56;
283 u32 mpt_byte_60;
284 u32 mpt_byte_64;
285};
286
287#define MPT_BYTE_4_KEY_STATE_S 0
288#define MPT_BYTE_4_KEY_STATE_M (((1UL << 2) - 1) << MPT_BYTE_4_KEY_STATE_S)
289
290#define MPT_BYTE_4_KEY_S 8
291#define MPT_BYTE_4_KEY_M (((1UL << 8) - 1) << MPT_BYTE_4_KEY_S)
292
293#define MPT_BYTE_4_PAGE_SIZE_S 16
294#define MPT_BYTE_4_PAGE_SIZE_M (((1UL << 2) - 1) << MPT_BYTE_4_PAGE_SIZE_S)
295
296#define MPT_BYTE_4_MW_TYPE_S 20
297
298#define MPT_BYTE_4_MW_BIND_ENABLE_S 21
299
300#define MPT_BYTE_4_OWN_S 22
301
302#define MPT_BYTE_4_MEMORY_LOCATION_TYPE_S 24
303#define MPT_BYTE_4_MEMORY_LOCATION_TYPE_M \
304 (((1UL << 2) - 1) << MPT_BYTE_4_MEMORY_LOCATION_TYPE_S)
305
306#define MPT_BYTE_4_REMOTE_ATOMIC_S 26
307#define MPT_BYTE_4_LOCAL_WRITE_S 27
308#define MPT_BYTE_4_REMOTE_WRITE_S 28
309#define MPT_BYTE_4_REMOTE_READ_S 29
310#define MPT_BYTE_4_REMOTE_INVAL_ENABLE_S 30
311#define MPT_BYTE_4_ADDRESS_TYPE_S 31
312
313#define MPT_BYTE_12_PBL_ADDR_H_S 0
314#define MPT_BYTE_12_PBL_ADDR_H_M \
315 (((1UL << 17) - 1) << MPT_BYTE_12_PBL_ADDR_H_S)
316
317#define MPT_BYTE_12_MW_BIND_COUNTER_S 17
318#define MPT_BYTE_12_MW_BIND_COUNTER_M \
319 (((1UL << 15) - 1) << MPT_BYTE_12_MW_BIND_COUNTER_S)
320
321#define MPT_BYTE_28_PD_S 0
322#define MPT_BYTE_28_PD_M (((1UL << 16) - 1) << MPT_BYTE_28_PD_S)
323
324#define MPT_BYTE_28_L_KEY_IDX_L_S 16
325#define MPT_BYTE_28_L_KEY_IDX_L_M \
326 (((1UL << 16) - 1) << MPT_BYTE_28_L_KEY_IDX_L_S)
327
328#define MPT_BYTE_36_PA0_H_S 0
329#define MPT_BYTE_36_PA0_H_M (((1UL << 5) - 1) << MPT_BYTE_36_PA0_H_S)
330
331#define MPT_BYTE_36_PA1_L_S 8
332#define MPT_BYTE_36_PA1_L_M (((1UL << 24) - 1) << MPT_BYTE_36_PA1_L_S)
333
334#define MPT_BYTE_40_PA1_H_S 0
335#define MPT_BYTE_40_PA1_H_M (((1UL << 13) - 1) << MPT_BYTE_40_PA1_H_S)
336
337#define MPT_BYTE_40_PA2_L_S 16
338#define MPT_BYTE_40_PA2_L_M (((1UL << 16) - 1) << MPT_BYTE_40_PA2_L_S)
339
340#define MPT_BYTE_44_PA2_H_S 0
341#define MPT_BYTE_44_PA2_H_M (((1UL << 21) - 1) << MPT_BYTE_44_PA2_H_S)
342
343#define MPT_BYTE_44_PA3_L_S 24
344#define MPT_BYTE_44_PA3_L_M (((1UL << 8) - 1) << MPT_BYTE_44_PA3_L_S)
345
346#define MPT_BYTE_48_PA3_H_S 0
347#define MPT_BYTE_48_PA3_H_M (((1UL << 29) - 1) << MPT_BYTE_48_PA3_H_S)
348
349#define MPT_BYTE_56_PA4_H_S 0
350#define MPT_BYTE_56_PA4_H_M (((1UL << 5) - 1) << MPT_BYTE_56_PA4_H_S)
351
352#define MPT_BYTE_56_PA5_L_S 8
353#define MPT_BYTE_56_PA5_L_M (((1UL << 24) - 1) << MPT_BYTE_56_PA5_L_S)
354
355#define MPT_BYTE_60_PA5_H_S 0
356#define MPT_BYTE_60_PA5_H_M (((1UL << 13) - 1) << MPT_BYTE_60_PA5_H_S)
357
358#define MPT_BYTE_60_PA6_L_S 16
359#define MPT_BYTE_60_PA6_L_M (((1UL << 16) - 1) << MPT_BYTE_60_PA6_L_S)
360
361#define MPT_BYTE_64_PA6_H_S 0
362#define MPT_BYTE_64_PA6_H_M (((1UL << 21) - 1) << MPT_BYTE_64_PA6_H_S)
363
364#define MPT_BYTE_64_L_KEY_IDX_H_S 24
365#define MPT_BYTE_64_L_KEY_IDX_H_M \
366 (((1UL << 8) - 1) << MPT_BYTE_64_L_KEY_IDX_H_S)
367
368struct hns_roce_wqe_ctrl_seg {
369 __be32 sgl_pa_h;
370 __be32 flag;
371 __be32 imm_data;
372 __be32 msg_length;
373};
374
375struct hns_roce_wqe_data_seg {
376 __be64 addr;
377 __be32 lkey;
378 __be32 len;
379};
380
381struct hns_roce_wqe_raddr_seg {
382 __be32 rkey;
383 __be32 len;/* reserved */
384 __be64 raddr;
385};
386
387struct hns_roce_rq_wqe_ctrl {
388
389 u32 rwqe_byte_4;
390 u32 rocee_sgl_ba_l;
391 u32 rwqe_byte_12;
392 u32 reserved[5];
393};
394
395#define RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S 16
396#define RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M \
397 (((1UL << 6) - 1) << RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S)
398
399#define HNS_ROCE_QP_DESTROY_TIMEOUT_MSECS 10000
400
401#define GID_LEN 16
402
403struct hns_roce_ud_send_wqe {
404 u32 dmac_h;
405 u32 u32_8;
406 u32 immediate_data;
407
408 u32 u32_16;
409 union {
410 unsigned char dgid[GID_LEN];
411 struct {
412 u32 u32_20;
413 u32 u32_24;
414 u32 u32_28;
415 u32 u32_32;
416 };
417 };
418
419 u32 u32_36;
420 u32 u32_40;
421
422 u32 va0_l;
423 u32 va0_h;
424 u32 l_key0;
425
426 u32 va1_l;
427 u32 va1_h;
428 u32 l_key1;
429};
430
431#define UD_SEND_WQE_U32_4_DMAC_0_S 0
432#define UD_SEND_WQE_U32_4_DMAC_0_M \
433 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_0_S)
434
435#define UD_SEND_WQE_U32_4_DMAC_1_S 8
436#define UD_SEND_WQE_U32_4_DMAC_1_M \
437 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_1_S)
438
439#define UD_SEND_WQE_U32_4_DMAC_2_S 16
440#define UD_SEND_WQE_U32_4_DMAC_2_M \
441 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_2_S)
442
443#define UD_SEND_WQE_U32_4_DMAC_3_S 24
444#define UD_SEND_WQE_U32_4_DMAC_3_M \
445 (((1UL << 8) - 1) << UD_SEND_WQE_U32_4_DMAC_3_S)
446
447#define UD_SEND_WQE_U32_8_DMAC_4_S 0
448#define UD_SEND_WQE_U32_8_DMAC_4_M \
449 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_4_S)
450
451#define UD_SEND_WQE_U32_8_DMAC_5_S 8
452#define UD_SEND_WQE_U32_8_DMAC_5_M \
453 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_5_S)
454
455#define UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S 22
456
457#define UD_SEND_WQE_U32_8_OPERATION_TYPE_S 16
458#define UD_SEND_WQE_U32_8_OPERATION_TYPE_M \
459 (((1UL << 4) - 1) << UD_SEND_WQE_U32_8_OPERATION_TYPE_S)
460
461#define UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S 24
462#define UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M \
463 (((1UL << 6) - 1) << UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S)
464
465#define UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S 31
466
467#define UD_SEND_WQE_U32_16_DEST_QP_S 0
468#define UD_SEND_WQE_U32_16_DEST_QP_M \
469 (((1UL << 24) - 1) << UD_SEND_WQE_U32_16_DEST_QP_S)
470
471#define UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S 24
472#define UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M \
473 (((1UL << 8) - 1) << UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S)
474
475#define UD_SEND_WQE_U32_36_FLOW_LABEL_S 0
476#define UD_SEND_WQE_U32_36_FLOW_LABEL_M \
477 (((1UL << 20) - 1) << UD_SEND_WQE_U32_36_FLOW_LABEL_S)
478
479#define UD_SEND_WQE_U32_36_PRIORITY_S 20
480#define UD_SEND_WQE_U32_36_PRIORITY_M \
481 (((1UL << 4) - 1) << UD_SEND_WQE_U32_36_PRIORITY_S)
482
483#define UD_SEND_WQE_U32_36_SGID_INDEX_S 24
484#define UD_SEND_WQE_U32_36_SGID_INDEX_M \
485 (((1UL << 8) - 1) << UD_SEND_WQE_U32_36_SGID_INDEX_S)
486
487#define UD_SEND_WQE_U32_40_HOP_LIMIT_S 0
488#define UD_SEND_WQE_U32_40_HOP_LIMIT_M \
489 (((1UL << 8) - 1) << UD_SEND_WQE_U32_40_HOP_LIMIT_S)
490
491#define UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S 8
492#define UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M \
493 (((1UL << 8) - 1) << UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S)
494
495struct hns_roce_sqp_context {
496 u32 qp1c_bytes_4;
497 u32 sq_rq_bt_l;
498 u32 qp1c_bytes_12;
499 u32 qp1c_bytes_16;
500 u32 qp1c_bytes_20;
501 u32 cur_rq_wqe_ba_l;
502 u32 qp1c_bytes_28;
503 u32 qp1c_bytes_32;
504 u32 cur_sq_wqe_ba_l;
505 u32 qp1c_bytes_40;
506};
507
508#define QP1C_BYTES_4_QP_STATE_S 0
509#define QP1C_BYTES_4_QP_STATE_M \
510 (((1UL << 3) - 1) << QP1C_BYTES_4_QP_STATE_S)
511
512#define QP1C_BYTES_4_SQ_WQE_SHIFT_S 8
513#define QP1C_BYTES_4_SQ_WQE_SHIFT_M \
514 (((1UL << 4) - 1) << QP1C_BYTES_4_SQ_WQE_SHIFT_S)
515
516#define QP1C_BYTES_4_RQ_WQE_SHIFT_S 12
517#define QP1C_BYTES_4_RQ_WQE_SHIFT_M \
518 (((1UL << 4) - 1) << QP1C_BYTES_4_RQ_WQE_SHIFT_S)
519
520#define QP1C_BYTES_4_PD_S 16
521#define QP1C_BYTES_4_PD_M (((1UL << 16) - 1) << QP1C_BYTES_4_PD_S)
522
523#define QP1C_BYTES_12_SQ_RQ_BT_H_S 0
524#define QP1C_BYTES_12_SQ_RQ_BT_H_M \
525 (((1UL << 17) - 1) << QP1C_BYTES_12_SQ_RQ_BT_H_S)
526
527#define QP1C_BYTES_16_RQ_HEAD_S 0
528#define QP1C_BYTES_16_RQ_HEAD_M (((1UL << 15) - 1) << QP1C_BYTES_16_RQ_HEAD_S)
529
530#define QP1C_BYTES_16_PORT_NUM_S 16
531#define QP1C_BYTES_16_PORT_NUM_M \
532 (((1UL << 3) - 1) << QP1C_BYTES_16_PORT_NUM_S)
533
534#define QP1C_BYTES_16_SIGNALING_TYPE_S 27
535#define QP1C_BYTES_16_LOCAL_ENABLE_E2E_CREDIT_S 28
536#define QP1C_BYTES_16_RQ_BA_FLG_S 29
537#define QP1C_BYTES_16_SQ_BA_FLG_S 30
538#define QP1C_BYTES_16_QP1_ERR_S 31
539
540#define QP1C_BYTES_20_SQ_HEAD_S 0
541#define QP1C_BYTES_20_SQ_HEAD_M (((1UL << 15) - 1) << QP1C_BYTES_20_SQ_HEAD_S)
542
543#define QP1C_BYTES_20_PKEY_IDX_S 16
544#define QP1C_BYTES_20_PKEY_IDX_M \
545 (((1UL << 16) - 1) << QP1C_BYTES_20_PKEY_IDX_S)
546
547#define QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S 0
548#define QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M \
549 (((1UL << 5) - 1) << QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S)
550
551#define QP1C_BYTES_28_RQ_CUR_IDX_S 16
552#define QP1C_BYTES_28_RQ_CUR_IDX_M \
553 (((1UL << 15) - 1) << QP1C_BYTES_28_RQ_CUR_IDX_S)
554
555#define QP1C_BYTES_32_TX_CQ_NUM_S 0
556#define QP1C_BYTES_32_TX_CQ_NUM_M \
557 (((1UL << 16) - 1) << QP1C_BYTES_32_TX_CQ_NUM_S)
558
559#define QP1C_BYTES_32_RX_CQ_NUM_S 16
560#define QP1C_BYTES_32_RX_CQ_NUM_M \
561 (((1UL << 16) - 1) << QP1C_BYTES_32_RX_CQ_NUM_S)
562
563#define QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S 0
564#define QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M \
565 (((1UL << 5) - 1) << QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S)
566
567#define QP1C_BYTES_40_SQ_CUR_IDX_S 16
568#define QP1C_BYTES_40_SQ_CUR_IDX_M \
569 (((1UL << 15) - 1) << QP1C_BYTES_40_SQ_CUR_IDX_S)
570
571#define HNS_ROCE_WQE_INLINE (1UL<<31)
572#define HNS_ROCE_WQE_SE (1UL<<30)
573
574#define HNS_ROCE_WQE_SGE_NUM_BIT 24
575#define HNS_ROCE_WQE_IMM (1UL<<23)
576#define HNS_ROCE_WQE_FENCE (1UL<<21)
577#define HNS_ROCE_WQE_CQ_NOTIFY (1UL<<20)
578
579#define HNS_ROCE_WQE_OPCODE_SEND (0<<16)
580#define HNS_ROCE_WQE_OPCODE_RDMA_READ (1<<16)
581#define HNS_ROCE_WQE_OPCODE_RDMA_WRITE (2<<16)
582#define HNS_ROCE_WQE_OPCODE_LOCAL_INV (4<<16)
583#define HNS_ROCE_WQE_OPCODE_UD_SEND (7<<16)
584#define HNS_ROCE_WQE_OPCODE_MASK (15<<16)
585
586struct hns_roce_qp_context {
587 u32 qpc_bytes_4;
588 u32 qpc_bytes_8;
589 u32 qpc_bytes_12;
590 u32 qpc_bytes_16;
591 u32 sq_rq_bt_l;
592 u32 qpc_bytes_24;
593 u32 irrl_ba_l;
594 u32 qpc_bytes_32;
595 u32 qpc_bytes_36;
596 u32 dmac_l;
597 u32 qpc_bytes_44;
598 u32 qpc_bytes_48;
599 u8 dgid[16];
600 u32 qpc_bytes_68;
601 u32 cur_rq_wqe_ba_l;
602 u32 qpc_bytes_76;
603 u32 rx_rnr_time;
604 u32 qpc_bytes_84;
605 u32 qpc_bytes_88;
606 union {
607 u32 rx_sge_len;
608 u32 dma_length;
609 };
610 union {
611 u32 rx_sge_num;
612 u32 rx_send_pktn;
613 u32 r_key;
614 };
615 u32 va_l;
616 u32 va_h;
617 u32 qpc_bytes_108;
618 u32 qpc_bytes_112;
619 u32 rx_cur_sq_wqe_ba_l;
620 u32 qpc_bytes_120;
621 u32 qpc_bytes_124;
622 u32 qpc_bytes_128;
623 u32 qpc_bytes_132;
624 u32 qpc_bytes_136;
625 u32 qpc_bytes_140;
626 u32 qpc_bytes_144;
627 u32 qpc_bytes_148;
628 union {
629 u32 rnr_retry;
630 u32 ack_time;
631 };
632 u32 qpc_bytes_156;
633 u32 pkt_use_len;
634 u32 qpc_bytes_164;
635 u32 qpc_bytes_168;
636 union {
637 u32 sge_use_len;
638 u32 pa_use_len;
639 };
640 u32 qpc_bytes_176;
641 u32 qpc_bytes_180;
642 u32 tx_cur_sq_wqe_ba_l;
643 u32 qpc_bytes_188;
644 u32 rvd21;
645};
646
647#define QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S 0
648#define QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M \
649 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S)
650
651#define QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S 3
652#define QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S 4
653#define QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S 5
654#define QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S 6
655#define QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S 7
656
657#define QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S 8
658#define QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M \
659 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S)
660
661#define QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S 12
662#define QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M \
663 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S)
664
665#define QP_CONTEXT_QPC_BYTES_4_PD_S 16
666#define QP_CONTEXT_QPC_BYTES_4_PD_M \
667 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_4_PD_S)
668
669#define QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S 0
670#define QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M \
671 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S)
672
673#define QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S 16
674#define QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M \
675 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S)
676
677#define QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S 0
678#define QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M \
679 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S)
680
681#define QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S 16
682#define QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M \
683 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S)
684
685#define QP_CONTEXT_QPC_BYTES_16_QP_NUM_S 0
686#define QP_CONTEXT_QPC_BYTES_16_QP_NUM_M \
687 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_16_QP_NUM_S)
688
689#define QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S 0
690#define QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M \
691 (((1UL << 17) - 1) << QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S)
692
693#define QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S 18
694#define QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M \
695 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S)
696
697#define QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S 23
698
699#define QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S 0
700#define QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M \
701 (((1UL << 17) - 1) << QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S)
702
703#define QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S 18
704#define QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M \
705 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S)
706
707#define QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S 20
708#define QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S 21
709#define QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S 22
710#define QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S 23
711
712#define QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S 24
713#define QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M \
714 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S)
715
716#define QP_CONTEXT_QPC_BYTES_36_DEST_QP_S 0
717#define QP_CONTEXT_QPC_BYTES_36_DEST_QP_M \
718 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_36_DEST_QP_S)
719
720#define QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S 24
721#define QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M \
722 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S)
723
724#define QP_CONTEXT_QPC_BYTES_44_DMAC_H_S 0
725#define QP_CONTEXT_QPC_BYTES_44_DMAC_H_M \
726 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_44_DMAC_H_S)
727
728#define QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S 16
729#define QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M \
730 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S)
731
732#define QP_CONTEXT_QPC_BYTES_44_HOPLMT_S 24
733#define QP_CONTEXT_QPC_BYTES_44_HOPLMT_M \
734 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_44_HOPLMT_S)
735
736#define QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S 0
737#define QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M \
738 (((1UL << 20) - 1) << QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S)
739
740#define QP_CONTEXT_QPC_BYTES_48_TCLASS_S 20
741#define QP_CONTEXT_QPC_BYTES_48_TCLASS_M \
742 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_48_TCLASS_S)
743
744#define QP_CONTEXT_QPC_BYTES_48_MTU_S 28
745#define QP_CONTEXT_QPC_BYTES_48_MTU_M \
746 (((1UL << 4) - 1) << QP_CONTEXT_QPC_BYTES_48_MTU_S)
747
748#define QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S 0
749#define QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M \
750 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S)
751
752#define QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S 16
753#define QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M \
754 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S)
755
756#define QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S 0
757#define QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M \
758 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S)
759
760#define QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S 8
761#define QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M \
762 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S)
763
764#define QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S 0
765#define QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M \
766 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S)
767
768#define QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S 24
769#define QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M \
770 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S)
771
772#define QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S 0
773#define QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M \
774 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S)
775
776#define QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S 24
777#define QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S 25
778
779#define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S 26
780#define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M \
781 (((1UL << 2) - 1) << \
782 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S)
783
784#define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S 29
785#define QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M \
786 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S)
787
788#define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S 0
789#define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M \
790 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S)
791
792#define QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S 24
793#define QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S 25
794
795#define QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S 0
796#define QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M \
797 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S)
798
799#define QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S 24
800#define QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M \
801 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S)
802
803#define QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S 0
804#define QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M \
805 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S)
806
807#define QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S 0
808#define QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M \
809 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S)
810
811#define QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S 16
812#define QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M \
813 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S)
814
815#define QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S 0
816#define QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M \
817 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S)
818
819#define QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S 24
820
821#define QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S 25
822#define QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M \
823 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S)
824
825#define QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S 27
826
827#define QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S 0
828#define QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M \
829 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S)
830
831#define QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S 24
832#define QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M \
833 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S)
834
835#define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S 0
836#define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M \
837 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S)
838
839#define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S 24
840#define QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M \
841 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S)
842
843#define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S 0
844#define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M \
845 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S)
846
847#define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S 16
848#define QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M \
849 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S)
850
851#define QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S 31
852
853#define QP_CONTEXT_QPC_BYTES_144_QP_STATE_S 0
854#define QP_CONTEXT_QPC_BYTES_144_QP_STATE_M \
855 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_144_QP_STATE_S)
856
857#define QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S 0
858#define QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M \
859 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S)
860
861#define QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S 2
862#define QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M \
863 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S)
864
865#define QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S 5
866#define QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M \
867 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S)
868
869#define QP_CONTEXT_QPC_BYTES_148_LSN_S 8
870#define QP_CONTEXT_QPC_BYTES_148_LSN_M \
871 (((1UL << 16) - 1) << QP_CONTEXT_QPC_BYTES_148_LSN_S)
872
873#define QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S 0
874#define QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M \
875 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S)
876
877#define QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S 3
878#define QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M \
879 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S)
880
881#define QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S 8
882#define QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M \
883 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S)
884
885#define QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S 11
886#define QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M \
887 (((1UL << 3) - 1) << QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S)
888
889#define QP_CONTEXT_QPC_BYTES_156_SL_S 14
890#define QP_CONTEXT_QPC_BYTES_156_SL_M \
891 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_156_SL_S)
892
893#define QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S 16
894#define QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M \
895 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S)
896
897#define QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S 24
898#define QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M \
899 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S)
900
901#define QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S 0
902#define QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M \
903 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S)
904
905#define QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S 24
906#define QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M \
907 (((1UL << 8) - 1) << QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S)
908
909#define QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S 0
910#define QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M \
911 (((1UL << 24) - 1) << QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S)
912
913#define QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S 24
914#define QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M \
915 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S)
916
917#define QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S 26
918#define QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M \
919 (((1UL << 2) - 1) << QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S)
920
921#define QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S 28
922#define QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S 29
923#define QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S 30
924
925#define QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S 0
926#define QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M \
927 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S)
928
929#define QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S 16
930#define QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M \
931 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S)
932
933#define QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S 0
934#define QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M \
935 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S)
936
937#define QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S 16
938#define QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M \
939 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S)
940
941#define QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S 0
942#define QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M \
943 (((1UL << 5) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S)
944
945#define QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S 8
946
947#define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S 16
948#define QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M \
949 (((1UL << 15) - 1) << QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S)
950
951struct hns_roce_rq_db {
952 u32 u32_4;
953 u32 u32_8;
954};
955
956#define RQ_DOORBELL_U32_4_RQ_HEAD_S 0
957#define RQ_DOORBELL_U32_4_RQ_HEAD_M \
958 (((1UL << 15) - 1) << RQ_DOORBELL_U32_4_RQ_HEAD_S)
959
960#define RQ_DOORBELL_U32_8_QPN_S 0
961#define RQ_DOORBELL_U32_8_QPN_M (((1UL << 24) - 1) << RQ_DOORBELL_U32_8_QPN_S)
962
963#define RQ_DOORBELL_U32_8_CMD_S 28
964#define RQ_DOORBELL_U32_8_CMD_M (((1UL << 3) - 1) << RQ_DOORBELL_U32_8_CMD_S)
965
966#define RQ_DOORBELL_U32_8_HW_SYNC_S 31
967
968struct hns_roce_sq_db {
969 u32 u32_4;
970 u32 u32_8;
971};
972
973#define SQ_DOORBELL_U32_4_SQ_HEAD_S 0
974#define SQ_DOORBELL_U32_4_SQ_HEAD_M \
975 (((1UL << 15) - 1) << SQ_DOORBELL_U32_4_SQ_HEAD_S)
976
977#define SQ_DOORBELL_U32_4_SL_S 16
978#define SQ_DOORBELL_U32_4_SL_M \
979 (((1UL << 2) - 1) << SQ_DOORBELL_U32_4_SL_S)
980
981#define SQ_DOORBELL_U32_4_PORT_S 18
982#define SQ_DOORBELL_U32_4_PORT_M (((1UL << 3) - 1) << SQ_DOORBELL_U32_4_PORT_S)
983
984#define SQ_DOORBELL_U32_8_QPN_S 0
985#define SQ_DOORBELL_U32_8_QPN_M (((1UL << 24) - 1) << SQ_DOORBELL_U32_8_QPN_S)
986
987#define SQ_DOORBELL_HW_SYNC_S 31
988
989struct hns_roce_ext_db {
990 int esdb_dep;
991 int eodb_dep;
992 struct hns_roce_buf_list *sdb_buf_list;
993 struct hns_roce_buf_list *odb_buf_list;
994};
995
996struct hns_roce_db_table {
997 int sdb_ext_mod;
998 int odb_ext_mod;
999 struct hns_roce_ext_db *ext_db;
1000};
1001
1002struct hns_roce_bt_table {
1003 struct hns_roce_buf_list qpc_buf;
1004 struct hns_roce_buf_list mtpt_buf;
1005 struct hns_roce_buf_list cqc_buf;
1006};
1007
1008struct hns_roce_tptr_table {
1009 struct hns_roce_buf_list tptr_buf;
1010};
1011
1012struct hns_roce_qp_work {
1013 struct work_struct work;
1014 struct ib_device *ib_dev;
1015 struct hns_roce_qp *qp;
1016 u32 db_wait_stage;
1017 u32 sdb_issue_ptr;
1018 u32 sdb_inv_cnt;
1019 u32 sche_cnt;
1020};
1021
1022struct hns_roce_des_qp {
1023 struct workqueue_struct *qp_wq;
1024 int requeue_flag;
1025};
1026
1027struct hns_roce_mr_free_work {
1028 struct work_struct work;
1029 struct ib_device *ib_dev;
1030 struct completion *comp;
1031 int comp_flag;
1032 void *mr;
1033};
1034
1035struct hns_roce_recreate_lp_qp_work {
1036 struct work_struct work;
1037 struct ib_device *ib_dev;
1038 struct completion *comp;
1039 int comp_flag;
1040};
1041
1042struct hns_roce_free_mr {
1043 struct workqueue_struct *free_mr_wq;
1044 struct hns_roce_qp *mr_free_qp[HNS_ROCE_V1_RESV_QP];
1045 struct hns_roce_cq *mr_free_cq;
1046 struct hns_roce_pd *mr_free_pd;
1047};
1048
1049struct hns_roce_v1_priv {
1050 struct hns_roce_db_table db_table;
1051 struct hns_roce_raq_table raq_table;
1052 struct hns_roce_bt_table bt_table;
1053 struct hns_roce_tptr_table tptr_table;
1054 struct hns_roce_des_qp des_qp;
1055 struct hns_roce_free_mr free_mr;
1056};
1057
1058int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset);
1059int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1060int hns_roce_v1_destroy_qp(struct ib_qp *ibqp);
1061
1062#endif