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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Generic driver for memory-mapped GPIO controllers.
4 *
5 * Copyright 2008 MontaVista Software, Inc.
6 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
7 *
8 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
9 * ...`` ```````..
10 * ..The simplest form of a GPIO controller that the driver supports is``
11 * `.just a single "data" register, where GPIO state can be read and/or `
12 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
13 * `````````
14 ___
15_/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
16__________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
17o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
18 `....trivial..'~`.```.```
19 * ```````
20 * .```````~~~~`..`.``.``.
21 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
22 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
23 * . register the device with -be`. .with a pair of set/clear-bit registers ,
24 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
25 * ``.`.``...``` ```.. output pins are also supported.`
26 * ^^ `````.`````````.,``~``~``~~``````
27 * . ^^
28 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
29 * .. The expectation is that in at least some cases . ,-~~~-,
30 * .this will be used with roll-your-own ASIC/FPGA .` \ /
31 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
32 * ..````````......``````````` \o_
33 * |
34 * ^^ / \
35 *
36 * ...`````~~`.....``.`..........``````.`.``.```........``.
37 * ` 8, 16, 32 and 64 bits registers are supported, and``.
38 * . the number of GPIOs is determined by the width of ~
39 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
40 * `.......````.```
41 */
42
43#include <linux/bitops.h>
44#include <linux/compiler.h>
45#include <linux/err.h>
46#include <linux/init.h>
47#include <linux/io.h>
48#include <linux/ioport.h>
49#include <linux/log2.h>
50#include <linux/mod_devicetable.h>
51#include <linux/module.h>
52#include <linux/platform_device.h>
53#include <linux/property.h>
54#include <linux/slab.h>
55#include <linux/spinlock.h>
56#include <linux/types.h>
57
58#include <linux/gpio/driver.h>
59
60#include "gpiolib.h"
61
62static void bgpio_write8(void __iomem *reg, unsigned long data)
63{
64 writeb(data, reg);
65}
66
67static unsigned long bgpio_read8(void __iomem *reg)
68{
69 return readb(reg);
70}
71
72static void bgpio_write16(void __iomem *reg, unsigned long data)
73{
74 writew(data, reg);
75}
76
77static unsigned long bgpio_read16(void __iomem *reg)
78{
79 return readw(reg);
80}
81
82static void bgpio_write32(void __iomem *reg, unsigned long data)
83{
84 writel(data, reg);
85}
86
87static unsigned long bgpio_read32(void __iomem *reg)
88{
89 return readl(reg);
90}
91
92#if BITS_PER_LONG >= 64
93static void bgpio_write64(void __iomem *reg, unsigned long data)
94{
95 writeq(data, reg);
96}
97
98static unsigned long bgpio_read64(void __iomem *reg)
99{
100 return readq(reg);
101}
102#endif /* BITS_PER_LONG >= 64 */
103
104static void bgpio_write16be(void __iomem *reg, unsigned long data)
105{
106 iowrite16be(data, reg);
107}
108
109static unsigned long bgpio_read16be(void __iomem *reg)
110{
111 return ioread16be(reg);
112}
113
114static void bgpio_write32be(void __iomem *reg, unsigned long data)
115{
116 iowrite32be(data, reg);
117}
118
119static unsigned long bgpio_read32be(void __iomem *reg)
120{
121 return ioread32be(reg);
122}
123
124static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
125{
126 if (gc->be_bits)
127 return BIT(gc->bgpio_bits - 1 - line);
128 return BIT(line);
129}
130
131static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
132{
133 unsigned long pinmask = bgpio_line2mask(gc, gpio);
134 bool dir = !!(gc->bgpio_dir & pinmask);
135
136 if (dir)
137 return !!(gc->read_reg(gc->reg_set) & pinmask);
138 else
139 return !!(gc->read_reg(gc->reg_dat) & pinmask);
140}
141
142/*
143 * This assumes that the bits in the GPIO register are in native endianness.
144 * We only assign the function pointer if we have that.
145 */
146static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
147 unsigned long *bits)
148{
149 unsigned long get_mask = 0;
150 unsigned long set_mask = 0;
151
152 /* Make sure we first clear any bits that are zero when we read the register */
153 *bits &= ~*mask;
154
155 set_mask = *mask & gc->bgpio_dir;
156 get_mask = *mask & ~gc->bgpio_dir;
157
158 if (set_mask)
159 *bits |= gc->read_reg(gc->reg_set) & set_mask;
160 if (get_mask)
161 *bits |= gc->read_reg(gc->reg_dat) & get_mask;
162
163 return 0;
164}
165
166static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
167{
168 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
169}
170
171/*
172 * This only works if the bits in the GPIO register are in native endianness.
173 */
174static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
175 unsigned long *bits)
176{
177 /* Make sure we first clear any bits that are zero when we read the register */
178 *bits &= ~*mask;
179 *bits |= gc->read_reg(gc->reg_dat) & *mask;
180 return 0;
181}
182
183/*
184 * With big endian mirrored bit order it becomes more tedious.
185 */
186static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
187 unsigned long *bits)
188{
189 unsigned long readmask = 0;
190 unsigned long val;
191 int bit;
192
193 /* Make sure we first clear any bits that are zero when we read the register */
194 *bits &= ~*mask;
195
196 /* Create a mirrored mask */
197 for_each_set_bit(bit, mask, gc->ngpio)
198 readmask |= bgpio_line2mask(gc, bit);
199
200 /* Read the register */
201 val = gc->read_reg(gc->reg_dat) & readmask;
202
203 /*
204 * Mirror the result into the "bits" result, this will give line 0
205 * in bit 0 ... line 31 in bit 31 for a 32bit register.
206 */
207 for_each_set_bit(bit, &val, gc->ngpio)
208 *bits |= bgpio_line2mask(gc, bit);
209
210 return 0;
211}
212
213static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
214{
215}
216
217static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
218{
219 unsigned long mask = bgpio_line2mask(gc, gpio);
220 unsigned long flags;
221
222 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
223
224 if (val)
225 gc->bgpio_data |= mask;
226 else
227 gc->bgpio_data &= ~mask;
228
229 gc->write_reg(gc->reg_dat, gc->bgpio_data);
230
231 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
232}
233
234static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
235 int val)
236{
237 unsigned long mask = bgpio_line2mask(gc, gpio);
238
239 if (val)
240 gc->write_reg(gc->reg_set, mask);
241 else
242 gc->write_reg(gc->reg_clr, mask);
243}
244
245static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
246{
247 unsigned long mask = bgpio_line2mask(gc, gpio);
248 unsigned long flags;
249
250 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
251
252 if (val)
253 gc->bgpio_data |= mask;
254 else
255 gc->bgpio_data &= ~mask;
256
257 gc->write_reg(gc->reg_set, gc->bgpio_data);
258
259 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
260}
261
262static void bgpio_multiple_get_masks(struct gpio_chip *gc,
263 unsigned long *mask, unsigned long *bits,
264 unsigned long *set_mask,
265 unsigned long *clear_mask)
266{
267 int i;
268
269 *set_mask = 0;
270 *clear_mask = 0;
271
272 for_each_set_bit(i, mask, gc->bgpio_bits) {
273 if (test_bit(i, bits))
274 *set_mask |= bgpio_line2mask(gc, i);
275 else
276 *clear_mask |= bgpio_line2mask(gc, i);
277 }
278}
279
280static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
281 unsigned long *mask,
282 unsigned long *bits,
283 void __iomem *reg)
284{
285 unsigned long flags;
286 unsigned long set_mask, clear_mask;
287
288 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
289
290 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
291
292 gc->bgpio_data |= set_mask;
293 gc->bgpio_data &= ~clear_mask;
294
295 gc->write_reg(reg, gc->bgpio_data);
296
297 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
298}
299
300static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
301 unsigned long *bits)
302{
303 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
304}
305
306static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
307 unsigned long *bits)
308{
309 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
310}
311
312static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
313 unsigned long *mask,
314 unsigned long *bits)
315{
316 unsigned long set_mask, clear_mask;
317
318 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
319
320 if (set_mask)
321 gc->write_reg(gc->reg_set, set_mask);
322 if (clear_mask)
323 gc->write_reg(gc->reg_clr, clear_mask);
324}
325
326static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
327{
328 return 0;
329}
330
331static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
332 int val)
333{
334 return -EINVAL;
335}
336
337static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
338 int val)
339{
340 gc->set(gc, gpio, val);
341
342 return 0;
343}
344
345static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
346{
347 unsigned long flags;
348
349 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
350
351 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
352
353 if (gc->reg_dir_in)
354 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
355 if (gc->reg_dir_out)
356 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
357
358 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
359
360 return 0;
361}
362
363static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
364{
365 /* Return 0 if output, 1 if input */
366 if (gc->bgpio_dir_unreadable) {
367 if (gc->bgpio_dir & bgpio_line2mask(gc, gpio))
368 return GPIO_LINE_DIRECTION_OUT;
369 return GPIO_LINE_DIRECTION_IN;
370 }
371
372 if (gc->reg_dir_out) {
373 if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio))
374 return GPIO_LINE_DIRECTION_OUT;
375 return GPIO_LINE_DIRECTION_IN;
376 }
377
378 if (gc->reg_dir_in)
379 if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)))
380 return GPIO_LINE_DIRECTION_OUT;
381
382 return GPIO_LINE_DIRECTION_IN;
383}
384
385static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
386{
387 unsigned long flags;
388
389 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
390
391 gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
392
393 if (gc->reg_dir_in)
394 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
395 if (gc->reg_dir_out)
396 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
397
398 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
399}
400
401static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
402 int val)
403{
404 bgpio_dir_out(gc, gpio, val);
405 gc->set(gc, gpio, val);
406 return 0;
407}
408
409static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,
410 int val)
411{
412 gc->set(gc, gpio, val);
413 bgpio_dir_out(gc, gpio, val);
414 return 0;
415}
416
417static int bgpio_setup_accessors(struct device *dev,
418 struct gpio_chip *gc,
419 bool byte_be)
420{
421
422 switch (gc->bgpio_bits) {
423 case 8:
424 gc->read_reg = bgpio_read8;
425 gc->write_reg = bgpio_write8;
426 break;
427 case 16:
428 if (byte_be) {
429 gc->read_reg = bgpio_read16be;
430 gc->write_reg = bgpio_write16be;
431 } else {
432 gc->read_reg = bgpio_read16;
433 gc->write_reg = bgpio_write16;
434 }
435 break;
436 case 32:
437 if (byte_be) {
438 gc->read_reg = bgpio_read32be;
439 gc->write_reg = bgpio_write32be;
440 } else {
441 gc->read_reg = bgpio_read32;
442 gc->write_reg = bgpio_write32;
443 }
444 break;
445#if BITS_PER_LONG >= 64
446 case 64:
447 if (byte_be) {
448 dev_err(dev,
449 "64 bit big endian byte order unsupported\n");
450 return -EINVAL;
451 } else {
452 gc->read_reg = bgpio_read64;
453 gc->write_reg = bgpio_write64;
454 }
455 break;
456#endif /* BITS_PER_LONG >= 64 */
457 default:
458 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
459 return -EINVAL;
460 }
461
462 return 0;
463}
464
465/*
466 * Create the device and allocate the resources. For setting GPIO's there are
467 * three supported configurations:
468 *
469 * - single input/output register resource (named "dat").
470 * - set/clear pair (named "set" and "clr").
471 * - single output register resource and single input resource ("set" and
472 * dat").
473 *
474 * For the single output register, this drives a 1 by setting a bit and a zero
475 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
476 * in the set register and clears it by setting a bit in the clear register.
477 * The configuration is detected by which resources are present.
478 *
479 * For setting the GPIO direction, there are three supported configurations:
480 *
481 * - simple bidirection GPIO that requires no configuration.
482 * - an output direction register (named "dirout") where a 1 bit
483 * indicates the GPIO is an output.
484 * - an input direction register (named "dirin") where a 1 bit indicates
485 * the GPIO is an input.
486 */
487static int bgpio_setup_io(struct gpio_chip *gc,
488 void __iomem *dat,
489 void __iomem *set,
490 void __iomem *clr,
491 unsigned long flags)
492{
493
494 gc->reg_dat = dat;
495 if (!gc->reg_dat)
496 return -EINVAL;
497
498 if (set && clr) {
499 gc->reg_set = set;
500 gc->reg_clr = clr;
501 gc->set = bgpio_set_with_clear;
502 gc->set_multiple = bgpio_set_multiple_with_clear;
503 } else if (set && !clr) {
504 gc->reg_set = set;
505 gc->set = bgpio_set_set;
506 gc->set_multiple = bgpio_set_multiple_set;
507 } else if (flags & BGPIOF_NO_OUTPUT) {
508 gc->set = bgpio_set_none;
509 gc->set_multiple = NULL;
510 } else {
511 gc->set = bgpio_set;
512 gc->set_multiple = bgpio_set_multiple;
513 }
514
515 if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
516 (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
517 gc->get = bgpio_get_set;
518 if (!gc->be_bits)
519 gc->get_multiple = bgpio_get_set_multiple;
520 /*
521 * We deliberately avoid assigning the ->get_multiple() call
522 * for big endian mirrored registers which are ALSO reflecting
523 * their value in the set register when used as output. It is
524 * simply too much complexity, let the GPIO core fall back to
525 * reading each line individually in that fringe case.
526 */
527 } else {
528 gc->get = bgpio_get;
529 if (gc->be_bits)
530 gc->get_multiple = bgpio_get_multiple_be;
531 else
532 gc->get_multiple = bgpio_get_multiple;
533 }
534
535 return 0;
536}
537
538static int bgpio_setup_direction(struct gpio_chip *gc,
539 void __iomem *dirout,
540 void __iomem *dirin,
541 unsigned long flags)
542{
543 if (dirout || dirin) {
544 gc->reg_dir_out = dirout;
545 gc->reg_dir_in = dirin;
546 if (flags & BGPIOF_NO_SET_ON_INPUT)
547 gc->direction_output = bgpio_dir_out_dir_first;
548 else
549 gc->direction_output = bgpio_dir_out_val_first;
550 gc->direction_input = bgpio_dir_in;
551 gc->get_direction = bgpio_get_dir;
552 } else {
553 if (flags & BGPIOF_NO_OUTPUT)
554 gc->direction_output = bgpio_dir_out_err;
555 else
556 gc->direction_output = bgpio_simple_dir_out;
557 gc->direction_input = bgpio_simple_dir_in;
558 }
559
560 return 0;
561}
562
563static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
564{
565 if (gpio_pin < chip->ngpio)
566 return 0;
567
568 return -EINVAL;
569}
570
571/**
572 * bgpio_init() - Initialize generic GPIO accessor functions
573 * @gc: the GPIO chip to set up
574 * @dev: the parent device of the new GPIO chip (compulsory)
575 * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
576 * @dat: MMIO address for the register to READ the value of the GPIO lines, it
577 * is expected that a 1 in the corresponding bit in this register means the
578 * line is asserted
579 * @set: MMIO address for the register to SET the value of the GPIO lines, it is
580 * expected that we write the line with 1 in this register to drive the GPIO line
581 * high.
582 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
583 * expected that we write the line with 1 in this register to drive the GPIO line
584 * low. It is allowed to leave this address as NULL, in that case the SET register
585 * will be assumed to also clear the GPIO lines, by actively writing the line
586 * with 0.
587 * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
588 * that setting a line to 1 in this register will turn that line into an
589 * output line. Conversely, setting the line to 0 will turn that line into
590 * an input.
591 * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
592 * that setting a line to 1 in this register will turn that line into an
593 * input line. Conversely, setting the line to 0 will turn that line into
594 * an output.
595 * @flags: Different flags that will affect the behaviour of the device, such as
596 * endianness etc.
597 */
598int bgpio_init(struct gpio_chip *gc, struct device *dev,
599 unsigned long sz, void __iomem *dat, void __iomem *set,
600 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
601 unsigned long flags)
602{
603 int ret;
604
605 if (!is_power_of_2(sz))
606 return -EINVAL;
607
608 gc->bgpio_bits = sz * 8;
609 if (gc->bgpio_bits > BITS_PER_LONG)
610 return -EINVAL;
611
612 raw_spin_lock_init(&gc->bgpio_lock);
613 gc->parent = dev;
614 gc->label = dev_name(dev);
615 gc->base = -1;
616 gc->request = bgpio_request;
617 gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
618
619 ret = gpiochip_get_ngpios(gc, dev);
620 if (ret)
621 gc->ngpio = gc->bgpio_bits;
622 else
623 gc->bgpio_bits = roundup_pow_of_two(round_up(gc->ngpio, 8));
624
625 ret = bgpio_setup_io(gc, dat, set, clr, flags);
626 if (ret)
627 return ret;
628
629 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
630 if (ret)
631 return ret;
632
633 ret = bgpio_setup_direction(gc, dirout, dirin, flags);
634 if (ret)
635 return ret;
636
637 gc->bgpio_data = gc->read_reg(gc->reg_dat);
638 if (gc->set == bgpio_set_set &&
639 !(flags & BGPIOF_UNREADABLE_REG_SET))
640 gc->bgpio_data = gc->read_reg(gc->reg_set);
641
642 if (flags & BGPIOF_UNREADABLE_REG_DIR)
643 gc->bgpio_dir_unreadable = true;
644
645 /*
646 * Inspect hardware to find initial direction setting.
647 */
648 if ((gc->reg_dir_out || gc->reg_dir_in) &&
649 !(flags & BGPIOF_UNREADABLE_REG_DIR)) {
650 if (gc->reg_dir_out)
651 gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
652 else if (gc->reg_dir_in)
653 gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
654 /*
655 * If we have two direction registers, synchronise
656 * input setting to output setting, the library
657 * can not handle a line being input and output at
658 * the same time.
659 */
660 if (gc->reg_dir_out && gc->reg_dir_in)
661 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
662 }
663
664 return ret;
665}
666EXPORT_SYMBOL_GPL(bgpio_init);
667
668#if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
669
670static void __iomem *bgpio_map(struct platform_device *pdev,
671 const char *name,
672 resource_size_t sane_sz)
673{
674 struct resource *r;
675 resource_size_t sz;
676
677 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
678 if (!r)
679 return NULL;
680
681 sz = resource_size(r);
682 if (sz != sane_sz)
683 return IOMEM_ERR_PTR(-EINVAL);
684
685 return devm_ioremap_resource(&pdev->dev, r);
686}
687
688static const struct of_device_id bgpio_of_match[] = {
689 { .compatible = "brcm,bcm6345-gpio" },
690 { .compatible = "wd,mbl-gpio" },
691 { .compatible = "ni,169445-nand-gpio" },
692 { }
693};
694MODULE_DEVICE_TABLE(of, bgpio_of_match);
695
696static struct bgpio_pdata *bgpio_parse_fw(struct device *dev, unsigned long *flags)
697{
698 struct bgpio_pdata *pdata;
699
700 if (!dev_fwnode(dev))
701 return NULL;
702
703 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
704 if (!pdata)
705 return ERR_PTR(-ENOMEM);
706
707 pdata->base = -1;
708
709 if (device_is_big_endian(dev))
710 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
711
712 if (device_property_read_bool(dev, "no-output"))
713 *flags |= BGPIOF_NO_OUTPUT;
714
715 return pdata;
716}
717
718static int bgpio_pdev_probe(struct platform_device *pdev)
719{
720 struct device *dev = &pdev->dev;
721 struct resource *r;
722 void __iomem *dat;
723 void __iomem *set;
724 void __iomem *clr;
725 void __iomem *dirout;
726 void __iomem *dirin;
727 unsigned long sz;
728 unsigned long flags = 0;
729 int err;
730 struct gpio_chip *gc;
731 struct bgpio_pdata *pdata;
732
733 pdata = bgpio_parse_fw(dev, &flags);
734 if (IS_ERR(pdata))
735 return PTR_ERR(pdata);
736
737 if (!pdata) {
738 pdata = dev_get_platdata(dev);
739 flags = pdev->id_entry->driver_data;
740 }
741
742 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
743 if (!r)
744 return -EINVAL;
745
746 sz = resource_size(r);
747
748 dat = bgpio_map(pdev, "dat", sz);
749 if (IS_ERR(dat))
750 return PTR_ERR(dat);
751
752 set = bgpio_map(pdev, "set", sz);
753 if (IS_ERR(set))
754 return PTR_ERR(set);
755
756 clr = bgpio_map(pdev, "clr", sz);
757 if (IS_ERR(clr))
758 return PTR_ERR(clr);
759
760 dirout = bgpio_map(pdev, "dirout", sz);
761 if (IS_ERR(dirout))
762 return PTR_ERR(dirout);
763
764 dirin = bgpio_map(pdev, "dirin", sz);
765 if (IS_ERR(dirin))
766 return PTR_ERR(dirin);
767
768 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
769 if (!gc)
770 return -ENOMEM;
771
772 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
773 if (err)
774 return err;
775
776 if (pdata) {
777 if (pdata->label)
778 gc->label = pdata->label;
779 gc->base = pdata->base;
780 if (pdata->ngpio > 0)
781 gc->ngpio = pdata->ngpio;
782 }
783
784 platform_set_drvdata(pdev, gc);
785
786 return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
787}
788
789static const struct platform_device_id bgpio_id_table[] = {
790 {
791 .name = "basic-mmio-gpio",
792 .driver_data = 0,
793 }, {
794 .name = "basic-mmio-gpio-be",
795 .driver_data = BGPIOF_BIG_ENDIAN,
796 },
797 { }
798};
799MODULE_DEVICE_TABLE(platform, bgpio_id_table);
800
801static struct platform_driver bgpio_driver = {
802 .driver = {
803 .name = "basic-mmio-gpio",
804 .of_match_table = bgpio_of_match,
805 },
806 .id_table = bgpio_id_table,
807 .probe = bgpio_pdev_probe,
808};
809
810module_platform_driver(bgpio_driver);
811
812#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
813
814MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
815MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
816MODULE_LICENSE("GPL");
1/*
2 * Generic driver for memory-mapped GPIO controllers.
3 *
4 * Copyright 2008 MontaVista Software, Inc.
5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
13 * ...`` ```````..
14 * ..The simplest form of a GPIO controller that the driver supports is``
15 * `.just a single "data" register, where GPIO state can be read and/or `
16 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
17 * `````````
18 ___
19_/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
20__________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
21o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
22 `....trivial..'~`.```.```
23 * ```````
24 * .```````~~~~`..`.``.``.
25 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
26 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
27 * . register the device with -be`. .with a pair of set/clear-bit registers ,
28 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
29 * ``.`.``...``` ```.. output pins are also supported.`
30 * ^^ `````.`````````.,``~``~``~~``````
31 * . ^^
32 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
33 * .. The expectation is that in at least some cases . ,-~~~-,
34 * .this will be used with roll-your-own ASIC/FPGA .` \ /
35 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
36 * ..````````......``````````` \o_
37 * |
38 * ^^ / \
39 *
40 * ...`````~~`.....``.`..........``````.`.``.```........``.
41 * ` 8, 16, 32 and 64 bits registers are supported, and``.
42 * . the number of GPIOs is determined by the width of ~
43 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
44 * `.......````.```
45 */
46
47#include <linux/init.h>
48#include <linux/err.h>
49#include <linux/bug.h>
50#include <linux/kernel.h>
51#include <linux/module.h>
52#include <linux/spinlock.h>
53#include <linux/compiler.h>
54#include <linux/types.h>
55#include <linux/errno.h>
56#include <linux/log2.h>
57#include <linux/ioport.h>
58#include <linux/io.h>
59#include <linux/gpio/driver.h>
60#include <linux/slab.h>
61#include <linux/bitops.h>
62#include <linux/platform_device.h>
63#include <linux/mod_devicetable.h>
64#include <linux/of.h>
65#include <linux/of_device.h>
66
67static void bgpio_write8(void __iomem *reg, unsigned long data)
68{
69 writeb(data, reg);
70}
71
72static unsigned long bgpio_read8(void __iomem *reg)
73{
74 return readb(reg);
75}
76
77static void bgpio_write16(void __iomem *reg, unsigned long data)
78{
79 writew(data, reg);
80}
81
82static unsigned long bgpio_read16(void __iomem *reg)
83{
84 return readw(reg);
85}
86
87static void bgpio_write32(void __iomem *reg, unsigned long data)
88{
89 writel(data, reg);
90}
91
92static unsigned long bgpio_read32(void __iomem *reg)
93{
94 return readl(reg);
95}
96
97#if BITS_PER_LONG >= 64
98static void bgpio_write64(void __iomem *reg, unsigned long data)
99{
100 writeq(data, reg);
101}
102
103static unsigned long bgpio_read64(void __iomem *reg)
104{
105 return readq(reg);
106}
107#endif /* BITS_PER_LONG >= 64 */
108
109static void bgpio_write16be(void __iomem *reg, unsigned long data)
110{
111 iowrite16be(data, reg);
112}
113
114static unsigned long bgpio_read16be(void __iomem *reg)
115{
116 return ioread16be(reg);
117}
118
119static void bgpio_write32be(void __iomem *reg, unsigned long data)
120{
121 iowrite32be(data, reg);
122}
123
124static unsigned long bgpio_read32be(void __iomem *reg)
125{
126 return ioread32be(reg);
127}
128
129static unsigned long bgpio_pin2mask(struct gpio_chip *gc, unsigned int pin)
130{
131 return BIT(pin);
132}
133
134static unsigned long bgpio_pin2mask_be(struct gpio_chip *gc,
135 unsigned int pin)
136{
137 return BIT(gc->bgpio_bits - 1 - pin);
138}
139
140static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
141{
142 unsigned long pinmask = gc->pin2mask(gc, gpio);
143
144 if (gc->bgpio_dir & pinmask)
145 return !!(gc->read_reg(gc->reg_set) & pinmask);
146 else
147 return !!(gc->read_reg(gc->reg_dat) & pinmask);
148}
149
150static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
151{
152 return !!(gc->read_reg(gc->reg_dat) & gc->pin2mask(gc, gpio));
153}
154
155static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
156{
157}
158
159static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
160{
161 unsigned long mask = gc->pin2mask(gc, gpio);
162 unsigned long flags;
163
164 spin_lock_irqsave(&gc->bgpio_lock, flags);
165
166 if (val)
167 gc->bgpio_data |= mask;
168 else
169 gc->bgpio_data &= ~mask;
170
171 gc->write_reg(gc->reg_dat, gc->bgpio_data);
172
173 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
174}
175
176static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
177 int val)
178{
179 unsigned long mask = gc->pin2mask(gc, gpio);
180
181 if (val)
182 gc->write_reg(gc->reg_set, mask);
183 else
184 gc->write_reg(gc->reg_clr, mask);
185}
186
187static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
188{
189 unsigned long mask = gc->pin2mask(gc, gpio);
190 unsigned long flags;
191
192 spin_lock_irqsave(&gc->bgpio_lock, flags);
193
194 if (val)
195 gc->bgpio_data |= mask;
196 else
197 gc->bgpio_data &= ~mask;
198
199 gc->write_reg(gc->reg_set, gc->bgpio_data);
200
201 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
202}
203
204static void bgpio_multiple_get_masks(struct gpio_chip *gc,
205 unsigned long *mask, unsigned long *bits,
206 unsigned long *set_mask,
207 unsigned long *clear_mask)
208{
209 int i;
210
211 *set_mask = 0;
212 *clear_mask = 0;
213
214 for (i = 0; i < gc->bgpio_bits; i++) {
215 if (*mask == 0)
216 break;
217 if (__test_and_clear_bit(i, mask)) {
218 if (test_bit(i, bits))
219 *set_mask |= gc->pin2mask(gc, i);
220 else
221 *clear_mask |= gc->pin2mask(gc, i);
222 }
223 }
224}
225
226static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
227 unsigned long *mask,
228 unsigned long *bits,
229 void __iomem *reg)
230{
231 unsigned long flags;
232 unsigned long set_mask, clear_mask;
233
234 spin_lock_irqsave(&gc->bgpio_lock, flags);
235
236 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
237
238 gc->bgpio_data |= set_mask;
239 gc->bgpio_data &= ~clear_mask;
240
241 gc->write_reg(reg, gc->bgpio_data);
242
243 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
244}
245
246static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
247 unsigned long *bits)
248{
249 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
250}
251
252static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
253 unsigned long *bits)
254{
255 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
256}
257
258static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
259 unsigned long *mask,
260 unsigned long *bits)
261{
262 unsigned long set_mask, clear_mask;
263
264 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
265
266 if (set_mask)
267 gc->write_reg(gc->reg_set, set_mask);
268 if (clear_mask)
269 gc->write_reg(gc->reg_clr, clear_mask);
270}
271
272static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
273{
274 return 0;
275}
276
277static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
278 int val)
279{
280 return -EINVAL;
281}
282
283static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
284 int val)
285{
286 gc->set(gc, gpio, val);
287
288 return 0;
289}
290
291static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
292{
293 unsigned long flags;
294
295 spin_lock_irqsave(&gc->bgpio_lock, flags);
296
297 gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
298 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
299
300 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
301
302 return 0;
303}
304
305static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
306{
307 /* Return 0 if output, 1 of input */
308 return !(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
309}
310
311static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
312{
313 unsigned long flags;
314
315 gc->set(gc, gpio, val);
316
317 spin_lock_irqsave(&gc->bgpio_lock, flags);
318
319 gc->bgpio_dir |= gc->pin2mask(gc, gpio);
320 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
321
322 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
323
324 return 0;
325}
326
327static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
328{
329 unsigned long flags;
330
331 spin_lock_irqsave(&gc->bgpio_lock, flags);
332
333 gc->bgpio_dir |= gc->pin2mask(gc, gpio);
334 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
335
336 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
337
338 return 0;
339}
340
341static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
342{
343 unsigned long flags;
344
345 gc->set(gc, gpio, val);
346
347 spin_lock_irqsave(&gc->bgpio_lock, flags);
348
349 gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
350 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
351
352 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
353
354 return 0;
355}
356
357static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
358{
359 /* Return 0 if output, 1 if input */
360 return !!(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
361}
362
363static int bgpio_setup_accessors(struct device *dev,
364 struct gpio_chip *gc,
365 bool bit_be,
366 bool byte_be)
367{
368
369 switch (gc->bgpio_bits) {
370 case 8:
371 gc->read_reg = bgpio_read8;
372 gc->write_reg = bgpio_write8;
373 break;
374 case 16:
375 if (byte_be) {
376 gc->read_reg = bgpio_read16be;
377 gc->write_reg = bgpio_write16be;
378 } else {
379 gc->read_reg = bgpio_read16;
380 gc->write_reg = bgpio_write16;
381 }
382 break;
383 case 32:
384 if (byte_be) {
385 gc->read_reg = bgpio_read32be;
386 gc->write_reg = bgpio_write32be;
387 } else {
388 gc->read_reg = bgpio_read32;
389 gc->write_reg = bgpio_write32;
390 }
391 break;
392#if BITS_PER_LONG >= 64
393 case 64:
394 if (byte_be) {
395 dev_err(dev,
396 "64 bit big endian byte order unsupported\n");
397 return -EINVAL;
398 } else {
399 gc->read_reg = bgpio_read64;
400 gc->write_reg = bgpio_write64;
401 }
402 break;
403#endif /* BITS_PER_LONG >= 64 */
404 default:
405 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
406 return -EINVAL;
407 }
408
409 gc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
410
411 return 0;
412}
413
414/*
415 * Create the device and allocate the resources. For setting GPIO's there are
416 * three supported configurations:
417 *
418 * - single input/output register resource (named "dat").
419 * - set/clear pair (named "set" and "clr").
420 * - single output register resource and single input resource ("set" and
421 * dat").
422 *
423 * For the single output register, this drives a 1 by setting a bit and a zero
424 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
425 * in the set register and clears it by setting a bit in the clear register.
426 * The configuration is detected by which resources are present.
427 *
428 * For setting the GPIO direction, there are three supported configurations:
429 *
430 * - simple bidirection GPIO that requires no configuration.
431 * - an output direction register (named "dirout") where a 1 bit
432 * indicates the GPIO is an output.
433 * - an input direction register (named "dirin") where a 1 bit indicates
434 * the GPIO is an input.
435 */
436static int bgpio_setup_io(struct gpio_chip *gc,
437 void __iomem *dat,
438 void __iomem *set,
439 void __iomem *clr,
440 unsigned long flags)
441{
442
443 gc->reg_dat = dat;
444 if (!gc->reg_dat)
445 return -EINVAL;
446
447 if (set && clr) {
448 gc->reg_set = set;
449 gc->reg_clr = clr;
450 gc->set = bgpio_set_with_clear;
451 gc->set_multiple = bgpio_set_multiple_with_clear;
452 } else if (set && !clr) {
453 gc->reg_set = set;
454 gc->set = bgpio_set_set;
455 gc->set_multiple = bgpio_set_multiple_set;
456 } else if (flags & BGPIOF_NO_OUTPUT) {
457 gc->set = bgpio_set_none;
458 gc->set_multiple = NULL;
459 } else {
460 gc->set = bgpio_set;
461 gc->set_multiple = bgpio_set_multiple;
462 }
463
464 if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
465 (flags & BGPIOF_READ_OUTPUT_REG_SET))
466 gc->get = bgpio_get_set;
467 else
468 gc->get = bgpio_get;
469
470 return 0;
471}
472
473static int bgpio_setup_direction(struct gpio_chip *gc,
474 void __iomem *dirout,
475 void __iomem *dirin,
476 unsigned long flags)
477{
478 if (dirout && dirin) {
479 return -EINVAL;
480 } else if (dirout) {
481 gc->reg_dir = dirout;
482 gc->direction_output = bgpio_dir_out;
483 gc->direction_input = bgpio_dir_in;
484 gc->get_direction = bgpio_get_dir;
485 } else if (dirin) {
486 gc->reg_dir = dirin;
487 gc->direction_output = bgpio_dir_out_inv;
488 gc->direction_input = bgpio_dir_in_inv;
489 gc->get_direction = bgpio_get_dir_inv;
490 } else {
491 if (flags & BGPIOF_NO_OUTPUT)
492 gc->direction_output = bgpio_dir_out_err;
493 else
494 gc->direction_output = bgpio_simple_dir_out;
495 gc->direction_input = bgpio_simple_dir_in;
496 }
497
498 return 0;
499}
500
501static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
502{
503 if (gpio_pin < chip->ngpio)
504 return 0;
505
506 return -EINVAL;
507}
508
509int bgpio_init(struct gpio_chip *gc, struct device *dev,
510 unsigned long sz, void __iomem *dat, void __iomem *set,
511 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
512 unsigned long flags)
513{
514 int ret;
515
516 if (!is_power_of_2(sz))
517 return -EINVAL;
518
519 gc->bgpio_bits = sz * 8;
520 if (gc->bgpio_bits > BITS_PER_LONG)
521 return -EINVAL;
522
523 spin_lock_init(&gc->bgpio_lock);
524 gc->parent = dev;
525 gc->label = dev_name(dev);
526 gc->base = -1;
527 gc->ngpio = gc->bgpio_bits;
528 gc->request = bgpio_request;
529
530 ret = bgpio_setup_io(gc, dat, set, clr, flags);
531 if (ret)
532 return ret;
533
534 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN,
535 flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
536 if (ret)
537 return ret;
538
539 ret = bgpio_setup_direction(gc, dirout, dirin, flags);
540 if (ret)
541 return ret;
542
543 gc->bgpio_data = gc->read_reg(gc->reg_dat);
544 if (gc->set == bgpio_set_set &&
545 !(flags & BGPIOF_UNREADABLE_REG_SET))
546 gc->bgpio_data = gc->read_reg(gc->reg_set);
547 if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
548 gc->bgpio_dir = gc->read_reg(gc->reg_dir);
549
550 return ret;
551}
552EXPORT_SYMBOL_GPL(bgpio_init);
553
554#if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
555
556static void __iomem *bgpio_map(struct platform_device *pdev,
557 const char *name,
558 resource_size_t sane_sz)
559{
560 struct resource *r;
561 resource_size_t sz;
562
563 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
564 if (!r)
565 return NULL;
566
567 sz = resource_size(r);
568 if (sz != sane_sz)
569 return IOMEM_ERR_PTR(-EINVAL);
570
571 return devm_ioremap_resource(&pdev->dev, r);
572}
573
574#ifdef CONFIG_OF
575static const struct of_device_id bgpio_of_match[] = {
576 { .compatible = "brcm,bcm6345-gpio" },
577 { .compatible = "wd,mbl-gpio" },
578 { }
579};
580MODULE_DEVICE_TABLE(of, bgpio_of_match);
581
582static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
583 unsigned long *flags)
584{
585 struct bgpio_pdata *pdata;
586
587 if (!of_match_device(bgpio_of_match, &pdev->dev))
588 return NULL;
589
590 pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
591 GFP_KERNEL);
592 if (!pdata)
593 return ERR_PTR(-ENOMEM);
594
595 pdata->base = -1;
596
597 if (of_device_is_big_endian(pdev->dev.of_node))
598 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
599
600 if (of_property_read_bool(pdev->dev.of_node, "no-output"))
601 *flags |= BGPIOF_NO_OUTPUT;
602
603 return pdata;
604}
605#else
606static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
607 unsigned long *flags)
608{
609 return NULL;
610}
611#endif /* CONFIG_OF */
612
613static int bgpio_pdev_probe(struct platform_device *pdev)
614{
615 struct device *dev = &pdev->dev;
616 struct resource *r;
617 void __iomem *dat;
618 void __iomem *set;
619 void __iomem *clr;
620 void __iomem *dirout;
621 void __iomem *dirin;
622 unsigned long sz;
623 unsigned long flags = 0;
624 int err;
625 struct gpio_chip *gc;
626 struct bgpio_pdata *pdata;
627
628 pdata = bgpio_parse_dt(pdev, &flags);
629 if (IS_ERR(pdata))
630 return PTR_ERR(pdata);
631
632 if (!pdata) {
633 pdata = dev_get_platdata(dev);
634 flags = pdev->id_entry->driver_data;
635 }
636
637 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
638 if (!r)
639 return -EINVAL;
640
641 sz = resource_size(r);
642
643 dat = bgpio_map(pdev, "dat", sz);
644 if (IS_ERR(dat))
645 return PTR_ERR(dat);
646
647 set = bgpio_map(pdev, "set", sz);
648 if (IS_ERR(set))
649 return PTR_ERR(set);
650
651 clr = bgpio_map(pdev, "clr", sz);
652 if (IS_ERR(clr))
653 return PTR_ERR(clr);
654
655 dirout = bgpio_map(pdev, "dirout", sz);
656 if (IS_ERR(dirout))
657 return PTR_ERR(dirout);
658
659 dirin = bgpio_map(pdev, "dirin", sz);
660 if (IS_ERR(dirin))
661 return PTR_ERR(dirin);
662
663 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
664 if (!gc)
665 return -ENOMEM;
666
667 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
668 if (err)
669 return err;
670
671 if (pdata) {
672 if (pdata->label)
673 gc->label = pdata->label;
674 gc->base = pdata->base;
675 if (pdata->ngpio > 0)
676 gc->ngpio = pdata->ngpio;
677 }
678
679 platform_set_drvdata(pdev, gc);
680
681 return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
682}
683
684static const struct platform_device_id bgpio_id_table[] = {
685 {
686 .name = "basic-mmio-gpio",
687 .driver_data = 0,
688 }, {
689 .name = "basic-mmio-gpio-be",
690 .driver_data = BGPIOF_BIG_ENDIAN,
691 },
692 { }
693};
694MODULE_DEVICE_TABLE(platform, bgpio_id_table);
695
696static struct platform_driver bgpio_driver = {
697 .driver = {
698 .name = "basic-mmio-gpio",
699 .of_match_table = of_match_ptr(bgpio_of_match),
700 },
701 .id_table = bgpio_id_table,
702 .probe = bgpio_pdev_probe,
703};
704
705module_platform_driver(bgpio_driver);
706
707#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
708
709MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
710MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
711MODULE_LICENSE("GPL");